Solar cell, stacked cell, and photovoltaic module

Abstract

This application relates to the field of solar cell technology, and more particularly to a solar cell, a tandem cell, and a photovoltaic module. In the embodiments of this application, the first surface adopts a localized doping design, with a first doped polycrystalline silicon layer only set in the first electrode region and an emitter layer set in the first non-electrode region. This relatively reduces the area of ​​the polycrystalline silicon film, which is beneficial for reducing parasitic absorption and contact resistance in the electrode region. It also helps to reduce the carrier recombination rate of the first surface, thereby improving the photoelectric conversion efficiency. By aligning each first electrode region with each second electrode region along the thickness direction, the current can be directly discharged in a direction perpendicular to the substrate (longitudinal direction), shortening the carrier transport path, reducing series resistance, and reducing recombination losses in the electrode contact region, further optimizing the fill factor (FF) and overall output performance of the cell.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to a solar cell, a tandem cell, and a photovoltaic module. Background Technology

[0002] With the accelerated transition from traditional fossil fuels and the increasing demand for sustainable development, solar cells, as a clean and renewable energy technology, are increasingly becoming an important component of the energy system. A solar cell is essentially a semiconductor device that directly converts solar energy into electrical energy. Its working principle is based on the photovoltaic effect: when sunlight shines on the cell, photon energy excites electron-hole pairs (i.e., charge carriers) to be generated inside the semiconductor. These charge carriers then separate under the influence of a built-in electric field, forming a potential difference. By effectively extracting these charge carriers through the metal electrodes on the front and back of the cell, direct current can be generated for use in external circuits, thus achieving the efficient conversion and utilization of solar energy into electrical energy.

[0003] Because polycrystalline silicon films exhibit strong parasitic absorption, which severely impacts the photocurrent of the solar cell, tunneling oxide layers and phosphorus-doped polycrystalline silicon stacked structures are generally only used on the back side of solar cells in related technologies. The front-side metal contact area typically employs a boron-diffused emitter, where an ohmic contact is formed directly between the metal electrode and the boron emitter. However, these structures still suffer from high recombination rates, which is detrimental to improving conversion efficiency. Summary of the Invention

[0004] In view of the above problems, this application provides a solar cell, a tandem cell, and a photovoltaic module to solve the aforementioned technical problems that are not conducive to improving conversion efficiency.

[0005] In a first aspect, embodiments of this application provide a solar cell, comprising: The substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction. The first surface includes a first electrode region and a first non-electrode region disposed alternately along a first direction. The second surface includes a second electrode region and a second non-electrode region disposed alternately along a first direction. The first surface has a textured surface structure, and the second surface has a polished surface structure. Each first electrode region and the corresponding second electrode region are aligned along the thickness direction. An emitter layer is disposed in the first non-electrode region; A first passivation contact structure is provided in the first electrode region, the first passivation contact structure comprising a first tunneling oxide layer and a first doped polysilicon layer sequentially stacked on the first surface, wherein the conductivity type of the substrate is opposite to that of the first doped polysilicon layer; and, A second passivation contact structure is provided in the second electrode region. The second passivation contact structure includes a second tunneling oxide layer and a second doped polysilicon layer sequentially stacked on the second surface. The conductivity type of the substrate is the same as that of the second doped polysilicon layer. The ratio of the sum of the widths of the first electrode region along the first direction to the width of the first surface along the first direction is 2 to 10:100.

[0006] Secondly, embodiments of this application provide a method for preparing a solar cell, comprising: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other along its thickness direction, the first surface including a first electrode region and a first non-electrode region disposed alternately along a first direction, the second surface including a second electrode region and a second non-electrode region disposed alternately along the first direction, each first electrode region and the corresponding second electrode region being aligned along the thickness direction, and the ratio of the sum of the widths of the first electrode regions along the first direction to the width of the first surface along the first direction being 2 to 10:100; A first surface having a first pyramidal textured surface is subjected to thermal oxidation to form a first tunneling oxide layer, and a first semiconductor layer is deposited on the first tunneling oxide layer, wherein the first semiconductor layer includes a first polycrystalline silicon layer or a first amorphous silicon layer. The substrate is subjected to high-temperature oxidation treatment to form an oxide layer on the first surface, wherein the first semiconductor layer after high-temperature oxidation treatment is a first polycrystalline silicon layer; Laser scanning is performed on the first non-electrode region of the first surface to modify the oxide layer in the first non-electrode region; The first surface is subjected to alkaline texturing treatment to remove the first tunneling oxide layer, the first polysilicon layer and the oxide layer in the first non-electrode region, and to form a second pyramid texturing structure in the first non-electrode region. The first surface is subjected to boron diffusion treatment to transform the first polysilicon layer in the first electrode region into a first doped polysilicon layer, and an emitter layer is formed in the first non-electrode region. A first mask layer is formed on the side of the first doped polysilicon layer away from the first tunneling oxide layer and on the side of the emitter layer away from the substrate. The second surface of the substrate is polished, and the polished second surface is thermally oxidized to form a second tunneling oxide layer. A second semiconductor layer is deposited on the second tunneling oxide layer, wherein the second semiconductor layer includes a second polycrystalline silicon layer or a second amorphous silicon layer. The second semiconductor layer is subjected to phosphorus diffusion treatment to transform the second semiconductor layer on the second surface into a second doped polysilicon layer, and a second mask layer is formed on the side of the second doped polysilicon layer away from the second tunneling oxide layer. Laser scanning is performed on the second non-electrode region of the second surface to modify the second mask layer of the second non-electrode region; The second surface is subjected to alkaline etching to remove the second tunneling oxide layer, the second doped polysilicon layer, and the second mask layer in the second non-electrode region.

[0007] Thirdly, embodiments of this application provide a stacked battery, comprising: Top-mounted cells can be perovskite cells, cadmium telluride solar cells, copper indium gallium selenide solar cells, or gallium arsenide solar cells. Intermediate connecting layer; and The bottom battery is the aforementioned solar cell; The top battery, the intermediate connecting layer, and the bottom battery are stacked and connected.

[0008] Fourthly, embodiments of this application provide a photovoltaic module, including the aforementioned solar cell or the aforementioned tandem cell.

[0009] In this embodiment, a first passivated contact structure and a second passivated contact structure are respectively provided on the first and second surfaces. This double-sided passivated contact structure reduces the interfacial carrier recombination rate, thereby effectively improving the open-circuit voltage and photoelectric conversion efficiency of the battery. The first surface adopts a localized doping design, with a first doped polycrystalline silicon layer of a different conductivity type from the substrate only provided in the first electrode region, and an emitter layer provided in the first non-electrode region. The ratio of the sum of the widths of the first electrode regions along the first direction to the width of the first surface along the first direction is controlled to be 2 to 10:100. While ensuring sufficient emitter area, the area of ​​the polycrystalline silicon film layer is relatively reduced, which is beneficial to reducing parasitic absorption and contact resistance in the electrode region. At the same time, it is beneficial to reduce the carrier recombination rate of the first surface to improve the photoelectric conversion efficiency. By aligning each first electrode region with each second electrode region along the thickness direction, the current can be directly discharged in the direction perpendicular to the substrate (longitudinal direction), shortening the carrier transport path, reducing the series resistance, and reducing the recombination loss in the electrode contact region, further optimizing the fill factor (FF) and overall output performance of the battery.

[0010] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of a solar cell according to an embodiment of this application.

[0012] Figure 2 This is another structural schematic diagram of a solar cell according to an embodiment of this application.

[0013] Figure 3 for Figure 2 Enlarged diagram of point A in the middle.

[0014] Figure 4 This is a schematic diagram of the structure of the battery string in the photovoltaic module provided in the embodiments of this application.

[0015] Figure 5 This is a schematic diagram of the structure of a photovoltaic module provided in an embodiment of this application. Detailed Implementation

[0016] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0017] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0019] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0020] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0021] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0022] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0023] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0024] One embodiment of this application provides a solar cell 100; please refer to [link / reference]. Figure 1 and Figure 2 As shown, the solar cell 100 includes a substrate 11, an emitter layer 12 disposed on the substrate 11, and a first passivation contact structure 13 and a second passivation contact structure 14 disposed on the substrate 11.

[0025] The substrate 11 has a first surface 11a and a second surface 11b disposed opposite to each other along its thickness direction. The first surface 11a includes a first electrode region 111 and a first non-electrode region 112 disposed alternately along a first direction. The second surface 11b includes a second electrode region 113 and a second non-electrode region 114 disposed alternately along a first direction. The first surface 11a has a textured surface structure, and the second surface 11b has a polished surface structure.

[0026] Each first electrode region 111 is aligned with its corresponding second electrode region 113 along the thickness direction. For example, regarding the aligned first electrode region 111 and second electrode region 113, the first electrode region 111 has a first central axis L1, which is perpendicular to both the first direction and the thickness direction. The second electrode region 113 has a second central axis L2, which is perpendicular to both the first direction and the thickness direction. The first central axis L1 and the second central axis L2 are directly opposite each other in the thickness direction, meaning that the projection of the first central axis L1 along the thickness direction onto the second electrode region 113 coincides with the second central axis L2. During laser-assisted sintering (LECO) of the electrode structure, this results in a more uniform current distribution, facilitating LECO control. Simultaneously, it simplifies the alignment process of the electrode patterns on the first surface 11a and the second surface 11b, reducing the risk of alignment deviation. It eliminates the need to adjust alignment parameters due to width differences, allowing for stable production using a single alignment standard, improving process yield and mass production consistency, and reducing production management costs.

[0027] The emitter layer 12 is disposed on the first non-electrode region 112.

[0028] The first passivation contact structure 13 is disposed in the first electrode region 111. The first passivation contact structure 13 includes a first tunneling oxide layer 131 and a first doped polysilicon layer 132 sequentially stacked on the first surface 11a. The conductivity type of the substrate 11 is opposite to that of the first doped polysilicon layer 132.

[0029] The second passivation contact structure 14 is disposed in the second electrode region 113. The second passivation contact structure 14 includes a second tunneling oxide layer 141 and a second doped polysilicon layer 142 sequentially stacked on the second surface 11b. The conductivity type of the substrate 11 is the same as that of the second doped polysilicon layer 142.

[0030] On the first surface 11a of the solar cell 100, the conductivity type of the emitter layer 12 is opposite to that of the substrate 11, and the conductivity type of the first doped polysilicon layer 132 is also opposite to that of the substrate 11. A PN junction is formed between the emitter layer 12 and the substrate 11, and a PN junction is also formed on the surface of the substrate 11 below the first doped polysilicon layer 132. That is, the first doped polysilicon layer 132, the first tunneling oxide layer 131, and the substrate 11 form a tunneling oxide PN junction. The first doped polysilicon layer 132 can also serve as the emitter. Both the first electrode region 111 and the first non-electrode region 112 of the first surface 11a are covered with emitters.

[0031] The ratio of the sum of the widths of the first electrode region 111 along the first direction to the width of the first surface 11a along the first direction is 2 to 10:100. That is, the ratio of the sum of the widths of the first passivation contact structure 13 along the first direction to the width of the first surface 11a along the first direction is 2 to 10:100. Since both the first electrode region 111 and the first non-electrode region 112 of the first surface 11a are covered with emitters, controlling the total width of the first passivation contact structure 13 within the aforementioned range can relatively reduce the area of ​​the first doped polysilicon layer 132, which is beneficial for reducing parasitic absorption and the contact resistance of the electrode region.

[0032] When the first surface 11a is the light-receiving surface, light irradiates the first surface 11a, generating electron-hole pairs on the first surface 11a of the substrate 11. When the substrate 11 is an N-type substrate, the photogenerated holes flow to the first electrode region 111 under the influence of the built-in electric field of the PN junction, and the photogenerated electrons flow to the second electrode region 113 under the influence of the built-in electric field of the PN junction. When the substrate 11 is a P-type substrate, the photogenerated electrons flow to the first electrode region 111 under the influence of the built-in electric field of the PN junction, and the photogenerated holes flow to the second electrode region 113 under the influence of the built-in electric field of the PN junction.

[0033] In this embodiment, a first passivated contact structure and a second passivated contact structure are respectively provided on the first and second surfaces. This double-sided passivated contact structure reduces the interfacial carrier recombination rate, thereby effectively improving the open-circuit voltage and photoelectric conversion efficiency of the battery. The first surface adopts a localized doping design, with a first doped polycrystalline silicon layer only provided in the first electrode region and an emitter layer provided in the first non-electrode region. This relatively reduces the area of ​​the polycrystalline silicon film, which can reduce parasitic absorption of short-wavelength light, increase the battery short-circuit current density (Jsc), and also helps to reduce the contact resistance of the electrode region. At the same time, the relatively reduced area of ​​the emitter layer helps to reduce the carrier recombination rate of the first surface, thereby improving the photoelectric conversion efficiency. By aligning each first electrode region with each second electrode region along the thickness direction, the current can be directly discharged in the direction perpendicular to the substrate (longitudinal direction), shortening the carrier transport path, reducing the series resistance, and reducing the recombination loss in the electrode contact region, further optimizing the battery's fill factor (FF) and overall output performance.

[0034] From an overall structural perspective, the electrode regions of the first side 11a and the second side 11b of the solar cell in this embodiment of the invention are both provided with a tunneling oxide layer and a doped polycrystalline silicon layer, forming a double-sided passivated contact solar cell with a doped polycrystalline silicon structure on both sides. This achieves passivation of the entire contact area, realizes low recombination throughout the cell, reduces the series resistance and recombination loss in the electrode area, synergistically improves the fill factor FF, increases the open-circuit voltage Voc, and improves the photoelectric conversion efficiency of the cell.

[0035] In some embodiments, the substrate 11 can be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type dopant element, which can be any one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type dopant element, which can be any one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In). Taking an N-type substrate as an example, the first tunneling oxide layer 131 and the first doped polysilicon layer 132 are disposed on the first surface 11a. This avoids the electrode structure on the first surface 11a from directly contacting the substrate 11, while the first doped polysilicon layer 132 and the substrate 11 form an inverted band structure, which can repel electrons in the substrate 11 and reduce the probability of electrons migrating and recombinating to the electrode structure on the first surface 11a. The first tunneling oxide layer 131 and the first doped polysilicon layer 132 work together to achieve excellent field-effect passivation and chemical passivation, directly weakening the high recombination loss induced by metal, isolating the metal from the substrate 11, reducing the damage to the surface of the substrate 11 caused by the subsequent fabrication of the electrode structure on the first surface 11a, and fundamentally reducing the recombination loss in the electrode region of the first surface 11a.

[0036] For example, the substrate 11 is an N-type semiconductor substrate, the doping element in the first doped polysilicon layer 132 is a P-type doping element, such as boron; the doping element in the second doped polysilicon layer 142 is an N-type doping element, such as phosphorus.

[0037] In one implementation, the ratio of the sum of the widths of the second electrode region 113 along the first direction to the width of the second surface 11b along the first direction is 1 to 10:100. That is, the ratio of the sum of the widths of the second passivation contact structure 14 along the first direction to the width of the second surface 11b along the first direction is 1 to 10:100.

[0038] In this embodiment, the total width of the second passivation contact structure 14 is controlled within the above range. While relatively reducing the area of ​​the second doped polysilicon layer 142, a certain width of the second electrode region 113 is maintained. This ensures the collection probability of minority carriers during lateral transport in the substrate 11, prevents Jsc loss due to bulk recombination, and further reduces the carrier recombination rate.

[0039] In some embodiments, each first electrode region 111 has the same width along the first direction, and each second electrode region 113 has the same width along the first direction.

[0040] In one implementation, the width of the first electrode region 111 along the first direction is equal to the width of the second electrode region 113 along the first direction.

[0041] In this embodiment, by making the widths of the two electrode regions the same, uneven current density distribution caused by width differences is avoided.

[0042] In one embodiment, the first non-electrode region 112 is a first groove structure. The first groove structure includes a first groove bottom surface 112a formed by a recess in the thickness direction of the substrate 11 and a first groove sidewall 112b connecting the first electrode region 111 and the first groove bottom surface 112a. The emitter layer 12 covers the first groove bottom surface 112a and the first groove sidewall 112b respectively. Exemplarily, the first groove sidewall 112b may be perpendicular to the first surface 11a, or the first groove sidewall 112b may be inclined toward the first electrode region 111.

[0043] In this embodiment, the first non-electrode region 112 is a first groove structure, which can relatively increase the area of ​​the emitter layer 12. Furthermore, the emitter layer 12 covers the bottom surface 112a and the sidewall 112b of the first groove, forming a continuous heavily doped electric field effect region. At the connection between the bottom surface 112a and the sidewall 112b of the first groove, the heavily doped electric field can effectively repel minority carriers, thereby reducing the surface recombination rate.

[0044] The textured structure includes a first pyramid textured structure formed in the first electrode region 111 and a second pyramid textured structure formed in the first non-electrode region 112. The first pyramid textured structure includes a first pyramid, and the second pyramid textured structure includes a second pyramid. The height of the first pyramid is greater than the height of the second pyramid, and the density of the first pyramid is less than the density of the second pyramid. That is, the number of first pyramids per unit area in the first electrode region 111 is less than the number of second pyramids per unit area in the first non-electrode region 112.

[0045] On the first surface 11a, the first pyramids are distributed in a large size and a small number in the first electrode region 111, which is conducive to the uniform spreading of the electrode slurry and the densification after sintering, reducing contact voids in the electrode structure, further reducing contact recombination and resistance; at the same time, it makes the contact between the electrode structure on the first surface 11a and the first passivated contact structure 13 below more uniform, improves the contact interface morphology, reduces contact resistance and series loss, and increases the battery fill factor FF.

[0046] On the first surface 11a, the second pyramid is distributed in a small size and in a large number on the first non-electrode region 112, which can ensure good light trapping effect and light absorption efficiency, maintain a high concentration of photogenerated carriers, further reduce the reflectivity of the first surface a and increase the short-circuit current density of the battery.

[0047] In this embodiment, by combining the first pyramidal textured surface structure and the second pyramidal textured surface structure, the recombination loss in the first electrode region can be reduced, the hole lifetime and open-circuit voltage Voc can be effectively improved, the fill factor can be optimized in a synergistic manner, and the efficiency limitation caused by the high recombination on the first surface can be overcome, thereby improving the photoelectric conversion efficiency of the battery.

[0048] In some embodiments, the ratio of the total width of the first electrode region 111 along the first direction to the width of the first surface 11a along the first direction is 1 to 10:100, and the ratio of the total width of the second electrode region 113 along the first direction to the width of the second surface 11b along the first direction is 1 to 10:100.

[0049] In this embodiment, by controlling the proportion of the first electrode region within the aforementioned range, the coverage area of ​​the polycrystalline silicon layer on the front surface is effectively reduced, significantly decreasing the parasitic absorption of short-wavelength light by the doped polycrystalline silicon layer, thereby significantly improving the short-circuit current density (Jsc) of the battery. Furthermore, while minimizing the light-shielding area on the front surface, sufficient effective area of ​​the first passivation contact structure is maintained to ensure excellent field passivation and chemical passivation effects. Simultaneously, controlling the proportion of the second electrode region within the aforementioned range reduces the back surface metal contact area and lowers the interfacial recombination rate, while ensuring that the second passivation contact structure has a sufficient carrier collection window. This not only guarantees the lateral transport efficiency of minority carriers in the substrate, preventing bulk recombination losses due to incomplete collection, but also achieves the optimal balance between reducing back surface recombination and maintaining good contact conductivity, further synergistically improving the battery's open-circuit voltage and fill factor.

[0050] In one embodiment, the solar cell 100 further includes a first electrode substrate 151 connected to the first passivation contact structure 13, a first electrode 152 stacked on the first electrode substrate 151, a second electrode substrate 161 connected to the second passivation contact structure 14, and a second electrode 162 stacked on the second electrode substrate 161. On the first surface 11a, the first electrode substrate 151 and the first electrode 152 form a first electrode structure, and the first electrode substrate 151 is in contact with the first doped polycrystalline silicon layer 132; on the second surface 11b, the second electrode substrate 161 and the second electrode 162 form a second electrode structure, and the second electrode substrate 161 is in contact with the second doped polycrystalline silicon layer 142.

[0051] In this embodiment, the electrode structures of both the first and second surfaces are configured as an electrode underlay and an electrode. The electrode underlay and the electrode can use the same or different electrode pastes, which helps to increase the flexibility of the electrode structure configuration.

[0052] In some embodiments, at least the composition of the first electrode underlayment 151 includes metallic silver, that is, the composition of the first electrode underlayment 151 includes metallic silver, while the composition of the first electrode 152 does not include metallic silver; or, the composition of the first electrode underlayment 151 includes metallic silver, and the composition of the first electrode 152 also includes metallic silver.

[0053] At least the composition of the second electrode underlayment 161 and the second electrode 162 includes metallic silver, that is, the composition of the second electrode underlayment 161 includes metallic silver, while the composition of the second electrode 162 does not include metallic silver; or, the composition of the second electrode underlayment 161 includes metallic silver, and the composition of the second electrode 162 also includes metallic silver.

[0054] The electrode structures of the first side 11a and the second side 11b of the solar cell employ a silver-containing electrode underlayer. Because the electrode underlayer contains silver, it can form good ohmic contacts with the first doped polycrystalline silicon layer 132 of the first side 11a and the second doped polycrystalline silicon layer 142 of the second side 11b, respectively, reducing contact resistance and suppressing interfacial recombination. This provides an excellent electrical contact foundation for the overall electrode structure on the first electrode region 111 and the second electrode region 113. Simultaneously, the presence of silver in the electrode underlayer ensures the structural performance of the electrode structure while allowing the first electrode 152 and the second electrode 162 to use lower-cost conductive materials or pastes with lower silver content. This reduces the amount of silver paste used and the consumption of precious metals without compromising conductivity or device performance, thereby reducing the overall production cost of the electrode structure and the solar cell while maintaining contact performance.

[0055] For example, the silver content in the first electrode underlay 151 is 80-100% by mass percentage, for example, 80%, 85%, 90%, 95%, or 100%. The silver content in the second electrode underlay 161 is also 80-100%, for example, 80%, 85%, 90%, 95%, or 100%. It is understood that the silver content in the first electrode underlay 151 and the second electrode underlay 161 can be the same or different.

[0056] For example, the silver content in the first electrode 152 is 0-95% by mass, for example, 0%, 20%, 50%, 85%, or 95%. The silver content in the second electrode 162 is 0-95%, for example, 0%, 20%, 50%, 85%, or 95%. It is understood that the silver content in the first electrode underlayment 151 and the second electrode underlayment 161 can be the same or different.

[0057] In some embodiments, the solar cell 100 further includes a first passivation antireflection layer 17 disposed on the first surface 11a and a second passivation antireflection layer 18 disposed on the second surface 11b. A first electrode underlayment 151 penetrates the first passivation antireflection layer 17 and forms an electrical contact with the first passivation contact structure 13, and a second electrode underlayment 161 penetrates the second passivation antireflection layer 18 and forms an electrical contact with the second passivation contact structure 14.

[0058] Specifically, the first passivation antireflection layer 17 includes a first passivation layer 171 and a first antireflection layer 172 sequentially disposed on the first surface 11a of the substrate 11; the first electrode underlayment 151 sequentially penetrates the first antireflection layer 172 and the first passivation layer 171 and then contacts the first doped polysilicon layer 132, and the first electrode 152 is stacked on the side of the first electrode underlayment 151 away from the first doped polysilicon layer 132; the second passivation antireflection layer 18 includes a second passivation layer 181 and a second antireflection layer 182 sequentially disposed on the second surface 11b of the substrate 11; the second electrode underlayment 161 sequentially penetrates the second antireflection layer 182 and the second passivation layer 181 and then contacts the second doped polysilicon layer 142, and the second electrode 162 is stacked on the side of the second electrode underlayment 161 away from the second doped polysilicon layer 142.

[0059] In this embodiment, the first electrode region 111 is sequentially covered with a first tunneling oxide layer 131, a first doped polysilicon layer 132, a first passivation layer 171, and a first antireflection layer 172. The first non-electrode region 112 is sequentially covered with an emitter layer 12, a first passivation layer 171, and a first antireflection layer 172. The second electrode region 113 is sequentially covered with a second tunneling oxide layer 141, a second doped polysilicon layer 142, a second passivation layer 181, and a second antireflection layer 182. The second non-electrode region 114 is sequentially covered with a second passivation layer 181 and a second antireflection layer 182. On the one hand, this allows the electrode region to maintain a low saturation current density to increase the open-circuit voltage. On the other hand, it reduces the parasitic absorption losses in the two non-electrode regions to increase the short-circuit current.

[0060] In some embodiments, the second non-electrode region 114 is a second groove structure, which includes a second groove bottom surface 114a formed by a recess in the substrate 11 along the thickness direction and a second groove sidewall 114b connecting the second electrode region 113 and the second groove bottom surface 114a. The second passivation layer 181 covers the second groove bottom surface 114a and the second groove sidewall 114b respectively. Exemplarily, the second groove sidewall 114b may be perpendicular to the second surface 11b, or the second groove sidewall 114b may be inclined toward the second electrode region 113.

[0061] In some embodiments, the width of the first electrode underlayment 151 along the first direction is smaller than the width of the first electrode 152 along the first direction; the width of the second electrode underlayment 161 along the first direction is smaller than the width of the second electrode 162 along the first direction.

[0062] In this embodiment, the width of the electrode substrate of the electrode structure is smaller than the width of the electrode on it, which achieves low recombination and low contact resistivity, while reducing the amount of silver paste used, thus balancing battery performance and production cost.

[0063] Specifically, the narrower electrode bottom layer structure reduces the contact area between the electrode bottom layer and the doped polysilicon layer, which in turn reduces the contact area between the metal and the semiconductor. This can reduce the recombination current density J0 and increase the open-circuit voltage, effectively reducing metal-induced interface recombination while ensuring current collection capability.

[0064] Meanwhile, the first electrode 152 covers the first electrode underlayment 151 and extends to contact a portion of the first antireflection layer 172, and the second electrode 162 covers the second electrode underlayment 161 and extends to contact a portion of the second antireflection layer 182. A wider electrode is fabricated on a relatively narrow electrode underlayment. The extended portions of the fabricated electrode on both sides after covering the electrode underlayment cover the corresponding antireflection layer surface, which increases the conductive cross-sectional area without introducing additional interface recombination, reduces gate line resistance and series loss, and improves the fill factor.

[0065] In some embodiments, each first electrode underlayment 151 is aligned with the corresponding second electrode underlayment 161 along the thickness direction.

[0066] The first electrode underlayment 151 and the corresponding second electrode underlayment 161 are aligned. The first electrode underlayment 151 has a first electrode central axis that is perpendicular to the first direction and the thickness direction, respectively. The second electrode underlayment 161 has a second electrode central axis that is perpendicular to the first direction and the thickness direction, respectively. The first electrode central axis corresponds to the first central axis L1 of the corresponding first electrode region 111, and the second electrode central axis corresponds to the second central axis L2 of the corresponding second electrode region 113. The first electrode central axis and the second electrode central axis are directly opposite each other in the thickness direction.

[0067] In some embodiments, the emitter layer 12 may be formed by doping the original substrate 11. The emitter layer 12 and the substrate 11 are made of the same base material. Specifically, a portion of the original substrate corresponding to the first non-electrode region 112 may be doped. The doped original substrate serves as the emitter layer 12, and the undoped original substrate serves as the substrate 11. Furthermore, the doping element type in the emitter layer 12 is different from the doping element type in the substrate 11. For example, if the substrate 11 is an N-type silicon substrate, the emitter layer 12 is formed by P-type doping of a portion of the N-type silicon substrate.

[0068] In some embodiments, the first tunneling oxide layer 131 may be a silicon dioxide layer, and the second tunneling oxide layer 141 may be a silicon dioxide layer.

[0069] In some embodiments, the first passivation layer 171 may be a single-layer structure or a stacked structure, and the material for preparing the first passivation layer 171 may include one or two of silicon oxide or aluminum oxide; the material for preparing the first antireflection layer 172 may include one or more of silicon nitride, silicon oxynitride or aluminum oxide.

[0070] In some embodiments, the second passivation layer 181 may be a single-layer structure or a stacked structure, and the material for preparing the second passivation layer 181 may include one or both of silicon oxide and aluminum oxide; the material for preparing the second antireflection layer 182 may include one or more of silicon nitride, silicon oxynitride, or aluminum oxide.

[0071] One embodiment of this application provides a method for fabricating a solar cell, used to fabricate the aforementioned solar cell 100. The method for fabricating the solar cell includes the following steps: Step S1: Provide a substrate, the substrate including a first surface and a second surface disposed opposite to each other along its thickness direction, the first surface including a first electrode region and a first non-electrode region disposed alternately along a first direction, the second surface including a second electrode region and a second non-electrode region disposed alternately along the first direction, each first electrode region and the corresponding second electrode region being aligned along the thickness direction; For example, the substrate is an N-type silicon wafer, with the first side and the second side being the light-receiving side and the backlight side, respectively.

[0072] Step S2: Perform thermal oxidation on the first surface having the first pyramid textured surface to form a first tunneling oxide layer, and deposit a first semiconductor layer on the first tunneling oxide layer, wherein the first semiconductor layer includes a first polycrystalline silicon layer or a first amorphous silicon layer. In this process, before the first tunneling oxide layer and the first doped polysilicon layer are formed on the first surface, the first surface has a first pyramidal textured structure. Subsequently, the first tunneling oxide layer and the first doped polysilicon layer in the first non-electrode region are removed, and a second pyramidal textured structure is formed in the first non-electrode region. Exemplarily, the first pyramidal textured structure includes a plurality of first pyramids, the average height of the first pyramids is 1.2 μm to 1.5 μm, and the density of the first pyramids is 200,000 / ... Up to 500,000 / For example, the density of the First Pyramid is 200,000 / Up to 240,000 / .

[0073] The first surface is subjected to thermal oxidation to form a first tunneling oxide layer, which covers the entire first surface. For example, the thickness of the first tunneling oxide layer is 1-2 nm. Then, a first semiconductor layer can be deposited on the first tunneling oxide layer using low-pressure chemical vapor deposition (LPCVD). The first semiconductor layer includes a first polycrystalline silicon layer or a first amorphous silicon layer. For example, the thickness of the first semiconductor layer is 200-400 nm. The first polycrystalline silicon layer is an intrinsic polycrystalline silicon layer or the first amorphous silicon layer is an intrinsic amorphous silicon layer.

[0074] Step S3: Perform high-temperature oxidation treatment on the substrate to form an oxide layer on the first surface; In this process, an oxide layer is formed on the first semiconductor layer of the first surface, and an oxide layer is also formed on the second surface, with a thickness of 10-30 nm. The high-temperature oxidation process is specifically carried out at 800-950℃ for 30-90 minutes; the oxide layer is specifically silicon oxide.

[0075] When the first semiconductor layer is a first amorphous silicon layer, the substrate is subjected to high-temperature oxidation treatment to transform the first amorphous silicon layer into a first polycrystalline silicon layer, and an oxide layer is formed on the first surface; when the first semiconductor layer is a first amorphous silicon layer, the substrate is subjected to high-temperature oxidation treatment to form an oxide layer on the side of the first polycrystalline silicon layer away from the first tunneling oxide layer. In other words, the first semiconductor layer after high-temperature oxidation treatment is a first polycrystalline silicon layer.

[0076] Step S4: Perform laser scanning on the first non-electrode region of the first surface to modify the oxide layer of the first non-electrode region; In this process, the first non-electrode region is laser-scanned, which modifies the oxide layer. The modified oxide layer is unable to withstand the alkaline etching solution, and is removed during the subsequent alkaline texturing process. The first tunneling oxide layer and the first doped polysilicon layer in the first non-electrode region are also removed by the alkaline etching solution. Conversely, the oxide layer in the first electrode region remains intact, and the first tunneling oxide layer and the first doped polysilicon layer in the first electrode region are not removed during the subsequent alkaline texturing process.

[0077] Step S5: Perform alkaline texturing on the first surface to remove the first tunneling oxide layer, the first polysilicon layer and the oxide layer in the first non-electrode region, and form a second pyramid textured surface structure in the first non-electrode region. The second pyramid textured surface comprises multiple second pyramids, with an average height of 1 μm to 1.2 μm and a density of 220,000 pyramids per square meter. Up to 500,000 / For example, the density of the second pyramid is 250,000 / Up to 280,000 / .

[0078] Step S6: Perform boron diffusion treatment on the first surface to transform the first polysilicon layer in the first electrode region into a first doped polysilicon layer, and form an emitter layer in the first non-electrode region, and form a first mask layer on the side of the first doped polysilicon layer away from the first tunneling oxide layer and on the side of the emitter layer away from the substrate. In this process, a first doped polysilicon layer is obtained by boron diffusion into the first polysilicon layer, and an emitter layer is obtained by boron diffusion into the substrate in the first non-electrode region. For example, the thickness of the first mask layer is 50-100 nm, and the first mask layer is borosilicate glass (BSG). The first mask layer protects the first surface, ensuring that the functional film layer already formed on the first surface is not damaged during subsequent processing of the second surface.

[0079] Step S7: Polish the second surface of the substrate, perform thermal oxidation on the polished second surface to form a second tunneling oxide layer, and deposit a second semiconductor layer on the second tunneling oxide layer, wherein the second semiconductor layer includes a second polycrystalline silicon layer or a second amorphous silicon layer. Before polishing the second surface, the first surface of the substrate can be placed upwards, and the oxide layer around the second surface can be removed by HF in a chain wet process equipment. Subsequently, the second surface is subjected to alkaline polishing to expose a clean, flat N-type single crystal silicon surface free of parasitic dopants.

[0080] The polished second surface is subjected to thermal oxidation to form a second tunneling oxide layer, which covers the entire second surface. For example, the thickness of the second tunneling oxide layer is 1-2 nm. Then, a second semiconductor layer can be deposited by LPCVD. For example, the thickness of the second semiconductor layer is 100-200 nm. The second amorphous silicon layer is an intrinsic polycrystalline silicon layer or an intrinsic amorphous silicon layer.

[0081] Step S8: Perform phosphorus diffusion treatment on the second semiconductor layer to transform the second semiconductor layer on the second surface into a second doped polysilicon layer, and form a second mask layer on the side of the second doped polysilicon layer away from the second tunneling oxide layer; In this process, when the second semiconductor layer is a second amorphous silicon layer, the second amorphous silicon layer transforms into a second polycrystalline silicon layer during phosphorus diffusion. The second polycrystalline silicon layer then undergoes phosphorus diffusion to obtain a second doped polycrystalline silicon layer. For example, the sheet resistance after phosphorus diffusion doping is 50-100 Ω. The second mask layer is made of phosphorosilicon glass (PSG), and the thickness of the second mask layer is 30-60nm.

[0082] When the second semiconductor layer is a second polysilicon layer, boron diffusion treatment is performed on the second surface to transform the second polysilicon layer into a second doped polysilicon layer. For example, the sheet resistance after phosphorus diffusion doping is 50-100 Ω. The second mask layer is made of phosphorosilicon glass (PSG), and the thickness of the second mask layer is 30-60nm.

[0083] Step S9: Perform laser scanning on the second non-electrode region of the second surface to modify the second mask layer of the second non-electrode region; In this process, laser scanning is performed on the second non-electrode region. The laser scanning modifies the second mask layer, making it unable to withstand the alkaline etching solution. During subsequent alkaline etching, the modified second mask layer is removed by the etchant. Similarly, the second tunneling oxide layer and the second doped polysilicon layer in the second non-electrode region are also removed by the etchant. Conversely, the second mask layer in the second electrode region remains intact and is not removed during subsequent alkaline etching.

[0084] Step S10: Perform alkaline etching on the second surface to remove the second tunneling oxide layer, the second doped polysilicon layer, and the second mask layer in the second non-electrode region.

[0085] Before alkaline etching of the second side, the first side of the substrate can be facing down, and the second mask layer around the first side can be removed with HF in a chain wet etching apparatus, but the first mask layer covering the area of ​​the first mask layer is not completely removed; then, the second side is alkaline etched in a tank apparatus; then, the remaining first and second mask layers on the first and second sides are removed with HF.

[0086] In some implementations, after step S10, the following steps are further included: Step S11: Form a first passivation anti-reflection layer and a second passivation anti-reflection layer on the first and second surfaces, respectively; Specifically, atomic layer deposition (ALD) is used to deposit a first passivation layer on the first surface and a second passivation layer on the second surface, with the thickness of the first passivation layer being 4-7 nm and the thickness of the second passivation layer being 4-7 nm; plasma enhanced chemical vapor deposition (PECVD) is used to deposit a first antireflection layer on the first surface and a second antireflection layer on the second surface, with the thickness of the first antireflection layer being 60-100 nm and the thickness of the second antireflection layer being 60-100 nm.

[0087] Step S12: In the first electrode region, a first electrode underlayer and a first electrode are formed sequentially; in the second electrode region, a second electrode underlayer and a second electrode are formed sequentially.

[0088] The preparation methods for the first electrode as the underlayer and the second electrode as the underlayer can include one of screen printing, physical vapor deposition (PVD), electroplating or electroless plating, and the preparation methods for the first electrode and the second electrode can include one of screen printing or electroplating.

[0089] In some embodiments, the first passivation layer and the second passivation layer can be fabricated simultaneously, and the first antireflection layer and the second antireflection layer can be fabricated simultaneously.

[0090] One embodiment of this application provides a stacked battery, which includes a top battery, an intermediate connecting layer and a bottom battery, wherein the intermediate connecting layer is connected between the top battery and the bottom battery.

[0091] The top cell is one of a perovskite cell, a cadmium telluride solar cell, a copper indium gallium selenide solar cell, or a gallium arsenide solar cell, and the bottom cell is the aforementioned solar cell 100.

[0092] In some implementations, the interlayer can be a transparent material with a high refractive index. To reduce light reflection and absorption at the interlayer interface and achieve good conductivity to minimize the impact of series resistance on device performance, the interlayer typically needs to have high light transmittance. For example, the interlayer can be a transparent conductive metal oxide thin film (ITO).

[0093] One embodiment of this application provides a photovoltaic module 200. Please refer to [link / reference]. Figure 4 and Figure 5As shown, it includes a battery string 201, an encapsulating film 202, and a cover plate 203. Please refer to [the provided text]. Figure 4 As shown, the battery string 201 is formed by connecting multiple solar cells 100 as described above; the encapsulating film 202 is used to cover the surface of the battery string 201; the cover plate 203 is used to cover the surface of the encapsulating film 202 facing away from the surface of the battery string 201.

[0094] In some embodiments, the battery string 201 may also be formed by connecting multiple stacked batteries as described above.

[0095] In some embodiments, multiple solar cells 100 can be electrically connected to each other by solder ribbon 20, which is connected to each two adjacent solar cells 100. When electrodes are provided on the front and back surfaces of the solar cells 100, the solder ribbon 20 is connected to the front surface of the first solar cell 100 and the back surface of the second solar cell 100 in the two adjacent solar cells 100, respectively. When electrodes are provided only on the back surface of the solar cells 100, the solder ribbon 20 is connected to the back surface of the first solar cell 100 and the back surface of the second solar cell 100 in the two adjacent solar cells 100, respectively.

[0096] In some embodiments, the solar cells 100 may be spaced apart, and during string bonding, the solder strip 20 extends from the front surface of the first solar cell 100 to the gap, passes through the gap, and extends to the back surface of the second solar cell 100.

[0097] In some embodiments, no gap is provided between the solar cells 100, that is, two adjacent solar cells 100 overlap each other.

[0098] In some embodiments, the encapsulating film 202 includes a first encapsulating film and a second encapsulating film. The first encapsulating film covers one of the front or back sides of the solar cell 100, and the second encapsulating film covers the other of the front or back sides of the solar cell 100. Specifically, at least one of the first or second encapsulating film can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene coelastomer (POE) film, or polyethylene terephthalate (PET) film.

[0099] Example 1 The structure of the solar cell in this embodiment 1 is as follows: Figures 1 to 3 As shown, the method for fabricating the solar cell in Example 1 includes the following steps: Step 1-1. An alkaline texturing process is performed on an N-type silicon wafer to form a first pyramidal texturing structure. The first pyramidal texturing structure comprises multiple first pyramids, with an average height of 1.2 μm to 1.5 μm and a density of 200,000 pyramids per square meter. Up to 240,000 / .

[0100] Steps 1-2. A thermal oxide layer is grown on the front side of the silicon wafer to obtain a tunneling oxide layer with a thickness of 1-2 nm. An intrinsic amorphous silicon layer with a thickness of 200-400 nm is then deposited using LPCVD.

[0101] Steps 1-3. Perform high-temperature oxidation on the silicon wafer to form oxide layers with a thickness of 10-30nm on the front and back sides respectively, while the intrinsic amorphous silicon layer on the front side is transformed into an intrinsic polycrystalline silicon layer.

[0102] Steps 1-4. Perform laser scanning on the non-electrode area on the front side to modify the oxide layer in the non-electrode area, making it unable to resist alkaline etching.

[0103] Steps 1-5. The silicon wafer is texturized using an alkaline process, sequentially removing the oxide layer, intrinsic polysilicon, and tunnel oxide layer from the non-electrode area on the front side. A second pyramid textured structure is formed in the non-electrode area on the front side. The second pyramid textured structure comprises multiple second pyramids, with an average height of 1 μm to 1.2 μm and a density of 250,000 pyramids / day. Up to 280,000 / .

[0104] Steps 1-6. Boron diffusion is performed on the silicon wafer to transform the intrinsic polycrystalline silicon layer in the front electrode region into a boron-doped polycrystalline silicon layer. At the same time, a boron emitter layer is formed in the non-electrode region on the front side. A layer of 50-100nm borosilicate glass (BSG) is formed on the surface of both the electrode region and the non-electrode region on the front side.

[0105] Steps 1-7. With the silicon wafer facing up, remove the oxide layer wrapped around the back side using HF in a chain wet process equipment.

[0106] Steps 1-8. Perform alkaline polishing in a tank-type equipment to completely remove the polysilicon layer on the back of the silicon wafer.

[0107] Steps 1-9. A thermal oxide layer is grown on the back side of the silicon wafer to obtain a tunneling oxide layer with a thickness of 1-2 nm. Then, an intrinsic amorphous silicon layer with a thickness of 100-200 nm is deposited using LPCVD.

[0108] Steps 1-10. Phosphorus diffusion is performed on the back side of the silicon wafer to transform the intrinsic polycrystalline silicon layer in the electrode and non-electrode regions into a phosphorus-doped polycrystalline silicon layer. A layer of phosphosilicate glass (PSG) is formed on the surface of both the electrode and non-electrode regions on the back side. The sheet resistance of the phosphorus diffusion layer is 50-100 Ω·cm. .

[0109] Steps 1-11. Perform laser scanning on the non-electrode area on the back side to modify the PSG in the non-electrode area on the back side, making it unable to resist alkaline etching.

[0110] Steps 1-12. With the silicon wafer face down, use HF to remove the PSG wrapped around the front side in a chain wet process equipment, but do not completely remove the BSG from the unwrapped polysilicon or the area covered by BSG (i.e., the front side).

[0111] Steps 1-13. Alkali etching is performed in a tank apparatus to remove the phosphorus-doped polysilicon winding plating on the front side. Subsequently, HF is used to remove residual BSG and PSG on the front and back sides.

[0112] Steps 1-14. Deposit passivation layers on the front and back sides of the silicon wafer using ALD. The passivation layers can be silicon oxide, aluminum oxide, or a combination of both, and the thickness of the passivation layers is 4-7 nm.

[0113] Steps 1-15. Deposit antireflection layers on the front and back sides of the silicon wafer using PECVD. The antireflection layers can be silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof, and the thickness of the antireflection layers is 60-100 nm.

[0114] Steps 1-16. On the front and back electrode areas of the silicon wafer, prepare an electrode underlayer and electrodes. The electrode underlayer and electrodes can have the same or different metal compositions, and the electrode underlayer contains silver. The electrode underlayer can be formed by screen printing, physical vapor deposition (PVD), electroplating, or electroless plating. The electrodes can be formed by screen printing or electroplating.

[0115] Steps 1-17. Perform light injection and laser-assisted sintering on the silicon wafer after electrode formation.

[0116] Comparative Example 1 The structure of the solar cell in Comparative Example 1 is basically the same as that in Example 1, except that the electrode area on the first side (front side) does not have a first passivation contact structure (tunneling oxide layer and boron-doped polycrystalline silicon layer), and both the electrode area and non-electrode area on the first side (front side) are covered with a boron emitter layer.

[0117] Comparative Example 2 The structure of the solar cell in Comparative Example 2 is basically the same as that in Example 1, except that: the electrode area on the first side (front side) does not have a first passivation contact structure (tunneling oxide layer and boron-doped polycrystalline silicon layer), and both the electrode area and non-electrode area on the first side (front side) are covered with a boron emitter layer; the average height of the second pyramid is the same as the average height of the first pyramid, and the density of the second pyramid is the same as the density of the first pyramid.

[0118] The performance of the solar cells in Example 1, Comparative Examples 1 and 2 was compared and tested. The test conditions were as follows: using a pulsed solar simulator, at an ambient temperature of 25°C, AM1.5 atmospheric mass, and a solar irradiance of 1000 W / m², the photoelectric conversion efficiency Eta, fill factor FF, open-circuit voltage Voc, and short-circuit current Isc were measured. The results are shown in Table 1. Table 1. Performance test comparison table of the examples and comparative examples.

[0119] As can be seen, compared with the bifacial TOPCon solar cells in Comparative Examples 1 and 2, the bifacial TOPCon solar cell provided in Example 1 has improved electrical performance such as photoelectric conversion efficiency Eta, fill factor FF, open-circuit voltage Voc, and short-circuit current Jsc.

[0120] The above description is merely an embodiment of this application. It should be noted that those skilled in the art can make improvements without departing from the inventive concept of this application, but these improvements all fall within the protection scope of this application.

Claims

1. A solar cell, characterized in that, include: The substrate includes a first surface and a second surface disposed opposite to each other along its thickness direction. The first surface includes a first electrode region and a first non-electrode region disposed alternately along a first direction. The second surface includes a second electrode region and a second non-electrode region disposed alternately along a first direction. The first surface has a textured surface structure, and the second surface has a polished surface structure. Each first electrode region and the corresponding second electrode region are aligned along the thickness direction. An emitter layer is provided in the first non-electrode region; A first passivation contact structure is provided in the first electrode region, the first passivation contact structure comprising a first tunneling oxide layer and a first doped polysilicon layer sequentially stacked on the first surface, wherein the conductivity type of the substrate is opposite to that of the first doped polysilicon layer; and, A second passivation contact structure is provided in the second electrode region. The second passivation contact structure includes a second tunneling oxide layer and a second doped polysilicon layer sequentially stacked on the second surface. The conductivity type of the substrate is the same as that of the second doped polysilicon layer. The ratio of the sum of the widths of the first electrode region along the first direction to the width of the first surface along the first direction is 2 to 10:

100.

2. The solar cell according to claim 1, characterized in that, The ratio of the sum of the widths of the second electrode region along the first direction to the width of the second surface along the first direction is 1 to 10:

100.

3. The solar cell according to claim 1, characterized in that, The first non-electrode region is a first groove structure, which includes a first groove bottom surface formed by the substrate recessed along the thickness direction and a first groove sidewall connecting the first electrode region and the first groove bottom surface. The emitter layer covers the first groove bottom surface and the first groove sidewall respectively.

4. The solar cell according to claim 1, characterized in that, The velvet structure includes a first pyramid velvet structure formed in the first electrode region and a second pyramid velvet structure formed in the first non-electrode region. The first pyramid velvet structure includes a first pyramid, and the second pyramid velvet structure includes a second pyramid. The height of the first pyramid is greater than the height of the second pyramid, and the density of the first pyramid is less than the density of the second pyramid.

5. The solar cell according to claim 1, characterized in that, The solar cell further includes a first electrode substrate connected to the first passivation contact structure, a first electrode stacked on the first electrode substrate, a second electrode substrate connected to the second passivation contact structure, and a second electrode stacked on the second electrode substrate.

6. The solar cell according to claim 5, characterized in that, The first electrode substrate and at least the first electrode substrate of the first electrode include metallic silver, and the second electrode substrate and at least the second electrode substrate of the second electrode include metallic silver.

7. The solar cell according to claim 6, characterized in that, The width of the first electrode underlay along the first direction is less than the width of the first electrode along the first direction; the width of the second electrode underlay along the first direction is less than the width of the second electrode along the first direction.

8. The solar cell according to claim 7, characterized in that, Each first electrode underlayer and its corresponding second electrode underlayer are aligned along the thickness direction.

9. The solar cell according to any one of claims 4 to 8, characterized in that, The solar cell further includes a first passivation and antireflection layer disposed on the first surface and a second passivation and antireflection layer disposed on the second surface. The first electrode bottom layer penetrates the first passivation and antireflection layer and forms an electrical contact with the first passivation contact structure. The second electrode bottom layer penetrates the second passivation and antireflection layer and forms an electrical contact with the second passivation contact structure.

10. A method for preparing a solar cell, characterized in that, include: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other along its thickness direction, the first surface including a first electrode region and a first non-electrode region disposed alternately along a first direction, the second surface including a second electrode region and a second non-electrode region disposed alternately along the first direction, each first electrode region and the corresponding second electrode region being aligned along the thickness direction, and the ratio of the sum of the widths of the first electrode regions along the first direction to the width of the first surface along the first direction being 2 to 10:100; A first surface having a first pyramidal textured surface is subjected to thermal oxidation to form a first tunneling oxide layer, and a first semiconductor layer is deposited on the first tunneling oxide layer, wherein the first semiconductor layer includes a first polycrystalline silicon layer or a first amorphous silicon layer. The substrate is subjected to high-temperature oxidation treatment to form an oxide layer on the first surface, wherein the first semiconductor layer after high-temperature oxidation treatment is a first polycrystalline silicon layer; Laser scanning is performed on the first non-electrode region of the first surface to modify the oxide layer in the first non-electrode region; The first surface is subjected to alkaline texturing treatment to remove the first tunneling oxide layer, the first polysilicon layer and the oxide layer in the first non-electrode region, and to form a second pyramid texturing structure in the first non-electrode region. The first surface is subjected to boron diffusion treatment to transform the first polysilicon layer in the first electrode region into a first doped polysilicon layer, and an emitter layer is formed in the first non-electrode region. A first mask layer is formed on the side of the first doped polysilicon layer away from the first tunneling oxide layer and on the side of the emitter layer away from the substrate. The second surface of the substrate is polished, and the polished second surface is thermally oxidized to form a second tunneling oxide layer. A second semiconductor layer is deposited on the second tunneling oxide layer, wherein the second semiconductor layer includes a second polycrystalline silicon layer or a second amorphous silicon layer. The second semiconductor layer is subjected to phosphorus diffusion treatment to transform the second semiconductor layer on the second surface into a second doped polysilicon layer, and a second mask layer is formed on the side of the second doped polysilicon layer away from the second tunneling oxide layer. Laser scanning is performed on the second non-electrode region of the second surface to modify the second mask layer of the second non-electrode region; The second surface is subjected to alkaline etching to remove the second tunneling oxide layer, the second doped polysilicon layer, and the second mask layer in the second non-electrode region.

11. A stacked battery, characterized in that, include: Top cell, which can be a perovskite cell, cadmium telluride solar cell, copper indium gallium selenide solar cell, or gallium arsenide solar cell; Intermediate connection layer; and The base cell is the solar cell according to any one of claims 1 to 9; The top battery, the intermediate connecting layer, and the bottom battery are stacked and connected.

12. A photovoltaic module, characterized in that, Includes the solar cell according to any one of claims 1 to 9, or the tandem cell according to claim 11.

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