Silicon-based inp substrate and method of making the same

Abstract

This invention discloses a silicon-based InP substrate and its fabrication method. The silicon-based InP substrate includes a silicon substrate, multiple strain buffer layers sequentially stacked on the silicon substrate, and an InP capping layer stacked on top of the multiple strain buffer layers. Each strain buffer layer includes multiple dislocation filtering layers and an InP spacer layer, with the InP spacer layer stacked on the top surface of the multiple dislocation filtering layers. Each dislocation filtering layer includes InAs quantum dots grown using a droplet epitaxy process and an InP capping layer stacked on the InAs quantum dots. The areal density of the InAs quantum dots is 1 × 10⁻⁶. 6 cm ‑2 ~1×10 9 cm ‑2 The InP capping layer coats InAs quantum dots. In this scheme, the dislocation filtering layer can effectively eliminate dislocations and defects caused by lattice mismatch between the silicon substrate and group III-V materials, thereby obtaining a high-quality InP film on the silicon substrate.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic device fabrication and on-chip integration technology, and particularly to a silicon-based InP substrate and its fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and large-scale modeling technologies, there is an urgent need for communication networks with high transmission rates, high bandwidth, low power consumption, and low cost. To address this application scenario, silicon-based optoelectronics technology, which integrates lasers, modulators, and photodetectors on a silicon substrate, is considered a revolutionary solution for building such high-quality communication network systems. Although silicon-based optoelectronics technology has significant advantages, its development is severely hampered by problems such as differences in chemical polarity, lattice mismatch, and thermal expansion coefficient mismatch between silicon substrates and optoelectronic devices made of group III-V materials.

[0003] Currently, several advanced engineering technologies have driven the development of silicon-based optoelectronics, including heterobonding, microtransfer printing, lateral epitaxy, quantum dot technology, and patterned substrate technology. However, these technologies also face challenges in manufacturing processes, cost and yield control, and process compatibility. Therefore, obtaining high-quality III-V functional materials on silicon substrates, especially fabricating low-defect, high-crystal-quality silicon-based InP substrates, has become a critical technical issue that urgently needs to be addressed to develop high-performance silicon-based optoelectronic devices and achieve large-scale optoelectronic integration. Summary of the Invention

[0004] To address the aforementioned technical bottlenecks, this invention discloses a silicon-based InP substrate and its preparation method. A novel strain buffer layer is grown on the silicon substrate using droplet epitaxy technology, thereby obtaining a high-quality InP thin film on the silicon substrate.

[0005] This disclosure provides a silicon-based InP substrate, comprising:

[0006] silicon substrate,

[0007] Multiple strain buffer layers are stacked sequentially on the silicon substrate;

[0008] InP capping layer, stacked on the top surface of multiple strain buffer layers;

[0009] Each strain buffer layer comprises multiple dislocation filtering layers and an InP spacer layer, with the InP spacer layer stacked on the top surface of the multiple dislocation filtering layers; each dislocation filtering layer comprises InAs quantum dots grown using droplet epitaxy and an InP capping layer stacked on the InAs quantum dots, wherein the areal density of the InAs quantum dots is 1×10⁻⁶. 6 cm -2 ~1×10 9 cm-2 The InP capping layer covers the InAs quantum dots.

[0010] Optionally, the number of strain buffer layers is N, and the number of dislocation filter layers is M, where N and M are each independently selected from integers from 3 to 10, and N and M may be equal or unequal.

[0011] Optionally, the thickness of the InAs quantum dot is 1.5~10nm, the thickness of the InP capping layer is 5~20nm, the thickness of the InP spacer layer is 50~200nm, and the thickness of the InP capping layer is 100~300nm.

[0012] Optionally, the thickness of the silicon substrate is 250~750μm; the doping type is N-type, P-type or high-resistivity.

[0013] This disclosure also provides a method for preparing a silicon-based InP substrate, the method comprising the following steps:

[0014] S1, Provide silicon substrate;

[0015] S2. InAs quantum dots are grown on the surface of a silicon substrate using droplet epitaxy. An InP capping layer is then grown on the surface of the InAs quantum dots to cover them. The InAs quantum dots and the InP capping layer together form a dislocation filtering layer. The areal density of the InAs quantum dots is 1 × 10⁻⁶. 6 cm -2 ~1×10 9 cm -2 ;

[0016] S3. Repeat step S2 to form multiple dislocation filter layers in sequence from bottom to top on the silicon substrate, and deposit an InP spacer layer on the top surface of the multiple dislocation filter layers. The multiple dislocation filter layers and the InP spacer layer together form a strain buffer layer.

[0017] S4. Repeat step S3 to form multiple strain buffer layers in sequence from bottom to top on the silicon substrate;

[0018] S5. An InP capping layer is epitaxially grown on the top surface of multiple strain buffer layers to obtain a silicon-based InP composite substrate.

[0019] Optionally, the number of strain buffer layers is N, and the number of dislocation filter layers is M, where N and M are each independently selected from integers from 3 to 10, and N and M may be equal or unequal.

[0020] Optionally, step S1 includes: removing the silicon oxide layer on the surface of the silicon substrate, and then placing the silicon substrate in a metal-organic chemical vapor deposition apparatus and baking it in a hydrogen atmosphere at 700~1300°C for 5~30 minutes.

[0021] Optionally, step S2 specifically includes:

[0022] S21. Cool the silicon substrate to 320~450℃, control the flow rate of TMIn to 0.5~20μmol / min, and perform In droplet deposition for 5~120s.

[0023] S22. Cut off all source gas to interrupt growth for 5-160 seconds;

[0024] S23. Heat the silicon substrate to 480~600℃ at a heating rate of 0.1~2.5℃ / s; during the heating process, introduce AsH3 with a flow rate of 5~60μmol / min into the growth chamber. After the temperature reaches 480~600℃, maintain it for 1~30min to allow As atoms to fully enter the In droplets and crystallize to form InAs quantum dots.

[0025] S24. Maintain a constant temperature within the range of 480℃ to 600℃, and epitaxially grow an InP capping layer on the surface of the InAs quantum dot, wherein the thickness of the InP capping layer is 5 to 20 nm.

[0026] Optionally, step S3 includes: maintaining a constant temperature within a temperature range of 480℃ to 600℃, controlling the flow rate of TMIn to 10-50 μmol / min and the flow rate of PH3 to 3-25 mmol / min, and depositing an InP spacer layer with a thickness of 50-200 nm on the surface of the topmost dislocation filter layer.

[0027] Optionally, step S5 includes: raising the temperature to 600-700℃ and epitaxially growing an InP capping layer on the top surface of the N strain buffer layers, wherein the thickness of the InP capping layer is 100-300nm.

[0028] The beneficial effects of this invention are:

[0029] 1. This scheme uses InAs quantum dots and an InP capping layer to form a dislocation filtering layer. Since InAs quantum dots are insensitive to lattice mismatch between materials, the dislocation filtering layer can effectively eliminate dislocations and defects caused by lattice mismatch between the silicon substrate and group III-V materials. By repeating the dislocation filtering layer for multiple periods and separating it with InP spacers, the multi-layer repeating structure can amplify the dislocation suppression effect, thereby maximizing the prevention of bottom dislocation defects from propagating upwards to the top layer.

[0030] 2. This scheme innovatively adopts a droplet-epitaxial InAs quantum dot-InP coated composite structure as the core dislocation filtering layer. This structure has excellent dislocation and defect filtering capabilities, and can achieve a high-quality transition from silicon substrate to III-V materials under thin conditions with a total epitaxial growth thickness of only about 1 μm, which is very beneficial for subsequent optoelectronic integration.

[0031] 3. Traditional III-V materials are prone to reverse domain defects when directly epitaxially deposited on silicon. This invention employs a sequential deposition strategy of "first depositing III-V In, then introducing V-V As to achieve crystallization," which can effectively suppress the formation of reverse domains.

[0032] 4. Compared to InP substrates, silicon substrates have a more mature manufacturing process and can be fabricated to larger sizes. This solution, using silicon substrates as the base material to fabricate silicon-based InP substrates, has enormous potential in terms of saving raw materials and expanding wafer size. This also provides a solid foundation for the large-scale integration and industrial application of InP-based devices.

[0033] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0034] The disclosure of this invention will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this invention. Furthermore, similar numbers in the drawings are used to denote similar components, wherein:

[0035] Figure 1 This is a schematic diagram of the silicon-based InP substrate provided by the present invention.

[0036] Figure 2 This is a flowchart of the method for preparing a silicon-based InP substrate provided by the present invention.

[0037] Figure 3 This is a schematic diagram of the fabrication process of the silicon-based InP substrate provided by the present invention.

[0038] In the figure: 1-Silicon substrate, 3-InP capping layer, 21-InAs quantum dot, 22-InP capping layer, 23-InP spacer layer. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0041] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0042] In the description of this invention, it should be noted that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the workpiece of this invention is in use. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0043] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0044] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0045] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0046] This disclosure provides a silicon-based InP substrate that effectively solves the lattice mismatch problem between silicon substrates and group III-V materials. Please refer to... Figure 1 The silicon-based InP substrate includes a silicon substrate 1, N strain buffer layers, and an InP capping layer 3. The N strain buffer layers are stacked sequentially on the silicon substrate 1, and the InP capping layer 3 is stacked on the top surface of the N strain buffer layers. Each strain buffer layer includes M dislocation filtering layers and an InP spacer layer 23, with the InP spacer layer 23 stacked on the top surface of the M dislocation filtering layers. N and M are both integers selected from 3 to 10, and their values ​​can be the same or different. For example, the value of N can be 3, 4, 6, 7, or 10, and the value of M can be 3, 5, 8, 9, or 10.

[0047] The silicon substrate 1 has a crystal orientation of 001 and a bevel angle of 4°; its size ranges from 2 to 12 inches; its thickness is 250 to 750 μm; and its doping types cover N-type, P-type, and high-resistivity. Compared to InP substrates, the silicon substrate 1 has a more mature manufacturing process and can be fabricated to larger sizes. Silicon-based InP substrates, fabricated using silicon substrates as the base material, have enormous potential in terms of saving raw materials and expanding wafer size.

[0048] For example, the thickness of the silicon substrate 1 can be 250 μm, 300 μm, 550 μm, 610 μm, or 750 μm, but is not limited thereto.

[0049] Each dislocation filtering layer includes InAs quantum dots 21 grown using droplet epitaxy and an InP capping layer 22 stacked on the InAs quantum dots 21. The InP capping layer 22 covers the InAs quantum dots 21, and the areal density of the InAs quantum dots 21 is 1×10⁻⁶.6 cm -2 ~1×10 9 cm -2 The thickness of InAs quantum dots 21 is 1.5–10 nm, and the thickness of InP capping layer 22 is 5–20 nm. This scheme uses InAs quantum dots 21 and InP capping layer 22 to form a dislocation filtering layer. Since InAs quantum dots 21 are insensitive to lattice mismatch between materials, they can alleviate strain accumulation caused by lattice mismatch during heteroepitaxial growth through a local strain release mechanism, thus relieving interfacial stress. Simultaneously, the InP capping layer 22 encapsulates and constrains the InAs quantum dots, smoothing the epitaxial surface and providing spatial support for the subsequently grown InAs quantum dots 21. These two elements complement each other, effectively eliminating dislocations and defects caused by lattice mismatch between the silicon substrate 1 and group III-V materials, while avoiding reverse domain problems. Furthermore, the InAs quantum dots 21 grown using droplet epitaxy exhibit substrate non-selectivity, which has a natural compatibility with the silicon substrate 1.

[0050] For example, the thickness of InAs quantum dot 21 can be 1.5nm, 3nm, 6nm, 9.5nm, or 10nm, but is not limited to these.

[0051] For example, the thickness of the InP capping layer 22 can be 5nm, 9nm, 15nm, 17nm, or 20nm, but is not limited thereto.

[0052] The strain buffer layer consists of multiple dislocation filtering layers and an InP spacer layer 23, the thickness of which is 50~200nm. The strain buffer layer has 3-10 periods.

[0053] For example, the thickness of the InP spacer layer 23 can be 50nm, 99nm, 100nm, 180nm, or 200nm, but is not limited thereto.

[0054] After the growth of the multilayer dislocation filter layer, a thick InP spacer layer is deposited, which can provide sufficient bending and slip space for dislocations that are conducted from the bottom, causing dislocations to annihilate or change direction, reducing the probability of dislocations directly penetrating to subsequent dislocation filter layers, thereby enhancing the dislocation filtering effect. In addition, the InP spacer layer can also improve crystal quality and inhibit the continuous accumulation of surface roughness.

[0055] This scheme employs a multi-cycle dislocation filtering layer separated by InP spacer layers 23. This multi-layered, repeating structure amplifies the dislocation suppression effect. The InP spacer layers provide ample bending and slip space for dislocations propagating from the bottom, promoting annihilation or redirection and reducing the probability of dislocations directly penetrating to subsequent dislocation filtering layers. The combination of these two elements enhances the dislocation filtering effect, maximizing the prevention of bottom dislocation defects from propagating upwards to the top layer. Furthermore, the InP spacer layers improve crystal quality and suppress the continuous accumulation of surface roughness.

[0056] The InP capping layer 3 has a thickness of 100~300nm. The InP capping layer 3 is grown at high temperature and has high lattice quality, and is used as the upper surface of the silicon-based InP substrate.

[0057] For example, the thickness of the InP capping layer 3 can be 100nm, 150nm, 190nm, 250nm, or 300nm, but is not limited to these.

[0058] In this embodiment, the dislocation filtering layer and the strain buffer layer are designed as a multi-period nested stacked structure, so that the total epitaxial growth thickness on the silicon substrate is about 1μm. This achieves efficient elimination of dislocations and defects with a very thin growth thickness, which is different from the traditional large-thickness buffer layer scheme. This is very beneficial for subsequent optoelectronic integration.

[0059] This disclosure also provides a method for preparing a silicon-based InP substrate, for which the above-mentioned silicon-based InP substrate is prepared. Please refer to [link to relevant documentation]. Figure 2 The method includes steps S1 to S5.

[0060] S1, Provide silicon substrate 1.

[0061] In one possible implementation, step S1 may include: removing the silicon oxide layer on the surface of the silicon substrate 1; subsequently placing the silicon substrate 1 in a metal-organic chemical vapor deposition (MOCVD) apparatus and baking it in a hydrogen atmosphere at 700–1300°C for 5–30 minutes. The native silicon oxide layer on the surface of the silicon substrate 1 can be removed using an aqueous hydrofluoric acid solution or a buffered hydrofluoric acid (BOE) solution; after treatment, the substrate is then placed in the MOCVD chamber to prevent re-oxidation of the surface.

[0062] S2. InAs quantum dots 21 are grown on the surface of silicon substrate 1 using droplet epitaxy, and an InP capping layer 22 is grown on the surface of the InAs quantum dots 21 to cover them. The InAs quantum dots 21 and the InP capping layer 22 together form a dislocation filtering layer. The areal density of the InAs quantum dots 21 is 1×10⁻⁶. 6 cm -2 ~1×10 9 cm -2 .

[0063] In one possible implementation, step S2 specifically includes:

[0064] S21. Cool the silicon substrate 1 to 320~450℃, control the flow rate of TMIn to 0.5~20μmol / min, and perform In droplet deposition for 5~120s.

[0065] S22. Cut off all source gas and interrupt growth for 5-160 seconds to allow In droplets to reach a thermodynamically stable state and reduce the size dispersion of In droplets.

[0066] S23. The silicon substrate 1 is heated to 480~600℃ at a heating rate of 0.1~2.5℃ / s. During the heating process, AsH3 with a flow rate of 5~60μmol / min is introduced into the growth chamber. After the temperature reaches 480~600℃, it is maintained for 1~30min to allow As atoms to fully enter the In droplets and crystallize to form InAs quantum dots 21.

[0067] S24. Maintaining a constant growth temperature within the range of 480℃ to 600℃, an InP capping layer 22 is epitaxially grown on the surface of InAs quantum dots 21. The thickness of the InP capping layer 22 is 5–20 nm. The InP capping layer 22 and InAs quantum dots 21 form a whole, used to block and filter dislocations and defects at the bottom. There is a synergistic regulatory relationship between InAs quantum dots 21 and the InP capping layer: InAs quantum dots 21 alleviate strain accumulation caused by lattice mismatch during heteroepitaxialization through a local strain release mechanism, relieving interfacial stress. At the same time, the InP capping layer 22 provides encapsulation and constraint for the InAs quantum dots, smooths the epitaxial surface, and provides spatial support for the subsequently grown InAs quantum dots 21. The two complement each other to achieve efficient dislocation-defect filtering.

[0068] S3. Repeat step S2 to stack M dislocation filter layers on silicon substrate 1, and deposit an InP spacer layer 23 on the top surface of the M dislocation filter layers. The M dislocation filter layers and the InP spacer layer 23 together form a strain buffer layer. M is selected from an integer from 3 to 10.

[0069] The step of depositing an InP spacer layer 23 on the top surface of the M dislocation filter layers specifically includes: maintaining a constant temperature within the temperature range of 480℃ to 600℃, controlling the flow rate of TMIn to 10-50 μmol / min and the flow rate of PH3 to 3-25 mmol / min, and depositing an InP spacer layer 23 with a thickness of 50-200 nm on the top surface of the M dislocation filter layers.

[0070] This disclosure describes the deposition of a thick InP spacer layer after the growth of a multilayer dislocation filter layer. This provides sufficient bending and slip space for dislocations propagating from the bottom, causing dislocations to annihilate or deflect, reducing the probability of dislocations directly penetrating to subsequent dislocation filter layers, thereby enhancing the dislocation filtering effect. In addition, the InP spacer layer can also improve crystal quality and suppress the continuous accumulation of surface roughness.

[0071] S4. Repeat step S3 to form N strain buffer layers on the silicon substrate 1 from bottom to top. N is selected from an integer from 3 to 10.

[0072] By constructing a single strain buffer layer using an M-layer dislocation filter layer and an InP spacer layer 23, and then stacking N strain buffer layers to increase the number of InAs quantum dots 21 and InP layers, the accumulated strain can be released in layers, thereby enhancing its effect of blocking and filtering dislocations.

[0073] S5. An InP capping layer 3 is epitaxially grown on the top surface of N strain buffer layers to obtain a silicon-based InP composite substrate.

[0074] In one possible implementation, step S5 specifically includes: raising the growth temperature to 600-700℃, and epitaxially growing an InP capping layer 3 on the top surface of the N strain buffer layers, wherein the thickness of the InP capping layer 3 is 100~300nm.

[0075] The following will provide further details with reference to specific embodiments.

[0076] Please see Figure 3 The present invention discloses a method for preparing a silicon-based InP substrate, which specifically includes the following steps:

[0077] Step 1: Pretreatment of silicon substrate 1. A 2-inch N-type (001) crystal orientation silicon substrate 1 with a 4° bevel angle and a thickness of 400 μm was selected. The silicon substrate 1 was immersed in a 25% (w / w) dilute hydrofluoric acid solution and left to stand for 30 seconds to remove the silicon oxide layer on the surface of the silicon substrate 1; then the silicon substrate 1 was transferred to the MOCVD equipment and baked at 900°C in a hydrogen atmosphere for 10 minutes.

[0078] Step 2: Deposit In droplets. Cool the silicon substrate 1 to 340℃, control the TMIn source flow rate to 2.67 μmol / min, and deposit In droplets for 35 s. After deposition, cut off all source gas and perform a 25 s growth interruption process to allow the In droplets to reach a thermodynamically stable state and reduce the size dispersion of the In droplets.

[0079] Step 3: Crystallization to form InAs quantum dots 21. After completing step 2, the substrate is heated to 520°C at a heating rate of 0.75°C / s; during the heating process, AsH3 is introduced into the growth chamber at a flow rate of 26 μmol / min; after the temperature reaches 520°C, it is held for 5 min to allow As atoms to diffuse into the In droplets, thus obtaining fully crystallized InAs quantum dots 21.

[0080] Step 4: Grow the InP capping layer 22. Maintain a constant temperature of 520°C and epitaxially grow an InP capping layer 22 with a thickness of 10 nm on the InAs quantum dot 21. The InP capping layer 22 covers the InAs quantum dot 21, and the InAs quantum dot 21 and the InP capping layer 22 together constitute a single-layer dislocation filtering layer (InAs / InP layer) to block and filter dislocations and defects from the silicon substrate 1 side.

[0081] Step 5: Prepare a multi-period dislocation filter layer. Repeat steps 2 to 4 five times to obtain a five-period stacked InAs / InP layer. By increasing the number of dislocation filter layers, the structure's blocking and filtering effect on dislocations and defects is enhanced.

[0082] Step 6: Fabrication of a multi-stage strain buffer layer. After completing Step 5, under constant temperature of 500℃, TMIn flow rate of 30 μmol / min, and PH3 flow rate of 15 mmol / min, an InP spacer layer 23 with a thickness of 120 nm is grown on the top surface of the above 5-cycle InAs / InP layer; the 5-cycle InAs / InP layer and the InP spacer layer 23 together form a strain buffer layer (InP / (InAs / InP) layer); the strain buffer layer is stacked repeatedly for 5 cycles.

[0083] Step 7: Growth of InP capping layer 3. After completing the stacking of the 5-cycle strain buffer layer, the dislocations and defects caused by lattice mismatch have been controlled within an acceptable range. To further improve the surface crystal quality of the silicon-based InP substrate, the growth temperature was increased to 640℃, and a high-quality InP capping layer 3 with a thickness of 300 nm was epitaxially grown on the top surface of the 5-cycle strain buffer layer. This InP capping layer 3 serves as the upper surface of the silicon-based InP substrate.

[0084] The silicon-based InP substrates prepared by the above-mentioned complete process have surface quality that can reach the level of commercial InP substrates, and can directly meet the epitaxial growth requirements of various InP-based optoelectronic devices.

[0085] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A silicon-based InP substrate, characterized in that, include: silicon substrate, Multiple strain buffer layers are stacked sequentially on the silicon substrate; InP capping layer, stacked on the top surface of multiple strain buffer layers; Each strain buffer layer comprises multiple dislocation filtering layers and an InP spacer layer, with the InP spacer layer stacked on the top surface of the multiple dislocation filtering layers; each dislocation filtering layer comprises InAs quantum dots grown using droplet epitaxy and an InP capping layer stacked on the InAs quantum dots, with an areal density of 1×10⁻⁶. 6 cm -2 ~1×10 9 cm -2 InP capping layer covers InAs quantum dots.

2. The silicon-based InP substrate according to claim 1, characterized in that, The number of strain buffer layers is N, and the number of dislocation filter layers is M. N and M are each independently selected from integers from 3 to 10. N and M can be equal or unequal.

3. The silicon-based InP substrate according to claim 1, characterized in that, The thickness of the InAs quantum dots is 1.5~10nm; the thickness of the InP capping layer is 5~20nm; the thickness of the InP spacer layer is 50~200nm; and the thickness of the InP capping layer is 100~300nm.

4. The silicon-based InP substrate according to claim 1, characterized in that, The thickness of the silicon substrate is 250~750μm; the doping type is N-type, P-type or high-resistivity.

5. A method for preparing a silicon-based InP substrate, used to prepare the silicon-based InP substrate according to any one of claims 1 to 4, characterized in that, The method includes the following steps: S1, Provide silicon substrate; S2. InAs quantum dots are grown on the surface of a silicon substrate using droplet epitaxy. An InP capping layer is then grown on the surface of the InAs quantum dots to cover them. The InAs quantum dots and the InP capping layer together form a dislocation filtering layer. The areal density of the InAs quantum dots is 1 × 10⁻⁶. 6 cm -2 ~1×10 9 cm -2 ; S3. Repeat step S2 to form multiple dislocation filter layers in sequence from bottom to top on the silicon substrate, and deposit an InP spacer layer on the top surface of the multiple dislocation filter layers. The multiple dislocation filter layers and the InP spacer layer together form a strain buffer layer. S4. Repeat step S3 to form multiple strain buffer layers in sequence from bottom to top on the silicon substrate; S5. An InP capping layer is epitaxially grown on the top surface of multiple strain buffer layers to obtain a silicon-based InP composite substrate.

6. The method for preparing a silicon-based InP substrate according to claim 5, characterized in that, The number of strain buffer layers is N, and the number of dislocation filter layers is M. N and M are each independently selected from integers from 3 to 10. N and M can be equal or unequal.

7. The method for preparing a silicon-based InP substrate according to claim 5, characterized in that, Step S1 includes: removing the silicon oxide layer on the surface of the silicon substrate, and then placing the silicon substrate in a metal-organic chemical vapor deposition apparatus and baking it in a hydrogen atmosphere at 700~1300°C for 5~30 minutes.

8. The method for preparing a silicon-based InP substrate according to claim 5, characterized in that, Step S2 includes: S21. Cool the silicon substrate to 320~450℃, control the flow rate of TMIn to 0.5~20μmol / min, and perform In droplet deposition for 5~120s. S22. Cut off all source gas to interrupt growth for 5-160 seconds; S23. Heat the silicon substrate to 480~600℃ at a heating rate of 0.1~2.5℃ / s; during the heating process, introduce AsH3 with a flow rate of 5~60μmol / min into the growth chamber. After the temperature reaches 480~600℃, maintain it for 1~30min to allow As atoms to enter the In droplets and crystallize to form InAs quantum dots. S24. Maintain a constant temperature within the range of 480℃ to 600℃, and epitaxially grow an InP capping layer on the surface of the InAs quantum dot, wherein the thickness of the InP capping layer is 5 to 20 nm.

9. The method for preparing a silicon-based InP substrate according to claim 5, characterized in that, Step S3 includes: maintaining a constant temperature within the temperature range of 480℃ to 600℃, controlling the flow rate of TMIn to 10-50 μmol / min and the flow rate of PH3 to 3-25 mmol / min, and depositing an InP spacer layer with a thickness of 50-200 nm on the surface of the top dislocation filter layer.

10. The method for preparing a silicon-based InP substrate according to claim 5, characterized in that, Step S5 includes: raising the temperature to 600-700℃ and epitaxially growing an InP capping layer on the top surface of the N strain buffer layers, wherein the thickness of the InP capping layer is 100~300nm.

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