Light emitting diode for optical communication, method of manufacturing the same and light emitting array

Abstract

This disclosure provides a light-emitting diode (LED) for optical communication, its fabrication method, and a light-emitting array, belonging to the field of optoelectronic manufacturing technology. The LED includes an epitaxial layer, a first electrode, and a second electrode. The first and second electrodes are spaced apart on a first surface of the epitaxial layer and are electrically connected to semiconductor layers of different conductivity types on the epitaxial layer. The first and second electrodes are located in two regions farthest apart on the first surface. In a cross-section perpendicular to the first surface, the width of the cross-section farther from the epitaxial layer is greater than the width of the cross-section closer to the epitaxial layer. This disclosure can improve the problem of parasitic capacitance easily forming between pads after LED packaging.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode for optical communication, its fabrication method, and its light-emitting array. Background Technology

[0002] An optical module (optical transceiver module) is a core component in an optical fiber communication system. An optical module consists of an optical transmitter and an optical receiver, both connected to the optical fiber via their respective optical interfaces. The optical transmitter performs electro-optical conversion and includes a light-emitting array and a control chip. The control chip generates and modulates electrical signals to drive the light-emitting array, generating an optical signal. The optical receiver converts the optical signal from the optical fiber into an electrical signal and amplifies it.

[0003] In related technologies, light-emitting arrays typically include multiple arrays of micro light-emitting diodes (Micro LEDs), with each Micro LED chip electrically connected to a complementary metal-oxide-semiconductor (CMOS) driving substrate. Utilizing hundreds of parallel, low-speed optical channels, the light-emitting array employs a wide and slow parallel architecture to achieve optical interconnection, trading extremely low single-channel power consumption for high system-level bandwidth and low energy consumption.

[0004] For flip-chip Micro LED chips, they are directly bonded to the driver substrate via pads. When a large number of Micro LED chips are co-packaged on the driver substrate, the spacing between adjacent pads is compressed to the micrometer level, which can easily lead to parasitic capacitance, affecting the bandwidth of a single chip and thus reducing the transmission rate. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) for optical communication, its fabrication method, and a light-emitting array, which can improve the problem of parasitic capacitance easily forming between pads after LED packaging. The technical solution is as follows: This disclosure provides a light-emitting diode (LED) comprising: an epitaxial layer, a first electrode, and a second electrode. The first electrode and the second electrode are spaced apart on a first surface of the epitaxial layer and are electrically connected to semiconductor layers of different conductivity types of the epitaxial layer, respectively. The first electrode and the second electrode are located in two regions farthest apart on the first surface. In a cross-section perpendicular to the first surface, the width of the cross-section of the first electrode and the second electrode farther from the epitaxial layer is greater than the width of the cross-section closer to the epitaxial layer.

[0006] In another implementation of the present disclosure, both the first electrode and the second electrode include a first columnar segment and a second columnar segment, the first columnar segment and the second columnar segment are coaxially connected, the width of the first columnar segment is smaller than the width of the second columnar segment, and the end of the first columnar segment away from the second columnar segment is connected to the epitaxial layer.

[0007] In another implementation of the present disclosure, the light-emitting diode further includes a dielectric layer located on the side of the first surface of the epitaxial layer and between the first electrode and the second electrode, and the dielectric layer has a plurality of spaced air cavities.

[0008] In another implementation of the present disclosure, the maximum width of the air cavity is 1 nm to 100 nm.

[0009] In another implementation of the present disclosure, the first surface of the epitaxial layer has a first groove, the first electrode is located in the first groove, the second electrode is located outside the first groove, and the end face of the first electrode away from the epitaxial layer is flush with the end face of the second electrode away from the epitaxial layer.

[0010] In another implementation of this disclosure, the light-emitting diode further includes a first insulating layer and a transparent conductive layer; the transparent conductive layer is located on the first surface and outside the first groove, the first insulating layer is located on the first surface and inside the first groove, and covers the transparent conductive layer, the first insulating layer has vias that expose the bottom of the transparent conductive layer and the first groove respectively; the first electrode and the second electrode are both located on the surface of the first insulating layer away from the epitaxial layer, the first electrode is electrically connected to the semiconductor layer exposed in the first groove through the vias, and the second electrode is electrically connected to the transparent conductive layer through the vias.

[0011] In another implementation of this disclosure, the light-emitting diode further includes a first insulating layer and a transparent conductive layer; the first surface of the epitaxial layer has a first groove and a second groove arranged at intervals, the groove depth of the first groove being the same as the groove depth of the second groove; the first insulating layer is located within the first surface, the first groove, and the second groove, and the first insulating layer has vias that expose the bottom of the first surface and the first groove, respectively; the transparent conductive layer is located on the surface of the first insulating layer away from the epitaxial layer and within the second groove, and the transparent conductive layer is connected to the first surface through the vias; the first electrode is located within the first groove and is electrically connected to the semiconductor layer exposed in the first groove through the vias; the second electrode is located within the second groove and is located on the surface of the transparent conductive layer away from the epitaxial layer.

[0012] This disclosure provides a light-emitting array, which includes a substrate and light-emitting diodes as described above, wherein the array of light-emitting diodes is arranged on the substrate.

[0013] This disclosure provides a light-emitting array in which the orthographic projection of each light-emitting diode on the substrate is rectangular, and the first electrode and the second electrode are respectively located at two opposite corners of the orthographic projection of the rectangle; along the row direction of the substrate, in each light-emitting diode in the same row, the first electrode and the second electrode are located at the same diagonal position; in two adjacent rows of light-emitting diodes, the first electrode and the second electrode are located at opposite diagonal positions, and the light-emitting diodes in two adjacent rows are staggered in the row direction.

[0014] This disclosure provides a method for fabricating a light-emitting diode (LED). The method includes: forming an epitaxial layer on a substrate; forming a first electrode and a second electrode spaced apart on a first surface of the epitaxial layer, wherein the first electrode and the second electrode are electrically connected to semiconductor layers of different conductivity types of the epitaxial layer, the first electrode and the second electrode are located in two regions farthest apart on the first surface, and in a cross-section perpendicular to the first surface, the width of the cross-section farther from the epitaxial layer is greater than the width of the cross-section closer to the epitaxial layer.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: The light-emitting diode provided in this disclosure has its first electrode and second electrode respectively disposed in the two farthest regions on the first surface of the epitaxial layer, thereby maximizing the distance between the two metal electrodes along the first surface within the same light-emitting diode. In scenarios where several to hundreds, or even more, Micro LED chips are co-packaged and the spacing between adjacent pads is compressed to the micrometer level, the larger the distance between the two electrodes, the smaller the parasitic capacitance C between them. The reduction in parasitic capacitance directly weakens the constraint on the single-channel bandwidth of the chip, thereby reducing the loss in transmission rate and helping to maintain high system-level bandwidth and low power consumption in a wide and slow parallel optical interconnect architecture.

[0016] Furthermore, the first and second electrodes exhibit a variable cross-section structure in the direction perpendicular to the first surface, meaning the cross-sectional width farther from the epitaxial layer is greater than the cross-sectional width closer to the epitaxial layer. On the side electrically connected to the driving substrate (farther from the epitaxial layer), the electrode cross-sectional width is larger, resulting in a correspondingly larger electrical connection area. This is beneficial for improving the bonding strength and interconnect reliability between the electrode and the driving substrate, and reducing the risk of bonding failure during co-packaging. On the side connected to the epitaxial layer of the chip (closer to the epitaxial layer), the electrode cross-sectional width is smaller, narrowing the metal connection surface area. This allows for further compression of the spacing between adjacent electrodes, thereby further reducing the parasitic capacitance between adjacent electrodes. Therefore, the aforementioned variable cross-section electrode structure optimizes the high-frequency bandwidth performance of the chip while ensuring the reliability of the co-packaging process. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the hierarchy of a light-emitting diode provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the hierarchy of another light-emitting diode provided in an embodiment of this disclosure; Figure 4 This is a flowchart of a method for fabricating a light-emitting diode according to an embodiment of this disclosure; Figure 5 This is a fabrication state diagram of a light-emitting diode provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of a light-emitting array provided in an embodiment of this disclosure.

[0019] The markings in the diagram are explained as follows: 10. Epitaxial layer; 101. First surface; 11. First groove; 12. Second groove; 21. First electrode; 22. Second electrode; 201. First columnar segment; 202. Second columnar segment; 30. Dielectric layer; 31. Air cavity; 41. First insulating layer; 42. Second insulating layer; 50. Transparent conductive layer; 60. Substrate; 70. Substrate; 80. Light-emitting diode (LED). Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0022] Figure 1 This is a top view of a light-emitting diode provided in an embodiment of this disclosure. Figure 2 This is a schematic diagram of the hierarchy of a light-emitting diode provided in an embodiment of this disclosure. For example... Figure 1 , 2 As shown, the light-emitting diode includes an epitaxial layer 10, a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 are arranged at intervals on the first surface 101 of the epitaxial layer 10, and the first electrode 21 and the second electrode 22 are electrically connected to semiconductor layers of different conductivity types of the epitaxial layer 10, respectively. The first electrode 21 and the second electrode 22 are located in the two regions that are furthest apart on the first surface 101.

[0023] Among them, the two regions that are farthest apart on the first surface 101 refer to the two positions that are the most far apart along the in-plane direction within the plane of the first surface 101.

[0024] For example, in a rectangular or square light-emitting diode, the two points furthest apart on the first surface 101 are the apex regions of the two ends of the diagonal of the rectangle. By placing the first electrode 21 and the second electrode 22 in these two furthest regions respectively, the arrangement of the two electrodes on the first surface 101 is maximized, so that the distance between the centers of the two electrodes in the same light-emitting diode reaches the maximum value on the first surface 101.

[0025] like Figure 2 As shown, in the cross-section of the first electrode 21 and the second electrode 22 in the direction perpendicular to the first surface 101, the width of the cross-section farther from the epitaxial layer 10 is greater than the width of the cross-section closer to the epitaxial layer 10.

[0026] In this embodiment of the disclosure, the direction perpendicular to the first surface 101 is along the thickness direction of the electrode; the cross section in the direction perpendicular to the first surface 101 refers to observing several horizontal cross sections cut at different heights along this vertical thickness direction of the electrode.

[0027] The section closer to the epitaxial layer 10 refers to the section near the first surface 101, that is, the section at the end where the electrode contacts the semiconductor layer of the epitaxial layer 10; the section farther from the epitaxial layer 10 refers to the section away from the first surface 101, that is, the section at the end where the electrode faces the driving substrate.

[0028] In these two horizontal cross-sections at different heights, the cross-sectional width at the end closer to the driving substrate is greater than the cross-sectional width at the end closer to the epitaxial layer 10. That is, the first electrode 21 and the second electrode 22 each have a variable cross-sectional configuration, making the root of the electrode connected to the epitaxial layer 10 narrower, while the free end facing the driving substrate and used for bonding is wider, and the overall shape is stepped.

[0029] The light-emitting diode provided in this embodiment has the first electrode 21 and the second electrode 22 respectively disposed in the two farthest regions on the first surface 101 of the epitaxial layer 10, thereby maximizing the distance between the two metal electrodes along the first surface 101 within the same light-emitting diode. In scenarios where several to hundreds, or even more, Micro LED chips are co-packaged and the spacing between adjacent pads is compressed to the micrometer level, the larger the distance between the two electrodes, the smaller the parasitic capacitance C between them. The reduction in parasitic capacitance directly weakens the constraint on the single-channel bandwidth of the chip, thereby reducing the loss in transmission rate and helping to maintain high system-level bandwidth and low power consumption in a wide and slow parallel optical interconnect architecture.

[0030] Furthermore, the first electrode 21 and the second electrode 22 have a variable cross-section structure in the direction perpendicular to the first surface 101, meaning that the cross-sectional width farther from the epitaxial layer 10 is greater than the cross-sectional width closer to the epitaxial layer 10. On the side electrically connected to the driving substrate (farther from the epitaxial layer 10), the electrode cross-sectional width is larger, and the electrical connection area is correspondingly increased, which is beneficial to improving the bonding strength and interconnect reliability between the electrode and the driving substrate, and reducing the risk of bonding failure during the co-packaging process. On the side connected to the chip epitaxial layer 10 (closer to the epitaxial layer 10), the electrode cross-sectional width is smaller, and the metal connection surface area is narrowed, allowing the spacing between adjacent electrodes to be further compressed, thereby further reducing the parasitic capacitance between adjacent electrodes. Therefore, the above-mentioned variable cross-section electrode structure optimizes the high-frequency bandwidth performance of the chip while ensuring the reliability of the co-packaging process.

[0031] Optionally, the epitaxial layer 10 includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially. One of the first semiconductor layer and the second semiconductor layer is an n-type layer, and the other is a p-type layer.

[0032] In this embodiment of the present disclosure, one electrode is connected to the p-type layer of the epitaxial layer 10, i.e., this electrode is a p electrode. The other electrode is connected to the n-type layer of the epitaxial layer 10, i.e., this electrode is an n electrode.

[0033] For example, the p-type layer includes a p-type AlInP layer.

[0034] The light-emitting layer comprises alternating layers of AlGaInP quantum wells and AlGaInP quantum barriers, wherein the Al content in the AlGaInP quantum wells and AlGaInP quantum barriers differs. The first light-emitting layer may comprise 3 to 8 alternating stacked cycles of AlGaInP quantum wells and AlGaInP quantum barriers.

[0035] The n-type layer includes an n-type AlGaInP current-spreading layer.

[0036] Optionally, such as Figure 2 As shown, both the first electrode 21 and the second electrode 22 include a first columnar segment 201 and a second columnar segment 202. The first columnar segment 201 and the second columnar segment 202 are coaxially connected. The width of the first columnar segment 201 is smaller than the width of the second columnar segment 202. The end of the first columnar segment 201 away from the second columnar segment 202 is connected to the epitaxial layer 10.

[0037] The first electrode 21 and the second electrode 22 each have a two-segment coaxial columnar structure. Each electrode is formed by connecting a thinner segment (i.e., the first columnar segment 201) closer to the epitaxial layer 10 and a thicker segment (i.e., the second columnar segment 202) further away from the epitaxial layer 10 along the same central axis.

[0038] The first columnar segment 201 forms the root of the electrode connected to the semiconductor layer of the epitaxial layer 10. Its cross-sectional size is smaller than that of the second columnar segment 202 above. The two segments are aligned and connected in the axial direction, so that the entire electrode presents a stepped shape that gradually widens from the epitaxial layer 10 towards the driving substrate.

[0039] The first columnar segment 201, closer to the epitaxial layer 10, has a smaller width, which correspondingly narrows the metal surface area connecting the electrode to the epitaxial layer 10. In scenarios where several to hundreds, or even more, Micro LED chips are co-packaged and the spacing between adjacent pads is compressed to the micrometer level, the spacing between adjacent electrodes can be further reduced without increasing coupling. This effectively reduces the parasitic capacitance C within the same chip and between adjacent chips, alleviating the constraint on single-chip bandwidth and mitigating the decrease in transmission rate. Furthermore, the second columnar segment 202, farther from the epitaxial layer 10 and facing the driving substrate, has a larger width, increasing the electrical connection area and bonding contact surface between the electrode and the driving substrate. This is beneficial for improving flip-chip bonding strength and interconnect reliability, and reducing the risk of bonding failure during co-packaging.

[0040] Meanwhile, the two coaxial connections ensure that the electrodes form a continuous conductive path in the thickness direction, and the current smoothly transitions from the epitaxial layer 10 through the thinner root to the thicker bonding end without introducing additional interface contact resistance.

[0041] Optionally, such as Figure 1 , 2 As shown, the light-emitting diode also includes a dielectric layer 30, which is located on the side of the first surface 101 of the epitaxial layer 10 and between the first electrode 21 and the second electrode 22. The dielectric layer 30 has a plurality of spaced air cavities 31.

[0042] The dielectric layer 30 is disposed on the side of the first surface 101 of the epitaxial layer 10, and fills the gap region between the first electrode 21 and the second electrode 22 when viewed from the plane, thereby isolating the two electrodes from each other in the lateral direction. At the same time, multiple air cavities 31 are arranged at intervals along the in-plane direction inside the dielectric layer 30, so that the dielectric layer 30 as a whole presents a composite structure of a solid dielectric substrate containing discrete air cavities 31.

[0043] For example, the dielectric layer 30 may be a silicon oxide layer, that is, a silicon oxide layer is used as an isolation dielectric between the two electrodes.

[0044] Silicon oxide itself is a low dielectric constant material, which can better suppress the electric field coupling formed between the two electrodes through the gap medium, thereby helping to reduce the parasitic capacitance C between the two electrodes within the same core. The multiple air cavities 31 discretely arranged within the dielectric layer 30 further play a role: the dielectric constant of air (about 1.0) is much lower than that of silicon oxide (about 3.9~4.0). The multiple air cavities 31 are distributed between the two electrodes in an alternating manner, which essentially constructs a composite dielectric system of alternating silicon oxide and air in the electrode gap, lowering the effective dielectric constant of the medium between the first electrode 21 and the second electrode 22; the decrease in the effective dielectric constant can reduce the parasitic capacitance between the two electrodes, further weakening the constraint on the single-chip bandwidth and alleviating the decrease in transmission rate.

[0045] Optionally, the maximum width of the air cavity 31 is from 1 nm to 100 nm.

[0046] The maximum width of the air cavity 31 refers to the maximum lateral dimension of the air cavity 31 when each independent air cavity 31 is measured according to its lateral span, that is, the distance between the two farthest points within the same air cavity 31.

[0047] For example, the cross-sectional shape of the air cavity 31 can be circular, elliptical, or irregular. For instance, when the air cavity 31 is circular, the maximum width of the air cavity 31 is equal to the diameter of the air cavity 31.

[0048] A larger air cavity 31 results in a higher volume fraction and a lower equivalent dielectric constant of the dielectric layer 30, which better compresses the parasitic capacitance C between the two electrodes. However, if the width is too large, the effective cross-section of the silicon oxide layer and the continuity of the bonding support will be excessively weakened. Limiting the maximum width to within 100 nm reduces parasitic capacitance while maintaining the structural strength of the silicon oxide dielectric layer 30. Simultaneously, the lower limit of 1 nm ensures that the air cavity 31 can be physically formed.

[0049] Optionally, such as Figure 2 As shown, the first surface 101 of the epitaxial layer 10 has a first groove 11, the first electrode 21 is located inside the first groove 11, the second electrode 22 is located outside the first groove 11, and the end face of the first electrode 21 away from the epitaxial layer 10 is flush with the end face of the second electrode 22 away from the epitaxial layer 10.

[0050] In this design, the light-emitting diode has a first groove 11 recessed into the epitaxial layer 10 on its first surface 101. The first electrode 21 is not directly attached to the flat area of ​​the first surface 101, but is disposed within the first groove 11, thus penetrating a certain depth into the epitaxial layer 10. The second electrode 22 is independently formed on the flat area of ​​the first surface 101 outside the first groove 11. The end face of the first electrode 21 located in the groove, facing the driving substrate, and the end face of the second electrode 22 located on the flat area, also away from the epitaxial layer 10, are on the same plane and flush with each other.

[0051] The first electrode 21 is embedded in the first groove 11 so that it can penetrate downward through the upper semiconductor of the epitaxial layer 10 and contact the buried layer of different conductivity types. Thus, with the two electrodes being disposed on the same side of the first surface 101, they are electrically connected to semiconductor layers of different conductivity types, satisfying the same-surface electrode structure required for flip-chip co-packaging.

[0052] The two electrode bonding faces are flush, allowing both electrodes to bond to the driving substrate simultaneously and at the same height during flip-chip bonding. This avoids bonding tilt, poor soldering, or uneven bonding height caused by one end protruding, improving the bonding yield and interconnect reliability of co-packaged Micro LED chips from several to hundreds. Since the main body of the first electrode 21 is covered and shielded by the epitaxial layer 10 semiconductor of the groove, the lateral electric field coupling between it and the second electrode 22 mainly occurs only between their coplanar top ends, through the dielectric layer 30 between them. The groove structure is equivalent to hiding the main body of the first electrode 21 inside the epitaxial layer 10 with a semiconductor wall, reducing the effective lateral coupling area between the two electrodes, further compressing the parasitic capacitance between the two electrodes within the same chip, and reducing the constraint on the bandwidth of a single chip.

[0053] Optionally, such as Figure 2 As shown, the light-emitting diode also includes a first insulating layer 41 and a transparent conductive layer 50.

[0054] like Figure 2 As shown, the transparent conductive layer 50 is located on the first surface 101 and outside the first groove 11. The first insulating layer 41 is located inside the first surface 101 and the first groove 11 and covers the transparent conductive layer 50. The first insulating layer 41 has through holes that expose the bottom of the grooves of the transparent conductive layer 50 and the first groove 11, respectively.

[0055] like Figure 2 As shown, the first electrode 21 and the second electrode 22 are both located on the surface of the first insulating layer 41 away from the epitaxial layer 10. The first electrode 21 is electrically connected to the semiconductor layer exposed in the first groove 11 through a via, and the second electrode 22 is electrically connected to the transparent conductive layer 50 through a via.

[0056] For example, the first insulating layer 41 may be at least one of a silicon oxide layer, a titanium oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0057] For example, the transparent conductive layer 50 may be an ITO layer or an IZO layer.

[0058] In this embodiment, the transparent conductive layer 50 acts as a lateral current spreading layer. Located on the first surface 101 and outside the first groove 11, the transparent conductive layer 50 directly covers and contacts the upper semiconductor layer on the first surface 101. This allows the current injected by the second electrode 22 to spread uniformly in-plane before reaching the active region, alleviating current congestion near the contact point, improving current injection uniformity and luminous efficiency, and reducing the adverse effects of localized overheating on the modulation bandwidth.

[0059] Secondly, the first insulating layer 41 covers the first surface 101 and the first groove 11, and encapsulates the transparent conductive layer 50 therein. Vias are provided to expose the transparent conductive layer 50 and the bottom of the first groove 11. The first electrode 21 and the second electrode 22 are both formed on the surface of the first insulating layer 41 away from the epitaxial layer 10, and are respectively connected to the bottom semiconductor layer of the groove and the transparent conductive layer 50 via corresponding vias. The first insulating layer 41 provides electrical isolation and reduces coupling capacitance. The insulating layer separates the top electrode metal from the transparent conductive layer 50 and the surface of the epitaxial layer 10, preventing short circuits between the two electrode metals and the underlying conductive structure.

[0060] Figure 3 This is a schematic diagram of the hierarchy of another light-emitting diode provided in an embodiment of this disclosure. For example... Figure 3 As shown, in another implementation, the light-emitting diode also includes a first insulating layer 41 and a transparent conductive layer 50.

[0061] like Figure 3 As shown, the first surface 101 of the epitaxial layer 10 has a first groove 11 and a second groove 12 arranged at intervals, and the groove depth of the first groove 11 is the same as the groove depth of the second groove 12.

[0062] like Figure 3 As shown, the first insulating layer 41 is located in the first surface 101, the first groove 11 and the second groove 12. The first insulating layer 41 has through holes that expose the bottom of the first surface 101 and the first groove 11 respectively. The transparent conductive layer 50 is located on the surface of the first insulating layer 41 away from the epitaxial layer 10 and in the second groove 12. The transparent conductive layer 50 is connected to the first surface 101 through the through holes.

[0063] like Figure 3As shown, the first electrode 21 is located in the first groove 11 and is electrically connected to the semiconductor layer exposed in the first groove 11 through a via. The second electrode 22 is located in the second groove 12 and is located on the surface of the transparent conductive layer 50 away from the epitaxial layer 10.

[0064] For example, the first insulating layer 41 may be at least one of a silicon oxide layer, a titanium oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0065] For example, the transparent conductive layer 50 may be an ITO layer or an IZO layer.

[0066] In this design, the bottom of the first groove 11 exposes a semiconductor layer with a different conductivity type than the upper layer of the first surface 101. The first electrode 21 is electrically connected to the semiconductor in the groove via a corresponding via. In the second groove 12, a transparent conductive layer 50 is connected to the upper semiconductor layer via a via exposed on the first surface 101, and the second electrode 22 rests on the transparent conductive layer 50. Thus, the first electrode 21 and the second electrode 22 are both arranged on the side where the first surface 101 is located, forming a same-surface electrode suitable for flip-chip co-packaging.

[0067] Secondly, the first groove 11 and the second groove 12 are of equal depth and spaced apart, so that both electrodes are embedded in their respective grooves, and their bonding end faces are set to be on the same plane and flush with each other. Compared with the scheme of one electrode in the groove and one electrode standing on the plane, the above implementation uses two grooves of equal depth to align the top faces of the two electrodes. During flip bonding, the two electrodes can contact the driving substrate simultaneously and at the same height, avoiding bonding tilt, poor soldering or uneven bonding height, and improving the bonding yield and interconnection reliability of co-packaging several to hundreds of Micro LED chips.

[0068] The transparent conductive layer 50 is connected to the upper semiconductor through a via exposed on the first surface 101, and spreads laterally along the top surface of the first insulating layer 41 and the second groove 12, so that the current of the second electrode 22 is uniformized before entering the active region, thereby alleviating current congestion and improving injection uniformity and light extraction efficiency.

[0069] The first insulating layer 41 covers the first surface 101 and the double grooves, and forms a relatively flat dielectric plane on the top, making the bonding surface of the arrayed Micro LED flatter and the bonding force more uniform, which facilitates high-precision interconnection with micron-level pad spacing.

[0070] Optionally, such as Figure 3 As shown, the light-emitting diode also includes a second insulating layer 42, which is located on the first insulating layer 41 and the transparent conductive layer 50, and surrounds a portion of the sidewalls of the first electrode 21 and the second electrode 22, and the dielectric layer 30 is located on the surface of the second insulating layer 42 away from the epitaxial layer 10.

[0071] For example, the second insulating layer 42 may be a silicon oxide layer.

[0072] Optionally, the first electrode 21 and the second electrode 22 are hollow structures, and the metal body of the first electrode 21 and / or the second electrode 22 has an opening that penetrates its thickness in the second columnar segment 202.

[0073] For example, the second columnar segment 202 is annular, with the electrode metal closed circumferentially and forming a through cavity in the center.

[0074] For example, the second columnar segment 202 is grid-shaped, and the metal body is divided by intersecting ribs to form multiple regularly arranged grid holes.

[0075] The aforementioned cutout extends through the electrode body in a direction perpendicular to the first surface 101. The opening can be filled by the subsequent dielectric layer 30 or air, while the electrode retains the peripheral or end-face metal area for bonding with the driving substrate. The cutout electrode also provides a stress relief channel inside the electrode, alleviating the concentration of metal thermal stress under co-packaging thermal cycling and improving long-term reliability.

[0076] Figure 4 This is a flowchart illustrating a method for fabricating a light-emitting diode according to an embodiment of this disclosure. Figure 4 As shown, the preparation method includes: Step S11: Form an epitaxial layer 10 on the substrate 60.

[0077] Step S12: Form a first electrode 21 and a second electrode 22 spaced apart on the first surface 101 of the epitaxial layer 10.

[0078] The first electrode 21 and the second electrode 22 are electrically connected to semiconductor layers of different conductivity types in the epitaxial layer 10. The first electrode 21 and the second electrode 22 are located in the two regions farthest apart on the first surface 101. In the cross-section of the first electrode 21 and the second electrode 22 in the direction perpendicular to the first surface 101, the width of the cross-section farther from the epitaxial layer 10 is greater than the width of the cross-section closer to the epitaxial layer 10.

[0079] The light-emitting diode provided in this embodiment has the first electrode 21 and the second electrode 22 respectively disposed in the two farthest regions on the first surface 101 of the epitaxial layer 10, thereby maximizing the distance between the two metal electrodes along the first surface 101 within the same light-emitting diode. In scenarios where several to hundreds, or even more, Micro LED chips are co-packaged and the spacing between adjacent pads is compressed to the micrometer level, the larger the distance between the two electrodes, the smaller the parasitic capacitance C between them. The reduction in parasitic capacitance directly weakens the constraint on the single-channel bandwidth of the chip, thereby reducing the loss in transmission rate and helping to maintain high system-level bandwidth and low power consumption in a wide and slow parallel optical interconnect architecture.

[0080] Furthermore, the first electrode 21 and the second electrode 22 have a variable cross-section structure in the direction perpendicular to the first surface 101, meaning that the cross-sectional width farther from the epitaxial layer 10 is greater than the cross-sectional width closer to the epitaxial layer 10. On the side electrically connected to the driving substrate (farther from the epitaxial layer 10), the electrode cross-sectional width is larger, and the electrical connection area is correspondingly increased, which is beneficial to improving the bonding strength and interconnect reliability between the electrode and the driving substrate, and reducing the risk of bonding failure during the co-packaging process. On the side connected to the chip epitaxial layer 10 (closer to the epitaxial layer 10), the electrode cross-sectional width is smaller, and the metal connection surface area is narrowed, allowing the spacing between adjacent electrodes to be further compressed, thereby further reducing the parasitic capacitance between adjacent electrodes. Therefore, the above-mentioned variable cross-section electrode structure optimizes the high-frequency bandwidth performance of the chip while ensuring the reliability of the co-packaging process.

[0081] like Figure 5 As shown, step S11 may include: epitaxially growing an epitaxial layer 10 constituting a light-emitting diode on the substrate 60 in sequence.

[0082] For example, the substrate 60 is a sapphire epitaxial substrate 60.

[0083] Optionally, the epitaxial layer 10 includes a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially. One of the first semiconductor layer and the second semiconductor layer is an n-type layer, and the other is a p-type layer.

[0084] In this embodiment of the present disclosure, one electrode is connected to the p-type layer of the epitaxial layer 10, i.e., this electrode is a p electrode. The other electrode is connected to the n-type layer of the epitaxial layer 10, i.e., this electrode is an n electrode.

[0085] For example, the p-type layer includes a p-type AlInP layer.

[0086] The light-emitting layer comprises alternating layers of AlGaInP quantum wells and AlGaInP quantum barriers, wherein the Al content in the AlGaInP quantum wells and AlGaInP quantum barriers differs. The first light-emitting layer may comprise 3 to 8 alternating stacked cycles of AlGaInP quantum wells and AlGaInP quantum barriers.

[0087] The n-type layer includes an n-type AlGaInP current-spreading layer.

[0088] like Figure 5 As shown, step S12 may include the following steps: The first step is to etch the first groove 11. On the first surface 101 of the epitaxial layer 10, the first groove 11, which is recessed along the thickness direction, is formed by photolithography and etching. The first groove 11 penetrates the upper second conductivity type semiconductor layer and the active region, so that the bottom of the groove exposes the first conductivity type semiconductor layer (i.e., a semiconductor layer with a different conductivity type than the upper layer of the first surface 101), providing a non-conductive layer contact channel for the first electrode 21.

[0089] The second step is to form a transparent conductive layer 50. A transparent conductive layer 50 is formed on the first surface 101 in a region outside the first groove 11. The transparent conductive layer 50 is in ohmic contact with the second conductivity type semiconductor layer exposed on the first surface 101, serving as a lateral current spreading layer on one side of the second electrode 22.

[0090] The third step is to form a first insulating layer 41. The first insulating layer 41 is deposited on the first surface 101, the inner wall of the first groove 11, and the transparent conductive layer 50, so that the first insulating layer 41 covers the first surface 101, the inner wall of the first groove 11, and the transparent conductive layer 50.

[0091] For example, the first insulating layer 41 is at least one of a silicon oxide layer, a titanium oxide layer, a silicon nitride layer, and an aluminum oxide layer.

[0092] The fourth step is to form vias. The first insulating layer 41 is patterned and etched to form two vias that expose the surface of the transparent conductive layer 50 and the bottom semiconductor layer of the first groove 11, respectively.

[0093] The fifth step is to form a dielectric layer 30 containing spaced air cavities 31. A dielectric layer 30 is deposited between the areas to be formed of the first electrode 21 and the second electrode 22 on the first surface 101, with the dielectric layer 30 located between the two electrodes. Subsequently, multiple air cavities 31 arranged in-plane are formed in the dielectric layer 30 by a nanopore forming process (such as photolithography definition or annealing to form cavities), and the maximum width of each air cavity 31 is controlled to be between 1 nm and 100 nm, thereby reducing the equivalent dielectric constant between the electrodes.

[0094] For example, the dielectric layer 30 is a silicon oxide layer.

[0095] Step 6: Form a first electrode 21 and a second electrode 22 with variable cross-sections and coplanarity.

[0096] On the surface of the first insulating layer 41 away from the epitaxial layer 10, in the two regions furthest apart on the first surface 101, for example, at a pair of opposite corners of a rectangular top view projection, a first electrode 21 and a second electrode 22 are formed, respectively. Each electrode includes a first columnar segment 201 and a second columnar segment 202 coaxially connected, such that in a cross-section perpendicular to the first surface 101, the cross-sectional width farther from the epitaxial layer 10 is greater than the cross-sectional width closer to the epitaxial layer 10.

[0097] The first electrode 21 is filled through a via located above the first groove 11 and extends to the bottom of the first groove 11, and is electrically connected to the exposed first conductive type semiconductor layer. The second electrode 22 is electrically connected to the transparent conductive layer 50 through another via and is located outside the first groove 11. The deposition and planarization process is controlled so that the end face of the first electrode 21 away from the epitaxial layer 10 is flush with the end face of the second electrode 22 away from the epitaxial layer 10, thereby forming a flip-chip bonding end with the same surface and common height.

[0098] Figure 6 This is a schematic diagram of a light-emitting array provided in an embodiment of this disclosure. Figure 6 As shown, the light-emitting array includes a substrate 70 and light-emitting diodes 80 as described above, the array of light-emitting diodes 80 being arranged on the substrate 70.

[0099] like Figure 6 As shown, the orthographic projection of each light-emitting diode 80 on the substrate 70 is rectangular, and the first electrode 21 and the second electrode 22 are located at two opposite corners of the orthographic projection of the rectangle.

[0100] like Figure 6 As shown, along the row direction of the substrate 70, the first electrode 21 and the second electrode 22 are located at the same diagonal position in each of the light-emitting diodes 80 in the same row.

[0101] like Figure 6 As shown, in two adjacent rows of LEDs 80, the first electrode 21 and the second electrode 22 are located at opposite diagonal positions, and the two adjacent rows of LEDs 80 are staggered in the row direction.

[0102] In this embodiment of the present disclosure, the light-emitting diodes are arranged in a matrix on the substrate. The projection of a single light-emitting diode on the substrate is a rectangular unit, and the two electrodes of the same rectangular unit are respectively located at a pair of opposite corners of the rectangular unit, forming a diagonal connection inside the unit.

[0103] like Figure 6 As shown, along the row extension direction of the substrate 70, the first electrode 21 of each rectangular unit in the same row is located on the same diagonal side of its rectangular projection, and the second electrode 22 is located on the other diagonal side; when crossing into an adjacent row, the diagonal orientations of the electrodes of each rectangular unit in that row are completely opposite. That is, for two light-emitting diodes in adjacent rows, the diagonals connecting the first and second electrodes in their respective rectangular units intersect each other on the top view projection.

[0104] For example, in one row of rectangular cells, the electrode connection is from the top left to the bottom right, and in adjacent rows of rectangular cells, the electrode connection is from the top right to the bottom left.

[0105] Figure 6The diagram illustrates the staggered arrangement of the light-emitting diode array. Figure 6 In the diagram, 'a' represents half the side length of LED 80, and 'b' represents half the spacing between two adjacent LEDs 80 in the same row.

[0106] like Figure 6 As shown, the LEDs 80 between adjacent rows are not vertically aligned, but rather staggered along the row direction, with an overlap of half a spacing b. For example, the center of the first LED in the second row (see...) Figure 6 The location of half-side length 'a' of LED 80 (as shown in the diagram) falls precisely in the center of the line connecting the centers of two adjacent LEDs in the first row (see...). Figure 6 The position of half the spacing b between two adjacent LEDs 80 in the array makes the entire array appear misaligned. By using the diagonal reversal of adjacent rows and the half-spacing misalignment, the diagonal distance between the two electrodes of the same LED is maximized at the unit level, and the minimum spacing between the electrodes of any two LEDs in adjacent rows is maximized at the array level.

[0107] In the above implementation, at the array level, adjacent rows of electrodes face opposite directions and are staggered by half a spacing along the row direction, so that the second row of cells is precisely embedded between the two cells of the first row. This maximizes the minimum spacing between any two electrodes in adjacent rows on the entire array. In co-packaging scenarios with micron-level pad spacing, this maximization directly reduces the mutual parasitic capacitance and signal crosstalk between adjacent chips, mitigating the loss of system bandwidth and speed due to cross-channel coupling.

[0108] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes an epitaxial layer (10), a first electrode (21), and a second electrode (22). The first electrode (21) and the second electrode (22) are arranged at intervals on the first surface (101) of the epitaxial layer (10) and are electrically connected to semiconductor layers of different conductivity types of the epitaxial layer (10). The first electrode (21) and the second electrode (22) are located in the two regions farthest apart on the first surface (101). In the cross-section of the first electrode (21) and the second electrode (22) in the direction perpendicular to the first surface (101), the width of the cross-section farther from the epitaxial layer (10) is greater than the width of the cross-section closer to the epitaxial layer (10).

2. The light-emitting diode according to claim 1, characterized in that, Both the first electrode (21) and the second electrode (22) include a first columnar segment (201) and a second columnar segment (202). The first columnar segment (201) and the second columnar segment (202) are coaxially connected. The width of the first columnar segment (201) is smaller than the width of the second columnar segment (202). The end of the first columnar segment (201) away from the second columnar segment (202) is connected to the epitaxial layer (10).

3. The light-emitting diode according to claim 1, characterized in that, The light-emitting diode further includes a dielectric layer (30), which is located on the side of the first surface (101) of the epitaxial layer (10) and between the first electrode (21) and the second electrode (22). The dielectric layer (30) has a plurality of spaced air cavities (31).

4. The light-emitting diode according to claim 3, characterized in that, The maximum width of the air cavity (31) is 1 nm to 100 nm.

5. The light-emitting diode according to any one of claims 1 to 4, characterized in that, The first surface (101) of the epitaxial layer (10) has a first groove (11), the first electrode (21) is located in the first groove (11), the second electrode (22) is located outside the first groove (11), and the end face of the first electrode (21) away from the epitaxial layer (10) is flush with the end face of the second electrode (22) away from the epitaxial layer (10).

6. The light-emitting diode according to claim 5, characterized in that, The light-emitting diode also includes a first insulating layer (41) and a transparent conductive layer (50). The transparent conductive layer (50) is located on the first surface (101) and outside the first groove (11). The first insulating layer (41) is located inside the first surface (101) and the first groove (11) and covers the transparent conductive layer (50). The first insulating layer (41) has through holes that expose the bottom of the grooves of the transparent conductive layer (50) and the first groove (11), respectively. The first electrode (21) and the second electrode (22) are both located on the surface of the first insulating layer (41) away from the epitaxial layer (10). The first electrode (21) is electrically connected to the semiconductor layer exposed by the first groove (11) through a via, and the second electrode (22) is electrically connected to the transparent conductive layer (50) through a via.

7. The light-emitting diode according to any one of claims 1 to 4, characterized in that, The light-emitting diode also includes a first insulating layer (41) and a transparent conductive layer (50). The first surface (101) of the epitaxial layer (10) has a first groove (11) and a second groove (12) arranged at intervals, wherein the groove depth of the first groove (11) is the same as the groove depth of the second groove (12); The first insulating layer (41) is located in the first surface (101), the first groove (11) and the second groove (12). The first insulating layer (41) has through holes that expose the bottom of the first surface (101) and the first groove (11) respectively. The transparent conductive layer (50) is located on the surface of the first insulating layer (41) away from the epitaxial layer (10) and in the second groove (12). The transparent conductive layer (50) is connected to the first surface (101) through the through holes. The first electrode (21) is located in the first groove (11) and is electrically connected to the semiconductor layer exposed in the first groove (11) through a via. The second electrode (22) is located in the second groove (12) and is located on the surface of the transparent conductive layer (50) away from the epitaxial layer (10).

8. A light-emitting array, characterized in that, The light-emitting array includes a substrate (70) and light-emitting diodes as described in any one of claims 1 to 7, wherein the light-emitting diodes (80) array is arranged on the substrate (70).

9. The light-emitting array according to claim 8, characterized in that, Each of the light-emitting diodes has a rectangular orthographic projection on the substrate (70), and the first electrode (21) and the second electrode (22) are located at two opposite corners of the rectangular orthographic projection. Along the row direction of the substrate (70), in each of the light-emitting diodes in the same row, the first electrode (21) and the second electrode (22) are located at the same diagonal position; In two adjacent rows of LEDs, the first electrode (21) and the second electrode (22) are located at opposite diagonal positions, and the LEDs in the two adjacent rows are staggered in the row direction.

10. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: An epitaxial layer (10) is formed on a substrate (60); A first electrode (21) and a second electrode (22) are formed on the first surface (101) of the epitaxial layer (10), and the first electrode (21) and the second electrode (22) are electrically connected to semiconductor layers of different conductivity types of the epitaxial layer (10), respectively. The first electrode (21) and the second electrode (22) are located in the two regions farthest apart on the first surface (101), and the width of the cross section of the first electrode (21) and the second electrode (22) in the direction perpendicular to the first surface (101) is greater than the width of the cross section of the first electrode (21) and the second electrode (22) that is farther away from the epitaxial layer (10).

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