Display device

Abstract

A display device according to one embodiment includes: a substrate, the substrate including a display area and a non-display area surrounding the display area; voltage lines disposed in the non-display area on the substrate; and a dam surrounding the voltage lines, wherein the voltage lines include: a first portion extending along a first direction; and a second portion positioned from the first portion along a second direction intersecting the first direction and having a curved shape, the second portions being provided as a plurality of second portions, the plurality of second portions being disposed spaced apart from each other in the first direction, and a second portion of the plurality of second portions disposed near the display area being covered by the dam.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0056045, filed on April 29, 2025, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This manual relates to display devices. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is constantly increasing, and various types of display devices are being used, such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) display devices.

[0005] The display device includes multiple pixels and multiple switching elements for driving and controlling the pixels. Summary of the Invention

[0006] The various embodiments described in this specification are intended to provide a display device capable of increasing the path of moisture penetration.

[0007] Various embodiments of this specification are also intended to provide a display device capable of preventing cracks in embossed patterns (or second parts or hammered pattern parts).

[0008] Various embodiments of this specification are also intended to provide a display device capable of reducing the stress applied to the embossed pattern (or the second part).

[0009] Various embodiments described herein are also intended to provide a display device capable of preventing cracks in the first encapsulation layer.

[0010] Various embodiments described in this specification are also intended to provide low-power display devices that can extend their lifespan.

[0011] The purpose of this specification is not limited to the above objectives, and other technical objectives can be deduced from the following embodiments.

[0012] According to one embodiment, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area; voltage lines disposed in the non-display area on the substrate; and a dam surrounding the voltage lines, wherein the voltage lines include: a first portion extending along a first direction; and a second portion positioned from the first portion along a second direction intersecting the first direction and having a curved shape, the second portions being provided as a plurality of second portions, the plurality of second portions being disposed spaced apart from each other in the first direction, and a second portion of the plurality of second portions disposed near the display area being covered by the dam.

[0013] According to one embodiment, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area; voltage lines disposed on the non-display area of ​​the substrate; a first overlay pattern; a dam overlapping the voltage lines; a first stop portion between the dam and the display area; and a second stop portion between the first stop portion and the dam, wherein the voltage lines include: a first portion extending along a first direction; and a second portion positioned from the first portion along a second direction intersecting the first direction and having a curved shape, the second portions being provided as a plurality of second portions, the plurality of second portions being disposed spaced apart from each other in the first direction, the dam and the first stop portion extending continuously along the second direction, the second stop portions overlapping the first portions and being disposed between adjacent second portions in the second direction, and the first overlay pattern overlapping the plurality of second portions disposed spaced apart from each other in the first direction.

[0014] Details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a plan view of a display device according to one embodiment.

[0016] Figure 2 It shows the basis Figure 1 A cross-sectional view of the display panel in a bent state.

[0017] Figure 3 It shows the basis Figure 1 A plan view of the curved state of the display device.

[0018] Figure 4 It is along Figure 3 A cross-sectional view of line B-B' in the diagram.

[0019] Figure 5 It is along Figure 3 A cross-sectional view of line C-C' in the diagram.

[0020] Figure 6 It is along Figure 1 A cross-sectional view of line A-A' in the diagram.

[0021] Figure 7 yes Figure 1 A magnified plan view of region Q1 in the image.

[0022] Figure 8 It is along Figure 7 A cross-sectional view of line D-D' in the diagram.

[0023] Figure 9 It is along Figure 7 A cross-sectional view of line E-E' in the diagram.

[0024] Figure 10 This is a plan view of a display panel according to yet another embodiment.

[0025] Figure 11 It is along Figure 10 A cross-sectional view of line F-F' in the diagram.

[0026] Figure 12 yes Figure 11 Enlarged cross-sectional view of region Q2 in the image.

[0027] Figure 13 This is a plan view of a display panel according to another embodiment.

[0028] Figure 14 It is along Figure 13 A cross-sectional view of line G-G' in the diagram. Detailed Implementation

[0029] In the following description, various embodiments will be described with reference to the accompanying drawings.

[0030] The same reference numerals indicate the same parts. Additionally, in the accompanying drawings, the thickness, scale, and dimensions of parts may be exaggerated for effective description. For ease of description, the scale of parts shown in the drawings differs from the actual scale, and is therefore not limited to the scale shown in the drawings.

[0031] In the specification, when a component (or area, layer, part, etc.) is described as "on another component", "connected to", or "coupled to" another component, it means that the component can be directly connected / coupled to the other component, or that another component can be placed between them.

[0032] The term “and / or” includes all one or more combinations that can be defined by the associated configuration.

[0033] Terms such as "first," "second," etc., can be used to describe various components, but components are not limited by these terms. These terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of various embodiments, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular includes the plural.

[0034] Terms such as “below,” “under,” “above,” and “over” are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described relative to the directions marked in the drawings. For example, one or more other parts may be positioned between two parts, provided that “closely to” or “directly” is not used. Spatially relative terms such as “below or below,” “lower part,” “above,” and “upper part” can be used to readily describe the relationship between one element or component and another element or component as shown in the accompanying drawings. Spatially relative terms should be understood to include terms for different orientations of the elements in use or operation, in addition to those shown in the accompanying drawings. For example, in the case of flipping the elements shown in the accompanying drawings, an element described as being positioned “below” or “under” another element may be positioned “above” another element. Thus, the exemplary term “below” can include both downward and upward directions.

[0035] It should be understood that terms such as “comprising” or “having” are intended to specify the presence of features, numbers, steps, operations, components, parts or combinations thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0036] Features of the various embodiments described herein can be coupled or combined in part or in whole, making it possible for various technologies to interoperate and drive each other, and various embodiments can be implemented independently of each other or together in an associated relationship.

[0037] The display device described herein will be described below with reference to the following figures and embodiments.

[0038] Figure 1 This is a plan view of a display device according to one embodiment.

[0039] Reference Figure 1 According to one embodiment, the display device 1 may include a display panel 100. The display panel 100 may include a display area DA and a non-display area NDA surrounding the display area DA, the display area DA including a plurality of pixels PX. The flat surface shape of the display area DA may be rectangular. However, various embodiments of this specification are not limited thereto, and the flat surface shape of the display area DA may be square, circular, elliptical, or other polygonal shapes. For example, the display area DA may have a rectangular shape with rounded corners, but is not limited thereto, and may also have a rectangular shape with angled corners.

[0040] In various embodiments, the first direction DR1 and the second direction DR2 are different directions that intersect each other, for example, directions that intersect perpendicularly in a plan view. Figure 1 In this embodiment, the first direction DR1 may be substantially the same as the extension direction of the short side of the display panel 100, and the second direction DR2 may be the same as the extension direction of the long side of the display panel 100. However, the directions described in the various embodiments should be understood as indicating relative directions, and the various embodiments are not limited to the described directions.

[0041] The display area DA may include a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The non-display area NDA may surround the display area DA. The non-display area NDA may be located on one side and the other side of the display area DA in the first direction DR1, and on one side and the other side of the display area DA in the second direction DR2.

[0042] The display panel 100 may further include a sensor non-display area NDA_S and sensor holes SH1 and SH2 surrounded by the sensor non-display area NDA_S. In a plan view, sensor holes SH1 and SH2 may be surrounded by the display area NDA_S. Sensor holes SH1 and SH2 may be, for example... Figure 1 The two sensor holes in the display area DA are not limited to this. For example, the sensor holes can be provided as a single sensor hole. The two sensor holes SH1 and SH2 can each include a sensor hole in which an infrared sensor is disposed and a sensor hole in which a camera sensor is disposed, but the various embodiments of this specification are not limited to this. The sensor non-display area NDA_S can be disposed between the sensor holes SH1 and SH2 and the display area DA. The sensor non-display area NDA_S can completely surround the sensor holes SH1 and SH2. Pixels PX may not be disposed in the sensor non-display area NDA_S. In some embodiments, sensor holes SH1 and SH2 may not be disposed, and the infrared sensor or camera sensor may be disposed in the display area DA. In this case, the number of pixels PX per unit area of ​​the display area DA in which the infrared sensor or camera sensor is disposed may be less than the number of pixels PX per unit area of ​​the display area DA in which the infrared sensor or camera sensor is not disposed. That is, the display area DA in which the infrared sensor or camera sensor is disposed may also include a transmissive area.

[0043] The gate driving unit GIP can be disposed in the non-display area NDA, located on one side and the other side of the display area DA in the first direction DR1. A low-potential voltage line VSSL can be disposed outside the gate driving unit GIP in the non-display area NDA. For example, as Figure 1As shown, the low-potential voltage line VSSL can extend from the printed circuit board FPCB, passing through the sub-region SR and the curved region BR. It can be positioned outside the gate driving unit GIP on the non-display region NDA and is configured to surround the display region DA. The high-potential voltage line VDDL can be positioned outside the gate driving unit GIP on the non-display region NDA. The high-potential voltage line VDDL can also be positioned between the low-potential voltage line VSSL and the gate driving unit GIP.

[0044] The non-display area NDA, located on the other side of the display area DA in the second direction DR2, can extend further from the center portion of the display area DA on the other side of the second direction DR2 toward the other side of the display area DA in the second direction DR2. The width of the non-display area NDA extending further from the center portion of the other side toward the other side of the display area DA in the second direction DR2 in the first direction DR1 can be smaller than the width of the non-display area NDA adjacent to the other side of the display area DA in the second direction DR2 in the first direction DR1.

[0045] Display device 1 may include a main region MR, a sub-region SR, and a curved region BR between the main region MR and the sub-region SR. A display region DA and a non-display region NDA surrounding the four surfaces of the display region DA may form the main region MR, and a portion extending from the center portion on one side toward the display region DA on the other side in a second direction DR2 may form the curved region BR and the sub-region SR. The curved region BR may be disposed between the sub-region SR and the main region MR. The sub-region SR may include a first pad region PA1 and a second pad region PA2 located at the end portion of the sub-region SR on the other side in the second direction DR2. Display device 1 may also include a data driver unit DIC and a printed circuit board FPCB. The data driver unit DIC may be disposed in the first pad region PA1, and the printed circuit board FPCB may be attached to the second pad region PA2. Multiple pads connected to the data driver unit DIC and the printed circuit board FPCB may be disposed in each of the first pad region PA1 and the second pad region PA2. The data driver unit DIC may be configured, for example, in the form of a driver chip (IC), but is not limited thereto. In one embodiment, a method for setting the data driving unit DIC by directly mounting it on a chip-on-plastic structure on the display panel 100 is described. However, various embodiments of this specification are not limited to this, and the data driving unit DIC can be set by a chip-on-glass or chip-on-film method.

[0046] Multiple pads can be set in the second pad area PA2. These pads may include power pads (low-potential voltage pad VSSP, high-potential voltage pad VDDP) and data voltage pads DP. The data voltage pad DP can be located in the center of the second pad area PA2, while the low-potential voltage pad VSSP and the high-potential voltage pad VDDP can be located on the outer edges of the second pad area PA2. The high-potential voltage pad VDDP can be located between the low-potential voltage pad VSSP and the data voltage pad DP. The voltage pads VDDP and VSSP can be located on the left and right sides of the second pad area PA2, respectively. The data voltage pad DP can be connected to the data line DL. The data line DL can be connected to each of the pixels PX in the display area DA.

[0047] Figure 2 It shows the basis Figure 1 A cross-sectional view of the display panel in a bent state.

[0048] Reference Figure 2 According to one embodiment, the curved region BR of the display panel 100 of the display device 1 can be curved in the thickness direction (or the third direction DR3). Therefore, the main region MR and the sub-region SR can overlap each other in the thickness direction. The display panel 100 can be curved such that the lower surface of the main region MR faces the upper surface of the sub-region SR. A printed circuit board FPCB can be attached to the end portion of the sub-region SR.

[0049] Figure 3 It shows the basis Figure 1 A plan view of the curved state of the display device.

[0050] Reference Figure 3 The display device 1 may also include a molding portion MDP. The molding portion MDP may be positioned on the upper short edge of the display panel 100 in the second direction DR2, the left and right long edges of the display panel 100, the corners of the display panel 100, and the lower short edge of the display panel 100 in the second direction DR2.

[0051] Figure 4 It is along Figure 3 A cross-sectional view of line B-B' in the diagram.

[0052] Reference Figure 3 and Figure 4 The display device 1 may include a display panel 100, a polarizing layer 200, a cover layer 300, a back plate layer 600, a plate layer 800, bonding layers 710, 720, 730, 740, 750, 760, 770, 780 and 790, a cover layer MCL, a molding part MDP, a molded frame MFP and a housing HSP.

[0053] The curved area BR of the display panel 100 can have a curved shape and can be curved in the thickness direction. The main area MR and the sub-area SR of the display panel 100 can overlap each other.

[0054] A polarization layer 200 can be disposed on the main region MR of the display panel 100. The polarization layer 200 can polarize light emitted from the display panel 100 by a polarization angle. The polarization layer 200 can transmit the polarized light to the outside. The polarization layer 200 may include the function of blocking the reflection of external light that does not contain light polarized by a polarization angle. The polarization layer 200 may include a first phase retardation layer, a second phase retardation layer on the first phase retardation layer, and a polarization layer on the second phase retardation layer. Figure 5 and Figure 6 In this diagram, the polarization layer 200 and the display panel 100 are shown as separate, but this is not a limitation, and the polarization layer 200 may be included in the display panel 100. In some embodiments, the polarization layer 200 may be omitted, and a color filter may be provided.

[0055] The cover layer 300 can be disposed on the polarizing layer 200. The cover layer 300 can be made of glass materials including glass, quartz, etc., but various embodiments of this specification are not limited thereto, and the cover layer 300 can also be made of plastic materials. The cover layer 300 can be disposed above the display panel 100 to protect components disposed below it from the outside. The cover layer 300 can be formed by chemical reinforcement, but various embodiments of this specification are not limited thereto. The cover layer 300 can be a cover window, a window cover, or a cover component, but various embodiments of this specification are not limited thereto.

[0056] The cover layer 300 can protect the components disposed beneath it from the outside. However, as described above, since the cover layer 300 is made of glass, it may be damaged by external forces, resulting in glass fragments. These glass fragments may break off to the outside of the display device 1. According to various embodiments of this specification, to prevent glass fragment breakage due to damage to the cover layer 300 or to increase the durability of the cover layer 300, the display device 1 may also include at least one additional layer on the cover layer 300. For example, the display device 1 may also include a film or coating on the cover layer 300, but the various embodiments of this specification are not limited thereto.

[0057] The side surface of the cover layer 300 may protrude further outward than the side surface of the display panel 100. For example, the side surface of the cover layer 300 may protrude further outward than the end of the curved region BR of the display panel 100, but the various embodiments described herein are not limited thereto.

[0058] The backplate layer 600 can be disposed below the display panel 100. The backplate layer 600 can be disposed below the display panel 100 to support the display panel 100. The backplate layer 600 may include a material capable of supporting the display panel 100. For example, the backplate layer 600 may include polyethylene terephthalate (PET), polyimide (PI), or polycarbonate (PC), but various embodiments of this specification are not limited thereto. When the display device 1 is bent, the backplate layer 600 can maintain a constant curvature of the bent region BR and suppress wrinkles on the upper surface of the display panel 100.

[0059] The back panel layer 600 may include a first back panel layer 610 on the main region MR and a second back panel layer 620 on the sub-region SR. The first back panel layer 610 may be disposed between the main region MR of the display panel 100 and the panel layer 800, and the second back panel layer 620 may be disposed between the sub-region SR of the display panel 100 and the panel layer 800. The back panel layer 600 may not be disposed on the curved region BR.

[0060] A plate layer 800 may be disposed between the first backplate layer 610 and the second backplate layer 620. The plate layer 800 may include metal. For example, the plate layer 800 may include stainless steel, but various embodiments of this specification are not limited thereto. The plate layer 800 may include a first plate layer 810 between the first backplate layer 610 and the second backplate layer 620, and a second plate layer 820 between the first plate layer 810 and the second backplate layer 620.

[0061] The bonding layer may be additionally provided between components 100, 200, 300, 610, 620, 810 and 820. The bonding layer may include a first bonding layer 710, a second bonding layer 720, a third bonding layer 730, a fourth bonding layer 740, a fifth bonding layer 750, a sixth bonding layer 760 and a seventh bonding layer 770.

[0062] The first bonding layer 710 can be disposed between the display panel 100 and the polarizing layer 200. The first bonding layer 710 can connect or couple the display panel 100 to the polarizing layer 200.

[0063] The second bonding layer 720 can be disposed between the polarizing layer 200 and the capping layer 300. The second bonding layer 720 can connect or couple the polarizing layer 200 to the capping layer 300.

[0064] The third bonding layer 730 can be disposed between the first backplane layer 610 and the display panel 100. The third bonding layer 730 can connect or couple the first backplane layer 610 to the display panel 100.

[0065] The fourth bonding layer 740 may be disposed between the first backplane layer 610 and the first board layer 810. The fourth bonding layer 740 may connect or couple the first backplane layer 610 to the first board layer 810.

[0066] The fifth bonding layer 750 can be disposed between the second backplane layer 620 and the display panel 100 in the sub-region SR. The fifth bonding layer 750 can connect or couple the second backplane layer 620 to the display panel 100.

[0067] A sixth bonding layer 760 may be disposed between the second backplane layer 620 and the second board layer 820. The sixth bonding layer 760 may connect or couple the second backplane layer 620 to the second board layer 820.

[0068] A seventh bonding layer 770 may be disposed between the first plate layer 810 and the second plate layer 820. The seventh bonding layer 770 may connect or couple the first plate layer 810 to the second plate layer 820.

[0069] The eighth bonding layer 780 can be disposed between the molded frame MFP and the cover layer MCL. The eighth bonding layer 780 can connect or couple the molded frame MFP to the cover layer MCL.

[0070] The ninth bonding layer 790 may be disposed between the fourth molding part MDP4 (or the molding part) and the housing HSP. The ninth bonding layer 790 may connect or couple the molding part MDP to the housing HSP.

[0071] Each of the first bonding layer 710 and the second bonding layer 720 may include a transparent adhesive, but various embodiments of this specification are not limited thereto. For example, the transparent adhesive may be a transparent resin (OCR) or a transparent adhesive (OCA), but various embodiments of this specification are not limited thereto. Each of the third bonding layer 730, the fourth bonding layer 740, the fifth bonding layer 750, the sixth bonding layer 760, the seventh bonding layer 770, the eighth bonding layer 780, and the ninth bonding layer 790 may include a pressure-sensitive adhesive (PSA), but various embodiments of this specification are not limited thereto.

[0072] A cover layer MCL can be disposed on one surface of the curved region BR of the display panel 100. The cover layer MCL may include a plastic material and can be coated on one surface of the curved region BR of the display panel 100 to cover the curved region BR of the display panel 100. Link wires can be disposed on the curved region BR. The cover layer MCL can protect the link wires from external impacts and prevent moisture from penetrating into the link wires. Additionally, when the curved region BR of the display panel 100 is bent into a curved shape with a constant radius of curvature, the cover layer MCL can be used to position the link wires on a neutral plane. Since a neutral plane with zero tension and compressive force is formed in the curved region BR, and the link wires are positioned on the neutral plane, the link wires can withstand zero bending stress when the display panel 100 is bent, and therefore can be bent without being damaged by bending stress.

[0073] The capping layer MCL can contact the side surfaces of the polarizing layer 200 and the first bonding layer 710. A portion of the capping layer MCL can extend to the sub-region SR. On the sub-region SR, the capping layer MCL can be coupled to the molded frame MFP via the eighth bonding layer 780.

[0074] The data driver unit (DIC) can be disposed in the first pad area PA1 of the sub-region SR, and the printed circuit board (FPCB) can be disposed in the second pad area PA2. The printed circuit board (FPCB) can be electrically connected to the pads on the display panel 100 via an anisotropic conductive film (ACF). The cover layer (MCL) may not overlap with the data driver unit (DIC), but various embodiments of this specification are not limited thereto.

[0075] The molded frame (MFP) can be placed below the cover layer (MCL).

[0076] The molded portion MDP can be disposed on the cover layer MCL. The molded portion MDP can cover the outer surface of the curved region BR of the display panel 100 and can directly contact, for example, the cover layer MCL, the lower surface of the cover layer 300, and the upper, side, and lower surfaces of the molded frame MFP. The molded portion MDP can also contact the inner surface of the housing HSP. The molded portion MDP can also be disposed inside the curved region BR. The molded portion MDP can contact the inner surface of the curved region BR, the side surfaces of the first backplate layer 610 and the second backplate layer 620, and the side surfaces of the plate layers 810 and 820.

[0077] The housing HSP can be disposed on the outermost part of the display device 1. The portion of the housing HSP extending in the thickness direction (or the third direction DR3) can directly contact the cover layer 300 and the molded part MDP. The portion of the housing HSP extending in the second direction DR2 can be coupled to the molded part MDP via the ninth bonding layer 790.

[0078] Figure 5 It is along Figure 3 A cross-sectional view of line C-C' in the diagram.

[0079] Figure 5 The main region MR is shown, which includes the display area DA and the non-display area NDA. Figure 5 A cross-sectional view of the right side region (or the short edge along one side of the first direction DR1) of the display device 1 is shown. The cross-sectional view of the right side region of the display device 1 may be substantially the same as the cross-sectional views of the left side region and the upper region of the display device 1.

[0080] Reference Figure 3 and Figure 5 The molded portion MDP can directly contact the side surfaces of the display panel 100, the first back panel layer 610, and the first plate layer 810. The molded portion MDP can directly contact the side and lower surfaces of the molded frame MFP. The molded portion MDP can be bonded to the housing HSP via the ninth bonding layer 790. The molded portion MDP can contact the lower surface of the cover layer 300 and the inner surface of the housing HSP.

[0081] In a display device 1 according to one embodiment, the molded portion MDP may include an organic material. The molded portion MDP may include an organic material that repeatedly contracts and expands in response to heat. The molded portion MDP is in direct contact with the non-display area NDA of the display panel 100 and deforms significantly (expands or contracts) in response to heat, thereby affecting the encapsulation layers 171 and 173 of the display panel 100 located in the non-display area NDA (see...). Figure 9 This can cause cracks. A structure for preventing cracks according to one embodiment will be described below.

[0082] Figure 6 It is along Figure 1 A cross-sectional view of line A-A' in the diagram.

[0083] Reference Figure 6 The display panel 100 may include a substrate 101, a buffer layer 102, a first thin film transistor 120, a second thin film transistor 130, a storage electrode 140, a light-emitting part 150, an encapsulation part 170, a touch part 180, and an upper organic layer 190.

[0084] The substrate 101 may include one or more plastic materials. For example, the substrate 101 may be a multi-substrate including a variety of plastic materials such as polyimide, but is not limited thereto.

[0085] A buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 may minimize or delay the diffusion of moisture or oxygen that permeates the substrate 101. The buffer layer 102 may be formed by, but is not limited to, alternatingly stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once.

[0086] The first light-shielding layer 126 may be disposed on the buffer layer 102. The first light-shielding layer 126 can prevent light from being transmitted through the first semiconductor layer 123 of the first thin-film transistor 120. For example, the first semiconductor layer 123 may be disposed overlapping the first light-shielding layer 126. The first light-shielding layer 126 may be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but is not limited thereto.

[0087] The first insulating layer 103 may be disposed on the first optical shielding layer 126. The first insulating layer 103 can prevent short circuits between the components of the first thin-film transistor 120 and the first optical shielding layer 126. The first insulating layer 103 may be made of the same material as the buffer layer 102, but is not limited thereto. For example, the first insulating layer 103 may be made of inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx), but is not limited thereto.

[0088] The first thin-film transistor 120 may be disposed on the first insulating layer 103. The first thin-film transistor 120 may include a first source electrode 121, a first gate electrode 122, a first semiconductor layer 123, and a first drain electrode 124.

[0089] The first semiconductor layer 123 may be disposed on the first insulating layer 103. The first semiconductor layer 123 may include metal oxide semiconductors such as indium gallium zinc oxide (IGZO), and silicon-based semiconductor materials such as amorphous silicon, polycrystalline silicon, etc., but is not limited thereto. The first semiconductor layer 123 may include a channel region, a source region, and a drain region.

[0090] Because polycrystalline semiconductor layers have higher mobility than amorphous semiconductor layers and oxide semiconductor layers, they can achieve lower power consumption and superior reliability. Therefore, driving transistors can be formed from polycrystalline semiconductor layers.

[0091] The second insulating layer 104 may be disposed on the first semiconductor layer 123. The second insulating layer 104 may be formed of the same material as the first insulating layer 103 and may prevent short circuits between the first semiconductor layer 123 and another component of the first thin-film transistor 120.

[0092] The first gate electrode 122 may be disposed on the second insulating layer 104. The first gate electrode 122 may be disposed on the second insulating layer 104 to overlap with the channel region of the first semiconductor layer 123. The first gate electrode 122 may be formed from a single layer or multiple layers made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) or compounds thereof. The first gate electrode 122 may be disposed together with the gate line.

[0093] A third insulating layer 105 may be disposed on the first gate electrode 122. The third insulating layer 105 may be made of the same material as the first insulating layer 103 or the second insulating layer 104.

[0094] A first source electrode 121 and a first drain electrode 124 may be disposed on the third insulating layer 105.

[0095] The first source electrode 121 and the first drain electrode 124 can be electrically connected to the first semiconductor layer 123 via contact holes. The first source electrode 121 and the first drain electrode 124 can be made of metallic materials. For example, the first source electrode 121 and the first drain electrode 124 can be formed from a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but are not limited thereto.

[0096] The first source electrode 121 and the first drain electrode 124 can be disposed together with the data line. For example, the data line can be made of the same material as the first source electrode 121 and the first drain electrode 124, and can be formed on the same layer as the first source electrode 121 and the first drain electrode 124, but is not limited thereto.

[0097] The storage electrode 140 may be configured to be spaced apart from the first thin-film transistor 120. The storage electrode 140 may include a first storage electrode 141, a second storage electrode 142, and a third storage electrode 143.

[0098] The first storage electrode 141 may be disposed on the same layer as the first gate electrode 122, and may be made of the same material as the first gate electrode 122, but is not limited thereto.

[0099] The second storage electrode 142 may be disposed on the first storage electrode 141. The second storage electrode 142 may be disposed on the third insulating layer 105, and the third insulating layer 105 between the first storage electrode 141 and the second storage electrode 142 may serve as a dielectric to generate a capacitor. The second storage electrode 142 may be made of the same material as the first storage electrode 141, but is not limited thereto.

[0100] The second thin-film transistor 130 may be configured to be spaced apart from the first thin-film transistor 120 and the storage electrode 140. The second thin-film transistor 130 may include a second source electrode 131, a second gate electrode 132, a second semiconductor layer 133, and a second drain electrode 134.

[0101] The second optical shielding layer 136 can be disposed on the same layer as the second storage electrode 142.

[0102] Similar to the first light shielding layer 126, the second light shielding layer 136 can prevent light from traveling to the second semiconductor layer 133, thereby extending the lifetime of the second thin-film transistor 130. For example, the second semiconductor layer 133 can be configured to overlap with the second light shielding layer 136.

[0103] A fourth insulating layer 106 may be disposed on the second optical shielding layer 136. The fourth insulating layer 106 may be made of the same material as the first insulating layer 103, the second insulating layer 104 or the third insulating layer 105, but is not limited thereto.

[0104] A second semiconductor layer 133 may be disposed on the fourth insulating layer 106. The second semiconductor layer 133 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0105] The second semiconductor layer 133 may include, but is not limited to, metal oxide semiconductors such as IGZO and silicon-based semiconductor materials such as amorphous silicon and polycrystalline silicon.

[0106] A fifth insulating layer 108 may be disposed on the second semiconductor layer 133. The fifth insulating layer 108 may be made of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layer 105 or the fourth insulating layer 106, but is not limited thereto.

[0107] The second gate electrode 132 can be disposed on the fifth insulating layer 108.

[0108] The second gate electrode 132 may be made of the same material as the first gate electrode 122. For example, the second gate electrode 132 may be formed of a single layer or multiple layers made of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd) or compounds thereof, but is not limited thereto.

[0109] The sixth insulating layer 109 may be disposed on the second gate electrode 132. The sixth insulating layer 109 may be made of the same material as the first insulating layer 103, the second insulating layer 104, the third insulating layer 105, the fourth insulating layer 106 or the fifth insulating layer 108, but is not limited thereto.

[0110] The first source electrode 121, the first drain electrode 124, the third storage electrode 143, the second source electrode 131, and the second drain electrode 134 can be disposed on the sixth insulating layer 109.

[0111] The third storage electrode 143, the second source electrode 131, and the second drain electrode 134 may be made of the same material as the first source electrode 121 and the first drain electrode 124 and may be arranged coplanarly with them. For example, the third storage electrode 143, the second source electrode 131, and the second drain electrode 134 may be formed from a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof, but are not limited thereto.

[0112] The first thin-film transistor 120 may be a switching transistor, and the second thin-film transistor 130 may be a driving transistor, but the various embodiments described herein are not limited thereto.

[0113] The first protective layer 111 can be disposed on the first source electrode 121 and the first drain electrode 124.

[0114] The first protective layer 111 can planarize the upper portion of the first thin-film transistor 120 and protect the first thin-film transistor 120. The first protective layer 111 can be made of organic materials. For example, the first protective layer 111 can be made of organic materials including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but is not limited thereto.

[0115] A second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be made of the same material as the first protective layer 111, but is not limited thereto.

[0116] A connecting electrode 145 may be provided between the first protective layer 111 and the second protective layer 112.

[0117] The connecting electrode 145 can electrically connect the first thin-film transistor 120 to the light-emitting part 150. The connecting electrode 145 can be made of the same material as the first source electrode 121 and the first drain electrode 124, but is not limited thereto.

[0118] The connecting electrode 145 may be formed from a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof, but is not limited thereto.

[0119] The light-emitting part 150 may be disposed on the second protective layer 112. The light-emitting part 150 may include a first electrode 151, an organic layer 152, and a second electrode 153. The first electrode 151 may be used as an anode, and the second electrode 153 may be used as a cathode, but the various embodiments described herein are not limited thereto.

[0120] The first electrode 151 may be disposed on the second protective layer 112. The first electrode 151 may be electrically connected to the first thin-film transistor 120 via a contact hole formed in the second protective layer 112. The first electrode 151 may be a reflective electrode for reflecting light, but is not limited thereto. The first electrode 151 may include a stacked structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a stacked structure of aluminum (Al) and indium tin oxide (ITO) (ITO / Al / ITO), or an APC alloy, and may be formed from a single layer or multiple layers, but is not limited thereto.

[0121] An organic layer 152 may be disposed on the first electrode 151. The organic layer 152 may include one or more light-emitting structures (or one or more light-emitting elements) stacked on the first electrode 151 in a sequence or reverse order of hole transport layers and electron transport layers. The organic layer 152 may be an organic light-emitting layer, an inorganic light-emitting layer, a quantum dot light-emitting layer, a micro light-emitting diode, a miniature light-emitting diode, etc., but is not limited thereto. For example, the organic layer 152 of a display panel 100 according to one embodiment of this specification may include an organic light-emitting layer. The organic layer 152 may include a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer.

[0122] The second electrode 153 may be disposed on the organic layer 152. The second electrode 153 may be a transparent electrode that transmits light, but is not limited thereto. For example, the second electrode 153 may include a transparent conductive material, such as ITO or IZO, or a metal that transmits visible light.

[0123] A dam 154 can be configured to expose the first electrode 151. The dam 154 can define an opening (or light-emitting area) for a sub-pixel and can be configured to cover the edge portion of the first electrode 151. Each of the plurality of sub-pixels may include a red light-emitting area, a green light-emitting area, and a blue light-emitting area.

[0124] Spacer 155 can also be set on embankment 154.

[0125] The encapsulation portion 170 may be disposed on the dam 154 or the light-emitting portion 150. The encapsulation portion 170 may include one or more insulating layers. For example, the encapsulation portion 170 may include a first encapsulation layer 171, a second encapsulation layer 172 disposed on the first encapsulation layer 171, and a third encapsulation layer 173 disposed on the second encapsulation layer 172. The encapsulation portion 170 may include one or more inorganic layers and one or more organic layers. For example, the first encapsulation layer 171 and the third encapsulation layer 173 may include inorganic materials, and the second encapsulation layer 172 may include organic materials.

[0126] A touch buffer layer 181 may be provided on the encapsulation portion 170. For example, the touch buffer layer 181 may be provided on the third encapsulation layer 173. The touch buffer layer 181 may be made of the same material as the buffer layer 102. A first touch conductive layer may be provided on the touch buffer layer 181. A first touch insulating layer 183 may be provided on the first touch conductive layer. The first touch insulating layer 183 can prevent short circuits between touch electrodes. The first touch insulating layer 183 may include organic or inorganic materials. A second touch conductive layer may be provided on the first touch insulating layer 183.

[0127] The first touch conductive layer may include a second touch electrode 182, and the second touch conductive layer may include a first touch electrode 185. The first touch electrode 185 may include a 1a touch electrode 185a extending in a first direction and a 1b touch electrode 185b extending in a second direction different from the first direction.

[0128] The second touch electrode 182 can be electrically connected to the 1a touch electrode 185a via a contact hole formed in the first touch insulating layer 183. For example, the 1a touch electrode 185a and the second touch electrode 182 can extend in a first direction.

[0129] The first touch electrode 185 and the second touch electrode 182 may include metallic materials. For example, the first touch electrode 185 and the second touch electrode 182 may be made of titanium (Ti), nickel (Ni), aluminum (Al) or alloys thereof, and may be formed of a three-layer structure such as titanium (Ti) / aluminum (Al) / titanium (Ti), but are not limited thereto.

[0130] A second touch insulating layer 184 may be disposed on the second touch conductive layer. The second touch insulating layer 184 may include an organic insulating material.

[0131] An organic layer 190 may be provided on the touch portion 180, but the various embodiments described herein are not limited thereto. The organic layer 190 may include an organic material.

[0132] Figure 7 yes Figure 1 A magnified plan view of region Q1 in the image. Figure 8 It is along Figure 7 A cross-sectional view of line D-D' in the diagram. Figure 9 It is along Figure 7 A cross-sectional view of line E-E' in the diagram.

[0133] Figure 7 It shows the basis Figure 1 Detailed plan view of the low-potential voltage line VSSL and the high-potential voltage line VDDL. Figure 7 The non-display area NDA is shown, located within the main region MR.

[0134] The low-potential voltage line VSSL and the high-potential voltage line VDDL may each include a first line portion VSSL1 and VDDL1. The first line portion VSSL1 of the low-potential voltage line VSSL may include a 1-1 line portion VSSL1a and a 1-2 line portion VSSL1b on the 1-1 line portion VSSL1a, and the first line portion VDDL1 of the high-potential voltage line VDDL may include a 1-1 line portion VDDL1a and a 1-2 line portion VDDL1b on the 1-1 line portion VDDL1a. A hole H extending through the 1-2 line portions VSSL1b and VDDL1b in the thickness direction may be formed in the 1-2 line portions VSSL1b and VDDL1b. Multiple holes H may be provided. The holes H may completely extend through the 1-2 line portions VSSL1b and VDDL1b in the thickness direction. Gas generated within the first protective layer 111 can be discharged to the outside via the holes H.

[0135] The low-potential voltage line VSSL and the high-potential voltage line VDDL can each include a patterning portion VSSL_P and VDDL_P, respectively. The patterning portions VSSL_P and VDDL_P can be directly connected to the first line portions VSSL1 and VDDL1, respectively. The patterning portion VSSL_P of the low-potential voltage line VSSL can include a portion extending from the second pad area PA2 towards the display area DA (see...). Figure 1 The first part of VSSL_P1 extends from the first part of VSSL_P1 along the path from the second pad area PA2 toward the display area DA (see...). Figure 1 The second part VSSL_P2 (embossed or hammered pattern portion) is set in the direction of the intersection of the first part VSSL_P1 and the third part VSSL_P3 connects the first part VSSL_P1 to the second part VSSL_P2. The patterned portion VDDL_P of the high-potential voltage line VDDL may include the portion extending from the second pad area PA2 toward the display area DA (see...). Figure 1 The first part of VDDL_P1 extends from the first part of VDDL_P1 along the path from the second pad area PA2 toward the display area DA (see...). Figure 1The second part VDDL_P2 is set in the direction of the intersection of the first part VDDL_P1 and the third part VDDL_P3 connects the first part VDDL_P1 to the second part VDDL_P2. For example, from the second pad area PA2 toward the display area DA (see... Figure 1 The direction can be the second direction DR2, and is the same as the direction from the second pad area PA2 toward the display area DA (see...). Figure 1 The direction of the intersection can be the first direction DR1, but it should be understood that these directions are relative concepts. That is, the first direction DR1 and the second direction DR2 are merely directions and can be used interchangeably. Since the pattern arrangement portion VDDL_P of the high-potential voltage line VDDL has the same structure as the pattern arrangement portion VSSL_P of the low-potential voltage line VSSL, the following description will focus on the pattern arrangement portion VSSL_P.

[0136] The second part VSSL_P2 (or embossed pattern) can have a circular (or elliptical) shape. The second part VSSL_P2 can also have an embossed shape. The width of the second part VSSL_P2 in the second direction DR2 can be greater than the width of the third part VSSL_P3 in the second direction DR2. According to this specification, the second part VSSL_P2 and the third part VSSL_P3 can be configured to protrude from the first part VSSL_P1 in the first direction DR1 to increase the moisture penetration path along the low-potential voltage line VSSL, thereby delaying moisture penetration.

[0137] Each of the second part VSSL_P2 and the third part VSSL_P3 can be set at both one end (or the other end on the first direction DR1) and the other end (or one end on the first direction DR1) of the first part VSSL_P1. That is, each of the second part VSSL_P2 and the third part VSSL_P3 can be set at both ends of the first part VSSL_P1.

[0138] The first part (VSSL_P1) to the third part (VSSL_P3) of the pattern layout section VSSL_P can all be placed on the same layer and can include the same material. Similarly, the first part (VDDL_P1) to the third part (VDDL_P3) of the pattern layout section VDDL_P can all be placed on the same layer and can include the same material. The pattern layout sections VSSL_P and VDDL_P can be placed on the same layer as the 1-2 line sections VSSL1b and VDDL1b, respectively.

[0139] The low-potential voltage line VSSL and the high-potential voltage line VDDL can each include a second line portion VSSL2 and VDDL2, respectively. The second line portions VSSL2 and VDDL2 can be directly connected to the pattern arrangement portions VSSL_P and VDDL_P, respectively. The second line portion VSSL2 of the low-potential voltage line VSSL can include a 2-1 line portion VSSL2a and a 2-2 line portion VSSL2b on the 2-1 line portion VSSL2a, and the second line portion VDDL2 of the high-potential voltage line VDDL can include a 2-1 line portion VDDL2a and a 2-2 line portion VDDL2b on the 2-1 line portion VDDL2a. The 2-1 line portion VSSL2a can be disposed on the same layer as the 1-1 line portion VSSL1a, the 2-2 line portion VSSL2b can be disposed on the same layer as the 1-2 line portion VSSL1b or the patterned portion VSSL_P, the 2-1 line portion VDDL2a can be disposed on the same layer as the 1-1 line portion VDDL1a, and the 2-2 line portion VDDL2b can be disposed on the same layer as the 1-2 line portion VDDL1b or the patterned portion VDDL_P. Holes H passing through the 2-2 line portions VSSL2b and VDDL2b in the thickness direction can be formed in the 2-2 line portions VSSL2b and VDDL2b. Multiple holes H can be provided. Holes H can completely pass through the 2-2 line portions VSSL2b and VDDL2b in the thickness direction. Gas generated within the first protective layer 111 can be discharged to the outside via the holes H.

[0140] like Figure 7 As shown, dam 154 can cover the second part VSSL_P2 and VDDL_P2, which is positioned closest to the display area DA (see...). Figure 1 That is, the dam 154 can be positioned on the second direction DR2 of the second part VSSL_P2 and VDDL_P2 as closest to the display area DA (see...). Figure 1 On one side of the portion, but except for the dam DAM and the second stop ST2, the dike 154 may not be set on the second part VSSL_P2 and VDDL_P2 in the second direction DR2 closest to the display area DA (see Figure 1 On the other side of the part.

[0141] Figure 8 It is along Figure 7 A cross-sectional view of line D-D' in the diagram.

[0142] Reference Figure 8 At least one of insulating layers 102, 103, 104, 105-1, 105-2, 106, 108 and 109 may be disposed on substrate 101.

[0143] Line 1-1 portion VSSL1a and line 2-1 portion VSSL2a can be disposed on the sixth insulating layer 109. Line 1-1 portion VSSL1a and line 2-1 portion VSSL2a can be coupled with... Figure 6 The first source electrode 121 is disposed on the same layer. Line 1-1 portion VSSL1a and line 2-1 portion VSSL2a can be disposed in the main region MR.

[0144] The first protective layer 111 can be set on the 1-1 line portion VSSL1a and the 2-1 line portion VSSL2a.

[0145] The 1-2 line portion VSSL1b, the first portion VSSL_P1, and the 2-2 line portion VSSL2b can be set on the first protection layer 111. The 1-2 line portion VSSL1b, the first portion VSSL_P1, and the 2-2 line portion VSSL2b can be... Figure 6 The connecting electrode 145 is disposed on the same layer. The 1-2 line portion VSSL1b can be disposed in the main region MR and on the underlying first protective layer 111. The 2-2 line portion VSSL2b can be disposed in the main region MR and the underlying first protective layer 111.

[0146] The 1-2 line portion VSSL1b and the 2-2 line portion VSSL2b may include holes H passing through the 1-2 line portion VSSL1b and the 2-2 line portion VSSL2b in the thickness direction. Gas generated within the first protective layer 111 can be discharged to the outside via the holes H.

[0147] The first part VSSL_P1 can overlap with the second stop part ST2 and the dam DAM.

[0148] The second protective layer 112 can be disposed on the 1-2 line portion VSSL1b, the first portion VSSL_P1, and the 2-2 line portion VSSL2b. The second protective layer 112 can be disposed in the main region MR and can overlap with the first portion VSSL_P1. The second protective layer 112 can form the first layer of the dam DAM and the second stop ST2. The dam DAM and the second stop ST2 can each be disposed in the bending region BR (see...). Figure 1The first protective layer 112 can be disposed between the first stop ST1 and the display area, and the dam DAM can be disposed between the second stop ST2 and the bending area BR. The second protective layer 112 can overlap with the 1-2 line portion VSSL1b and the 2-2 line portion VSSL2b, and fill the hole H to directly contact the first protective layer 111. The second protective layer 112 can form the first layer of the first stop ST1, the first layer of the second stop ST2, and the first layer of the dam DAM. The first stop ST1 can be disposed between the second stop ST2 and the display area. The first stop ST1 can overlap with the first line portion VSSL1. Near the first line portion VSSL1, the second protective layer 112 can completely cover the first protective layer 111, and the end of the second protective layer 112 can be positioned between the end of the first protective layer 111 and the end of the dam 154.

[0149] Dike 154 can be disposed on the second protective layer 112. Dike 154 can be disposed in the main region MR and can overlap with the first part VSSL_P1. Dike 154 can form a second layer consisting of dam DAM, first stop ST1 and second stop ST2. Near the first line part VSSL1, dike 154 can completely cover the second protective layer 112.

[0150] Spacer 155 can be disposed on dam 154. Spacer 155 can be disposed in main region MR and can overlap with first part VSSL_P1. Spacer 155 can form a third layer of dam DAM, first stop ST1 and second stop ST2.

[0151] The first encapsulation layer 171 can be disposed on the spacer 155. The first encapsulation layer 171 can be disposed in the main region MR and can be in direct contact with the upper surface of the dam 154 and the third layer of each of the first stop ST1, the second stop ST2 and the dam DAM.

[0152] The second encapsulation layer 172 may be disposed on the first encapsulation layer 171. The second encapsulation layer 172 may terminate at the first stop ST1, but various embodiments of this specification are not limited thereto.

[0153] The third encapsulation layer 173 can be disposed on the second encapsulation layer 172. The third encapsulation layer 173 can directly contact the first encapsulation layer 171 on the upper surface of the first stop ST1, the upper surface of the second stop ST2, the upper surface of the dam DAM, between the first stop ST1 and the second stop ST2, and between the second stop ST2 and the dam DAM.

[0154] The touch buffer layer 181 and the first touch insulating layer 183 can be disposed in the main region MR. The touch buffer layer 181 and the first touch insulating layer 183 can overlap with the first stop ST1, the second stop ST2 and the dam DAM.

[0155] The second touch insulating layer 184 can be disposed on the first touch insulating layer 183. The upper organic layer 190 can be disposed on the second touch insulating layer 184.

[0156] Figure 9 It is along Figure 7 A cross-sectional view of line E-E' in the diagram.

[0157] exist Figure 9 The description will omit references to the already referenced items. Figure 8 Repeated description of the described part.

[0158] Reference Figure 9 The second part, VSSL_P2, can be positioned between the sixth insulating layer 109 and the second protective layer 112 of the dam DAM. The second part, VSSL_P2, can be... Figure 8 The first part of VSSL_P1 is disposed on the same layer. The second part VSSL_P2, located at the leftmost and rightmost positions, may not overlap with the first protective layer 111 and the second protective layer 112, and a portion of the second part VSSL_P2 located at the leftmost position may be covered by the dike 154. That is, a portion of the second part VSSL_P2 located at the leftmost position may be in direct contact with the dike 154. Therefore, the stress applied to the second part VSSL_P2 can be reduced. However, the second part VSSL_P2 located at the rightmost position may not overlap with the first protective layer 111, the second protective layer 112, or the dike 154.

[0159] The dam DAM and the adjacent second portion VSSL_P2 can overlap each other. In the overlapping area of ​​the dam DAM, one end portion of the second portion VSSL_P2 can be covered by the dam DAM, but the exposed portion of the dam DAM can directly contact the first encapsulation layer 171. In the area where the dam DAM is not provided, the side and top surfaces of the second portion VSSL_P2 can directly contact the first encapsulation layer 171.

[0160] As described above, the molding department MDP (see Figure 3 The encapsulation layers 171 and 173 of the display panel 100 are in direct contact with the non-display area NDA of the display panel 100 and deform significantly (expand or contract) in response to heat, thereby positioning the display panel 100 within the encapsulation layers 171 and 173 of the non-display area NDA (see See). Figure 9 Cracks appeared in it.

[0161] Cracks generated in encapsulation layers 171 and 173 can be applied to the second portion VSSL_P2, which is in direct contact with the first encapsulation layer 171 in the non-display area NDA. However, according to one embodiment, by covering the second portion VSSL_P2, which is located at the leftmost point where crack propagation begins, the stress applied to the second portion VSSL_P2 can be reduced, and crack propagation can be prevented.

[0162] Other embodiments will be described below. In the following description of the embodiments, references to previously mentioned embodiments will be omitted. Figures 1 to 9 A detailed description of the components or contents being described.

[0163] Figure 10 This is a plan view of a display panel according to yet another embodiment. Figure 11 It is along Figure 10 A cross-sectional view of line F-F' in the diagram. Figure 12 yes Figure 11 Enlarged cross-sectional view of region Q2 in the image.

[0164] Reference Figures 10 to 12 The display panel 100_1 according to this embodiment and according to Figure 7 The difference of the display panel 100 is that the display panel 100_1 also includes a first overlay pattern CVP1.

[0165] More specifically, the first overlay pattern CVP1 can be provided as multiple first overlay patterns. The multiple first overlay patterns CVP1 can overlap with the second part VSSL_P2.

[0166] For example, a second portion VSSL_P2 of the pattern arrangement of the low-potential voltage line VSSL_P can be disposed at both ends of the first portion VSSL_P1. The second portions VSSL_P2 located at the other end of the first portion VSSL_P1 in the first direction DR1 can be spaced apart from each other in the second direction DR2 (or column direction), and the second portions VSSL_P2 located at one end of the first portion VSSL_P1 in the first direction DR1 can also be spaced apart from each other in the second direction DR2 (or column direction). Any one of the first overlay patterns CVP1 can cover the second portion VSSL_P2 located at the other end of the first portion VSSL_P1 in the first direction DR1. The other of the first overlay patterns CVP1 can cover the second portion VSSL_P2 located at one end of the first portion VSSL_P1 in the first direction DR1.

[0167] For example, a second portion VDDL_P2 of the pattern arrangement of the high-potential voltage line VDDL_P can be disposed at both ends of the first portion VDDL_P1. The second portions VDDL_P2 located at the other end of the first portion VDDL_P1 in the first direction DR1 can be spaced apart from each other in the second direction DR2 (or column direction), and the second portions VDDL_P2 located at one end of the first portion VDDL_P1 in the first direction DR1 can also be spaced apart from each other in the second direction DR2 (or column direction). Any one of the first overlay patterns CVP1 can cover the second portion VDDL_P2 located at the other end of the first portion VDDL_P1 in the first direction DR1. The other of the first overlay patterns CVP1 can cover the second portion VDDL_P2 located at one end of the first portion VDDL_P1 in the first direction DR1.

[0168] Each of the first covering patterns CVP1 may overlap with the first stop ST1 and the dam DAM, but may not overlap with the second stop ST2. Each of the first covering patterns CVP1 may overlap with portions of the first parts VSSL_P1 and VDDL_P1 and the third parts VSSL_P3 and VDDL_P3.

[0169] Adjacent first overlay patterns CVP1 can be configured to be spaced apart from each other in the first direction DR1.

[0170] like Figure 11 As shown, the first overlay pattern CVP1 can be disposed between the second protective layer 112 and the dam 154, and can extend to directly contact the plurality of second portions VSSL_P2. The first overlay pattern CVP1 contacting each second portion VSSL_P2 can directly contact the first encapsulation layer 171. On the dam DAM, the first overlay pattern CVP1 can be disposed between the lower first layer and the upper second layer.

[0171] The first covering pattern CVP1 can be with Figure 6 The first electrode 151 is positioned on the same layer.

[0172] like Figure 12 As shown, the second part VSSL_P2 includes a first layer L1, a second layer L2 on the first layer L1, and a third layer L3 on the second layer L2, and the first overlay pattern CVP1 can directly contact each of the first layer L1, the second layer L2, and the third layer L3.

[0173] The first layer L1 and the third layer L3 may contain the same material, and the material of the first layer L1 may be different from the material of the second layer L2. For example, each of the first layer L1 and the third layer L3 may contain titanium (Ti), and the second layer L2 may contain aluminum (Al), but the various embodiments described herein are not limited thereto.

[0174] The ends of the first layer L1 and the third layer L3 may protrude further outward than the ends of the second layer L2. The first overlay pattern CVP1 may contact the upper, side, and lower surfaces of the third layer L3, which protrudes further outward than the ends of the second layer L2, may contact the side surface of the second layer L2, and may directly contact the upper and side surfaces of the first layer L1, which protrudes further outward than the ends of the second layer L2.

[0175] When the first overlay pattern CVP1 is not provided, cracks may appear in the first encapsulation layer 171 due to the tips formed by the first layer L1 to the third layer L3 (the ends of the first layer L1 and the third layer L3 protrude outwards than the ends of the second layer L2).

[0176] However, according to various embodiments of this specification, the first overlay pattern CVP1 may cover the tip, thereby preventing not only cracks in the first encapsulation layer 171, but also cracks in the embossed pattern or reducing the stress applied to the embossed pattern.

[0177] As mentioned above Figure 7 and Figure 9 The remaining components have been described, so their detailed descriptions will be omitted below.

[0178] Figure 13 This is a plan view of a display panel according to another embodiment. Figure 14 It is along Figure 13 A cross-sectional view of line G-G' in the diagram.

[0179] Reference Figure 13 and Figure 14 The display panel 100_2 according to this embodiment and according to Figure 11 and Figure 12 The difference between the display panel 100_1 and the display panel 100_2 is that the display panel 100_2 also includes a second overlay pattern CVP2.

[0180] More specifically, the second overlay pattern CVP2 can cover: the first overlay pattern CVP1 of the second portion VSSL_P2 located at one end of the first portion VSSL_P1 in the first direction DR1; and the first overlay pattern CVP1 of the second portion VDDL_P2 located at the other end of the first portion VDDL_P1 in the first direction DR1. The second overlay pattern CVP2 can also be disposed between the first overlay pattern CVP1 covering the second portion VSSL_P2 located at one end of the first portion VSSL_P1 in the first direction DR1 and the first overlay pattern CVP1 covering the second portion VDDL_P2 located at the other end of the first portion VDDL_P1 in the first direction DR1.

[0181] The second overlay pattern CVP2 may overlap with the first stop ST1 and the dam DAM, and also overlap with a portion of the second stop ST2.

[0182] The second overlay pattern CVP2 can be disposed between the first touch insulating layer 183 and the second touch insulating layer 184, and can be combined with... Figure 6 The first touch electrode 185 is positioned on the same layer, but various embodiments of this specification are not limited thereto.

[0183] According to various embodiments of this specification, cracks in the second portion VSSL_P2 can be prevented, or the stress applied to the embossed pattern can be reduced, by including a second overlay pattern CVP2 covering the second portion VSSL_P2.

[0184] As mentioned above Figure 10 and Figure 11 The remaining components have been described, so their detailed descriptions will be omitted below.

[0185] According to various embodiments of this specification, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area; voltage lines disposed in the non-display area on the substrate; and a dam surrounding the voltage lines, wherein the voltage lines include: a first portion extending along a first direction; and a second portion positioned from the first portion along a second direction intersecting the first direction and having a curved shape, the second portions being provided as a plurality of second portions, the plurality of second portions being disposed spaced apart from each other in the first direction, and a second portion of the plurality of second portions disposed near the display area being covered by the dam.

[0186] In the display device according to various embodiments of this specification, the voltage line may further include a third portion connecting the first portion to the second portion, and the width of the second portion in the first direction may be greater than the width of the third portion in the first direction.

[0187] In the display device according to various embodiments of this specification, the second part may be disposed on one side of the first part in the second direction and on the other side of the first part in the second direction.

[0188] In the display device according to various embodiments of this specification, the voltage line may include a high-potential voltage line or a low-potential voltage line.

[0189] In the display device according to various embodiments of this specification, the non-display area may include a pad area provided with power pads, and each of the first portion and the second portion may be disposed between the pad area and the display area.

[0190] The display device according to various embodiments of this specification may further include a dam, which comprises at least one organic material and extends along a second direction, wherein the dam may overlap with a second portion and a first portion adjacent in the second direction.

[0191] In the display device according to various embodiments of this specification, the dam may extend continuously along a second direction.

[0192] The display device according to various embodiments of this specification may further include a first stop portion between the dam and the display area, wherein the first stop portion may extend in a second direction and include at least one organic material.

[0193] The display device according to various embodiments of this specification may further include a second stop portion between the first stop portion and the dam, wherein the second stop portion may include at least one organic material, and the second stop portion may overlap with the first portion and may be disposed between adjacent second portions in a second direction.

[0194] In the display device according to various embodiments of this specification, at least one organic material may include at least one of a protective layer, a dam, and a spacer.

[0195] In the display device according to various embodiments of this specification, the protective layer may include a first protective layer on the substrate and a second protective layer between the first protective layer and the dam, and the end of the second protective layer may be positioned between the end of the dam and the end of the first protective layer.

[0196] According to various embodiments of this specification, a display device is provided, the display device comprising: a substrate including a display area and a non-display area surrounding the display area; voltage lines disposed on the non-display area of ​​the substrate; a first overlay pattern; a dam overlapping the voltage lines; a first stop portion between the dam and the display area; and a second stop portion between the first stop portion and the dam, wherein the voltage lines include: a first portion extending along a first direction; and a second portion positioned from the first portion along a second direction intersecting the first direction and having a curved shape, the second portions being provided as a plurality of second portions, the plurality of second portions being disposed spaced apart from each other in the first direction, the dam and the first stop portion extending continuously along the second direction, the second stop portions overlapping the first portions and being disposed between adjacent second portions in the second direction, and the first overlay pattern overlapping the plurality of second portions disposed spaced apart from each other in the first direction.

[0197] The display device according to various embodiments of this specification may further include a light-emitting portion disposed in a display area on a substrate, wherein the light-emitting portion may include a first electrode, an organic layer on the first electrode, and a second electrode on the organic layer, and the first overlay pattern may be disposed on the same layer as the first electrode.

[0198] In the display device according to various embodiments of this specification, the first overlay pattern may be in direct contact with the second portion.

[0199] In the display device according to various embodiments of this specification, the second part may include a first layer, a second layer on the first layer, and a third layer on the second layer. A first overlay pattern may contact each of the first, second, and third layers. The first and third layers may include the same material, and the material of the first layer may be different from the material of the second layer.

[0200] In the display device according to various embodiments of this specification, the first overlay pattern may overlap with the first stop and the dam, but may not overlap with the second stop.

[0201] In the display device according to various embodiments of this specification, the voltage line may include a first voltage line and a second voltage line spaced apart from the first voltage line in a second direction. The first voltage line may be a low-potential voltage line, and the second voltage line may be a high-potential voltage line.

[0202] In the display device according to various embodiments of this specification, the second portion of each of the first voltage line and the second voltage line may be provided on one side of the first portion in the second direction and on the other side of the first portion in the second direction.

[0203] The display device according to various embodiments of this specification may further include a second overlay pattern overlapping a plurality of second portions positioned on one side of the first voltage line in a second direction and a plurality of second portions positioned on the other side of the second voltage line in a second direction.

[0204] In the display device according to various embodiments of this specification, the second overlay pattern may overlap with the first stop, a portion of the second stop, and the dam.

[0205] In the display device according to various embodiments of this specification, the voltage line may further include a third portion connecting the first portion to the second portion, and the width of the second portion in the first direction may be greater than the width of the third portion in the first direction.

[0206] In the display device according to various embodiments of this specification, the non-display area may include a pad area provided with power pads, and each of the first portion and the second portion may be disposed between the pad area and the display area.

[0207] According to various embodiments of this specification, the moisture penetration path can be increased by making the embossed (or arc-shaped) second portion protrude in a direction that intersects the extension direction of the high-potential voltage line or low-potential voltage line located in the non-display area.

[0208] According to various embodiments of this specification, the stress applied to the embossed pattern can be reduced by partially covering the embossed pattern (or hammered pattern portion or second portion) near the display area using a dike.

[0209] According to various embodiments of this specification, by including a first covering pattern and / or a second covering pattern covering the embossed pattern, cracks in the embossed pattern can be prevented, or the stress applied to the embossed pattern can be reduced.

[0210] According to various embodiments of this specification, cracks in the first encapsulation layer can be prevented by including a first overlay pattern covering the embossed pattern.

[0211] According to various embodiments of this specification, a low-power display device capable of extending lifespan can be provided.

[0212] However, the effects that can be obtained from this specification are not limited to those described above, and those skilled in the art to which this specification pertains will be able to clearly understand other effects not described based on the following description.

[0213] Although various embodiments of this disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that the above-described technical configurations of this disclosure can be implemented in other specific forms without altering the technical spirit or essential characteristics of this disclosure. Therefore, it should be understood that the above embodiments are illustrative in all respects and not restrictive. Furthermore, the scope of this disclosure is described by the appended claims, rather than a detailed description. Additionally, the meaning and scope of the claims, as well as all changes or modifications derived from equivalent concepts, should be interpreted as being included within the scope of this disclosure.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area; Voltage lines disposed in the non-display area on the substrate; as well as The dike surrounding the voltage line, The voltage line includes: The first portion extending in the first direction; and The second portion is positioned along a second direction intersecting the first direction and has a curved shape from the first portion. The second part is provided as a plurality of second parts, the plurality of second parts being arranged to be spaced apart from each other in the first direction, and The second portion of the plurality of second portions located near the display area is covered by the dike.

2. The display device according to claim 1, wherein, The voltage line further includes a third portion connecting the first portion to the second portion, wherein the width of the second portion in the first direction is greater than the width of the third portion in the first direction.

3. The display device according to claim 1, wherein, The second part is disposed on one side of the first part in the second direction and on the other side of the first part in the second direction.

4. The display device according to claim 1, wherein, The voltage lines include high-potential voltage lines or low-potential voltage lines.

5. The display device according to claim 1, wherein, The non-display area includes a pad area with power pads, and each of the first portion and the second portion is disposed between the pad area and the display area.

6. The display device according to claim 1, further comprising: A dam comprising at least one organic material and extending along the second direction, wherein the dam overlaps with the second portion and the first portion adjacent in the second direction.

7. The display device according to claim 6, wherein, The dam extends continuously along the second direction.

8. The display device according to claim 6, further comprising: A first stop portion between the dam and the display area, wherein the first stop portion extends along the second direction and includes the at least one organic material.

9. The display device according to claim 8, further comprising: A second stop portion between the first stop portion and the dam, wherein the second stop portion comprises the at least one organic material, and the second stop portion overlaps with the first portion and is disposed between adjacent second portions in the second direction.

10. The display device according to claim 6, wherein, The at least one organic material includes at least one of the protective layer, the dike, and the spacer.

11. The display device according to claim 10, wherein, The protective layer includes a first protective layer on the substrate and a second protective layer between the first protective layer and the dike, with the end of the second protective layer positioned between the end of the dike and the end of the first protective layer.

12. A display device, comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area; Voltage lines disposed in the non-display area on the substrate; First overlay pattern; A dam overlapping with the voltage line; A first stop between the dam and the display area; as well as The second stop between the first stop and the dam. The voltage line includes: The first portion extending in the first direction; and The second portion is positioned along a second direction intersecting the first direction and has a curved shape from the first portion. The second part is provided as a plurality of second parts, the plurality of second parts being arranged to be spaced apart from each other in the first direction. The dam and the first stop extend continuously along the second direction. The second stop overlaps with the first portion and is disposed between adjacent second portions in the second direction. The first overlay pattern overlaps with the plurality of second portions that are spaced apart from each other in the first direction.

13. The display device according to claim 12, further comprising: The light-emitting portion is disposed in the display area on the substrate, wherein the light-emitting portion includes a first electrode, an organic layer on the first electrode, and a second electrode on the organic layer, and the first overlay pattern is disposed on the same layer as the first electrode.

14. The display device according to claim 12, wherein, The first overlay pattern is in direct contact with the second portion, wherein the second portion comprises a first layer, a second layer on the first layer, and a third layer on the second layer, the first overlay pattern being in contact with each of the first layer, the second layer, and the third layer, the first layer and the third layer comprising the same material, and the material of the first layer being different from the material of the second layer.

15. The display device according to claim 12, wherein, The first covering pattern overlaps with the first stop and the dam, but does not overlap with the second stop.

16. The display device according to claim 12, wherein, The voltage line includes a first voltage line and a second voltage line spaced apart from the first voltage line in the second direction, wherein the first voltage line is a low-potential voltage line and the second voltage line is a high-potential voltage line.

17. The display device according to claim 16, wherein, The second portion of each of the first voltage line and the second voltage line is disposed on one side of the first portion in the second direction and on the other side of the first portion in the second direction.

18. The display device according to claim 17, further comprising: A second covering pattern that overlaps with a plurality of second portions located on one side of the first voltage line in the second direction and a plurality of second portions located on the other side of the second voltage line in the second direction, wherein the second covering pattern overlaps with the first stop portion, a portion of the second stop portion and the dam.

19. The display device according to claim 12, wherein, The voltage line further includes a third portion connecting the first portion to the second portion, wherein the width of the second portion in the first direction is greater than the width of the third portion in the first direction.

20. The display device according to claim 12, wherein, The non-display area includes a pad area with power pads, and each of the first portion and the second portion is disposed between the pad area and the display area.

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