A three-dimensional low-temperature packaging structure for a superconducting quantum chip and a manufacturing method thereof

Abstract

This invention discloses a three-dimensional cryogenic packaging structure for superconducting quantum chips and its manufacturing method, comprising a superconducting quantum chip layer, a superconducting interconnect redistribution layer, a centrally located thermal anchor shielding composite layer, a cryogenic signal transfer layer, and a cryogenic packaging substrate layer, stacked or partially nested along the thickness direction; the centrally located thermal anchor shielding composite layer includes a high thermal conductivity thermal anchor skeleton, a superconducting electromagnetic shielding network, a parasitic mode suppression unit, and a cryogenic stress relief structure; a thermal path and signal path decoupling structure is formed within the centrally located thermal anchor shielding composite layer, wherein the thermal path is connected to the cryogenic packaging substrate layer, and the signal path is connected to the cryogenic signal transfer layer; the thermal path, signal path, electromagnetic shielding path, parasitic mode suppression path, and stress relief path are coordinated and configured within the same composite layer according to spatial partitioning and functional coupling relationships.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional integrated packaging technology for chips, specifically to a three-dimensional low-temperature packaging structure with a centrally located thermal anchor shielding composite layer for superconducting quantum chips and its manufacturing method. Background Technology

[0002] Superconducting quantum chips typically rely on Josephson junctions, superconducting resonant cavities, microwave control lines, readout lines, and magnetic flux bias lines to achieve quantum state manipulation and readout. Their operating temperature range is usually below 4K, with some systems requiring operation in the milliKelvin range. Compared to conventional integrated circuit packaging, superconducting quantum chip packaging not only needs to provide mechanical support, external leads, and chip protection, but also requires simultaneous control of thermal leakage, electromagnetic crosstalk, parasitic modes within the packaging cavity, magnetic flux noise, and low-temperature thermal stress. As the number of qubits increases, planar leads and traditional metal enclosure structures are increasingly unable to meet the combined requirements of high-density interconnection and low-loss, low-noise operation.

[0003] In existing cryogenic packaging solutions, metal housings or metal covers can provide a certain level of mechanical protection and electromagnetic shielding. Ball arrays, indium bumps, or multilayer transition substrates can increase interconnect density, while back-side electromagnetic shielding layers, shielding sealing rings, grounding via arrays, or package cavity protrusion structures can suppress cavity modes to some extent. However, these solutions typically optimize for one specific issue in thermal anchoring, shielding, interconnection, or parasitic modes, lacking a systematic structure that integrates a central composite layer between the chip layer and the cryogenic substrate layer, and coordinates thermal paths, signal paths, electromagnetic shielding, parasitic mode suppression, and cryogenic stress relief within the same layer.

[0004] In particular, in superconducting quantum chip packaging, thermal anchor structures typically require high thermal conductivity metals or ceramics to connect to a low-temperature cold end, while microwave signal paths demand low-loss media, impedance continuity, and stable grounding boundaries. If a high thermal conductivity metal structure is directly close to or crosses the microwave transmission line, it may introduce additional parasitic capacitance, local impedance mismatch, microwave field distortion, or increased loss. Conversely, if the thermal anchor structure is completely avoided to ensure signal integrity, it can lead to insufficient local thermalization of the chip and an increased temperature gradient. Existing technologies often handle thermal design and signal design separately, making it difficult to balance both within limited package thickness and low-temperature thermal budgets.

[0005] Furthermore, parasitic modes within the packaging cavity and low-temperature stress also have coupled effects. To suppress parasitic modes, existing solutions typically employ methods such as package geometry adjustments, grounding protrusions, shielding cavities, or absorbing materials; to alleviate low-temperature thermal stress, flexible gaskets, release grooves, or material matching methods are commonly used. If these structures are arranged independently, they will occupy packaging space and may disrupt shielding continuity or reduce thermal connection efficiency. Therefore, a three-dimensional cryogenic packaging structure is needed that integrates thermal anchors, electromagnetic shielding, parasitic mode suppression, and low-temperature stress release in a central composite layer, while simultaneously spatially decoupling the thermal path from the signal path. Summary of the Invention

[0006] The purpose of this invention is to address the problems of large packaging space, mutual interference between thermal and signal paths, insufficient local thermalization capability, high microwave crosstalk, and difficulty in releasing low-temperature thermal stress caused by the dispersed design of thermal anchoring, interconnection, shielding, parasitic mode suppression, and stress release in existing superconducting quantum chip packaging. The invention provides a three-dimensional low-temperature packaging structure for superconducting quantum chips and its manufacturing method.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: In a first aspect, a three-dimensional cryogenic packaging structure for superconducting quantum chips is provided, comprising a superconducting quantum chip layer, a superconducting interconnect redistribution layer, a centrally located thermal anchor shielding composite layer, a cryogenic signal transfer layer, and a cryogenic packaging substrate layer, stacked or partially nested along the thickness direction; the centrally located thermal anchor shielding composite layer includes a high thermal conductivity thermal anchor skeleton, a superconducting electromagnetic shielding network, a parasitic mode suppression unit, and a cryogenic stress relief structure; a thermal path and signal path decoupling structure is formed within the centrally located thermal anchor shielding composite layer, wherein the thermal path is connected to the cryogenic packaging substrate layer, and the signal path is connected to the cryogenic signal transfer layer; the parasitic mode suppression unit is an inherent component of the centrally located thermal anchor shielding composite layer and electrically connected to the superconducting electromagnetic shielding network; the cryogenic stress relief structure is disposed around the boundary region of the high thermal conductivity thermal anchor skeleton.

[0008] In some embodiments, the superconducting quantum chip layer is located on top of the package or inside the package near the cap, and includes a superconducting quantum bit, a Josephson junction, a readout resonant cavity, a microwave control line, a magnetic flux bias line, and a grounding structure; the high thermal conductivity anchor frame is arranged in a region outside the sensitive area of ​​the superconducting quantum bit.

[0009] In some embodiments, the superconducting electromagnetic shielding network includes a superconducting grounding layer, a superconducting grounding via array, an annular superconducting shielding groove, a gridded superconducting shielding wire, or a combination thereof. The material of the superconducting electromagnetic shielding network includes one or more composite films selected from aluminum, niobium, niobium nitride, niobium titanium nitride, and tantalum. The high thermal conductivity anchor skeleton is a composite structure selected from one or more of metallized diamond, aluminum nitride, silicon carbide, high-purity copper, molybdenum copper alloy, and copper tungsten alloy.

[0010] In some embodiments, the parasitic mode suppression unit includes a periodic electromagnetic bandgap structure, a grounding hole array structure, an annular grounding groove structure, a stepped impedance structure, an absorption cavity structure, or a combination thereof; the low-temperature stress relief structure includes an annular relief groove, a segmented relief groove, a serpentine flexible bridge, a locally thinned region, a gradient thermal expansion transition region, or a flexible metal buffer layer.

[0011] In some embodiments, the superconducting interconnect redistribution layer is used to convert two-dimensional wiring on the chip surface into vertical interconnects or edge interconnects suitable for three-dimensional packaging, including superconducting microbumps, superconducting vertical vias, a superconducting redistribution layer, a low-loss dielectric layer, and a ground reference layer. The superconducting microbumps are indium bumps, aluminum bumps, niobium bumps, indium tin alloy bumps, or composite bumps thereof.

[0012] In some embodiments, the low-temperature packaging substrate layer is provided with a thermal connection interface that connects to the cold end of the mixing chamber of the dilution refrigerator, the cold plate, or the low-temperature sample stage. The thermal connection interface includes a metallized contact surface, a screw pressing surface, an indium sheet thermal interface layer, a sintered metal layer, or an elastic pressing structure.

[0013] In some embodiments, the thermal path and the signal path are spatially decoupled through a low-loss dielectric isolation region, a ground reference layer, a superconducting ground via array, or a clearance gap; wherein the minimum spacing between the high thermal conductivity anchor frame and the microwave transmission line in the chip is not less than 50 μm, or the via spacing of the superconducting ground via array is not greater than twice the width of the microwave transmission line.

[0014] Secondly, a method for manufacturing a three-dimensional low-temperature packaging structure for superconducting quantum chips is provided, the method comprising the following steps: Obtain the qubit layout, readout line layout, control line layout, allowable thermal budget, and operating frequency band of the superconducting quantum chip layer; Determine the initial parameters of the thermal path, signal path, superconducting electromagnetic shielding network, parasitic mode suppression unit, and low-temperature stress release structure in the centrally located thermal anchor shielding composite layer; Determining packaging structure parameters based on thermo-electromagnetic-mechanical collaborative constraints; Prepare the centrally located heat anchor shielding composite layer according to the determined packaging structure parameters; A superconducting interconnect rewiring layer and a low-temperature signal transfer layer are formed above and below the centrally located thermal anchor shielding composite layer; The superconducting quantum chip layer is low-temperature compatiblely bonded to the centrally placed thermal anchor shielding composite layer; Install the capping layer and form a cryogenic encapsulation cavity; Low-temperature thermal cycling, microwave S-parameters, interconnect continuity, and warpage tests were conducted.

[0015] Furthermore, when determining the packaging structure parameters, a thermo-electromagnetic-mechanical coupling simulation model is established with thermal leakage, temperature gradient, insertion loss, crosstalk, parasitic mode frequency, low-temperature warpage, and interconnect stress as optimization objectives. The thermo-electromagnetic-mechanical coupling simulation model is constructed based on the finite element method, boundary element method, transmission line model, or a combination thereof, and the structural parameters of the centrally located thermal anchor shielding composite layer are determined by parameter scanning.

[0016] Furthermore, the process temperature for the low-temperature compatible bonding is no higher than 200°C. The low-temperature test includes measuring the cold end heat flow, chip area temperature rise, microwave S-parameters, parasitic mode frequency shift, warpage, and microbump resistance changes in the temperature range of 4K or below, and the test results are used to correct the parameters of the next batch of centrally located thermal anchor shielding composite layers.

[0017] Thirdly, a superconducting quantum computing system is also provided, including a dilution refrigerator, a cryogenic control readout module, and a three-dimensional cryogenic packaging structure as described above; the three-dimensional cryogenic packaging structure is installed at the cold end of the dilution refrigerator, and the cryogenic control readout module is connected to the superconducting quantum chip layer through the cryogenic signal transfer layer.

[0018] Compared with existing technologies, the beneficial effects of this invention are: 1. Integrating the thermal anchor skeleton, superconducting shielding network, parasitic mode suppression unit, and stress relief structure in the same central thermal anchor shielding composite layer transforms the dispersed arrangement of each functional structure into a collaborative arrangement, reducing the space occupied by the low-temperature packaging; 2. By spatially decoupling the thermal path from the signal path, the thermal efficiency of the chip area towards the cold end is ensured, while reducing the influence of high thermal conductivity metal on the impedance, loss, and field distribution of microwave transmission lines; 3. The superconducting electromagnetic shielding network and the high thermal conductivity thermal anchor skeleton can partially share the grounding and thermal diffusion boundaries, keeping the shielding structure in a more stable low-temperature state and reducing local performance fluctuations caused by the temperature gradient of the shielding network; 4. The parasitic mode suppression unit, as an inherent structure of the central composite layer rather than an external packaging box structure, can suppress the mode formation area close to the packaging, facilitating composite design with grounding vias, annular shielding grooves, and release grooves; 5. The annular grounding groove can also serve as a stress relief groove, and the low-loss dielectric isolation area can also serve as a thermal-electric isolation and flexible buffer area, thereby achieving multi-functionality in one structure and improving the freedom of packaging design and manufacturing compatibility. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of each layer of a three-dimensional low-temperature packaging structure for superconducting quantum chips according to the present invention. It shows the thickness direction relationship of the superconducting quantum chip layer, the superconducting interconnect redistribution layer, the centrally located thermal anchor shielding composite layer, the low-temperature signal transfer layer and the low-temperature packaging substrate layer, as well as the overall direction of the thermal path and the signal path. Figure 2 This is a spatial decoupling diagram of the thermal path, signal path and isolation structure within the thermal anchor shielding composite layer of the present invention, showing the relative positions of the high thermal conductivity anchor skeleton, low loss dielectric isolation area, grounding through-hole array, annular release groove and microwave transmission line. Figure 3 This is a planar schematic diagram of the superconducting electromagnetic shielding network and parasitic mode suppression unit of the present invention, showing the layout relationship between the periodic electromagnetic bandgap structure, the annular grounding groove, the grounding via array, and the sensitive quantum region; Figure 4 This is a schematic diagram of the low-temperature stress relief structure of the present invention, showing the relative arrangement of the annular relief groove, the serpentine flexible bridge, the local thinning area, and the quantum chip projection area; Figure 5 This is a schematic flowchart illustrating the manufacturing method of the three-dimensional low-temperature packaging structure for superconducting quantum chips according to the present invention.

[0020] In the figure: 1. Superconducting quantum chip layer; 2. Superconducting interconnect redistribution layer; 3. Centrally placed thermal anchor shielding composite layer; 301, high thermal conductivity thermal anchor skeleton; 4. Low temperature signal transfer layer; 5. Low temperature packaging substrate layer; 6. Thermal path; 7. Signal path; 8. Superconducting grounding via array; 9. Microwave transmission line; 10. Annular release groove; 11. Quantum chip projection area; 12. Periodic electromagnetic bandgap structure. Detailed Implementation

[0021] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] In the description of this invention, it should be noted that the terms "middle", "upper", "lower", "left", "right", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0023] Example 1: A three-dimensional low-temperature packaging structure for superconducting quantum chips is provided, such as... Figure 1 and Figure 2 As shown, the system includes a superconducting quantum chip layer 1, a superconducting interconnect redistribution layer 2, a centrally located thermal anchor shielding composite layer 3, a low-temperature signal transfer layer 4, and a low-temperature packaging substrate layer 5, which are stacked or partially nested along the thickness direction. The centrally located thermal anchor shielding composite layer 3 includes a high thermal conductivity thermal anchor skeleton 301, a superconducting electromagnetic shielding network, a parasitic mode suppression unit, and a low-temperature stress relief structure. A decoupling structure for thermal path 6 and signal path 7 is formed within the centrally located thermal anchor shielding composite layer 3, wherein the thermal path 6 is connected to the low-temperature packaging substrate layer 5, and the signal path 7 is connected to the low-temperature signal transfer layer 4. The parasitic mode suppression unit is an inherent component of the centrally located thermal anchor shielding composite layer and is electrically connected to the superconducting electromagnetic shielding network. The low-temperature stress relief structure is arranged around the boundary region of the high thermal conductivity thermal anchor skeleton 301.

[0024] This three-dimensional cryogenic packaging structure does not simply involve stacking heat sinks, shielding layers, or release slots within the package. Instead, it employs a centrally located thermal anchor shielding composite layer between the superconducting quantum chip layer and the cryogenic packaging substrate layer. This allows the thermal path, signal path, electromagnetic shielding path, parasitic mode suppression path, and stress relief path to be collaboratively configured within the same composite layer according to spatial partitioning and functional coupling. The centrally located thermal anchor composite layer serves both as a heat dissipation function and a grounding shield boundary, while also suppressing parasitic modes and thermal stress within the packaging cavity.

[0025] The centrally located thermal anchor composite layer is situated between the superconducting quantum chip layer and the cryogenic packaging substrate layer. Its high thermal conductivity thermal anchor framework is used to guide heat from the chip edge, dense interconnect regions, or readout line convergence regions to the cryogenic cold end without directly traversing the sensitive region of the quantum bits. The superconducting electromagnetic shielding network is used to form a continuous or quasi-continuous low-impedance ground boundary, reducing external electromagnetic noise and internal crosstalk. The parasitic mode suppression unit is used to change the equivalent electromagnetic boundary conditions in the packaging cavity or transition layer, causing the parasitic resonant frequency to deviate from the quantum bit operating frequency band and readout frequency band, or to form bandgap suppression within the target frequency band. The cryogenic stress relief structure is used to absorb thermal expansion mismatch deformation during the cooling process from room temperature to cryogenic temperature, reducing additional stress in the microbumps, Josephson junction adjacent regions, and chip substrate.

[0026] To avoid disturbance to the microwave signal path caused by the high thermal conductivity metal structure, this invention forms a decoupled structure between the thermal path and the signal path within the central composite layer. The thermal path can be composed of a high thermal conductivity anchor frame, a heat diffusion layer, a metallized contact surface, a flexible metal buffer layer, and a cold-end thermal connection interface, and is connected to a cryogenic cold source. The signal path can be composed of superconducting micro-bumps, a superconducting redistribution layer, a low-loss dielectric layer, a microwave transmission line, a ground reference layer, and a cryogenic signal transition layer, and is connected to a cryogenic control readout module. A low-loss dielectric isolation region, a ground reference layer, a superconducting ground via array, or a clearance gap are provided between the thermal path and the signal path to allow the high thermal conductivity metal structure to avoid areas of concentrated microwave field strength, while maintaining the impedance continuity and grounding integrity of the microwave transmission line through the ground via array.

[0027] In this embodiment, the superconducting quantum chip layer refers to a chip layer on silicon, sapphire, gallium arsenide, silicon carbide, or other low-loss substrates on which superconducting qubits, Josephson junctions, readout resonant cavities, microwave control lines, magnetic flux bias lines, and grounding structures are formed. "Transmon" refers to a superconducting qubit structure that is relatively insensitive to charge noise; a Josephson junction is a nonlinear quantum circuit element formed by two superconducting electrodes and a thin insulating barrier; a dilution refrigerator refers to a refrigeration system capable of providing a low-temperature environment below 4K or even in the milliKelvin temperature range; EBG stands for electromagnetic band gap, which is used to suppress electromagnetic wave propagation or change local mode distribution within a specific frequency band.

[0028] The term "centralized" in the context of the centrally located thermal anchor shielding composite layer does not require its geometric center to perfectly coincide with the center of the overall package thickness. Rather, it emphasizes that the layer is situated between the superconducting quantum chip layer and the low-temperature packaging substrate layer, serving as an intermediary in the processes of thermal connection, signal transfer, and electromagnetic boundary formation. This composite layer can be a continuous plate-like structure, or a partially nested structure, an island-like structure, a frame structure, or a multi-material composite structure.

[0029] In some embodiments, the superconducting quantum chip layer is located on top of the package or inside the package near the cap, and includes superconducting quantum bits, a Josephson junction, a readout resonant cavity, microwave control lines, magnetic flux bias lines, and a grounding structure. The cryogenic packaging substrate layer is located at the bottom of the package and has a thermal interface connecting to the cold end of the mixing chamber of the dilution refrigerator, a cold plate, or a cryogenic sample stage. This thermal interface includes a metallized contact surface, a screw pressing surface, an indium thermal interface layer, a sintered metal layer, or an elastic pressing structure, ensuring stable thermal contact between the package and the cryogenic cold end. The cryogenic packaging substrate layer can be made of oxygen-free copper, gold-plated copper, molybdenum-copper alloy, copper-tungsten alloy, metallized ceramic, or a high thermal conductivity composite material. The cryogenic packaging substrate layer may also include a shielding cap, a magnetic shielding layer, a blackening absorption layer, an infrared absorption layer, or a getter to reduce residual radiation and contamination risks within the packaging cavity.

[0030] The superconducting interconnect redistribution layer is disposed between the superconducting quantum chip layer and the low-temperature signal transition layer, and is used to convert the two-dimensional wiring on the chip surface into vertical interconnects or edge interconnects suitable for three-dimensional packaging. This layer may include a low-loss dielectric layer, a superconducting redistribution metal layer, a ground reference layer, superconducting vertical vias, and superconducting microbumps. The low-loss dielectric layer may be made of high-purity silicon, sapphire, silicon nitride, silicon dioxide, benzocyclobutene, polyimide, or other low-temperature low-loss dielectrics. The superconducting redistribution metal layer may be made of aluminum, niobium, tantalum, niobium nitride, or niobium-titanium nitride. The superconducting microbumps may be indium bumps, aluminum bumps, niobium bumps, indium-tin alloy bumps, or composite bumps thereof. The diameter of the superconducting microbumps may be 5 μm to 100 μm, and the spacing between the superconducting microbumps may be 10 μm to 300 μm.

[0031] The cryogenic signal transition layer is used to convert signals from the high-density ports on the chip side to the external cryogenic control readout module. This layer can be made of low-loss ceramic substrate, silicon-based transition board, glass-based transition board, sapphire transition board, or multilayer superconducting circuit board. Coplanar waveguides, microstrip lines, striplines, DC bias lines, flux control lines, and ground vias can be placed on the cryogenic signal transition layer. For readout lines, the cryogenic signal transition layer can be further connected to cryogenic isolators, filters, attenuators, amplifiers, or cryogenic coaxial connectors.

[0032] In a preferred embodiment, the substrate of the centrally located thermal anchor shielding composite layer is made of diamond, aluminum nitride, silicon carbide, or a high thermal conductivity ceramic composite material. Diamond has high thermal conductivity and a low coefficient of thermal expansion, making it suitable for use as a low-temperature thermal anchor skeleton; aluminum nitride has good thermal conductivity and electrical insulation properties, making it suitable for use when both thermal and electrical isolation are required; silicon carbide has good mechanical strength and processing compatibility, making it suitable as a composite substrate. The substrate thickness can be from 50 μm to 1 mm, and the specific thickness can be determined based on the encapsulation cavity height, interconnect height, thermal resistance requirements, and stress relief space.

[0033] The high thermal conductivity anchor frame 301 is arranged in a region outside the sensitive area of ​​the superconducting quantum bit, such as the chip edge region, the readout line convergence region, the low-temperature signal transfer region, or the external cold junction connection region. The thermal anchor frame can be a continuous frame, radial beam, island-shaped thermal anchor, gridded thermal anchor, or locally metallized thermal diffusion sheet. To reduce the risk of microwave loss, the high thermal conductivity anchor frame should not directly cross the readout resonant cavity or the top of the quantum bit capacitor arm; when it must be close to the signal line, a ground reference layer, a ground via array, or a low-loss dielectric isolation region should be set between it and the signal line.

[0034] In one specific structure, titanium / platinum / gold, molybdenum / gold, titanium / tungsten / gold, niobium / gold, or aluminum / gold metallization layers are sequentially formed on the surface of the diamond thermal anchor skeleton. These metallization layers improve the reliability of thermal contact between the thermal anchor skeleton and the flexible metal buffer layer and the low-temperature packaging substrate layer. Furthermore, they can connect to the superconducting grounding layer or grounding via array to form a thermal-ground composite boundary. The local width of the thermal anchor can range from 20 μm to 500 μm, and the horizontal spacing between the thermal anchor and the microwave signal line is preferably not less than 50 μm; for high-field-strength regions, this spacing can be further increased to over 100 μm.

[0035] In some embodiments, the superconducting electromagnetic shielding network includes a superconducting grounding layer, a superconducting grounding via array, an annular superconducting shielding groove, a gridded superconducting shielding wire, or a combination thereof, and the material of the superconducting electromagnetic shielding network includes one or more composite thin films selected from aluminum, niobium, niobium nitride, niobium titanium nitride, and tantalum.

[0036] The superconducting grounding via 8 can be a through-hole, a blind via, or a partially metallized via, with a via diameter ranging from 5 μm to 200 μm and a via period ranging from 20 μm to 1 mm. For coplanar waveguides or striplines, the grounding via array can be placed on both sides of the signal line, making the transmission environment close to a quasi-coaxial shielding structure, thereby reducing crosstalk and external electromagnetic disturbances.

[0037] In some embodiments, the parasitic mode suppression unit includes a periodic electromagnetic bandgap structure 12, a grounding hole array structure, a ring grounding groove structure, a stepped impedance structure, an absorption cavity structure, or a combination thereof; such as Figure 3 As shown, the periodic electromagnetic bandgap structure 12 can be composed of metal patches, grounding holes, annular slots, or mushroom-shaped units. The unit period can be 50 μm to 2 mm, and the slot width or gap width can be 2 μm to 200 μm. During the design, the possible cavity parasitic modes can be estimated based on the package cavity height, dielectric constant of the medium, quantum bit operating frequency band, and readout frequency band. The bandgap unit period, grounding hole spacing, and annular slot radius can be selected to ensure that the suppression frequency band avoids or covers the target parasitic mode frequency.

[0038] In some embodiments, the low-temperature stress relief structure can be partially reused with a parasitic mode suppression unit or a shielding structure, and includes annular (stress) relief grooves, segmented relief grooves, serpentine flexible bridges, locally thinned regions, gradient thermal expansion transition regions, or flexible metal buffer layers. For example... Figure 4As shown, the annular release groove 10 can be set around the quantum chip projection area 11 or the microbump array area to reduce the pulling effect of the packaging substrate shrinkage on the central area of ​​the chip during low-temperature cooling; the segmented release groove can be set between the thermal anchor frame and the signal transfer area to reduce the stress concentration caused by the rigid thermal anchor structure; the serpentine flexible bridge can be set between the local thermal anchor island and the main frame to simultaneously achieve thermal connection and mechanical compliance; the local thinning area can be set around the microbump array to reduce the shear stress on the microbumps; the flexible metal buffer layer can be made of indium, gold, indium-tin alloy, gold-tin alloy or other low-temperature compatible soft metals.

[0039] In some embodiments, the thermal path 6 and the signal path 7 are spatially decoupled through a low-loss dielectric isolation region, a ground reference layer, a superconducting ground via array 8, or a clearance gap; the via spacing of the superconducting ground via array 8 is no greater than twice the width of the microwave transmission line 9.

[0040] The thermal path connects to the cryogenic cold source via a high thermal conductivity anchor frame, a heat diffusion layer, a flexible metal buffer layer, and a cold-end thermal connection interface; the signal path connects to the external cryogenic control readout module via superconducting micro-bumps, a superconducting redistribution layer, a microwave transmission line, a low-loss dielectric layer, and a cryogenic signal transfer layer. Spatially, they are separated by clearance gaps, a grounding reference layer, a low-loss dielectric isolation area, or a grounding via array; functionally, their parameters are jointly determined through thermo-electromagnetic-mechanical co-simulation.

[0041] In some implementations, the microwave control lines and readout lines employ a coplanar waveguide structure. Grounding metal is placed on both sides of the signal lines, and this grounding metal is connected to the upper and lower grounding layers of the central composite layer via an array of grounding vias to reduce grounding inductance and crosstalk between adjacent channels. The distance between the grounding vias and the signal lines can be determined based on the target characteristic impedance, dielectric thickness, dielectric constant, and microwave loss requirements. For a 50Ω transmission line, the signal line width and gap width can be determined first using a transmission line model, and then the period of the grounding vias can be controlled within a range that does not cause significant periodic impedance disturbances.

[0042] In other embodiments, the readout line employs a stripline or microstrip line structure. The high thermal conductivity anchor frame in the centrally located thermal anchor shielding composite layer does not directly cross above the readout resonant cavity, but is arranged along the outer side of the readout line convergence area. If the thermal anchor frame is adjacent to the signal line, a ground reference layer or ground via fence is placed between them, so that the microwave field is mainly confined between the signal line and the ground reference layer, thereby reducing the disturbance of the microwave field distribution by the high thermal conductivity metal structure.

[0043] The low-temperature thermal interface can be located at the bottom or side of the low-temperature packaging substrate layer. This interface includes a metallized contact surface, a screw pressing surface, an indium thermal interface layer, a sintered metal layer, or a flexible pressing structure. The metallized contact surface can be made of gold-plated copper, gold-plated molybdenum-copper, gold-plated copper-tungsten, or metallized ceramic. To reduce contact thermal resistance, the surface roughness of the contact surface can be controlled within the range of 0.05μm to 2μm, and positioning holes or limiting steps can be provided in the pressing area to ensure stable contact pressure after multiple thermal cycles.

[0044] In one embodiment, the high thermal conductivity anchor frame is connected to the low-temperature packaging substrate layer via a flexible metal buffer layer. The flexible metal buffer layer compensates for the thermal expansion differences between the diamond, ceramic, copper substrate, and superconducting thin film, while maintaining stable thermal contact between the thermal anchor frame and the cold end. The buffer layer thickness can range from 1 μm to 100 μm, preferably from 5 μm to 50 μm. For structures requiring detachable installation, indium sheet bonding or elastic bonding can be used; for structures requiring long-term stable thermal contact, a sintered silver layer, a metal diffusion layer, or a low-temperature compatible solder layer can be used.

[0045] Example 2: A method for manufacturing a three-dimensional low-temperature packaging structure for superconducting quantum chips.

[0046] Combination Figure 5 As shown, the manufacturing method includes the following steps: S1: Obtain the design input information for the superconducting quantum chip. The design input information includes the quantum bit layout, readout resonant cavity layout, control line layout, magnetic flux bias line layout, chip-side pad layout, allowable thermal budget, allowable bonding temperature, quantum bit operating frequency band, readout frequency band, and low-temperature cold junction interface location. For chips containing Josephson junctions, their allowable process temperature, allowable mechanical stress, and sensitive region locations should be further determined.

[0047] S2: Determine the initial parameters of the centrally located thermal anchor shielding composite layer. The initial parameters include the composite layer matrix material, composite layer thickness, thermal anchor frame width and position, grounding hole diameter and period, shielding groove width, annular grounding groove radius, periodic electromagnetic bandgap structure unit period, stress relief groove depth, flexible metal buffer layer thickness, micro-bump diameter and spacing, minimum clearance between thermal path and signal path, etc. The initial parameters can be estimated based on low-temperature thermal resistance, transmission line impedance, encapsulation cavity height, and stress concentration location.

[0048] S3: Establish a coupled thermo-electromagnetic-mechanical simulation model and determine the package structure parameters. Thermal simulation can be used to calculate cold-end heat flow, chip area temperature rise, thermal anchor skeleton thermal resistance, and temperature gradient; electromagnetic simulation can be used to calculate insertion loss, return loss, crosstalk, package cavity parasitic mode frequencies, and electromagnetic bandgap suppression band; mechanical simulation can be used to calculate package warpage, microbump shear stress, chip substrate stress, and Josephson junction adjacent region stress during cooling from room temperature to 4K or milliKelvin. The above simulation models can be established based on the finite element method, boundary element method, transmission line model, or equivalent thermal resistance network model, and the structural parameters can be determined through parameter scanning. Optionally, a machine learning surrogate model can be used to accelerate parameter search.

[0049] S4: Prepare the centrally located thermal anchor shielding composite layer according to the determined packaging structure parameters; first, provide a diamond, aluminum nitride, silicon carbide or high thermal conductivity composite substrate, and cut, grind, polish and clean it according to the design parameters; then use laser processing, reactive ion etching, deep reactive ion etching, mechanical micromachining or wet etching to form through holes, annular grooves, release grooves, local thinning areas and electromagnetic bandgap patterns; then use sputtering, evaporation, electroplating, atomic layer deposition or chemical vapor deposition to form metallization layers, superconducting grounding layers, grounding through hole metal and shielding groove metal; for through hole structures, a seed layer can be formed first, and then superconducting metal filling or sidewall metallization can be performed.

[0050] S5: Forming the superconducting interconnect redistribution layer and the cryogenic signal transition layer; depositing a superconducting metal thin film on a low-loss dielectric layer, and forming coplanar waveguides, microstrip lines, striplines, ground reference layers, and redistribution patterns through photolithography and etching; forming superconducting microbumps, vertical vias, or pads at designated locations. For the cryogenic signal transition layer, ports for connection to external coaxial cables, flexible cables, filters, attenuators, or cryogenic control modules can be formed.

[0051] S6: Perform low-temperature compatible bonding between the superconducting quantum chip layer and the centrally located thermal anchor shielding composite layer; Specifically, the superconducting quantum chip layer, superconducting interconnect redistribution layer, centrally located thermal anchor shielding composite layer, low-temperature signal transfer layer, and low-temperature packaging substrate layer are aligned and bonded. The bonding methods may include indium bump flip bonding, low-temperature thermo-press bonding, ultrasonic-assisted bonding, metal diffusion bonding, or hybrid bonding. To avoid thermal damage to the Josephson junction and superconducting thin film, the low-temperature compatible bonding temperature is preferably not higher than 200°C, and more preferably not higher than 150°C. The bonding pressure, time, and atmosphere can be determined based on the tolerance of the microbump material, metallization layer material, and dielectric layer.

[0052] S7: Install the capping layer and form a cryogenic packaging cavity; the capping layer can be made of oxygen-free copper, gold-plated copper, aluminum alloy, superconducting metallized silicon cover plate or low-loss ceramic cover plate. A magnetic shielding layer, blackening absorption layer, infrared absorption layer or getter can be set inside the capping layer. However, the absorption material should be isolated from the quantum bit sensitive area by a superconducting shielding structure to avoid introducing additional loss or noise. The capping layer and the cryogenic packaging substrate layer can be fixed by metal sealing, cryogenic compatible sealing ring, mechanical pressing or screw connection.

[0053] S8: Perform low-temperature thermal cycling, microwave S-parameter, interconnect continuity and warpage tests; Specifically, the testing includes microscopic inspection, X-ray inspection, acoustic scanning inspection, microbump continuity testing, and initial S-parameter testing; low-temperature testing includes cold-end heat flow, chip area temperature rise, interconnect resistance, package warpage, insertion loss, return loss, crosstalk, and parasitic resonance peak position during the process of cooling from room temperature to the 4K or millikelvin operating temperature range; if the test finds that a parasitic resonance peak is close to the quantum bit operating frequency band, the grounding hole period, annular groove radius, electromagnetic bandgap unit period, or package cavity height can be adjusted in the next batch of designs; if low-temperature warpage causes an increase in microbump resistance, the release groove depth, flexible metal buffer layer thickness, or thermal expansion gradient transition region structure can be adjusted.

[0054] When test results show that the chip area temperature rises above a preset threshold, the width of the thermal anchor skeleton can be increased, the thermal connection interface area can be increased, the thermal resistance of the flexible metal buffer layer can be reduced, or the connection position between the thermal anchor skeleton and the cold end can be adjusted. When test results show increased insertion loss or significant impedance mismatch, the clearance between the thermal anchor and the signal line can be increased, the period of the grounding via can be adjusted, the thickness of the low-loss dielectric can be modified, or the shape of the grounding reference layer can be optimized. When test results show that the parasitic resonance peak is close to the quantum bit frequency band or the readout frequency band, the period of the periodic electromagnetic bandgap unit, the radius of the annular groove, the height of the package cavity, or the position of the local absorption cavity can be adjusted. When test results show low-temperature warpage or micro-bump resistance changes exceeding a threshold, the depth of the release groove can be increased, the segmentation method of the release groove can be changed, the flexible metal buffer layer can be thickened, or a gradient thermal expansion transition region can be introduced.

[0055] The aforementioned feedback correction is not simply a software algorithm optimization, but rather a modification of manufacturing parameters for the thermal anchor geometry, shielding network, electromagnetic bandgap units, release groove, and thermal connection interface of the centrally located thermal anchor shielding composite layer, targeting the cryogenic packaging physical structure. Through batch iteration, this invention can adapt to different quantum chip layouts, different packaging cavity sizes, and different cryogenic cooling interfaces, thereby improving the engineering feasibility and reliability of the three-dimensional cryogenic packaging structure.

[0056] This invention can be applied to the packaging of superconducting quantum computers, cryogenic quantum processors, cryogenic microwave measurement modules, quantum sensors, and superconducting electronic devices that require stable operation below 4K. The structure can be realized using existing micro / nano fabrication, thin film deposition, through-hole metallization, cryogenic bonding, and cryogenic testing processes, providing a clear industrial manufacturing path. By adjusting the material, thickness, through-hole period, release groove size, and thermal connection interface of the centrally located thermal anchor shielding composite layer, this invention can adapt to different qubit scales and cryogenic platforms, demonstrating promising prospects for industrial application.

[0057] Example 3: Taking the metallized diamond-coated composite layer encapsulation as an example, this encapsulation structure and method are further illustrated.

[0058] In this specific embodiment, the superconducting quantum chip layer includes a two-dimensional transmon qubit array, with readout lines and control lines extending from the chip edge; the centrally located thermal anchor shielding composite layer uses a metallized diamond substrate with a substrate thickness of 300 μm; a ring-shaped thermal anchor frame is formed on the diamond substrate, the thermal anchor frame is arranged along the chip edge and the readout line convergence area, and is connected to the cold end of the mixing chamber of the dilution refrigerator through the gold-plated copper contact surface at the bottom of the low-temperature packaging substrate layer; a distance of not less than 100 μm is maintained between the thermal anchor frame and the projection area of ​​the qubit capacitor arm.

[0059] In this embodiment, the superconducting electromagnetic shielding network includes upper and lower niobium grounding layers and an array of niobium grounding vias penetrating the diamond substrate. The via diameter is 20 μm and the via period is 100 μm. Grounding via fences are set on both sides of the microwave signal line, and the fences are connected to the upper and lower grounding layers to form a quasi-coaxial shielded transmission environment. A low-loss dielectric isolation zone and a grounding reference layer are set between the high thermal conductivity anchor and the microwave signal line to prevent the high thermal conductivity metal structure from directly entering the microwave field intensity concentration area.

[0060] The parasitic mode suppression unit comprises a ring-shaped grounding slot and periodic electromagnetic bandgap units. The ring-shaped grounding slot is arranged around the outside of the qubit array and connected to the upper and lower grounding layers through grounding vias. The periodic electromagnetic bandgap units are located near the edge of the package cavity and the readout line convergence area, with a unit period of 400 μm and a slot width of 20 μm. This structure is used to cut off, frequency shift, or attenuate parasitic modes propagating along the planar direction within the package cavity, thereby reducing parasitic resonance peaks in the readout frequency band.

[0061] The low-temperature stress relief structure includes an annular relief groove surrounding the projection area of ​​the quantum chip and a locally thinned region located outside the microbump array. The annular relief groove has a depth of 150 μm and a width of 30 μm. The thickness of the locally thinned region is reduced by 30% to 60% compared to the thickness of the composite layer. A 20 μm thick indium buffer layer is provided between the thermal anchor frame and the low-temperature packaging substrate to compensate for the thermal expansion difference between the diamond and the copper substrate and to maintain stable thermal contact.

[0062] Example 4: Taking aluminum nitride-centered composite layer packaging as an example, this packaging structure and method are further illustrated.

[0063] In this embodiment, the centrally located thermal anchor shielding composite layer uses an aluminum nitride substrate. The aluminum nitride substrate has both high thermal conductivity and electrical insulation, making it suitable for reducing short-circuit risk in packages with high signal path density. A segmented copper-tungsten alloy thermal anchor skeleton is formed on the surface of the aluminum nitride substrate. The thermal anchor skeleton is covered by a niobium film and then connected to the superconducting grounding layer. In order to reduce the influence of the metal thermal anchor on the microwave signal line, the thermal anchor skeleton adopts an island-shaped distribution and is connected to the outer main thermal frame through multiple short thermal bridges.

[0064] In this embodiment, the parasitic mode suppression unit adopts a combination of grounding hole array and stepped impedance structure. The grounding hole array is arranged along the edge of the low-temperature signal transfer layer, and the stepped impedance structure is set near the boundary of the packaging cavity. The stress relief structure adopts segmented relief groove and serpentine flexible bridge. The serpentine flexible bridge connects the local thermal anchor island and the main thermal frame, so that the thermal path remains continuous, while reducing the rigid constraint of the thermal anchor island on the chip area. This implementation is suitable for low-temperature quantum processors with large quantum bit scale, high signal port density and limited packaging cavity thickness.

[0065] Comparative Verification Examples: To illustrate the technical effects of the structure of this invention, three comparative packaging models can be established. Comparative Example A is a traditional metal box package with planar leads; Comparative Example B is a package with ball array or microbump interconnects but without a centrally located thermal anchor shielding composite layer; and Example C is a package using the centrally located thermal anchor shielding composite layer of this invention. The three packaging models have the same chip area, the same cold junction temperature, the same number of readout lines, and the same external connection conditions. The thermal model calculates the steady-state temperature rise of the chip area; the electromagnetic model calculates the insertion loss and crosstalk between adjacent channels in the readout frequency band; and the mechanical model calculates the chip area warpage and the maximum shear stress of the microbumps during the cooling process from room temperature to 4 K.

[0066] In a series of thermo-electromagnetic-mechanical co-simulation verifications, as shown in Table 1, the steady-state temperature rise of the chip region in Comparative Example A was 38 mK, the crosstalk between adjacent channels of the readout line was -38 dB, and the maximum warpage of the chip region after 4 K cooling was 18 μm; the steady-state temperature rise of the chip region in Comparative Example B was 26 mK, the crosstalk was -43 dB, and the maximum warpage was 15 μm; the steady-state temperature rise of the chip region in Example C was 11 mK, the crosstalk was -55 dB, and the maximum warpage was 7 μm. These results demonstrate that, under the same boundary conditions, this invention achieves lower chip region temperature rise, stronger microwave crosstalk suppression capability, and smaller low-temperature warpage through a centrally located thermal anchor shielding composite layer.

[0067] Table 1: Exemplary thermo-electromagnetic-mechanical comparison results of different packaging structures

[0068] In the packaging model without parasitic mode suppression units, a significant parasitic resonance peak exists near the readout frequency band, and the return loss curve exhibits sharp fluctuations in the target frequency band. After adding periodic electromagnetic bandgap units and annular grounding slots, the parasitic resonance peaks are shifted to the non-operating frequency band or significantly reduced. For the model without stress relief structure, high shear stress appears in the edge region of the microbump array. After adding annular relief slots and local thinning areas, the maximum shear stress of the microbumps is reduced, and the tensile stress concentration in the central region of the chip is alleviated.

[0069] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A three-dimensional cryogenic packaging structure for superconducting quantum chips, characterized in that, The system comprises a superconducting quantum chip layer, a superconducting interconnect redistribution layer, a centrally located thermal anchor shielding composite layer, a cryogenic signal transfer layer, and a cryogenic packaging substrate layer, all stacked or partially nested along the thickness direction. The centrally located thermal anchor shielding composite layer includes a high thermal conductivity thermal anchor skeleton, a superconducting electromagnetic shielding network, a parasitic mode suppression unit, and a cryogenic stress relief structure. A thermal path and signal path decoupling structure is formed within the centrally located thermal anchor shielding composite layer, wherein the thermal path is connected to the cryogenic packaging substrate layer, and the signal path is connected to the cryogenic signal transfer layer. The parasitic mode suppression unit, as an inherent component of the centrally located thermal anchor shielding composite layer, is electrically connected to the superconducting electromagnetic shielding network. The cryogenic stress relief structure is disposed around the boundary region of the high thermal conductivity thermal anchor skeleton.

2. The three-dimensional low-temperature packaging structure for superconducting quantum chips according to claim 1, characterized in that, The superconducting quantum chip layer is located on the top of the package or inside the package near the cover, and includes a superconducting quantum bit, a Josephson junction, a readout resonant cavity, a microwave control line, a magnetic flux bias line, and a grounding structure; the high thermal conductivity anchor frame is arranged in the area outside the sensitive region of the superconducting quantum bit.

3. The three-dimensional low-temperature packaging structure for superconducting quantum chips according to claim 1, characterized in that, The superconducting electromagnetic shielding network includes a superconducting grounding layer, a superconducting grounding through-hole array, an annular superconducting shielding groove, a gridded superconducting shielding wire, or a combination thereof. The material of the superconducting electromagnetic shielding network includes one or more composite films selected from aluminum, niobium, niobium nitride, niobium titanium nitride, and tantalum. The high thermal conductivity anchor skeleton is a composite structure selected from one or more composite structures selected from metallized diamond, aluminum nitride, silicon carbide, high-purity copper, molybdenum copper alloy, and copper tungsten alloy.

4. The three-dimensional cryogenic packaging structure for superconducting quantum chips according to claim 1, characterized in that, The parasitic mode suppression unit includes a periodic electromagnetic bandgap structure, a grounding hole array structure, an annular grounding groove structure, a stepped impedance structure, an absorption cavity structure, or a combination thereof; the low-temperature stress relief structure includes an annular relief groove, a segmented relief groove, a serpentine flexible bridge, a locally thinned region, a gradient thermal expansion transition region, or a flexible metal buffer layer.

5. The three-dimensional low-temperature packaging structure for superconducting quantum chips according to claim 1, characterized in that, The superconducting interconnect redistribution layer is used to convert two-dimensional wiring on the chip surface into vertical interconnects or edge interconnects suitable for three-dimensional packaging. It includes superconducting microbumps, superconducting vertical vias, a superconducting redistribution layer, a low-loss dielectric layer, and a ground reference layer. The superconducting microbumps are indium bumps, aluminum bumps, niobium bumps, indium tin alloy bumps, or composite bumps thereof.

6. The three-dimensional cryogenic packaging structure for superconducting quantum chips according to claim 1, characterized in that, The low-temperature packaging substrate layer is provided with a thermal connection interface that connects to the cold end of the mixing chamber of the dilution refrigerator, the cold plate, or the low-temperature sample stage. The thermal connection interface includes a metallized contact surface, a screw pressing surface, an indium sheet thermal interface layer, a sintered metal layer, or an elastic pressing structure.

7. The three-dimensional low-temperature packaging structure for superconducting quantum chips according to claim 1, characterized in that, The thermal path and the signal path are spatially decoupled through a low-loss dielectric isolation region, a ground reference layer, a superconducting ground via array, or a clearance gap; wherein the minimum distance between the high thermal conductivity anchor frame and the microwave transmission line in the chip is not less than 50 μm, or the via spacing of the superconducting ground via array is not greater than twice the width of the microwave transmission line.

8. A method for manufacturing a three-dimensional cryogenic packaging structure for superconducting quantum chips, used to manufacture the three-dimensional cryogenic packaging structure for superconducting quantum chips as described in any one of claims 1 to 7, characterized in that, The manufacturing method includes the following steps: Obtain the qubit layout, readout line layout, control line layout, allowable thermal budget, and operating frequency band of the superconducting quantum chip layer; Determine the initial parameters of the thermal path, signal path, superconducting electromagnetic shielding network, parasitic mode suppression unit, and low-temperature stress release structure in the centrally located thermal anchor shielding composite layer; Determining packaging structure parameters based on thermo-electromagnetic-mechanical collaborative constraints; Prepare the centrally located heat anchor shielding composite layer according to the determined packaging structure parameters; A superconducting interconnect rewiring layer and a low-temperature signal transfer layer are formed above and below the centrally located thermal anchor shielding composite layer; The superconducting quantum chip layer is low-temperature compatiblely bonded to the centrally placed thermal anchor shielding composite layer; Install the capping layer and form a cryogenic encapsulation cavity; Low-temperature thermal cycling, microwave S-parameters, interconnect continuity, and warpage tests were conducted.

9. The method for manufacturing a three-dimensional low-temperature packaging structure for superconducting quantum chips according to claim 8, characterized in that, When determining the packaging structure parameters, a thermo-electromagnetic-mechanical coupled simulation model is established with thermal leakage, temperature gradient, insertion loss, crosstalk, parasitic mode frequency, low-temperature warpage, and interconnect stress as optimization objectives. The thermo-electromagnetic-mechanical coupled simulation model is constructed based on the finite element method, boundary element method, transmission line model, or a combination thereof, and the structural parameters of the central thermal anchor shielding composite layer are determined by parameter scanning.

10. The method for manufacturing a three-dimensional low-temperature packaging structure for superconducting quantum chips according to claim 8, characterized in that, The process temperature for the low-temperature compatible bonding is no higher than 200°C. The low-temperature test includes measuring the cold end heat flow, chip area temperature rise, microwave S-parameters, parasitic mode frequency shift, warpage, and microbump resistance changes in the temperature range of 4K or below. The test results are used to correct the parameters of the next batch of centrally located thermal anchor shielding composite layers.

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