A superconducting quantum bit structure and method of fabrication thereof

Abstract

This application discloses a superconducting quantum bit structure and its fabrication method. The superconducting quantum bit structure includes: a substrate layer with a raised portion; the raised portion is disposed on the top surface of the substrate layer, and the raised portion includes a first inclined side surface and a second inclined side surface opposite to each other. The top surface of the raised portion is located on the side away from the top surface of the substrate layer, and the top surface of the raised portion intersects with the first inclined side surface and the second inclined side surface, respectively; a first superconducting material layer covering the first inclined side surface; a second superconducting material layer covering the second inclined side surface; and a Josephson junction structure disposed on the top surface of the raised portion. The Josephson junction structure, the first superconducting material layer, and the second superconducting material layer constitute the superconducting quantum bit structure. By replacing the traditional planar capacitor with a three-dimensional inclined capacitor extending along the side surface of the raised portion, the electric field distribution of the capacitor and the main current conduction path are distributed along the normal and radial directions of the inclined side surface, thereby improving the performance of the quantum bit.

Description

Technical Field

[0001] This application relates to the field of superconducting quantum mechanics, and more particularly to a superconducting quantum bit structure and its fabrication method. Background Technology

[0002] In the field of superconducting quantum computing device technology, as quantum computing continues to evolve towards high bit integration, long coherence time and high operational stability, superconducting qubits, as the core functional unit of superconducting quantum chips, have their energy relaxation time and device reliability directly determining the computing performance of quantum chips. Optimizing the qubit structure to improve core performance indicators has become one of the core directions of superconducting quantum device research and development.

[0003] Conventional superconducting qubits typically employ a two-dimensional planar structure. This usually involves depositing superconducting material on a flat surface of an insulating substrate, etching it to form two separate superconducting capacitive plates, and then fabricating a Josephson junction between them to form a planar capacitor structure. However, in this planar capacitor structure, the electric field distribution and the main current conduction path are highly concentrated in the etched edge region adjacent to the two superconducting materials. The main region of the superconducting plates contributes very little to the device performance. Simultaneously, the etching process inevitably generates numerous defects at the edges of the superconducting material. These defects are located precisely on the areas of high electric field density and the core current conduction path, severely degrading the device's electrical performance. This leads to a significant reduction in the energy relaxation time of the superconducting qubit, a substantial decrease in fabrication stability and uniformity, and makes it difficult to meet the requirements for the fabrication and use of high-order superconducting quantum chips. Summary of the Invention

[0004] The purpose of this application is to provide a superconducting quantum bit structure and its fabrication method, which makes the electric field distribution of the capacitor and the main conduction path of the current distributed along the normal and radial directions of the inclined side, thereby improving the performance of the quantum bit structure.

[0005] To achieve the above objectives, in a first aspect, embodiments of this application provide a superconducting quantum bit structure, comprising:

[0006] A substrate layer, the substrate layer including protrusions; The protrusion is disposed on the top surface of the substrate layer. The protrusion includes a first inclined side surface and a second inclined side surface that are opposite each other. The top surface of the protrusion is located on the side away from the top surface of the substrate layer. The top surface of the protrusion intersects with the first inclined side surface and the second inclined side surface, respectively. A first superconducting material layer, the first superconducting material layer covering the first inclined side surface; A second superconducting material layer, the second superconducting material layer covering the second inclined side surface; A Josephson junction structure is disposed on the top surface of the protrusion, and the Josephson junction structure, together with the first superconducting material layer and the second superconducting material layer, constitutes a superconducting quantum bit structure.

[0007] In some embodiments of this application, the top surface of the substrate layer is provided with a transition region along the circumferential direction of the protrusion, and the transition region intersects with the first inclined side surface and the second inclined side surface, respectively.

[0008] In some embodiments of this application, it also includes: A third superconducting material layer covers a portion of the top surface of the substrate layer and is located away from the transition region.

[0009] In some embodiments of this application, it also includes: A third superconducting material layer covers the top surface of the substrate layer, and the third superconducting material layer in the transition region is used to form other circuit structures required for the superconducting quantum chip.

[0010] In some embodiments of this application, the substrate layer is made of one or a combination of silicon, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and sapphire.

[0011] In some embodiments of this application, the materials of the first superconducting material layer, the second superconducting material layer and the third superconducting material layer are one or a combination of tantalum, aluminum, indium, titanium, niobium or titanium nitride.

[0012] In some embodiments of this application, the protrusion has a rectangular or trapezoidal cross-sectional shape along the direction perpendicular to the top surface of the substrate.

[0013] In some embodiments of this application, the top surface of the protrusion is circular; The first and second inclined sides of the protrusion are curved surfaces.

[0014] In some embodiments of this application, the top surface of the protrusion is rectangular; The first and second inclined sides of the protrusion are planes.

[0015] Secondly, embodiments of this application provide a method for preparing a superconducting quantum bit structure, comprising the following steps: A protruding portion is formed on the top surface of a substrate. A mask layer with a preset shape is prepared on the top surface of the substrate. The substrate is etched using the mask layer as a shield. After removing part of the substrate material, a substrate layer with a protruding portion is formed. The protruding portion includes a first inclined side surface and a second inclined side surface. A superconducting material layer is formed on the top surface of the substrate layer, so that the superconducting material layer uniformly covers the top surface of the substrate layer and the protrusion; The superconducting material layer is patterned by photolithography and etching processes, and the superconducting material in the preset area is removed, so that the remaining superconducting material layer covering the protrusion forms a first superconducting material layer and a second superconducting material layer covering the first inclined side and the second inclined side respectively. A Josephson junction is fabricated on the top surface of the protrusion, such that the two ends of the Josephson junction, together with the first superconducting material layer and the second superconducting material layer, form a superconducting quantum bit structure.

[0016] The beneficial effects of this application are: The superconducting quantum bit structure of this application includes: A substrate layer, the substrate layer including protrusions; The protrusion is disposed on the top surface of the substrate layer. The protrusion includes a first inclined side surface and a second inclined side surface that are opposite each other. The top surface of the protrusion is located on the side away from the top surface of the substrate layer. The top surface of the protrusion intersects with the first inclined side surface and the second inclined side surface, respectively. A first superconducting material layer, the first superconducting material layer covering the first inclined side surface; A second superconducting material layer, the second superconducting material layer covering the second inclined side surface; A Josephson junction structure is disposed on the top surface of the protrusion, and the Josephson junction structure, together with the first superconducting material layer and the second superconducting material layer, constitutes a superconducting quantum bit structure.

[0017] In this application, firstly, since the first superconducting material layer covers the first inclined side and the second superconducting material layer covers the second inclined side, the two separate first and second superconducting material layers extend and are arranged along the first and second inclined sides of the protruding portion, forming a three-dimensional inclined capacitor structure. This transforms the electric field distribution of the superconducting capacitor from a narrow region concentrated near the etched edge of the two superconducting layers in the traditional planar structure to a large-scale distribution in the main region of the superconducting material layer on the inclined side. This causes the electric field distribution of the capacitor and the main current conduction path to be distributed along the normal and radial directions of the inclined side, significantly reducing the proportion of edge defects generated by the etching process in the core conduction path of the capacitor. This significantly weakens the degrading effect of etching edge defects on the overall performance of the capacitor, effectively improves the energy relaxation time of the superconducting quantum bit, and solves the technical problem that etching boundary defects in existing planar superconducting quantum bits severely restrict the performance and stability of the device. Meanwhile, the first superconducting material layer and the second superconducting material layer are directly deposited and grown on the inclined side surface of the substrate. The number of growth defects at the interface between the superconducting material and the substrate is much less than the number of edge defects formed by the etching process, which further reduces the negative impact of defect sites on the performance of superconducting qubits. This improves the device's operating performance and long-term stability from two dimensions: structural layout optimization and interface quality improvement.

[0018] Secondly, since the Josephson junction structure is located on the top surface of the protruding portion, and the top surface of the protruding portion intersects with the first inclined side surface and the second inclined side surface respectively, the two ends of the Josephson junction structure can be directly and with low loss to the first superconducting material layer and the second superconducting material layer on both sides respectively. The flat top surface of the protruding portion provides a horizontal fabrication support surface for the Josephson junction, which can ensure the patterning fabrication accuracy and electrical performance consistency of the Josephson junction, avoiding the problems of uneven thickness and large performance dispersion caused by fabricating the Josephson junction on the inclined surface. At the same time, the superconducting material layer on the inclined side surface and the Josephson junction on the top surface form a continuous three-dimensional superconducting circuit, which can complete the electrical connection between the capacitor plate and the Josephson junction without the need to set additional planar transition leads, simplifying the structural hierarchy of the device, avoiding the transmission loss and process defect risks introduced by additional leads, and ensuring the electrical integrity of the core circuit of the superconducting quantum bit.

[0019] Furthermore, since the protrusion is integrally formed from the substrate layer through an etching process, the first superconducting material layer, the second superconducting material layer, and the Josephson junction structure are all fabricated on this three-dimensional substrate through thin film deposition and photolithography etching processes. The overall process flow is fully compatible with conventional semiconductor manufacturing processes, without the need for additional special process equipment. It can be directly adapted to existing superconducting quantum device fabrication lines, has strong process feasibility, and has a good foundation for mass production and promotion. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0021] Figure 1 This is a side view schematic diagram of the superconducting quantum bit structure provided in some embodiments of this application; Figure 2 This is a top view schematic diagram of the superconducting quantum bit structure provided in some embodiments of this application; Figure 3 This is a schematic diagram of the process for forming the encapsulation structure provided in some embodiments of this application.

[0022] Explanation of reference numerals in the attached figures: 1: Substrate layer; 11: Transition region; 2: Protrusion; 21: First inclined side; 22: Second inclined side; 31: First superconducting material layer; 32: Second superconducting material layer; 33: Third superconducting material layer; 4: Josephson junction structure. Detailed Implementation

[0023] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0024] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0025] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects, and is not necessarily used to describe a specific order or sequence, unless the context clearly indicates otherwise.

[0026] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0027] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with the other component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or electrical coupling, or they can be in electrical contact or electrical coupling through an intermediate component.

[0028] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0029] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0030] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0031] It is understood that in some of the accompanying drawings of this application, adjacent films with the same processing material are drawn as connected to make them resemble the actual structure.

[0032] Firstly, embodiments of this application provide a superconducting quantum bit structure, please refer to... Figure 1 and Figure 2 ,include: Substrate 1, wherein the substrate 1 includes a protrusion 2; The protrusion 2 is disposed on the top surface of the substrate layer 1. The protrusion 2 includes a first inclined side surface 21 and a second inclined side surface 22 opposite to each other. The top surface of the protrusion 2 is located on the side away from the top surface of the substrate layer 1. The top surface of the protrusion 2 intersects with the first inclined side surface 21 and the second inclined side surface 22 respectively. A first superconducting material layer 31 covers the first inclined side surface 21; The second superconducting material layer 32 covers the second inclined side surface 22; Josephson junction structure 4 is disposed on the top surface of the protrusion 2, and the Josephson junction structure 4, together with the first superconducting material layer 31 and the second superconducting material layer 32, constitutes a superconducting quantum bit structure.

[0033] In this application, firstly, since the first superconducting material layer 31 covers the first inclined side 21 and the second superconducting material layer 32 covers the second inclined side 22, the two separate first superconducting material layers 31 and 32 extend along the first inclined side 21 and the second inclined side 22 of the protruding portion 2, forming a three-dimensional inclined capacitor structure. This transforms the electric field distribution of the superconducting capacitor from a narrow region concentrated near the etched edge of the two superconducting layers in the traditional planar structure to a large-scale distribution in the main region of the superconducting material layer on the inclined side. This causes the electric field distribution of the capacitor and the main current conduction path to be distributed along the normal and radial directions of the inclined side, significantly reducing the proportion of edge defects generated by the etching process in the core conduction path of the capacitor. This significantly weakens the degrading effect of etching edge defects on the overall performance of the capacitor, effectively improves the energy relaxation time of the superconducting quantum bit, and solves the technical problem that etching boundary defects in existing planar superconducting quantum bits severely restrict the performance and stability of the device. Meanwhile, the first superconducting material layer 31 and the second superconducting material layer 32 are directly deposited and grown on the inclined side surface of the substrate layer 1. The number of growth defects at the interface between the superconducting material and the substrate is much less than the number of edge defects formed by the etching process, which further reduces the negative impact of defect sites on the performance of superconducting qubits. The device's operating performance and long-term stability are improved from two dimensions: structural layout optimization and interface quality improvement.

[0034] Secondly, since the Josephson junction structure 4 is located on the top surface of the protrusion 2, and the top surface of the protrusion 2 intersects with the first inclined side surface 21 and the second inclined side surface 22 respectively, the two ends of the Josephson junction structure 4 can be directly and with low loss electrically connected to the first superconducting material layer 31 and the second superconducting material layer 32 on both sides respectively. The flat top surface of the protrusion 2 provides a horizontal fabrication support surface for the Josephson junction, which can ensure the patterning fabrication accuracy and electrical performance consistency of the Josephson junction, and avoid the problems of uneven thickness and large performance dispersion caused by fabricating the Josephson junction on the inclined surface. At the same time, the superconducting material layer on the inclined side and the Josephson junction on the top surface form a continuous three-dimensional superconducting circuit, which can complete the electrical connection between the capacitor plate and the Josephson junction without the need to set additional planar transition leads, simplifying the structural hierarchy of the device, avoiding the transmission loss and process defect risks introduced by additional leads, and ensuring the electrical integrity of the core circuit of the superconducting quantum bit.

[0035] Furthermore, since the protrusion 2 is integrally formed from the substrate 1 through an etching process, the first superconducting material layer 31, the second superconducting material layer 32, and the Josephson junction structure 4 are all fabricated on this three-dimensional substrate through thin film deposition and photolithography etching processes. The overall process flow is fully compatible with conventional semiconductor manufacturing processes, without the need for additional special process equipment. It can be directly adapted to existing superconducting quantum device fabrication lines, has strong process feasibility, and has a good foundation for mass production and promotion.

[0036] The superconducting quantum bit structure described above will now be described in detail with reference to the accompanying drawings.

[0037] The substrate layer 1 is the insulating base carrier of the superconducting quantum bit structure. The top surface of the substrate layer 1 is the reference plane for device processing. Its own protrusions 2 provide structural support for the three-dimensional capacitor structure, ensuring that the three-dimensional superconducting material layer and Josephson junction structure 4 have a stable attachment base.

[0038] In some embodiments, reference Figure 1 and Figure 2 The top surface of the substrate layer 1 is provided with a transition region 11 along the circumferential direction of the protrusion 2, and the transition region 11 intersects with the first inclined side surface 21 and the second inclined side surface 22 respectively.

[0039] The transition region 11 is a gentle transition region between the first inclined side 21 and the second inclined side 22 of the protrusion 2 and the top surface of the substrate 1, avoiding the formation of a steep right-angle step between the inclined side and the top surface of the substrate 1; at the same time, the transition region 11 can alleviate the stress concentration of the thin film caused by the abrupt change in morphology, reduce the film cracking and defects caused by stress, and further reduce the interface defect density of the superconducting material.

[0040] In one example, the surface slope of the transition region 11 gradually flattens from the inclined side towards the top surface of the substrate, and the horizontal width of the transition region 11 ranges from 0.5μm to 5μm. A width that is too narrow cannot effectively alleviate the step coverage problem, while a width that is too large will occupy too much substrate planar space, which is not conducive to high-density bit integration. This transition region 11 can be integrally formed by combining grayscale photolithography with plasma etching, without the need for additional process steps.

[0041] In some embodiments, reference Figure 1 and Figure 2 It also includes: A third superconducting material layer 33 covers a portion of the top surface of the substrate layer 1 and is located away from the transition region 11.

[0042] The third superconducting material layer 33 is disposed in the planar region of the substrate layer 1 and is used to fabricate the peripheral functional circuits required for the superconducting quantum chip, including the readout resonant cavity of the quantum bit structure, control signal lines, coupling structures, and ground planes. This solves the problem of integrating the three-dimensional superconducting quantum bit structure with the peripheral circuits, spatially separating the core bit functional area from the peripheral circuit area, and avoiding damage to the superconducting thin film of the core bit area caused by the patterning process of the peripheral circuits. At the same time, the third superconducting material layer 33 can be fabricated with the first and second superconducting material layers 32 in the same step of thin film deposition and patterning process, without the need for additional steps, thus improving process compatibility.

[0043] In one example, the third superconducting material layer 33 is separated from the first superconducting material layer 31 and the second superconducting material layer 32 by a predetermined width of insulating space to ensure electrical isolation. The spacer region can be formed by removing the superconducting material through photolithography etching. The etching boundary is located in the planar region of the substrate, away from the conduction path of the capacitor core on the inclined side. Therefore, etching defects will not have a significant impact on the core performance of the quantum bit structure.

[0044] In some embodiments, it also includes: The third superconducting material layer 33 covers the top surface of the substrate layer 1, and the third superconducting material layer 33 in the transition region 11 is used to form other circuit structures required for the superconducting quantum chip.

[0045] The third superconducting material layer 33 completely covers the top planar area of ​​the substrate layer 1 and extends to the surface of the transition region 11, making full use of the entire planar space of the substrate to lay out the circuit, greatly improving the wiring density and integration of the chip; at the same time, the superconducting material on the surface of the transition region 11 can form coplanar waveguide transmission lines, inter-qubit coupling capacitors and other structures to achieve controllable coupling between adjacent quantum bit structures and low-loss transmission of control signals and readout signals.

[0046] In one example, the third superconducting material layer 33 of the transition region 11 can be designed as a transmission line structure with gradually varying impedance. The characteristic impedance of the transmission line can be controlled by the tilted morphology of the transition region 11, thereby optimizing signal transmission matching, reducing signal reflection and loss, and improving the performance of the quantum bit structure.

[0047] In some embodiments, the material of the substrate layer 1 is one or a combination of silicon, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and sapphire.

[0048] The protrusion 2 is located on the top surface of the substrate layer 1 and is the core structure for realizing the three-dimensional capacitor configuration. It expands the bearing surface of the traditional planar capacitor from a single plane to a three-dimensional inclined surface. The protrusion 2 includes a first inclined side 21 and a second inclined side 22, which provide inclined attachment interfaces for the two superconducting material layers, so that the electric field distribution and the main current conduction path of the capacitor are distributed along the normal and radial directions of the inclined side, thereby improving the performance of the quantum bit structure. The top surface of the protrusion 2 is located on the side away from the top surface of the substrate layer 1 and intersects with the first inclined side 21 and the second inclined side 22, respectively. The top surface of the protrusion 2 provides a horizontal fabrication platform for the Josephson junction structure 4, ensuring the consistency of the patterning accuracy and electrical performance of the Josephson junction, while realizing the connection of the top of the superconducting material layers on the two inclined side surfaces.

[0049] In some embodiments, reference Figure 1 and Figure 2 The protruding portion 2 has a rectangular or trapezoidal cross-sectional shape along the direction perpendicular to the top surface of the substrate layer 1.

[0050] The protrusion 2 has a rectangular or trapezoidal cross-sectional shape along the direction perpendicular to the top surface of the substrate 1. The cross-sectional shape corresponds to the sidewall morphology of the protrusion 2 and is determined by the type and parameters of the etching process. The two morphologies are adapted to different processes and integration requirements. The trapezoidal cross-section has continuously inclined sidewalls, corresponding to the complete first inclined sidewall 21 and second inclined sidewall 22. The capacitance and electric field dispersion effect is more significant, the etching edge ratio is lower, and the improvement effect on relaxation time is more obvious. The sidewalls of the rectangular cross-section are close to vertical, the protrusion 2 occupies a smaller substrate area, the space utilization rate is higher, and it is suitable for large-scale high-density quantum bit array integration. Moreover, the vertical sidewalls can be stably prepared by high-precision dry etching.

[0051] In one example, the sidewall inclination angle of the trapezoidal cross-section ranges from 30° to 70°. The smaller the inclination angle, the gentler the inclined side, the larger the capacitor plate area, and the wider the range of capacitor value adjustment, but the larger the plane area occupied by the protruding structure. The larger the inclination angle, the steeper the sidewall, and the higher the integration, but the difficulty of step coverage is slightly increased. The 30°-70° range can balance capacitor performance optimization and process feasibility.

[0052] In some embodiments, the top surface of the protrusion 2 is circular; The first inclined side 21 and the second inclined side 22 of the protrusion 2 are curved surfaces.

[0053] The protrusion 2 is a frustum-shaped structure with a continuous rotating curved surface on the inclined side. The combination of the circular top surface and the curved side surface makes the electric field distribution more uniform. The absence of electric field distortion and local enhancement at the corners can reduce the loss and breakdown risk caused by electric field concentration. At the same time, the curved surface structure has a more uniform thin film stress distribution, which can reduce the internal stress of the superconducting thin film after deposition, reduce stress-induced film cracking and defects, and improve the long-term reliability of the device.

[0054] In one example, the diameter of the top surface of the frustum-shaped protrusion ranges from 5μm to 50μm, and the height of the protrusion ranges from 2μm to 20μm. By adjusting the ratio of the top surface diameter to the height, the area and tilt angle of the inclined side can be precisely controlled, thereby enabling flexible design of the qubit capacitance value to adapt to the bit requirements of different frequencies.

[0055] In some embodiments, the top surface of the protrusion 2 is rectangular; The first inclined side 21 and the second inclined side 22 of the protrusion 2 are planes.

[0056] The inclined sides are flat planes. The first inclined side 21 and the second inclined side 22 are two sets of opposite inclined planes. The regular shape of the rectangular top surface is more suitable for large-scale array arrangement. The bit units can be closely arranged along the row and column directions, which significantly improves the space utilization and bit integration of the chip. At the same time, the patterning accuracy of the planar side is higher, and the size control in the photolithography and etching process is more precise. It is easy to realize the high-precision patterning of the superconducting capacitor plate and ensure the consistency of device performance in mass production.

[0057] In one example, the aspect ratio of the rectangular top surface can be flexibly designed between 1:1 and 5:1. When the aspect ratio is 1:1, the protrusion is a regular square frustum, and the lateral surface area in both directions is the same, which is suitable for symmetrical bit design. When the aspect ratio is greater than 1:1, the lateral surface area can be expanded along the long side to increase the capacitance value without increasing the width, which can meet the performance requirements of narrow-pitch bit arrays.

[0058] The first superconducting material layer 31 covers the first inclined side 21, and the second superconducting material layer 32 covers the second inclined side 22. The two layers are independently separated and together constitute the two superconducting plates of the three-dimensional capacitor. The first superconducting material layer 31 and the second superconducting material layer 32 extend and are distributed along the inclined side, so that the electric field and the main conduction path of the capacitor cover the main area of ​​the superconducting material over a large area. This significantly reduces the proportion of etching edge defects in the core conduction path, significantly weakens the negative impact of etching process defects on capacitor performance, and effectively improves the energy relaxation time and operational stability of the superconducting quantum bit. At the same time, the superconducting material layer is directly deposited and grown on the surface of the inclined side of the substrate. The number of growth defects at the interface is much lower than that of edge defects formed by etching, further reducing the degrading effect of defect sites on device performance.

[0059] In some embodiments, the materials of the first superconducting material layer 31, the second superconducting material layer 32, and the third superconducting material layer 33 are one or a combination of tantalum, aluminum, indium, titanium, niobium, or titanium nitride.

[0060] The Josephson junction structure 4 is located on the top surface of the protrusion 2 and is the core functional unit for realizing quantum state control and nonlinear inductance characteristics of superconducting qubits. The two ends of the Josephson junction structure 4 are electrically connected to the first superconducting material layer 31 and the second superconducting material layer 32, respectively, and together with the two superconducting capacitive plates, they form a complete superconducting qubit functional circuit. By relying on the horizontal top surface of the protrusion 2 to prepare the Josephson junction structure 4, the problems of uneven film thickness and high performance dispersion caused by the preparation of the inclined surface can be avoided, ensuring the performance consistency of the Josephson junction. At the same time, it can achieve low-loss direct connection with the inclined superconducting material layers on both sides, and form a complete three-dimensional superconducting circuit without the need to set additional planar transition leads, simplifying the device structure hierarchy and reducing the transmission loss and process defect risks introduced by additional leads.

[0061] Secondly, embodiments of this application provide a method for preparing a superconducting quantum bit structure. Figure 3 This is a schematic flowchart of a method for fabricating a superconducting quantum bit structure provided in some embodiments of this application. The method for fabricating the superconducting quantum bit structure includes the following steps: Step S101: A protruding portion is formed on the top surface of the substrate. A mask layer with a preset shape is prepared on the top surface of the substrate. The substrate is etched using the mask layer as a shield. After removing part of the substrate material, a substrate layer with a protruding portion is formed. The protruding portion includes a first inclined side and a second inclined side. Step S102: A superconducting material layer is formed on the top surface of the substrate layer, so that the superconducting material layer uniformly covers the top surface of the substrate layer and the protrusion; Step S103: The superconducting material layer is patterned by photolithography and etching processes to remove the superconducting material in the preset area, so that the remaining superconducting material layer covering the protrusion forms a first superconducting material layer and a second superconducting material layer covering the first inclined side and the second inclined side respectively. Step S104: Prepare a Josephson junction on the top surface of the protrusion, so that the two ends of the Josephson junction form a superconducting quantum bit structure with the first superconducting material layer and the second superconducting material layer.

[0062] In this application, firstly, the method first integrally forms a protrusion 2 with a first inclined side 21 and a second inclined side 22 on a substrate through mask etching, and then sequentially completes superconducting material deposition, patterning, and Josephson junction fabrication to finally obtain a superconducting quantum bit with a three-dimensional inclined capacitor structure. This fabrication process constructs a three-dimensional morphology on the substrate, so that the first superconducting material layer 31 and the second superconducting material layer 32 are extended and arranged along the inclined side. This transfers the electric field distribution and main inductance conduction path of the superconducting capacitor from the narrow band region of the etched edge of the traditional planar structure to the main superconducting material region of the inclined side. This significantly reduces the proportion of edge defects generated by patterning etching in the conduction path of the capacitor core. It solves the technical problem from the root of the existing planar quantum bit fabrication process that the etched boundary defects are located exactly in the conduction path of the capacitor core, which seriously degrades the device performance. This effectively improves the energy relaxation time and operating stability of the fabricated superconducting quantum bit. Meanwhile, the superconducting material layer is directly grown on the inclined side surface of the substrate layer 1 through a deposition process. The number of growth defects at the interface between the superconducting material and the substrate is much less than the number of edge defects formed by the etching process, which further reduces the negative impact of defect sites on the performance of superconducting qubits. The performance of the fabricated device is improved from two dimensions: structural layout optimization and interface quality enhancement.

[0063] Secondly, since this method fabricates the Josephson junction on the top surface of the protrusion 2, the flat top surface of the protrusion 2 provides a horizontal fabrication support surface for the Josephson junction, which can ensure the patterning accuracy and film thickness uniformity of the Josephson junction. This avoids the problems of uneven thickness, large performance dispersion, and low yield caused by fabricating the Josephson junction on an inclined surface. At the same time, the first superconducting material layer 31 and the second superconducting material layer 32 on the inclined side and the Josephson junction on the top surface can form a continuous three-dimensional superconducting circuit. The electrical connection between the capacitor plate and the Josephson junction can be completed without the need for additional planar transition leads. This simplifies the device fabrication process and avoids the transmission loss and process defect risks introduced by additional lead fabrication, ensuring the electrical integrity and fabrication yield of the core circuit of the superconducting quantum bit.

[0064] Furthermore, since all fabrication steps of this method are based on conventional semiconductor manufacturing processes such as mask fabrication, etching, thin film deposition, and photolithography patterning, the etching and shaping of the protrusion 2, the deposition and patterning of the superconducting material layer, and the fabrication of the Josephson junction can all be completed on existing superconducting device fabrication lines without the need for additional special process equipment or unconventional process steps. The overall process flow is highly compatible with existing superconducting quantum chip fabrication systems, has high process feasibility, and has a good foundation for mass production and promotion. At the same time, the morphology and size of the protrusion 2 can be flexibly controlled by adjusting the mask pattern and etching parameters, thereby flexibly controlling the capacitance and performance parameters of the quantum bit to adapt to the design requirements of different specifications of devices.

[0065] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0066] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0067] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A superconducting quantum bit structure, characterized in that, include: A substrate layer, the substrate layer including protrusions; The protrusion is disposed on the top surface of the substrate layer. The protrusion includes a first inclined side surface and a second inclined side surface that are opposite each other. The top surface of the protrusion is located on the side away from the top surface of the substrate layer. The top surface of the protrusion intersects with the first inclined side surface and the second inclined side surface, respectively. A first superconducting material layer, the first superconducting material layer covering the first inclined side surface; A second superconducting material layer, the second superconducting material layer covering the second inclined side surface; A Josephson junction structure is disposed on the top surface of the protrusion, and the Josephson junction structure, together with the first superconducting material layer and the second superconducting material layer, constitutes a superconducting quantum bit structure.

2. The superconducting quantum bit structure according to claim 1, characterized in that, The top surface of the substrate layer has a transition region along the circumferential direction of the protrusion, and the transition region intersects with the first inclined side surface and the second inclined side surface, respectively.

3. The superconducting quantum bit structure according to claim 1, characterized in that, Also includes: A third superconducting material layer covers a portion of the top surface of the substrate layer and is located away from the transition region.

4. The superconducting quantum bit structure according to claim 2, characterized in that, Also includes: A third superconducting material layer covers the top surface of the substrate layer, and the third superconducting material layer in the transition region is used to form other circuit structures required for the superconducting quantum chip.

5. The superconducting quantum bit structure according to claim 1, characterized in that, The substrate is made of one or a combination of silicon, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and sapphire.

6. The superconducting quantum bit structure according to claim 1, characterized in that, The materials of the first superconducting material layer, the second superconducting material layer and the third superconducting material layer are one or a combination of tantalum, aluminum, indium, titanium, niobium or titanium nitride.

7. The superconducting quantum bit structure according to claim 1, characterized in that, The protrusion has a rectangular or trapezoidal cross-sectional shape along the direction perpendicular to the top surface of the substrate.

8. The superconducting quantum bit structure according to claim 1, characterized in that, The top surface of the protrusion is circular; The first and second inclined sides of the protrusion are curved surfaces.

9. The superconducting quantum bit structure according to claim 1, characterized in that, The top surface of the protrusion is rectangular; The first and second inclined sides of the protrusion are planes.

10. A method for fabricating a superconducting quantum bit structure, characterized in that, Includes the following steps: A protruding portion is formed on the top surface of a substrate. A mask layer with a preset shape is prepared on the top surface of the substrate. The substrate is etched using the mask layer as a shield. After removing part of the substrate material, a substrate layer with a protruding portion is formed. The protruding portion includes a first inclined side surface and a second inclined side surface. A superconducting material layer is formed on the top surface of the substrate layer, so that the superconducting material layer uniformly covers the top surface of the substrate layer and the protrusion; The superconducting material layer is patterned by photolithography and etching processes, and the superconducting material in the preset area is removed, so that the remaining superconducting material layer covering the protrusion forms a first superconducting material layer and a second superconducting material layer covering the first inclined side and the second inclined side respectively. A Josephson junction is fabricated on the top surface of the protrusion, such that the two ends of the Josephson junction, together with the first superconducting material layer and the second superconducting material layer, form a superconducting quantum bit structure.

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