Classification method, process control method, device and medium

Abstract

This disclosure provides a classification method, processing control method, equipment, and medium. The classification method includes: obtaining height feature values ​​of a diced silicon wafer, wherein the height feature values ​​characterize the relative height polarity between the edge regions at both ends of the silicon wafer along the dicing direction; obtaining a positive threshold and a negative threshold; comparing the height feature values ​​with the positive and negative thresholds to obtain a comparison result, wherein the comparison result indicates the numerical relationship between the height feature values ​​and the positive and negative thresholds; and classifying the silicon wafer morphology into at least one of the following types based on the comparison result and preset classification rules: a centrally convex type, a centrally concave type, or a tilted type. This classification method can distinguish the types of morphologies of diced silicon wafers, providing a basis for differentiated processing of different morphologies, which is beneficial for improving the nanoscale flatness after subsequent polishing and increasing yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a method for classifying the morphology of diced silicon wafers, a method for controlling the processing of silicon wafers, equipment, and media. Background Technology

[0002] In the semiconductor manufacturing field, the quality of silicon wafers after dicing, such as wire dicing, directly determines whether they can successfully pass subsequent high-value processes such as grinding and polishing and achieve qualified nanometer-level flatness. Therefore, there is a need in this field to accurately evaluate the quality of diced silicon wafers in order to identify unfavorable morphologies that are detrimental to subsequent processing.

[0003] To evaluate the quality of diced silicon wafers, macroscopic geometric parameters such as warp and bow are commonly used in related technologies. While this approach can summarize the overall deformation range of the wafer with a single value and is easily incorporated into a quality control system, it only reflects the deformation range and cannot distinguish the macroscopic morphology of the wafer. In practice, it has been found that even silicon wafers with similar warp values ​​can exhibit significant differences in nanoscale flatness after subsequent polishing. This indicates that relying solely on macroscopic parameters such as warp cannot effectively characterize the macroscopic morphology features of silicon wafers that have a decisive impact on subsequent processes, thus highlighting the urgent need to differentiate the macroscopic morphology types of diced silicon wafers.

[0004] Therefore, how to effectively distinguish the macroscopic morphology types of diced silicon wafers has become a pressing technical problem to be solved in this field. Summary of the Invention

[0005] This disclosure provides a method for classifying the morphology of diced silicon wafers, a method for controlling the processing of silicon wafers, equipment, and a medium. The classification method compares the height characteristic value, which characterizes the relative height polarity of the edge regions at both ends along the dicing direction of the diced silicon wafer, with preset positive and negative thresholds. Based on the comparison results, the macroscopic morphology of the silicon wafer is classified into at least one of the following: a central convex type, a central concave type, or a tilted type, thereby enabling effective differentiation of the macroscopic morphology type of the diced silicon wafer.

[0006] The first aspect of this disclosure provides a method for classifying the morphology of a diced silicon wafer. The method includes: obtaining a height feature value of the diced silicon wafer, wherein the height feature value is used to characterize the relative height polarity between edge regions at both ends of the silicon wafer along the dicing direction; obtaining a positive threshold and a negative threshold, wherein the positive threshold and the negative threshold are preset numerical limits used to evaluate the polarity of the edge regions; comparing the height feature value with the positive threshold and the negative threshold to obtain a comparison result, wherein the comparison result is used to indicate the numerical relationship between the height feature value and the positive threshold and the negative threshold; and classifying the silicon wafer morphology into at least one of a centrally convex type, a centrally concave type, or a tilted type based on the comparison result and preset classification rules.

[0007] In one specific embodiment of the first aspect of this disclosure, the height feature value includes at least one of the following: the height value of a representative point in the edge region at both ends of the silicon wafer, the difference between the height values ​​of the representative points in the edge region at both ends of the silicon wafer, the ratio of the height values ​​of the representative points in the edge region at both ends of the silicon wafer, the slope value obtained by fitting the height data of the edge region at both ends of the silicon wafer, and the feature vector extracted from the height data of the edge region at both ends of the silicon wafer by a machine learning model.

[0008] In one specific embodiment of the first aspect of this disclosure, the height feature value includes the height values ​​of two representative points in the edge regions at both ends of the silicon wafer. Obtaining the height feature value of the diced silicon wafer includes: obtaining a height data sequence of the silicon wafer, wherein the height data sequence is a height data sequence of at least one measurement line on the surface of the silicon wafer along the dicing direction; and determining the representative height values ​​of two edge regions corresponding to the two ends of the measurement line, respectively, as the height values ​​of the two representative points.

[0009] In one specific embodiment of the first aspect of this disclosure, the representative height value is the height data corresponding to two measurement points within the edge region where the measurement line is located, or it is a value obtained by statistically calculating the height data of multiple measurement points within the edge region.

[0010] In one specific embodiment of the first aspect of this disclosure, the measurement line is the diameter of the silicon wafer along the cutting direction, and / or, when the representative height value is the height data corresponding to two measurement points located within the edge region of the measurement line, the two representative points are the first measurement point and the last measurement point on the measurement line.

[0011] In one specific embodiment of the first aspect of this disclosure, based on comparison results and preset classification rules, the silicon wafer morphology is classified into at least one of the following: a centrally protruding type, a centrally recessed type, or a tilted type. This includes: when the height values ​​of the first and last measurement points are both greater than a negative threshold and at least one is greater than a positive threshold, the wafer is classified as a centrally recessed type; when the height values ​​of the first and last measurement points are both less than a positive threshold and at least one is less than a negative threshold, the wafer is classified as a centrally protruding type; when the height values ​​of the first and last measurement points have opposite polarities and the one with the larger absolute value is greater than a positive threshold, the wafer is classified as a tilted type.

[0012] In one specific embodiment of the first aspect of this disclosure, the classification method further includes: if the classification is of the tilt type, then further classification is performed based on the sign of the height data with the larger absolute value: if the height data with the larger absolute value is positive, then further classification is of the positive tilt type; if the height data with the larger absolute value is negative, then further classification is of the negative tilt type.

[0013] In one specific embodiment of the first aspect of this disclosure, the classification method further includes: collecting nanoscale flatness data of the classified silicon wafers after subsequent polishing processes; and adjusting positive and negative thresholds based on the nanoscale flatness data.

[0014] The second aspect of this disclosure provides a processing control method for silicon wafers, the processing control method comprising: obtaining a classification result of the morphology of the diced silicon wafer, wherein the classification result is obtained by the classification method described in the first aspect above; determining a processing control decision for the silicon wafer based on the classification result, wherein the processing control decision includes flipping the silicon wafer or not flipping it; flipping the wafer when the classification result is a central concave type; not flipping the wafer when the classification result is a central convex type; determining a further classification of the tilt type when the classification result is a tilt type; flipping the wafer if the further classification is a positive tilt type; and not flipping the wafer if the further classification is a negative tilt type.

[0015] A third aspect of this disclosure provides a computing device including a processor and a memory, the processor being configured to execute instructions stored in the memory to implement the classification method of the first aspect and / or the processing control method of the second aspect.

[0016] The fourth aspect of this disclosure provides a computer storage medium storing at least one instruction, which is executed by a processor to implement the classification method in the first aspect and / or the processing control method in the second aspect. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a method for classifying the morphology of diced silicon wafers according to an embodiment of this disclosure.

[0018] Figure 2 This is a partial flowchart illustrating a method for classifying the morphology of diced silicon wafers according to an embodiment of this disclosure.

[0019] Figure 3 This is a flowchart illustrating a method for classifying the morphology of diced silicon wafers according to another embodiment of this disclosure.

[0020] Figure 4 This is a partial flowchart illustrating a method for classifying the morphology of diced silicon wafers according to an embodiment of this disclosure.

[0021] Figure 5 This is a flowchart illustrating a method for classifying the morphology of diced silicon wafers according to an embodiment of this disclosure.

[0022] Figure 6 This is a flowchart illustrating a method for classifying the morphology of diced silicon wafers according to another embodiment of this disclosure.

[0023] Figure 7 This is a partial flowchart illustrating a method for classifying the morphology of diced silicon wafers according to an embodiment of this disclosure.

[0024] Figure 8 This is a schematic flowchart illustrating a silicon wafer processing control method according to an embodiment of the present disclosure.

[0025] Figure 9 A schematic diagram of a classification device for the morphology of diced silicon wafers provided in an embodiment of this disclosure.

[0026] Figure 10 This is a schematic block diagram of a silicon wafer processing control device provided in one embodiment of the present disclosure.

[0027] Figure 11 A schematic block diagram of a computing device provided in an embodiment of this disclosure. Detailed Implementation

[0028] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] In the field of semiconductor silicon wafer manufacturing, a common technique for evaluating the quality of diced silicon wafers, such as those after wire dicing, is to obtain the overall macroscopic geometric parameters of the wafer. These parameters primarily include warp and bow values. This approach typically involves collecting height data from multiple points on the wafer surface using high-precision flatness measurement equipment, and calculating the overall deformation of the wafer based on a constructed ideal plane. The warp value reflects the total deviation of the highest and lowest points on the wafer surface relative to this ideal plane, while the bow value reflects the degree of deviation between the wafer's center point and the ideal plane. This method can summarize the overall flatness of the wafer with a single value, is easily incorporated into quality control systems, and can roughly characterize whether the wafer is suitable for subsequent processing steps; therefore, it is widely used.

[0030] However, when more refined classification of wire-cut silicon wafers is required to identify their morphological orientation type, i.e., macroscopic morphology, the aforementioned macroscopic geometric parameter scheme does not perform ideally. For example, a hat-shaped silicon wafer with a raised center and a bowl-shaped silicon wafer with a recessed center may exhibit similar Warp values, but the nanoscale flatness parameter of the hat-shaped silicon wafer will spontaneously improve during subsequent polishing processes, while that of the bowl-shaped silicon wafer will deteriorate.

[0031] This is due to a fundamental mismatch between the parameter definitions of Warp and Bow values ​​and the information required for morphological orientation classification: Warp values ​​rely on the algebraic difference between the highest and lowest points on the surface after constructing an ideal plane; this difference only reflects the deformation amplitude, not the sign polarity and relative size of the endpoints. Bow values ​​only reflect the bending direction and degree at the center of the silicon wafer, similarly failing to provide the relative height relationship between the edge regions at both ends. However, the key to distinguishing between hat-shaped, bowl-shaped, and S-shaped morphologies lies in the sign of the height values ​​of the edge regions at both ends of the silicon wafer relative to the reference plane along the cutting direction, as well as the numerical relationship between them. This information is naturally lost during the calculation of Warp and Bow values. These unscreened silicon wafers flow into subsequent processing steps, resulting in excessive nanometer-level flatness parameters and reduced yield in the final polished wafers.

[0032] Therefore, there is an urgent need to provide a new technical solution that can overcome the inherent limitations of macroscopic geometric parameters Warp and Bow values ​​in capturing macroscopic morphological directionality information, and achieve accurate classification of the morphological directionality type of silicon wafers after dicing.

[0033] In view of this, embodiments of the present disclosure provide a method for classifying the morphology of a diced silicon wafer. The classification method includes: obtaining a height feature value of the diced silicon wafer, wherein the height feature value is used to characterize the relative height polarity between the edge regions at both ends of the silicon wafer along the dicing direction; obtaining a positive threshold and a negative threshold, wherein the positive threshold and the negative threshold are preset numerical limits used to evaluate the polarity of the edge regions; comparing the height feature value with the positive threshold and the negative threshold to obtain a comparison result, wherein the comparison result is used to indicate the numerical relationship between the height feature value and the positive threshold and the negative threshold; and classifying the silicon wafer morphology into at least one of the following: a centrally convex type, a centrally concave type, or a tilted type, based on the comparison result and preset classification rules.

[0034] Thus, the classification method provided in this disclosure no longer relies on a single macroscopic parameter describing the overall deformation amplitude, such as the Warp value or Bow value, but adopts a morphology classification method based on the height polarity of the edge regions at both ends and a dual-threshold logical judgment. This method directly captures and utilizes the inherent height polarity differences of the edge regions of the silicon wafer after dicing, replacing the method that relies solely on macroscopic warp and curvature and cannot distinguish the morphological orientation type with a simple dual-threshold logical judgment. Therefore, it can accurately distinguish silicon wafer morphologies such as the centrally convex type (hat-shaped), the centrally concave type (bowl-shaped), and the tilted type (S-shaped) immediately and at low cost after online dicing, filling the gap in the existing macroscopic classification methods in morphological orientation recognition.

[0035] Therefore, this method achieves direct quantification of the essential features of morphology by extracting and comparing the polarity information. Simultaneously, the preset positive and negative thresholds provide a robust and tolerable boundary for measurement noise and process fluctuations, ensuring the simplicity and interpretability of the classification logic without introducing complex signal processing or gettering techniques.

[0036] The following describes, with reference to the accompanying drawings, a method for classifying the morphology of diced silicon wafers, a method for controlling the processing of silicon wafers, an apparatus, and a medium according to at least one embodiment of the present disclosure.

[0037] In the classification method for the morphology of diced silicon wafers provided in at least one embodiment of this disclosure, such as Figure 1 As shown, the classification method includes the following steps S100 to 400.

[0038] Step S100: Obtain the height feature value of the diced silicon wafer, wherein the height feature value is used to characterize the relative height polarity between the edge regions at both ends of the silicon wafer along the dicing direction.

[0039] Specifically, height characteristics can include any parameter or value that can quantify the relative height polarity between the edge regions at both ends of the silicon wafer along the cutting direction, i.e., the tendency and degree of height difference between one end and the other. The purpose is to transform the directional differences in the macroscopic morphology of the silicon wafer into a comparable numerical value.

[0040] Step S200: Obtain a positive threshold and a negative threshold, wherein the positive threshold and the negative threshold are preset numerical limits used to evaluate the polarity of the edge region.

[0041] Specifically, the positive threshold is a positive value, denoted as Th_high, and the negative threshold is a negative value, denoted as Th_low. Their function is to provide a certain tolerance range, namely the region between Th_low and Th_high, to effectively suppress random noise during the measurement process and normal fluctuations introduced by the manufacturing process, avoiding misjudging minor, non-essential fluctuations as characteristic morphologies. Compared to using zero as a single benchmark for determining positive or negative polarity, the dual-threshold mechanism provides a more robust decision boundary for classification.

[0042] This disclosure does not impose specific limitations on the values ​​of the positive and negative thresholds; they can be determined based on specific production line process conditions and historical data. For example, for a silicon wafer with a diameter of 300mm, Th_high can be set to +7μm and Th_low to -7μm, but the actual values ​​are not limited to these and can be dynamically adjusted according to the feedback optimization mechanism.

[0043] Step S300: Compare the height feature value with the positive threshold and the negative threshold to obtain the comparison result, wherein the comparison result is used to indicate the numerical relationship between the height feature value and the positive threshold and the negative threshold.

[0044] Specifically, the comparison result is not a single numerical value, but a set of logical states, such as indicating whether it is greater than Th_high, whether it is less than Th_low, whether it is between Th_low and Th_high, and whether the polarities of the two endpoints are the same.

[0045] Step S400: Based on the comparison results and preset classification rules, classify the silicon wafer morphology into at least one of the following: central convex type, central concave type, or inclined type.

[0046] Specifically, the preset classification rules are a set of logical mapping relationships that map the comparison results to morphological types. The essence of this mapping relationship is that the logical state output by step S300, which represents the numerical relationship between the height values ​​of the edge regions at both ends and the positive and negative thresholds, i.e., the comparison result, is used as the criterion input. Through a set of predetermined condition combinations, it is uniquely mapped to one of the morphological categories: convex in the middle, concave in the middle, or sloping.

[0047] A convex-center morphology refers to a silicon wafer whose central region is significantly higher than its two edge regions along the cutting direction, such as a hat-shaped morphology. A concave-center morphology refers to a silicon wafer whose central region is significantly lower than its two edge regions along the cutting direction, such as a bowl-shaped morphology. A tilted morphology refers to a silicon wafer whose relative height at one edge along the cutting direction differs significantly from that at the other edge, such as an S-shaped morphology.

[0048] Therefore, step S100 serves as the data input and feature extraction stage for the entire classification method. It provides the core physical quantity for subsequent threshold comparison. Essentially, this step transforms the morphological directionality problem, which is difficult to directly compare mathematically, into one or more quantifiable high-level feature values. By defining these high-level feature values, step S100 establishes a unified and computable evaluation object for subsequent steps S200 and S300, forming the cornerstone for the entire method to achieve quantitative discrimination from qualitative observation.

[0049] Step S200 aims to establish a benchmark for evaluating the classification method. It introduces two key numerical limits: a positive threshold and a negative threshold, providing a tolerant scale for classification. This step addresses the problem of excessive sensitivity to measurement noise and process fluctuations when relying solely on the zero endpoint height value for "positive / negative" judgment. By presetting positive and negative thresholds, step S200 constructs an asymmetric polarity saliency determination framework, making the classification results more robust.

[0050] Step S300 serves as a bridge and link between data and classification results. It logically compares the high-value features obtained in step S100 with the evaluation criteria set in step S200, generating a quantitative basis for the final decision, i.e., the comparison result. This step is a purely numerical / logical operation process, without relying on complex physical models or iterative calculations, ensuring the efficiency and repeatability of classification, and paving the way for the programmable implementation of step S400.

[0051] Step S400 serves as the final decision-making and morphology identification step in the entire method. Based on the comparison results generated in step S300, this step uses preset classification rules that match the physical mechanism to instantly and accurately classify the silicon wafer into one of three types: center-protruding, center-recessed, or tilted. This classification result provides a direct and reliable source of instructions for subsequent differential processing (such as whether to perform a flipping operation).

[0052] In some embodiments of this disclosure, the height feature value includes at least one of the following: the height value of a representative point in the edge region at both ends of the silicon wafer, the difference between the height values ​​of the representative points in the edge region at both ends of the silicon wafer, the ratio of the height values ​​of the representative points in the edge region at both ends of the silicon wafer, the slope value obtained by fitting the height data of the edge region at both ends of the silicon wafer, and the feature vector extracted from the height data of the edge region at both ends of the silicon wafer by a machine learning model.

[0053] Specifically, representative points are one or more key location points determined from the edge regions at both ends of the silicon wafer to characterize the height features of that region. These can be single measurement points directly taken from specific locations within the edge region on the measurement line, or virtual points obtained by statistically calculating the height data of multiple measurement points within the edge region, such as the mean, median, or weighted average. These virtual points correspond to a statistically representative height value.

[0054] Different forms of height eigenvalues ​​can extract information characterizing the relative height polarity of the two edge regions from different measurement data characteristics.

[0055] For example, the representative point height value can directly reflect the absolute height of the two endpoints of the silicon wafer. It is the simplest and most direct form of feature, with low computational complexity, and is suitable for production line environments with high measurement accuracy and low noise. For instance, the representative point height value can be directly taken from the height data of the first measurement point R1 and the last measurement point RN on the measurement line.

[0056] For example, the difference in the representative point height values ​​can characterize the magnitude of the height difference between the two ends, effectively offsetting the systematic errors introduced by fluctuations in the reference plane. For instance, subtracting the representative point height values ​​at both ends yields the difference ΔH = R1 - RN. The larger this difference is, the more significant and stronger the height difference between the two ends is.

[0057] For example, the ratio representing point height values, as a normalized relative quantity, can eliminate interference from differences in the absolute levels of thickness or curvature between different batches of silicon wafers. For instance, the ratio of the point height values ​​at both ends, Ratio = R1 / RN (or RN / R1), is calculated, and the degree to which the ratio deviates from 1 reflects the strength and direction of the polarity.

[0058] For example, the fitted slope value is obtained by linearly fitting the height data of multiple measurement points in the edge regions at both ends, such as using the least squares method, to obtain the slope of the fitted line. This slope value takes into account the overall trend of change in the edge region, rather than relying solely on a single measurement point, and thus can better suppress the influence of local measurement noise.

[0059] For example, machine learning feature vectors automatically learn the most discriminative feature representations from height data in the edge regions using pre-trained machine learning models such as convolutional neural networks and support vector machines. This approach can capture complex feature patterns that are difficult to define manually, and achieves higher classification accuracy in production line conditions with large amounts of data and complex morphological variations.

[0060] Thus, by expanding the height feature value from a single endpoint height value to the aforementioned alternative forms, the most discriminative and stable feature quantity can be flexibly selected based on the actual data noise level, measurement equipment characteristics, and production line conditions, thereby improving the adaptability and accuracy of the morphology classification method in different application scenarios.

[0061] In some implementations, the height feature value may also include two or more of the above-mentioned forms, and multiple feature values ​​are combined for joint judgment to further improve the robustness and fault tolerance of classification.

[0062] Based on the above embodiments, this disclosure further limits the implementation method for obtaining height feature values ​​when the height feature values ​​are two representative point height values. For example... Figure 2 As shown, in step S100, obtaining the height feature value of the cut silicon wafer includes the following steps S110 to S120.

[0063] Step S110: Obtain the height data sequence of the silicon wafer, wherein the height data sequence is the height data sequence of at least one measurement line on the surface of the silicon wafer along the cutting direction.

[0064] Specifically, a height data sequence refers to a dataset consisting of a series of relative height values ​​collected at equal or specific intervals along at least one selected measurement line on the surface of a silicon wafer along the cutting direction, arranged in the order of collection. The starting point of the collection sequence is the first measurement point, R1, and the ending point is the last measurement point, RN.

[0065] For example, this height data sequence can be obtained using high-precision flatness measurement equipment such as an optical interferometer or a contact profilometer, with each measurement point recording the height value relative to a reference plane.

[0066] Step S120: Determine the representative height values ​​of the two edge regions corresponding to the two ends of the measurement line, and use them as the height values ​​of the two representative points.

[0067] Specifically, the edge region in step S120 refers to a local area on the silicon wafer surface near both ends along the cutting direction, used to extract height feature values. The representative height value is a numerical value determined from the edge region that can represent the overall height level of that region.

[0068] Therefore, step S110 is intended as the acquisition step of the original morphology data. Its core is to select a measurement line that can fully reflect the relative height relationship between the two ends of the cutting direction, so as to ensure that the extracted feature values ​​have the highest correlation with the morphology directionality and provide high-resolution, quantifiable spatial information for subsequent feature extraction.

[0069] Step S120 is designed as a condensation and extraction step from the raw data to key features. It simplifies the entire height data sequence obtained in step S110 into only two values ​​representing the edge regions at both ends, i.e., two representative point height values. This compresses the complex overall shape contour information into only the two feature quantities most relevant to the shape orientation classification, simplifying the computational complexity of subsequent comparison and judgment. This allows the entire classification process to be completed in a very short time, making it suitable for real-time deployment in online production environments.

[0070] In at least one embodiment of this disclosure, the representative height value is the height data corresponding to two measurement points within the edge region of the measurement line, or it is a value obtained by statistically calculating the height data of multiple measurement points within the edge region. These two methods can be flexibly selected according to the actual measurement conditions.

[0071] For example, when there are few measurement points or the measurement accuracy is sufficient, the height data of a single measurement point within the edge region can be directly taken as the representative height value. For instance, the height values ​​of the first measurement point (R1) and the last measurement point (RN) on the measurement line can be directly used as the representative point height value. This method simplifies the calculation process, improves processing speed, and is suitable for online real-time classification scenarios.

[0072] For example, when the edge region contains multiple measurement points, the representative height value can be obtained by statistically calculating the height data of these measurement points, such as taking the arithmetic mean, median, mode, etc. Obtaining the value through statistical calculation effectively suppresses the disturbance of local noise to single-point data and improves the stability of feature values.

[0073] Based on the above embodiments, in some embodiments of this disclosure, the measurement line is the diameter of the silicon wafer along the cutting direction. Thus, selecting the measurement line as the diameter along the cutting direction allows for maximum coverage of both ends of the silicon wafer, thereby capturing the most significant height polarity differences and avoiding weakening of the classification signal due to measurement line offset.

[0074] Based on the above embodiments, in at least one embodiment of this disclosure, when the representative height value is the height data corresponding to two measurement points located within the edge region of the measurement line, the two representative points are the first and last measurement points on the measurement line. Thus, directly taking the first and last measurement points of the measurement line as representative points eliminates the need for additional interpolation or region division. This implementation method is the simplest and most direct, and is particularly suitable for online real-time deployment.

[0075] In the classification method for the morphology of diced silicon wafers provided in at least another embodiment of this disclosure, such as Figure 3 As shown, the classification method includes the following steps S11 to S40.

[0076] Step S11: Obtain the height data sequence of the silicon wafer, wherein the height data sequence is the height data sequence of at least one measurement line on the surface of the silicon wafer along the cutting direction.

[0077] Step S12: Determine the representative height values ​​of the two edge regions corresponding to the two ends of the measurement line, and use them as the height values ​​of the two representative points.

[0078] Step S20: Obtain a positive threshold and a negative threshold, wherein the positive threshold and the negative threshold are preset numerical limits used to evaluate the polarity of the edge region.

[0079] Step S30: Compare the height feature value with the positive threshold and the negative threshold to obtain the comparison result, wherein the comparison result is used to indicate the numerical relationship between the height feature value and the positive threshold and the negative threshold.

[0080] Step S40: Based on the comparison results and preset classification rules, classify the silicon wafer morphology into at least one of the following: central convex type, central concave type, or inclined type.

[0081] Furthermore, the specific implementation methods of steps S11 to S40 can be referred to the description of the above embodiments, and will not be repeated here.

[0082] Based on the height values ​​of the two representative points obtained in the above embodiments, the morphology classification step can be performed. In some embodiments of this disclosure, such as... Figure 4 As shown, in step S400, based on the comparison results and preset classification rules, the silicon wafer morphology is classified into at least one of the following types: central convex type, central concave type, or inclined type, including the following steps S401 to S403.

[0083] Step S401: When the height values ​​of the first and last measurement points are both greater than the negative threshold and at least one is greater than the positive threshold, the type is classified as a central depression.

[0084] Specifically, the central concave type corresponds to a bowl-shaped morphology, meaning that the relative height of the central region of the silicon wafer is lower than that of the two edge regions.

[0085] Step S402: When the height values ​​of the first and last measurement points are both less than the positive threshold and at least one is less than the negative threshold, the type is classified as a central convex type.

[0086] Specifically, the central convex shape corresponds to the hat-shaped morphology, meaning that the relative height of the central region of the silicon wafer is higher than that of the two edge regions.

[0087] Step S403: When the height values ​​of the first and last measurement points have opposite polarities, and the one with the larger absolute value is greater than the positive threshold, it is classified as a tilted type.

[0088] Specifically, the tilted type corresponds to the S-shaped morphology, that is, the relative height of the edge region at one end of the silicon wafer is significantly higher or lower than that at the other end.

[0089] Thus, the classification rules in the above embodiments are implemented directly through clear dual-threshold logic combination conditions, without relying on complex models or iterative calculations. They can be executed in real time in the control unit of embedded systems or measurement devices, ensuring the immediacy of classification and the interpretability of results.

[0090] Based on the above embodiments, this embodiment further subdivides the tilt type. In a specific embodiment of the first aspect of this disclosure, the classification method further includes: if classified as tilt type, further classification is performed based on the sign of the height data with the larger absolute value: if the height data with the larger absolute value is positive, it is further classified as positive tilt type; if the height data with the larger absolute value is negative, it is further classified as negative tilt type. Thus, subdividing the tilt type into positive and negative subtypes can accurately indicate the specific tilt direction of the S-shaped silicon wafer, providing precise guidance for subsequent targeted selection of whether to flip it, and avoiding unnecessary operations or adverse effects introduced by uniformly processing all S-shaped wafers.

[0091] In the classification method for the morphology of diced silicon wafers provided in at least one embodiment of this disclosure, such as Figure 5 As shown, the classification method includes the following steps S10a to S43a2.

[0092] Step S10a: Obtain the height feature value of the diced silicon wafer, wherein the height feature value is used to characterize the relative height polarity between the edge regions at both ends of the silicon wafer along the dicing direction.

[0093] Step S20a: Obtain a positive threshold and a negative threshold, wherein the positive threshold and the negative threshold are preset numerical limits used to evaluate the polarity of the edge region.

[0094] Step S30a: Compare the height feature value with the positive threshold and the negative threshold to obtain the comparison result, wherein the comparison result is used to indicate the numerical relationship between the height feature value and the positive threshold and the negative threshold.

[0095] Step S40a: Based on the comparison results and preset classification rules, classify the silicon wafer morphology into at least one of the following: central convex type, central concave type, or inclined type.

[0096] Step S41a: When the height values ​​of the first and last measurement points are both greater than the negative threshold and at least one is greater than the positive threshold, the type is classified as a central depression.

[0097] Step S42a: When the height values ​​of the first and last measurement points are both less than the positive threshold and at least one is less than the negative threshold, the type is classified as a central convex type.

[0098] Step S43a: When the height values ​​of the first and last measurement points have opposite polarities, and the one with the larger absolute value is greater than the positive threshold, it is classified as tilted, and further classified according to the sign of the height data with the larger absolute value.

[0099] Step S43a1: If the height data with a larger absolute value is positive, then it is further classified as positive slant type.

[0100] Step S43a2: If the height data with a larger absolute value is negative, it is further classified as negative skew type.

[0101] Based on the above embodiments, the classification method also includes a closed-loop dynamic adjustment mechanism for positive and negative thresholds, and the specific implementation is as follows.

[0102] In some embodiments of this disclosure, the classification method further includes: collecting nanoscale flatness data of the classified silicon wafers after subsequent polishing processes; and adjusting positive and negative thresholds based on the nanoscale flatness data.

[0103] In actual production line operation, due to factors such as fluctuations in cutting process parameters, batch differences in raw materials, or drift of measuring equipment, the originally calibrated fixed threshold may gradually cease to be the optimal classification boundary. If the threshold is set too wide, some bowl-shaped or unfavorable S-shaped silicon wafers may be missed and flow into subsequent processes; if the threshold is set too strict, some flat or non-directional silicon wafers may be misclassified as unfavorable, causing unnecessary flipping. Therefore, by introducing a feedback adjustment mechanism based on actual polishing results, the classification judgment rules can continuously adapt to process changes and maintain high accuracy in the long term.

[0104] In the classification method for the morphology of diced silicon wafers provided in at least one embodiment of this disclosure, such as Figure 6 As shown, the classification method includes the following steps S10b to S52b.

[0105] Step S10b: Obtain the height feature value of the diced silicon wafer, wherein the height feature value is used to characterize the relative height polarity between the edge regions at both ends of the silicon wafer along the dicing direction.

[0106] Step S20b: Obtain a positive threshold and a negative threshold, wherein the positive threshold and the negative threshold are preset numerical limits used to evaluate the polarity of the edge region.

[0107] Step S30b: Compare the height feature value with the positive threshold and the negative threshold to obtain the comparison result, wherein the comparison result is used to indicate the numerical relationship between the height feature value and the positive threshold and the negative threshold.

[0108] Step S40b: Based on the comparison results and preset classification rules, classify the silicon wafer morphology into at least one of the following: central convex type, central concave type, or inclined type.

[0109] Step S51b: Collect nanoscale flatness data of the classified silicon wafers after subsequent polishing processes.

[0110] Step S52b: Adjust the positive and negative thresholds based on nanoscale flatness data.

[0111] It should be noted that the specific implementation methods of steps S10b to 52b can be referred to the above embodiments, and will not be repeated here.

[0112] In some embodiments of this disclosure, in step S52b, such as Figure 7 As shown, adjusting the positive and negative thresholds based on nanoscale flatness data includes the following steps S52b1 to S52b2.

[0113] Step S52b1: Establish a correlation database between silicon wafer morphology type and final flatness.

[0114] Specifically, for each silicon wafer that has undergone morphology classification and processing (e.g., flipping or not flipping), the classification results, processing operations, and nanometer-level flatness indices measured after standard polishing processes are recorded. These flatness indices may include, for example, Site Front-surface referenced Least-squares Range (SFQR) or other equivalent nanometer-level flatness evaluation parameters. By continuously accumulating the above data, a database of correspondences between morphology types, processing methods, and flatness results is formed.

[0115] Step S52b2: Dynamically adjust the positive and negative thresholds based on the associated database.

[0116] Specifically, by analyzing historical data in the associated database, the flatness performance of silicon wafers of various morphologies under the current threshold conditions can be determined, and threshold intervals with a tendency to be misjudged or missed can be identified.

[0117] For example, if some silicon wafers classified as flat are found to have significantly worse flatness than expected after polishing, it may indicate that the current threshold is too wide and needs to be tightened to capture more undesirable topography. Conversely, if some silicon wafers classified as bowl-shaped and flipped show limited improvement in final flatness, it may indicate that the current threshold is too strict and needs to be appropriately relaxed to reduce unnecessary flipping operations.

[0118] Therefore, the method provided in this disclosure can dynamically adjust the specific values ​​of the positive and negative thresholds to optimize the overall classification and sorting effect. After re-executing the aforementioned classification steps based on the adjusted positive and negative thresholds, the subsequent classification results and polishing flatness data of silicon wafers are collected again and incorporated into the associated database, forming a continuous closed-loop feedback optimization mechanism. This adaptive threshold management method enables the accuracy and robustness of the classification method to continuously improve with the increase of production line operating time, thereby steadily improving the yield of the final polished wafers in the long term.

[0119] This disclosure also provides a method for controlling the processing of silicon wafers, such as... Figure 8 As shown, the processing control method includes the following steps S010 to S023b.

[0120] Step S010: Obtain the classification result of the morphology of the diced silicon wafer, wherein the classification result is obtained by the classification method in the above embodiment.

[0121] Step S020: Determine the processing control decision for the silicon wafer based on the classification results, wherein the processing control decision includes whether to flip the silicon wafer or not.

[0122] Step S021: When the classification result is a concave type, then flip it.

[0123] Step S022: When the classification result is a convex shape in the middle, do not flip it.

[0124] Step S023: When the classification result is skewed, determine the further classification of the skewed type.

[0125] Step S023a: If further classified as positive tilt type, then flip it.

[0126] Step S023b: If further classified as negative skew type, then no flipping is performed.

[0127] Thus, the concave-center, bowl-shaped wafer, which is unfavorable for planarization during subsequent polishing, can be transformed into a convex-center wafer by flipping it. This convex shape naturally improves planarity during subsequent processing, thereby reducing nanometer-level planarity parameters and increasing yield. The convex-center shape itself promotes planarization, so flipping is unnecessary. For the tilted wafer, the direction of tilt determines whether to flip it, resulting in a more uniform force distribution during polishing, similarly improving planarity. This method can be rapidly completed in the sorting stage using automated flipping equipment at extremely low cost, without increasing production cycle time.

[0128] This disclosure also provides a classification device for the morphology of diced silicon wafers, such as... Figure 9 As shown, the classification device 700 includes a height feature value acquisition module 710, a threshold acquisition module 720, a comparison module 730, and a classification module 740.

[0129] The height feature value acquisition module 710 is configured to acquire the height feature value of the diced silicon wafer, wherein the height feature value is used to characterize the relative height polarity between the edge regions at both ends of the silicon wafer along the dicing direction.

[0130] The threshold acquisition module 720 is configured to acquire a positive threshold and a negative threshold, wherein the positive threshold and the negative threshold are preset numerical limits used to evaluate the polarity of the edge region.

[0131] The comparison module 730 is configured to compare the height feature value with a positive threshold and a negative threshold to obtain a comparison result, wherein the comparison result is used to indicate the numerical relationship between the height feature value and the positive threshold and the negative threshold.

[0132] The classification module 740 is configured to classify the silicon wafer morphology into at least one of the following types based on the comparison results and preset classification rules: central convex type, central concave type, or inclined type.

[0133] This disclosure also provides a silicon wafer processing control device, such as... Figure 10 As shown, the processing control device 800 includes a classification result acquisition module 810 and an execution module 820. The classification result acquisition module 810 is configured to acquire the classification result of the morphology of the diced silicon wafer, wherein the classification result is obtained by the classification method in the above embodiment. The execution module 820 is configured to determine a processing control decision for the silicon wafer based on the classification result, wherein the processing control decision includes whether to flip the silicon wafer or not; when the classification result is a central concave type, flipping is performed; when the classification result is a central convex type, flipping is not performed; when the classification result is a tilted type, further classification of the tilted type is determined; if the further classification is a positive tilted type, flipping is performed; if the further classification is a negative tilted type, flipping is not performed.

[0134] The specific operation of each module of the above device can be referred to the description of the above embodiments, and will not be repeated here.

[0135] To enable those skilled in the art to more intuitively understand the specific implementation of this technical solution in production practice and the actual effects it can achieve, an exemplary description is provided below using a typical wafer manufacturing workshop application scenario.

[0136] In the dicing workshop of a semiconductor silicon wafer manufacturing plant, a multi-wire dicing machine has just completed the dicing of a batch of silicon wafers with a diameter of 300 mm. The wafers exhibit different macroscopic morphologies, including a centrally convex shape (hat-shaped), a centrally concave shape (bowl-shaped), and an S-shaped shape where one edge is higher than the other along the dicing direction. In related technologies, operators can only obtain macroscopic geometric parameters such as warp and bow for each wafer, making it impossible to accurately determine the specific directional morphology type of each wafer. This results in some centrally concave and S-shaped wafers, which are detrimental to subsequent processing, not being identified and removed in time. Instead, they are transferred to the grinding and polishing process along with the centrally convex wafers, ultimately causing localized flatness parameter deviations and overall yield loss after the final polishing process.

[0137] Our factory has integrated a shape classification scheme based on height feature values ​​into our existing flatness measurement equipment. When a freshly cut silicon wafer is fed into the measurement station by the conveyor arm, the equipment automatically triggers the shape classification process.

[0138] First, a high-precision optical interferometer scans along the cutting direction (diameter) of the silicon wafer surface to acquire a height data sequence containing 73 equally spaced measurement points. Each point records its height value relative to an ideal plane. The measurement line spans the entire diameter of the silicon wafer, ensuring that the height information of the edge regions at both ends is completely captured.

[0139] At the moment data acquisition is complete, the height values ​​of the first and last measurement points are extracted from the height sequence and denoted as R1 and RN, respectively. These two points correspond precisely to the edge regions at both ends of the silicon wafer's diameter, and their values ​​directly characterize the polarity of the relative height at both ends. In this scenario, the system uses the thresholds calibrated at the factory: a positive threshold Th_high of +7 micrometers and a negative threshold Th_low of -7 micrometers. Subsequently, R1 and RN are compared with these two thresholds, and a preset dual-threshold logic judgment is executed.

[0140] The current measurement results for the silicon wafer show that R1 is +9.2 micrometers and RN is +1.8 micrometers. Both values ​​are greater than the negative threshold of -7 micrometers, and R1 is greater than the positive threshold of +7 micrometers, meeting the criteria for a concave center. The equipment immediately classifies the silicon wafer as bowl-shaped and outputs a processing suggestion to flip it. Almost simultaneously, the equipment flips the silicon wafer from front to back in less than three seconds during the sorting process, changing it from a bowl shape to a hat shape. As a result, when the silicon wafer enters the subsequent double-sided grinding and chemical mechanical polishing processes, the material removal distribution is more conducive to achieving nanoscale planarization. The final local flatness SFQR of the polished wafer drops from an average of 13.3 micrometers for similar unflipped silicon wafers to about 11.2 micrometers, and the defect rate drops from 3.2% to below 1.8%.

[0141] For another silicon wafer, R1 was measured to be -8.5 micrometers and RN to be +0.6 micrometers. Since they have opposite signs, and the larger absolute value of R1 exceeds the positive threshold, the equipment identifies it as tilted, further subdividing it into negative tilted type based on the sign of the larger absolute value. The recommended treatment is not to flip it. This wafer then proceeds to the polishing process. Due to maintaining a favorable processing orientation, its stress distribution is relatively uniform, resulting in better flatness performance than the uniform flipping strategy.

[0142] The classification data continuously generated on the production line is also constantly aggregated into the quality control system. Every so often, the equipment correlates with the final nanometer-level flatness data of this batch of silicon wafers. If it detects a decrease in the improvement after the bowl-shaped inversion, or if certain boundary morphologies are misclassified, it automatically adjusts the positive and negative thresholds, for example, correcting Th_high from 7 micrometers to 6.5 micrometers, making the classification boundaries more closely match the current process state. This closed-loop feedback mechanism ensures that morphology classification maintains a high accuracy rate despite drift in the cutting process or changes in raw material batches.

[0143] In this scenario, the real-time classification of the silicon wafer morphology after dicing and the targeted flipping control enable users to improve the nanoscale flatness after polishing and increase the yield of finished products without increasing additional hardware investment or extending the production cycle.

[0144] To further quantitatively evaluate the overall technical effectiveness of the classification and processing control methods provided in this disclosure, the embodiments of this disclosure were systematically compared and verified based on 300mm silicon wafers produced in the same batch.

[0145] First, all silicon wafers in the batch were classified using the classification method described in the above embodiments, and all wafers classified as having a central concave shape were selected. These wafers were then randomly divided into a control group and an experimental group. The control group directly proceeded to the subsequent grinding and polishing processes; the experimental group, based on the processing control method, underwent a flipping operation at the sorting station before entering the same subsequent processes. After polishing, the local flatness (SFQR) of the two groups of wafers was measured.

[0146] The results showed that the average SFQR in the control group was 13.3 μm, with a defect rate (SFQR exceeding the standard) of 3.2%; while the average SFQR in the experimental group decreased to 11.2 μm, and the defect rate decreased to 1.8%. Compared with the control group, the average SFQR of the experimental group decreased by approximately 2.1 μm, the absolute defect rate improved by 1.4 percentage points, and the relative improvement exceeded 40%. This comparative experimental result clearly demonstrates that identifying the centrally recessed silicon wafer based on the morphology classification method of this disclosure and performing a flipping operation can bring about a significant technical effect of improving the average SFQR by approximately 2.1 μm and reducing the defect rate by more than 40%.

[0147] This disclosure also provides a computing device, such as... Figure 11 As shown, the computing device 900 includes a processor 910 and a memory 920. The processor 910 is used to execute instructions stored in the memory 920, such as application programs, to implement the classification method and / or processing control method in the above embodiments.

[0148] In at least one embodiment of this disclosure, the computing device 900 includes one or more processors 910. The application programs stored in the memory 920 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processors 910 are configured to execute instructions to perform the classification methods and / or processing control methods described in the above embodiments.

[0149] In at least one embodiment of this disclosure, the computing device 900 may further include a power supply component configured to perform power management of the computing device 900, a wired or wireless network interface configured to connect the computing device 900 to a network, and an input / output (I / O) interface. The computing device 900 may operate on an operating system stored in memory 920, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0150] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0151] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0152] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0153] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0154] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0155] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program verification codes, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0156] Furthermore, it should be noted that the combination of the various technical features in this case is not limited to the combination methods described in the claims of this case or the combination methods described in the specific embodiments. All technical features described in this case can be freely combined or combined in any way, unless they contradict each other.

[0157] It should be noted that the above examples are merely specific embodiments of the present invention, and the present invention is obviously not limited to the above embodiments, with many similar variations. All modifications that can be directly derived or conceived by those skilled in the art from the content disclosed in this invention should fall within the protection scope of this invention.

[0158] It should be understood that the terms "first," "second," etc., mentioned in the embodiments of the present invention are merely for the purpose of more clearly describing the use of the technical solutions in the embodiments of the present invention, and are not intended to limit the scope of protection of the present invention.

[0159] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for classifying the morphology of diced silicon wafers, characterized in that, include: Obtain the height feature value of the diced silicon wafer, wherein the height feature value is used to characterize the relative height polarity between the edge regions at both ends of the silicon wafer along the dicing direction; Obtain a positive threshold and a negative threshold, wherein the positive threshold and the negative threshold are preset numerical limits used to evaluate the polarity of the edge region; The height feature value is compared with the positive threshold and the negative threshold to obtain a comparison result, wherein the comparison result is used to indicate the numerical relationship between the height feature value and the positive threshold and the negative threshold; Based on the comparison results and the preset classification rules, the silicon wafer morphology is classified into at least one of the following: central convex type, central concave type, or inclined type.

2. The classification method according to claim 1, characterized in that, The height feature value includes at least one of the following: the height value of a representative point in the edge region at both ends of the silicon wafer, the difference between the height values ​​of the representative points in the edge region at both ends of the silicon wafer, the ratio of the height values ​​of the representative points in the edge region at both ends of the silicon wafer, the slope value obtained by fitting the height data of the edge region at both ends of the silicon wafer, and the feature vector extracted from the height data of the edge region at both ends of the silicon wafer by a machine learning model.

3. The classification method according to claim 2, characterized in that, The height feature value includes the height values ​​of two representative points in the edge regions at both ends of the silicon wafer. Obtaining the height feature value of the diced silicon wafer includes: Obtain a height data sequence of the silicon wafer, wherein the height data sequence is a height data sequence of at least one measurement line on the surface of the silicon wafer along the cutting direction; Determine the representative height values ​​of the two edge regions corresponding to the two ends of the measurement line, respectively, as the height values ​​of the two representative points.

4. The classification method according to claim 3, characterized in that, The representative height value is the height data corresponding to two measurement points within the edge region where the measurement line is located, or it is a value obtained by statistically calculating the height data of multiple measurement points within the edge region.

5. The classification method according to claim 4, characterized in that, The measuring line is the diameter of the silicon wafer along the cutting direction, and / or, When the representative height value is the height data corresponding to two measurement points located within the edge region of the measurement line, the two representative points are the first and last measurement points on the measurement line.

6. The classification method according to claim 5, characterized in that, Based on the comparison results and preset classification rules, the silicon wafer morphology is classified into at least one of the following: a centrally convex type, a centrally concave type, or a tilted type, including: When the height values ​​of the first and last measurement points are both greater than the negative threshold and at least one is greater than the positive threshold, the type is classified as a central depression. When the height values ​​of the first and last measurement points are both less than the positive threshold and at least one is less than the negative threshold, the type is classified as a central convex type. When the height values ​​of the first and last measurement points have opposite polarities, and the one with the larger absolute value is greater than the positive threshold, it is classified as a tilted type.

7. The classification method according to claim 6, characterized in that, Also includes: If classified as skewed, further classification is performed based on the sign of the height data with the larger absolute value: If the height data with a larger absolute value is positive, it is further classified as positive slant type; If the height data with a larger absolute value is negative, it is further classified as negative skew type.

8. The classification method according to any one of claims 1 to 6, characterized in that, Also includes: Collect nanoscale flatness data of silicon wafers after classification and subsequent polishing processes; The positive threshold and the negative threshold are adjusted based on the nanoscale flatness data.

9. A method for controlling the processing of silicon wafers, characterized in that, include: The classification results of the morphology of the diced silicon wafer are obtained, wherein the classification results are obtained by the classification method according to any one of claims 1 to 8; Based on the classification results, a processing control decision is determined for the silicon wafer, wherein the processing control decision includes flipping the silicon wafer or not flipping it. When the classification result is a concave type, it is flipped. When the classification result is a central convex type, it is not flipped; When the classification result is skewed, determine the further classification of the skewed type; If the further classification is positive tilt type, then flip it; If the further classification is negative skew type, then no flipping is performed.

10. A computing device, characterized in that, It includes a processor and a memory, the processor being configured to execute instructions stored in the memory to implement the classification method as described in any one of claims 1 to 8 and / or the processing control method as described in claim 9.

11. A computer storage medium, characterized in that, The storage medium stores at least one instruction, which is executed by a processor to implement the classification method as described in any one of claims 1 to 8 and / or the processing control method as described in claim 9.

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