Method for activating mg impurities in buried layer p-gan material and applications thereof

Abstract

This application discloses a method and its application for activating Mg impurities in buried p-type group III nitrides. An n-type semiconductor layer is stacked on the buried p-type semiconductor material, and the method includes: growing a p-type semiconductor sacrificial layer on the n-type semiconductor layer until H can be activated by H... + The buried p-type semiconductor material exists in an n-type semiconductor layer, followed by annealing. The buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are all made of group III nitrides. In this application, the buried p-type semiconductor material is activated by fabricating a p-type semiconductor sacrificial layer, which simplifies the semiconductor device fabrication process. The activation process has no etching window, which is beneficial for improving the performance and overall integration of the semiconductor device.

Description

Technical Field

[0001] This application specifically relates to a method for activating Mg impurities in buried p-GaN materials and its application, belonging to the field of semiconductor technology. Background Technology

[0002] In the field of power semiconductor devices, traditional silicon (Si)-based devices are limited by the inherent physical properties of the material, leading to performance bottlenecks in high-voltage, high-frequency, and high-efficiency applications. To meet the ever-increasing demands for power conversion efficiency, power density, and high-temperature operational stability, wide-bandgap semiconductors, especially gallium nitride (GaN), have attracted widespread attention due to their superior material properties. GaN possesses a wider bandgap (approximately 3.4 eV) and higher electron mobility (approximately 1500 cm⁻¹). 2 / V With its higher critical breakdown electric field (approximately 3.3 MV / cm) and good thermal stability, GaN power devices are expected to achieve superior power handling capabilities in new energy vehicles, industrial motor drives, data center power supplies, and renewable energy conversion systems, and are gradually becoming the preferred choice for next-generation high-performance power devices. In applications below 650 V, GaN high electron mobility transistors (HEMTs) based on lateral structures have been widely commercialized and are used in fast charging, server power supplies, and consumer-grade DC-DC converters. However, for applications with voltage levels exceeding 900 V and current requirements exceeding 100 amperes, such as automotive main drive inverters, industrial-grade DC-DC conversion modules, and grid interfaces, lateral devices are gradually revealing limitations in terms of on-resistance and heat dissipation. To address the system requirements of high voltage, high current, and high power density, GaN-based vertical devices are gaining attention. Due to their lower on-resistance, higher breakdown voltage, and easier chip stacking and system integration, vertical GaN power devices show great potential in improving efficiency and reducing system size, and are expected to provide superior power handling solutions for high-voltage, high-current applications.

[0003] In the structures of GaN vertical MOSFETs and HBT devices, efficient and stable doping and activation of the p-type GaN buried layer region has always been a critical technical problem that urgently needs to be solved. GaN grown using Metal-Organic Chemical Vapor Deposition (MOCVD) typically requires NH3 as the nitrogen source. However, Mg, as an acceptor impurity, readily forms an electrically neutral Mg-H passivation complex with H, causing Mg to lose its acceptor activity and be unable to provide holes. High-temperature annealing is required to break the Mg-H bond and drive H atoms to diffuse and escape to the material surface, ultimately restoring the electrical activity of the Mg acceptor impurity. The diffusion barrier of H in p-GaN is 0.7 eV. When p-GaN is on the surface, H can generally overcome the 0.7 eV barrier and escape from the p-GaN through high-temperature annealing. However, in the material structure of vertical power devices, the p-GaN layer forming the pn junction is located beneath the donor n-type semiconductor n-GaN layer. Therefore, the p-GaN layer, acting as a buried layer, is covered by the subsequently grown n-GaN layer. The diffusion barrier of hydrogen (H) in the highly doped n-GaN layer is very high (~3.4 eV). The energy gained by H through high-temperature annealing is insufficient to overcome this barrier, preventing H from penetrating the n-GaN layer and leaving the p-GaN layer. After being disconnected from Mg at high temperature, H will passivate Mg again at room temperature. The unactivated p-GaN layer leads to source-drain punch-through in the device, making it unable to withstand high voltages.

[0004] The existing technologies for activating Mg in p-GaN mainly include: (1) etching away n-GaN on the p-GaN by opening windows on the material surface or sidewalls to expose the buried p-GaN and activate the Mg acceptor. This method inevitably introduces a large amount of etching damage, causing leakage current and voltage reduction, and significantly compresses the effective area of ​​the device, thereby limiting the device integration. At the same time, in p-GaN far from the window area, H cannot be eliminated, and the activation rate will be significantly reduced. (2) Referring to US 2022 / 0230883A1, the method of activating buried p-GaN by introducing etching damage through ion implantation is adopted, that is, after ion implantation of the n-GaN layer, high-temperature annealing is carried out in N2 atmosphere to eliminate H ions in the buried p-GaN. Although this method can activate the buried p-GaN, ion implantation has a significant impact on the n-GaN on the surface and sidewalls. + The GaN layer caused damage, making it impossible to meet the requirements of low-resistivity ohmic contacts in the source region and high-quality pn junctions in subsequent devices. Summary of the Invention

[0005] The main objective of this application is to provide a method for activating Mg impurities in buried p-GaN materials and its application, in order to overcome the shortcomings of the prior art.

[0006] To achieve the aforementioned objectives, this application employs the following technical solution.

[0007] According to a first aspect of this application, a method for activating Mg impurities in a buried p-type semiconductor material, wherein an n-type semiconductor layer is stacked on the buried p-type semiconductor material; the method includes: growing a p-type semiconductor sacrificial layer on the n-type semiconductor layer until H can be activated by H + The buried p-type semiconductor material exists in the form of an n-type semiconductor, and then undergoes annealing. The buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are all made of group III nitride materials.

[0008] In one embodiment, the group III nitride includes, but is not limited to, one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, and AlN.

[0009] In one embodiment, the thicknesses of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are 10~1000nm, 10~150nm, and 10~1000nm, respectively.

[0010] Furthermore, in this application, based on the temperature at which the Mg-H bond can be broken, the closer the Fermi level in n-GaN is to the top of the valence band, the lower the required annealing temperature.

[0011] In one embodiment, the annealing process is performed in air, oxygen, or a protective atmosphere. The gas used to form the protective atmosphere includes one or more combinations of gases such as nitrogen and ammonia.

[0012] In one embodiment, the annealing temperature is 500~1000℃, and more preferably 550, 600, 650, 700, 750, 800, 850, 900, 950, or 1000℃, with 500~900℃ being the most preferred, 600~900℃ being the most preferred, 700~900℃ being the most preferred, and 800~900℃ being the most preferred. If the annealing temperature is too low, the activation effect will be affected; if the annealing temperature is too high, it will lead to the decomposition of Group III nitrides.

[0013] In one embodiment, the annealing process takes 30 seconds to 3 hours, and can further take 1 minute, 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 1 hour, 1.5 hours, 2 hours, 2.5 hours, or 3 hours. For example, it can take 15 minutes to 1 hour, or 15 minutes to 45 minutes. The annealing process can be completed in one go or in multiple stages; therefore, the annealing time can be a single continuous annealing time or the sum of multiple annealing times.

[0014] According to a second aspect of this application, a method for activating Mg impurities in a buried p-type semiconductor material is provided, wherein an n-type semiconductor layer is stacked on the buried p-type semiconductor material; the method includes: A p-type semiconductor sacrificial layer is grown on the n-type semiconductor layer until the distance between the Fermi level and the valence band top of the n-type semiconductor is ≤2.6eV, more preferably ≤2.5eV, more preferably ≤2.4eV, more preferably ≤2.3eV, more preferably ≤2.2eV, and especially preferably ≤2.1eV. Then, the buried p-type semiconductor material is annealed. The buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are all made of group III nitride materials.

[0015] In one embodiment, the group III nitride includes, but is not limited to, one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, and AlN.

[0016] In one embodiment, the thicknesses of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are 10~1000nm, 10~150nm, and 10~1000nm, respectively.

[0017] In one embodiment, the annealing process is performed in air, oxygen, or a protective atmosphere. The gas used to form the protective atmosphere includes one or more combinations of gases such as nitrogen and ammonia.

[0018] In one embodiment, the annealing temperature is 500~1000℃, and may further be 550, 600, 650, 700, 750, 800, 850, 900, 950, 1000℃, etc., preferably 500~900℃, more preferably 600~900℃, more preferably 700~900℃, and more preferably 800~900℃.

[0019] In one embodiment, the annealing time is 30 seconds to 3 hours, and can further be 1 minute, 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 1 hour, 1.5 hours, 2 hours, 2.5 hours, or 3 hours. For example, it can be 15 minutes to 1 hour, or 15 minutes to 45 minutes.

[0020] According to a third aspect of this application, the method for activating Mg impurities in a buried p-type semiconductor material is provided for use in the fabrication of a semiconductor device.

[0021] Furthermore, the semiconductor device includes, but is not limited to, power semiconductor devices such as MOSFETs.

[0022] According to a fourth aspect of this application, a semiconductor structure is provided, comprising a buried p-type semiconductor material, an n-type semiconductor layer, and a p-type semiconductor sacrificial layer sequentially stacked; and, in the n-type semiconductor layer, H can be H + It exists in form.

[0023] In one embodiment, the group III nitride includes, but is not limited to, one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, and AlN.

[0024] In one embodiment, the thicknesses of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are 10~1000nm, 10~150nm, and 10~1000nm, respectively.

[0025] In one embodiment, the doping concentrations of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are each 1×10⁻⁶. 17 ~1×10 20 cm -3 1×10 16 ~1×10 21 cm -3 1×10 17 ~1×10 20 cm -3 .

[0026] According to a fifth aspect of this application, a semiconductor structure is provided, comprising a buried p-type semiconductor material, an n-type semiconductor layer, and a p-type semiconductor sacrificial layer stacked sequentially; wherein the distance between the Fermi level and the valence band top of the n-type semiconductor in the n-type semiconductor layer is ≤2.6 eV, more preferably ≤2.5 eV, more preferably ≤2.4 eV, more preferably ≤2.3 eV, more preferably ≤2.2 eV, and particularly preferably ≤2.1 eV. The closer the distance between the Fermi level and the valence band top of the n-type semiconductor, the lower the annealing temperature required to activate the buried p-type semiconductor material, which is more conducive to ensuring the performance of the semiconductor material and reducing the difficulty of the process and energy consumption.

[0027] In one embodiment, the group III nitride includes, but is not limited to, one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, and AlN.

[0028] In one embodiment, the thicknesses of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are 10~1000nm, 10~150nm, and 10~1000nm, respectively.

[0029] In one embodiment, the doping concentrations of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are each 1×10⁻⁶. 17 ~1×10 20 cm -3 1×10 16 ~1×10 21 cm -3 1×10 17 ~1×10 20 cm -3 .

[0030] According to a sixth aspect of this application, a method for manufacturing a semiconductor device is provided, comprising: A buried p-type semiconductor material is provided, wherein an n-type semiconductor layer is stacked on the buried p-type semiconductor material; A p-type semiconductor sacrificial layer is grown on the n-type semiconductor layer until the distance between the Fermi level and the valence band top of the n-type semiconductor is ≤2.6eV, more preferably ≤2.5eV, more preferably ≤2.4eV, more preferably ≤2.3eV, more preferably ≤2.2eV, and especially preferably ≤2.1eV. Then, the buried p-type semiconductor material is annealed. The buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are all made of group III nitride materials.

[0031] The closer the distance between the Fermi level and the valence band top of the n-type semiconductor, the lower the annealing temperature required to activate the buried p-type semiconductor material, which is more conducive to ensuring the performance of the semiconductor material and reducing the difficulty of the process and energy consumption.

[0032] In one embodiment, the group III nitride includes, but is not limited to, one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, and AlN.

[0033] In one embodiment, the thicknesses of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are 10~1000nm, 10~150nm, and 10~1000nm, respectively.

[0034] In one embodiment, one or more of the buried p-type semiconductor material, n-type semiconductor layer and p-type semiconductor sacrificial layer may be grown by processes such as metal-organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), and programmed rate chemical vapor deposition (PRCVD), and are not limited thereto.

[0035] In one embodiment, the annealing process is performed in air, oxygen, or a protective atmosphere. The gas used to form the protective atmosphere includes one or more combinations of gases such as nitrogen and ammonia.

[0036] In one embodiment, the annealing temperature is 500~1000℃, and may further be 550, 600, 650, 700, 750, 800, 850, 900, 950, 1000℃, etc., preferably 500~900℃, more preferably 600~900℃, more preferably 700~900℃, and more preferably 800~900℃.

[0037] In one embodiment, the annealing time is 30 seconds to 3 hours, and can further be 1 minute, 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 1 hour, 1.5 hours, 2 hours, 2.5 hours, or 3 hours. For example, it can be 15 minutes to 1 hour, or 15 minutes to 45 minutes.

[0038] In one embodiment, the method may further include: after completing the annealing process, partially or completely removing the p-type semiconductor sacrificial layer.

[0039] Furthermore, methods for removing the p-type semiconductor sacrificial layer include, but are not limited to, dry etching, wet etching, etc.

[0040] In one embodiment, the method may further include: after removing the p-type semiconductor sacrificial layer, fabricating an electrode that cooperates with the buried p-type semiconductor material and / or the n-type semiconductor layer. Taking the semiconductor device as a MOSFET as an example, the electrode includes a gate, a source, a drain, etc.

[0041] In one embodiment, the method may further include conventional operations such as tabletop isolation and annealing.

[0042] The technical solution proposed in this application is mainly based on the following discovery: H exists in group III nitride semiconductor materials in the form of H1. + H - H 0 Three types, such as Figure 1 As shown. Taking GaN as an example, based on the formation energy, when the Fermi level in GaN material is 2.1 eV or less from the valence band top, H is... + H exists in the form of H, and when the Fermi level is more than 2.1 eV above the valence band top, H exists as H. - It exists in the form of H. The diffusion barrier of H in GaN is for H in a fixed charge state. + / H - Calculated, therefore when H is in GaN as H + If it exists in the form of [a specific type of property], its diffusion barrier will be greatly reduced.

[0043] Furthermore, this application grows a p-type semiconductor sacrificial layer on top of an n-type semiconductor layer stacked on a buried p-type semiconductor material. A pnp junction is formed between the p-type semiconductor sacrificial layer, the n-type semiconductor layer, and the buried p-type semiconductor material. The p-type semiconductor sacrificial layer modulates the energy band of the n-type semiconductor layer, raising its conduction band and lowering the diffusion barrier of hydrogen (H) within it. During high-temperature annealing, H from the buried p-type semiconductor material can penetrate the n-type semiconductor layer and enter the p-type semiconductor sacrificial layer, eventually escaping from it, thus activating the buried p-type semiconductor material. Moreover, after annealing and activating the buried p-type semiconductor material, and after etching away the surface p-type semiconductor sacrificial layer, a good ohmic contact can still be formed between the n-type semiconductor layer and the metal (for example, surface etching of n-GaN generates donor-type N vacancies, which are more conducive to the formation of ohmic contacts).

[0044] Taking the buried p-type semiconductor material, the p-type semiconductor sacrificial layer as p-GaN, and the n-type semiconductor layer as n-GaN as an example. (See also...) Figure 2After growing a p-GaN sacrificial layer on the n-GaN layer, the p-GaN sacrificial layer forms a pnp junction with the n-GaN layer / buried p-GaN, which raises the valence band top of the n-GaN to a distance of about 2.1 eV from the Fermi level, thereby significantly reducing the diffusion barrier of H in the n-GaN. Then, the buried p-GaN can be activated by high-temperature annealing.

[0045] Compared with the prior art, this application has at least the following beneficial technical effects: (1) When activating Mg impurities in buried p-type semiconductor material in this application, it is not necessary to expose buried p-type semiconductor material through etching window. This can avoid introducing etching damage on the surface of buried p-type semiconductor material, overcome the problems of difficult preparation of ohmic contacts of p-type semiconductor material and low device withstand voltage caused by this, and at the same time, it can prevent the destruction of n-type semiconductor layer caused by ion implantation, which cannot meet the requirements of low resistance ohmic contacts in the source region of subsequent devices.

[0046] (2) In this application, after the buried p-type semiconductor material is activated, the p-type semiconductor sacrificial layer can be removed by dry etching, wet etching and other processes, which will not affect the preparation of the ohmic contact between the source metal and the n-type semiconductor layer.

[0047] (3) In this application, by fabricating a p-type semiconductor sacrificial layer, the buried p-type semiconductor material can be activated before the semiconductor device is fabricated, which simplifies the device fabrication process from the process level. Furthermore, there is no etching window during activation, which is also beneficial to improving the overall integration of the semiconductor device. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 The existence forms and formation energies of H in GaN are shown; Figure 2 This diagram illustrates the principle of controlling the energy band in n-GaN through a p-GaN sacrificial layer in one embodiment of this application. Figure 3 The SIMS test diagram of the pnp junction before annealing in Example 4 is shown; Figure 4 The SIMS test diagram of the pnp junction after annealing in Example 4 is shown; Figure 5 A schematic diagram of the epitaxial wafer structure in Application Example 1 is shown; Figure 6 A schematic diagram of the sample structure after removing the p-GaN sacrificial layer in Application Example 1 is shown; Figure 7 A schematic diagram of the structure of the sample after the gate groove was fabricated in Application Example 1 is shown; Figure 8 A schematic diagram of the structure of the sample after the gate dielectric was fabricated in Application Example 1 is shown; Figure 9 This shows a schematic diagram of the sample structure after exposing the p-GaN buried layer through a window in Application Example 1; Figure 10 This shows a schematic diagram of the structure of the sample after depositing metallic Ni / Au to form an ohmic contact with the p-GaN buried layer in Application Example 1; Figure 11 A schematic diagram of the structure of the sample after depositing source metal Ti / Au in Application Example 1 is shown; Figure 12 A schematic diagram of the structure of the sample after depositing the gate metal is shown in Application Example 1; Figure 13 A schematic diagram of the sample structure after device isolation is shown in Application Example 1; Figure 14 A schematic diagram of the structure of the sample after depositing the drain metal in Application Example 1 is shown; Figure 15 A schematic diagram of the epitaxial wafer structure in Application Example 2 is shown; Figure 16 A schematic diagram of the sample structure after device isolation is shown in Application Example 2; Figure 17 A schematic diagram of the sample structure after basal region windowing is shown in Application Example 2; Figure 18 A schematic diagram of the sample structure after the passivation layer was deposited in Application Example 2 is shown; Figure 19 A schematic diagram of the sample structure after fabrication of the base region electrode in Application Example 2 is shown; Figure 20 A schematic diagram of the sample structure after fabrication of the emitter and collector electrodes is shown in Application Example 2; Figure 21 The IV test results of the fabrication of the ohmic contact ring transmission line (CTLM) on n+-GaN before ion implantation in Comparative Example 3 are shown. Figure 22 The results of the ohmic contact between the metal and n+-GaN before ion implantation in Comparative Example 3 are shown by fitting the CTLM test. Figure 23 The IV test results of the ohmic contact ring transmission line fabricated on n+-GaN after completing step S2 in Comparative Example 3 are shown. Figure 24The results of the ohmic contact between the metal and n+-GaN fitted by CTLM test after completing step S2 in Comparative Example 3 are shown. Detailed Implementation

[0050] The technical solution of this application will be clearly and completely described below with reference to the accompanying drawings and several embodiments. It should be understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0051] Example 1 Seven epitaxial wafer samples are provided. The first sample includes a stacked buried p-GaN and n-GaN layer, but no p-GaN sacrificial layer. These two structural layers are formed by a single-stage MOCVD process. The second to seventh samples all include a stacked buried p-GaN, n-GaN, and p-GaN sacrificial layer, which are also formed by a single-stage MOCVD process. In all seven samples, the n-GaN layer has a thickness of approximately 50 nm and a doping concentration of approximately 1 × 10⁻⁶. 18 cm -3 The thickness of the buried p-GaN layer is approximately 400 nm, and the carrier concentration is approximately 5 × 10⁻⁶. 17 cm -3 The second to seventh epitaxial wafer samples each included wafers with a thickness of 30 nm and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 30 nm and a carrier concentration of 8 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 50 nm and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 50 nm and a carrier concentration of 8 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer is 100 nm thick and has a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer is 100 nm thick and has a carrier concentration of 8 × 10⁻⁶. 17 cm -3 p-GaN sacrificial layer.

[0052] Using the TCAD simulation software Silvaco and the Deckbuild module, parameters such as material thickness, doping concentration, and doping type were set to simulate the band structure changes of the epitaxial layer. The band structure changes were then tested using Tonyplot, and the results are shown in Table 1 below.

[0053] Example 2 Seven epitaxial wafer samples are provided. The first sample includes a stacked buried p-GaN and n-GaN layer, but no p-GaN sacrificial layer. These two structural layers are formed by a single-stage MOCVD epitaxial growth process. The second to seventh samples all include a stacked buried p-GaN, n-GaN, and p-GaN sacrificial layer, which are also formed by a single-stage MOCVD epitaxial growth process. In all seven samples, the n-GaN layer has a thickness of approximately 80 nm and a doping concentration of approximately 5 × 10⁻⁶. 17 cm -3 The thickness of the buried p-GaN layer is approximately 400 nm, and the carrier concentration is approximately 5 × 10⁻⁶. 17 cm -3 The second to seventh epitaxial wafer samples each included wafers with a thickness of 30 nm and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 30 nm and a carrier concentration of 8 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 50 nm and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 50 nm and a carrier concentration of 8 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer is 100 nm thick and has a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer is 100 nm thick and has a carrier concentration of 8 × 10⁻⁶. 17 cm -3 p-GaN sacrificial layer.

[0054] Using the TCAD simulation software Silvaco and the Deckbuild module, parameters such as material thickness, doping concentration, carrier concentration, and doping type were set to simulate the band structure changes of the epitaxial layer. The band structure changes were then tested using Tonyplot, and the results are shown in Table 1 below.

[0055] Example 3 Seven epitaxial wafer samples are provided. The first sample includes a stacked buried p-GaN and n-GaN layer, but no p-GaN sacrificial layer. These two structural layers are formed by a single-stage MOCVD epitaxial growth process. The second to seventh samples all include a stacked buried p-GaN, n-GaN, and p-GaN sacrificial layer. These three structural layers are formed by a single-stage MOCVD epitaxial growth process. In the first to seventh samples, the n-GaN layer has a thickness of approximately 120 nm and a doping concentration of approximately 3 × 10⁻⁶. 17 cm -3 The thickness of the buried P-GaN layer is approximately 400 nm, and the carrier concentration is approximately 5 × 10⁻⁶. 17 cm -3 The second to seventh epitaxial wafer samples each included wafers with a thickness of 30 nm and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 30 nm and a carrier concentration of 8 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 50 nm and a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer has a thickness of 50 nm and a carrier concentration of 8 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer is 100 nm thick and has a carrier concentration of 5 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer is 100 nm thick and has a carrier concentration of 8 × 10⁻⁶. 17 cm -3 The p-GaN sacrificial layer was simulated using the TCAD simulation software Silvaco, with the Deckbuild module used to set parameters such as material thickness, doping concentration, and doping type. The band change of the epitaxial layer was simulated, and the amount of band change was tested using Tonyplot. The results are shown in Table 1 below.

[0056] In Examples 1-3 above, the acceptor impurity doped in the buried p-GaN layer and the p-GaN sacrificial layer is Mg. The donor impurity doped in the n-GaN layer is Si.

[0057] The materials in Examples 1-3 above were annealed at 800°C for 30 minutes in a nitrogen atmosphere after surface cleaning to activate the Mg impurities in the buried p-GaN.

[0058] Table 1. Characteristics of the p-GaN sacrificial layer and activation status of the buried p-GaN in Examples 1-3.

[0059] Note: In Table 1, × represents not activated, and √ represents activated.

[0060] Example 4 A semiconductor structure was formed by sequentially growing a buried p-GaN layer with a thickness of approximately 400 nm, an n-GaN layer with a thickness of approximately 50 nm, and a p-GaN sacrificial layer with a thickness of approximately 100 nm on a GaN single-crystal substrate using MOCVD. The Mg concentration in the buried p-GaN layer was approximately 1 × 10⁻⁶. 19 cm -3 The Si concentration in the n-GaN layer is approximately 1.5 × 10⁻⁶. 18 cm -3 The Mg concentration in the p-GaN sacrificial layer is approximately 4 × 10⁻⁶. 19 cm -3 The simulation experiment was conducted according to the method in Examples 1-3. The distance between the Fermi level and the top of the valence band in the n-GaN layer is approximately 2.3273 eV.

[0061] The aforementioned semiconductor structure was annealed at 850°C in a N2 atmosphere for 30 min, and the concentrations of Si, Mg, and H elements in the material were measured using a secondary ion mass spectrometer (SIMS). From before annealing ( Figure 3 ) and after annealing ( Figure 4 The SIMS test results show that the concentrations of Mg and H in the buried p-GaN layer were basically the same before annealing; however, after annealing, the Mg concentration in the buried p-GaN layer remained basically unchanged, while the H concentration increased from 1×10⁻⁶. 19 cm -3 It dropped to 3×10 17 cm -3 The decrease was over 97%. In the n-GaN layer, due to the tailing effect of Mg, H exists at the interface of the pn junction, but after annealing, the H in n-GaN decreased to 1×10⁻⁶. 17 cm -3 (Approximate H detection line concentration in GaN using SIMS testing).

[0062] Comparative Example 1 The semiconductor structure fabrication method and annealing process conditions in this comparative example are basically the same as those in Example 4, except that no p-GaN sacrificial layer is grown.

[0063] Before and after annealing, the concentrations of Mg and H in the buried p-GaN layer were tested using SIMS. The results showed that the concentrations of Mg and H remained basically unchanged.

[0064] Application Example 1: A method for fabricating a GaN metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising the following steps: S1. Epitaxial wafer fabrication. Epitaxial wafers are prepared using MOCVD technology on n... + The epitaxial structure required for growth on the front side of GaN substrate 1, from bottom to top, includes a 3μm thick Si doping concentration of 1×10⁻⁶. 16 cm -3 n - -GaN drift layer 2, with a thickness of 300 nm and a Mg doping concentration of 3 × 10⁻⁶. 19 cm -3 The buried p-GaN 3 layer has a thickness of 50 nm and a Si doping concentration of 1 × 10⁻⁶. 18 cm -3 n + -GaN source layer 4 and a 50nm thick Mg doping concentration of 3×10⁻⁶. 19 cm -3 The p-GaN sacrificial layer 5. The thickness and concentration of the p-GaN sacrificial layer 5 are determined based on the buried p-GaN and n... + The thickness and doping concentration of the GaN source layer are determined. For example... Figure 5 As shown.

[0065] S2. Activation of buried p-GaN. The sample was annealed at 850℃ for 30 min in an N2 atmosphere to activate the buried p-GaN layer.

[0066] S3. Etching the p-GaN sacrificial layer. Using photoresist as a mask, the p-GaN sacrificial layer 5 is etched away using a chlorine-based ICP (Inductively Coupled Plasma) dry etching method. Figure 6 As shown.

[0067] S4. Gate Trench Fabrication. Using SiO2 as a hard mask, trenches are fabricated via chlorine-based ICP dry etching. The trench sidewall morphology is repaired with a 25% tetramethylammonium hydroxide (TMAH) solution. The SiO2 mask is removed using an HF acid solution (or a buffer solution of HF acid and ammonium fluoride). Figure 7 As shown.

[0068] S5. Deposited gate dielectric. An atomic layer deposition of approximately 50 nm thick Al₂O₃ is used as the gate dielectric 6, such as... Figure 8 As shown.

[0069] S6. Buried p-GaN windowing. Using photoresist as a mask, a small-area window is created to expose the buried p-GaN layer by removing the source contact layer through chlorine-based ICP dry etching. Figure 9 As shown.

[0070] S7. Ni / Au deposition. A Ni / Au layer 7 (approximately 50 / 150 nm thick) was deposited using electron beam evaporation, annealed at 550 °C in an O2 atmosphere, and formed a source ohmic contact with the buried p-GaN layer, such as... Figure 10 As shown.

[0071] S8.Ti / Au deposition. Using photoresist as a mask, an 8-layer (approximately 50 / 150nm thick) of metallic Ti / Au was magnetron sputtered, with sidewalls and n... + - The GaN source region layer forms a source ohmic contact, and its bottom is interconnected with the Ni / Au layer 7. For example... Figure 11 As shown.

[0072] S9. Gate Metal Fabrication. A Ni / Au layer (approximately 50 / 150 nm thick) was deposited using photoresist as a mask and by electron beam evaporation as the gate metal. (Example:) Figure 12 As shown.

[0073] S10. Device isolation. Buried p-GaN and n-GaN layers are etched using ICP dry etching. + -GaN source region layer, forming a mesa isolation structure. For example... Figure 13 As shown.

[0074] S11. Drain electrode fabrication. A Ti / Au layer 10 (approximately 50 / 150 nm thick) is sputtered onto the back side of the GaN substrate to form an ohmic contact with the GaN substrate. For example... Figure 14 As shown.

[0075] Comparative Example 2 provides a GaN MOSFET device fabrication method that is basically the same as that in Application Example 1, except that the operation of growing a p-GaN sacrificial layer is omitted in step S1; and in step S2, the method in Reference 1 is used to etch the exposed sidewalls to allow H to overflow from the buried p-GaN layer by lateral H diffusion.

[0076] SIMS testing shows that, for devices with a lateral dimension <20μm or ≥20μm, the activation efficiency of Mg in the buried p-GaN layer in the final device obtained in Application Example 1 can reach over 97%, and the breakdown voltage can reach over 1700V. However, for the final device obtained in Comparative Example 2, when the lateral dimension is less than 20μm, the buried p-GaN layer can be activated, but only a Mg activation rate of 28% can be achieved, with a maximum breakdown voltage of approximately 1200V. When the lateral dimension is greater than 20μm, the Mg activation in the central region of the buried p-GaN layer is insufficient, and leakage current increases significantly.

[0077] Document 1: "Activation of buried p-GaN in MOCVD-regrown verticalstructures", Appl. Phys. Lett.， 2018, 113, 062105.

[0078] Application Example 2: A method for fabricating a GaN bipolar junction transistor (BJT) device, comprising the following steps: S1. Epitaxial wafer fabrication. The required epitaxial structure is grown on a high-resistivity substrate 11 by MOCVD, consisting of, from bottom to top, a 1μm thick Si doping concentration of 5×10⁻⁶. 18 cm -3 The collector region n-GaN layer 12 has a thickness of 80 nm and a Mg doping concentration of 2 × 10⁻⁶. 19 cm -3 The base region has a buried p-GaN13 layer with a thickness of 30 nm and a Si doping concentration of 1×10⁻⁶. 19 cm -3 launch area n + -GaN layer 14 and 80nm thick Mg doping concentration of 3×10⁻⁶ 19 cm -3 The p-GaN sacrificial layer 15. The thickness and concentration of the p-GaN sacrificial layer 15 are determined based on the buried p-GaN and n-type elements. + The thickness and doping concentration of the GaN source layer are determined. For example... Figure 15 As shown.

[0079] S2. Activation of buried p-GaN. The sample was placed in an N2 atmosphere and annealed at 850℃ for 30 min to activate the buried p-GaN.

[0080] S3. Etching of the p-GaN sacrificial layer. The p-GaN sacrificial layer was etched away using ICP dry etching.

[0081] S4. Device isolation. Using photoresist as a mask, the emitter region n outside the active region is etched away using a chlorine-based ICP dry etching process. + -GaN layer, buried p-GaN layer in the base region, and n+-GaN layer in the collector region, such as Figure 16 As shown.

[0082] S5. Base region windowing. Using photoresist as a mask, the n+-GaN layer in the base region is etched away using a chlorine-based ICP dry etching method. The morphology of the groove sidewalls is then repaired using tetramethylammonium hydroxide (TMAH) solution, such as... Figure 17 As shown.

[0083] S6. Deposition medium. An Al2O3 passivation layer of approximately 50 nm thickness was deposited using atomic layer deposition 16, such as... Figure 18 As shown.

[0084] S7. Base Electrode Fabrication. Using photoresist as a mask, windows were created on the Al2O3 passivation layer 16 via a BOE wet process, and a Ni / Au layer (approximately 50 / 150 nm thick) was formed by electron beam evaporation to create the base electrode 17. Annealing was performed at 550 °C in an O2 atmosphere to form an ohmic contact with the buried p-GaN layer. Figure 19 As shown.

[0085] S8. Emitter and Collector Fabrication. Using photoresist as a mask, windows are created on the Al2O3 passivation layer via a BOE wet process. Emitter 18 and collector 19 are formed by sputtering Ti / Au layers (approximately 50 / 150 nm thick), forming ohmic contacts with the n+GaN buried layer. Figure 20 As shown.

[0086] Comparative Example 3: The fabrication method of the GaN BJT device provided in this comparative example is basically the same as that in Application Example 2, except that the operation of growing the p-GaN sacrificial layer is omitted in step S1; and in step S2, the method of US 2022 / 0230883 A1 is followed for the emitter region n + The buried p-GaN layer was activated by ion implantation and then high-temperature annealing at 850℃ for 30 min in an N2 atmosphere.

[0087] See Figures 21-24 In Comparative Example 3, the sheet resistance of n-GaN increased from 274.8 Ω / sq to 1.77 × 10⁻⁶. 4 The ohmic contact resistivity of the metal with n+-GaN is Ω / sq, ranging from 2.65 × 10⁻⁶. -5 Ω·cm 2 Increased to 2.97×10 -3 Ω·cm 2 This represents an increase of two orders of magnitude. In contrast, the sheet resistance and ohmic contact resistivity of n+-GaN in Application Example 2 remain essentially unchanged.

[0088] Furthermore, Comparative Example 3 cannot achieve full-surface buried p-GaN activation; it still relies on the implantation region to achieve the lateral diffusion channel of H. When the lateral dimension of the implantation region is too large (>20μm), the buried p-GaN layer far from the implantation region still cannot be activated.

[0089] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for activating Mg impurities in a buried p-type semiconductor material, wherein an n-type semiconductor layer is stacked on the buried p-type semiconductor material, characterized in that... The method includes: growing a p-type semiconductor sacrificial layer on the n-type semiconductor layer until H can be generated by H. + The buried p-type semiconductor material exists in the form of an n-type semiconductor, and then undergoes annealing. The buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are all made of group III nitride materials.

2. The method according to claim 1, characterized in that: The group III nitrides include one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, and AlN; And / or, the annealing process is performed in air or a protective atmosphere; And / or, the annealing temperature is 500℃~900℃; And / or, the annealing process takes 10 seconds to 3 hours.

3. A method for activating Mg impurities in a buried p-type semiconductor material, wherein an n-type semiconductor layer is stacked on the buried p-type semiconductor material, characterized in that... The method includes: A p-type semiconductor sacrificial layer is grown on the n-type semiconductor layer until the distance between the Fermi level and the valence band top of the n-type semiconductor is ≤2.6eV, and then the buried p-type semiconductor material is annealed. The buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are all made of group III nitride materials.

4. The method according to claim 3, characterized in that: The group III nitrides include one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, and AlN; And / or, the thicknesses of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are 10~1000nm, 10~150nm, and 10~1000nm, respectively; And / or, the annealing process is performed in air or a protective atmosphere; And / or, the annealing temperature is 500~1000℃; And / or, the annealing process takes 30 seconds to 3 hours.

5. A semiconductor structure, characterized in that, It includes a buried p-type semiconductor material, an n-type semiconductor layer, and a p-type semiconductor sacrificial layer stacked sequentially; and, in the n-type semiconductor layer, H can be H + It exists in form.

6. The semiconductor structure according to claim 5, characterized in that: The group III nitrides include one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, and AlN; And / or, the doping concentrations of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are each 1×10⁻⁶. 17 ~1×10 20 cm -3 1×10 16 ~1×10 21 cm -3 1×10 17 ~1×10 20 cm -3 .

7. A semiconductor structure, characterized in that, It includes a buried p-type semiconductor material, an n-type semiconductor layer and a p-type semiconductor sacrificial layer stacked sequentially; and the distance between the Fermi level and the valence band top of the n-type semiconductor in the n-type semiconductor layer is ≤2.6eV.

8. The semiconductor structure according to claim 7, characterized in that: The group III nitrides include one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, and AlN; And / or, the thicknesses of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are 10~1000nm, 10~150nm, and 10~1000nm, respectively; And / or, the doping concentrations of the buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are each 1×10⁻⁶. 17 ~1×10 20 cm -3 1×10 16 ~1×10 21 cm -3 1×10 17 ~1×10 20 cm -3 .

9. A method for manufacturing a semiconductor device, characterized in that, include: A buried p-type semiconductor material is provided, wherein an n-type semiconductor layer is stacked on the buried p-type semiconductor material; A p-type semiconductor sacrificial layer is grown on the n-type semiconductor layer until the distance between the Fermi level and the valence band top of the n-type semiconductor is ≤2.6eV, and then the buried p-type semiconductor material is annealed. The buried p-type semiconductor material, the n-type semiconductor layer, and the p-type semiconductor sacrificial layer are all made of group III nitride materials.

10. The method according to claim 9, characterized in that: The group III nitrides include one or more combinations of GaN, InGaN, AlGaN, AlInGaN, AlInN, InN, and AlN; And / or, the annealing process is performed in air or a protective atmosphere; And / or, the annealing temperature is 500~1000℃; And / or, the annealing process takes 30 seconds to 3 hours.

11. The method according to claim 9, characterized in that, Also includes: After the annealing process is completed, the p-type semiconductor sacrificial layer is removed.

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