Interconnect structures and methods of forming the same

Abstract

Interconnect structures and methods of forming the same are described. The interconnect structures include a first dielectric layer disposed over a second dielectric layer, a first conductive feature disposed in the first dielectric layer, and a composite layer disposed between the first conductive feature and the first dielectric layer. The composite layer includes an alloy nitride.

Description

Technical Field

[0001] Embodiments of this application relate to interconnect structures and methods of forming them. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than its predecessor. Throughout IC development, functional density (the number of interconnect devices per chip area) has generally increased, while geometry (the smallest component (or line) created using manufacturing processes) has shrunk. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming an interconnect structure, comprising: depositing a first dielectric layer over a second dielectric layer; forming an opening in the first dielectric layer; forming a composite layer on the first dielectric layer in the opening, wherein the composite layer comprises an alloy nitride; and depositing a conductive component on the composite layer, wherein the conductive component fills the opening.

[0005] Other embodiments of this application provide a method for forming an interconnect structure, comprising: depositing a second dielectric layer over a first dielectric layer; forming an opening in the first dielectric layer to expose a first conductive component located in the second dielectric layer; selectively depositing a barrier layer on the first conductive component; forming a composite layer on the first dielectric layer in the opening, wherein the composite layer comprises an alloy nitride; and depositing a second conductive component on the composite layer, wherein the second conductive component fills the opening.

[0006] Some embodiments of this application provide an interconnect structure including: a first dielectric layer disposed above a second dielectric layer; a first conductive component disposed in the second dielectric layer; and a composite layer disposed between the first conductive component and the first dielectric layer, wherein the composite layer comprises an alloy nitride. Attached Figure Description

[0007] The following detailed description, taken in conjunction with the accompanying drawings, will best provide a comprehensive understanding of the various aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 This is a cross-sectional side view of a stage in the manufacturing of a semiconductor device structure according to some embodiments.

[0009] Figure 2 This is a cross-sectional side view of a stage in the manufacturing of a semiconductor device structure according to some embodiments.

[0010] Figure 3A , Figure 3B , Figure 3C , Figure 3C-1 , Figure 3C-2 , Figure 3C-3 , Figure 3D and Figure 3E These are cross-sectional side views of various stages of manufacturing interconnect structures according to some embodiments.

[0011] Figure 4A and Figure 4B This is a cross-sectional side view of each stage of forming the composite layer according to an alternative embodiment.

[0012] Figure 5A and Figure 5B This is a cross-sectional side view of each stage of forming the composite layer according to an alternative embodiment.

[0013] Figure 6A , Figure 6B and Figure 6C This is a cross-sectional side view of various stages of manufacturing the interconnect structure according to an alternative embodiment.

[0014] Figure 7A , Figure 7B and Figure 7C This is a cross-sectional side view of various stages of manufacturing the interconnect structure according to an alternative embodiment.

[0015] Figure 8A , Figure 8B and Figure 8C This is a cross-sectional side view of various stages of manufacturing the interconnect structure according to an alternative embodiment.

[0016] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E This is a cross-sectional side view of various stages of manufacturing the interconnect structure according to an alternative embodiment.

[0017] Figure 10A , Figure 10B and Figure 10C This is a cross-sectional side view of various stages of manufacturing the interconnect structure according to an alternative embodiment.

[0018] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11EThis is a cross-sectional side view of various stages of manufacturing the interconnect structure according to an alternative embodiment.

[0019] Figure 12A , Figure 12B and Figure 12C This is a cross-sectional side view of various stages of manufacturing the interconnect structure according to an alternative embodiment. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify the description of this disclosure, specific examples of components and arrangements are described below. These are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact; it may also include embodiments where an additional component is formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in different examples in this disclosure; such repetition is for the purpose of brevity and clarity only and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, spatial relative terms used herein (e.g., "below," "under," "lower part," "above," "above," "upper," "top," "upper part," etc.) are used to describe the relationship between one element or component and another shown in the accompanying drawings. In addition to the orientation depicted in the drawings, spatial relative terms also cover different orientations of the device during use or operation. The device may be oriented by rotation (e.g., 90-degree rotation or other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0022] While the embodiments of this disclosure are primarily discussed with respect to nanostructured channel field-effect transistors (such as gate-all-around (GAA) field-effect transistors, such as horizontal gate-all-around (HGAA) or vertical gate-all-around (VGAA) field-effect transistors), embodiments of certain aspects of this disclosure can also be used with other processes and / or other devices (such as planar field-effect transistors, fin field-effect transistors (Fin-FETs), and other suitable devices). Those skilled in the art will understand that other modifications are also possible within the scope of this disclosure. In examples employing a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned using any applicable method. For example, it can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography with self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than using a single direct photolithography process. Specifically, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process; spacers are formed on the sides of the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0023] Figures 1 to 3E An exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of this disclosure is shown. It should be understood that... Figures 1 to 3E Additional operations are provided before, during, and after the process shown, and for some other embodiments of the method, certain operations described below may be replaced or eliminated. The order of operations / processes is not limiting and can be interchanged.

[0024] Figure 1 The manufacturing stages of the semiconductor device structure 100 are illustrated. (For example...) Figure 1As shown, the semiconductor device structure 100 includes a substrate 102 having a substrate portion 104 extending therefrom and a source / drain (S / D) region 106 disposed above the substrate portion 104. The substrate 102 may be a semiconductor substrate, such as a bulk silicon substrate. In some embodiments, the substrate 102 may be a crystalline elemental semiconductor, such as silicon or germanium; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; other suitable materials; or combinations thereof. Possible substrates 102 may also include a silicon-on-insulator (SOI) substrate. SOI substrates are fabricated by oxygen implantation isolation (SIMOX), wafer bonding, and / or other suitable methods. The substrate portion 104 may be formed by recessing a portion of the substrate 102. Therefore, the substrate portion 104 may comprise the same material as the substrate 102. The substrate 102 and the substrate portion 104 may comprise respective regions appropriately doped with impurities (e.g., p-type or n-type impurities). Dopants include, for example, boron for p-type field-effect transistors (PFETs) and phosphorus for n-type field-effect transistors (NFETs). S / D region 106 may include semiconductor materials such as silicon (Si) or germanium (Ge), III-V compound semiconductors, II-VI compound semiconductors, or other suitable semiconductor materials. Exemplary S / D region 106 may include, but is not limited to, germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), silicon phosphide (SiP), indium arsenide (InAs), aluminum arsenide (AlAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), gallium antimonide (GaSb), aluminum phosphide (AlP), gallium phosphide (GaP), etc. S / D region 106 may include p-type dopants (e.g., boron); n-type dopants (e.g., phosphorus or arsenic); and / or other suitable dopants (including combinations thereof). In this disclosure, the source region and the drain region are used interchangeably, and their structures are substantially the same. Furthermore, the source / drain region may refer to the source or the drain, individually or jointly, depending on the context.

[0025] like Figure 1As shown, the source / drain regions 106 can be connected via one or more semiconductor layers 130, which can be channels of a field-effect transistor (FET). In some embodiments, the FET is a nanostructure FET comprising multiple semiconductor layers 130, and at least a portion of each semiconductor layer 130 is surrounded by a gate electrode layer 136. The semiconductor layers 130 can be or comprise materials such as silicon (Si), germanium (Ge), silicon carbide (SiC), germanium arsenide (GeAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), gallium arsenide phosphide (GaInAsP), or other suitable materials. In some embodiments, each semiconductor layer 130 is made of silicon. The gate electrode layer 136 comprises one or more conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium aluminum (TiAl), titanium tantalum nitride (TiTaN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum carbonitride (TaCN), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), metal alloys, other suitable materials, or combinations thereof. In some embodiments, the gate electrode layer 136 comprises a metal. A gate dielectric layer 134 may be disposed between the gate electrode layer 136 and the semiconductor layer 130. The gate dielectric layer 134 may include two or more layers, such as an interface layer and a high-k dielectric layer. In some embodiments, the interface layer is an oxide layer, and the high-k dielectric layer includes hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (LaO), aluminum oxide (AlO), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, or other suitable high-k materials.

[0026] The gate dielectric layer 134 and the gate electrode layer 136 may be separated from the source / drain region 106 by an internal spacer 132. The internal spacer 132 may include a dielectric material, such as silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOC), silicon carbonitride (SiOCN), or silicon nitride (SiN). The spacer 128 may be disposed over multiple semiconductor layers 130. The spacer 128 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride (SiCN), silicon carbonitride, silicon carbonitride (SiOCN), and / or combinations thereof.

[0027] like Figure 1 As shown, a contact etch stop layer (CESL) 118 and an interlayer dielectric (ILD) layer 120 are disposed above the source / drain region 106. CESL 118 may comprise an oxygen-containing or nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or combinations thereof. The material of ILD layer 120 may comprise an oxide formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials.

[0028] Conductive contact 126 may be disposed in ILD layer 120 and above source / drain region 106, such as Figure 1 As shown. The conductive contact 126 may include one or more conductive materials, such as ruthenium (Ru), molybdenum (Mo), cobalt (Co), nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), aluminum (Al), titanium nitride (TiN), and tantalum nitride (TaN). A silicide layer 124 may be disposed between the conductive contact 126 and the source / drain epitaxial component 106.

[0029] like Figure 1As shown, the semiconductor device structure 100 may include a substrate 102 and a device layer 200 disposed above the substrate 102. The device layer 200 may include one or more devices, such as transistors, diodes, imaging sensors, resistors, capacitors, inductors, memory cells, combinations thereof, and / or other suitable devices. In some embodiments, the device layer 200 includes transistors, such as nanostructured transistors having multiple channels enclosed by a gate electrode layer, as described above. The term "nanostructure" is used herein to refer to any portion of material having nanoscale or even microscale dimensions and being elongated in shape, regardless of the cross-sectional shape of that portion. Thus, the term refers both to elongated material portions with circular and substantially circular cross-sections, and to beam-shaped or strip-shaped material portions (including, for example, cylindrical or substantially rectangular cross-sections). The channels (one or more channels) of the semiconductor device structure 100 may be surrounded by a gate electrode layer. The nanostructured transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate-all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode layer surrounding the channels. In some embodiments, device layer 200 includes devices such as planar field-effect transistors, fin field-effect transistors (FinFETs), complementary field-effect transistors (CFETs), forksheet field-effect transistors (FFETs), or other suitable devices.

[0030] like Figure 2 As shown, the semiconductor device structure 100 may further include an interconnect structure 300 disposed above the device layer 200 and the substrate 102. The interconnect structure 300 includes various conductive components, such as a first plurality of conductive components 304 and a second plurality of conductive components 306, and an inter-metal dielectric (IMD) layer 302 for separating and isolating the respective conductive components 304, 306. In some embodiments, the first plurality of conductive components 304 are conductive lines and the second plurality of conductive components 306 are conductive vias. The interconnect structure 300 includes multiple layers of conductive components 304, and these conductive components 304 are arranged in each layer to provide electrical paths to various devices in the underlying device layer 200. The conductive components 306 provide vertical electrical paths from the device layer 200 to the conductive components 304 and vertical electrical paths between the conductive components 304. For example, the bottommost conductive component 306 of the interconnect structure 300 may be electrically connected to a conductive contact 126 (…). Figure 1 ) and gate electrode layer 136 ( Figure 1The conductive components 304 and 306 may be made of one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, conductive components 304 and 306 may be made of copper (Cu), aluminum (Al), aluminum-copper alloys, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium nitride silicon (TiSiN), zirconium (Zr), gold (Au), silver (Ag), cobalt (Co), nickel (Ni), tungsten (W), tungsten nitride (WN), tungsten nitride silicon (WsiN), platinum (Pt), chromium (Cr), molybdenum (Mo), hafnium (Hf), other suitable conductive materials, or combinations thereof.

[0031] The inter-metal dielectric (IMD) layer 302 includes one or more dielectric materials to provide isolation for the various conductive components 304, 306. The IMD layer 302 may include multiple dielectric layers embedded with multiple layers of conductive components 304, 306. In some embodiments, the IMD layer 302 includes a low-k dielectric material, the k-value of which is less than the k-value of silicon oxide. In some embodiments, the IMD layer 302 includes silicon oxycarbide (SiOC), silicon carbonitride (SiCxNy), boron carbonitride (BCxNy), silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiCx), silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), silicon hydroxide (SiOxCyHz), spin-coated glass (SOG), amorphous fluorinated carbon, amorphous fluorinated carbon (FSG), degelatin, aerogel, polyimide, parylene, bisbenzocyclobutene, non-porous material, or porous material, wherein X and Y are integers or non-integers. The IMD layer 302 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, physical vapor deposition (PVD), or other suitable processes.

[0032] Figure 3A – Figure 3E These are cross-sectional side views of various stages manufactured according to some embodiments of the interconnect structure 300. For example... Figure 3A As shown, the interconnect structure 300 includes a dielectric layer 301, which may be an interlayer dielectric (ILD) layer or an intermetallic dielectric (IMD) layer. For example, the dielectric layer 301 may be SiCOH and have a k value in the range of about 2.5 to about 3. In some embodiments, the dielectric layer 301 may be disposed on the interlayer dielectric (ILD) layer 120 ( Figure 1 The dielectric layer 301 may include one or more conductive components (not shown) disposed therein. These one or more conductive components may be electrically connected to the source / drain (S / D) region 106. Figure 1 ) and gate electrode layer 136 ( Figure 1 In some embodiments, the conductive component is... Figure 2 The conductive component 304 or conductive component 306 shown. The dielectric layer 301 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, physical vapor deposition (PVD) or other suitable processes.

[0033] like Figure 3A As shown, a dielectric layer 305 is formed above the dielectric layer 301. The dielectric layer 305 can be an IMD layer 302 (…). Figure 2 A hard mask layer 308 is formed on the dielectric layer 305, and a photoresist layer 310 is formed on the hard mask layer 308. The hard mask layer 308 may include any suitable dielectric material, such as silicon nitride (SiN). The photoresist layer 310 may include one or more layers. In some embodiments, the photoresist layer 310 is a three-layer photoresist layer, including a bottom layer, an intermediate layer disposed on the bottom layer, and a resist layer disposed on the intermediate layer. The bottom layer may be a bottom anti-reflective coating (BARC). The bottom layer 214 may include an organic material. The intermediate layer may be formed of or include an inorganic material, such as a nitride (e.g., silicon nitride), an oxide oxynitride (e.g., silicon oxynitride), an oxide (e.g., silicon oxide), etc. The resist layer is a photosensitive material. In some embodiments, the photoresist layer 310 formed over the hard mask layer 308 may be other types of photoresist, such as a single-layer photoresist or a double-layer photoresist.

[0034] Next, as Figure 3B As shown, an opening 312 is formed in the dielectric layer 305. The opening 312 can be formed by patterning a photoresist layer 310 and then transferring the pattern to a hard mask layer 308 and the dielectric layer 305. During the formation of the opening 312 in the dielectric layer 305, the photoresist layer 310 and the hard mask layer 308 may be removed. In some embodiments, conductive components (not shown) formed in the dielectric layer 301 are exposed at the bottom of the opening 312. In some embodiments, the dielectric layer 301 is exposed at the bottom of the opening 312.

[0035] like Figure 3C As shown, a composite layer 314 is formed in the opening 312. In some embodiments, the composite layer 314 is a single layer and includes an alloy nitride, such as cobalt niobium nitride (CoNbN), tantalum niobium nitride (TaNbN), ruthenium niobium nitride (RuNbN), cobalt tantalum nitride (CoTaN), cobalt tantalum niobium nitride (CoTaNbN), cobalt ruthenium nitride (CoRuNbN), cobalt ruthenium nitride (CoRuTaN), cobalt zirconium nitride (CoZrN), cobalt vanadium nitride (CoVN), or combinations thereof. In some embodiments, the alloy nitride comprises nitrides of two or more metals. The composite layer 314 containing the alloy nitride can simultaneously function as a barrier layer and an adhesive layer. In some embodiments, the subsequently formed conductive component 330 ( Figure 3EThe conductive component 330 may contain a diffuse metal (e.g., copper (Cu)), and the composite layer 314 prevents the metal from diffusing from the conductive component 330 to the dielectric layer 305. Furthermore, the composite layer 314 improves the adhesion between the conductive component 330 and the dielectric layer 305. In some embodiments, the thickness of the single-layer composite layer 314 may be in the range of about 5 angstroms to about 50 angstroms. This single-layer composite layer 314 is thinner than the combined thickness of a conventional barrier layer and a conventional adhesive layer. Due to the smaller thickness of the composite layer 314, the size of the conductive component 330 can be increased. The resistance of the conductive component 330 is less than the resistance of the composite layer 314. Therefore, the resistance in the interconnect structure 300 is reduced. In some embodiments, if the thickness of the composite layer 314 is less than about 5 angstroms, its ability to prevent metal diffusion may be adversely affected. On the other hand, if the thickness of the composite layer 314 is greater than about 50 angstroms, the volume of the conductive component 330 decreases, resulting in increased resistance.

[0036] The alloy nitride layer of composite layer 314 can be deposited by any suitable method. In some embodiments, the alloy nitride layer is deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), wet coating, electroplating, other suitable processes, or combinations thereof. The deposition temperature can be in the range of about 20 degrees Celsius to about 400 degrees Celsius.

[0037] In some embodiments, the composite layer 314 comprises two or more layers. Figures 3C-1 to 3C-3 The diagram shows... Figure 3C The interconnect structure 300 is a portion 316. In some embodiments, the composite layer 314 is a two-layer structure and includes a first layer 318 formed on the dielectric layer 305 and a second layer 320 formed on the first layer 318, such as... Figure 3C-1 As shown. In some embodiments, the combined thickness of the first layer 318 and the second layer 320 is in the range of about 5 angstroms to about 50 angstroms. In some embodiments, the first layer 318 includes Figure 3CThe first layer 318 comprises the alloy nitride, and the second layer 320 comprises the alloy. The alloy contains two or more metals, such as cobalt niobium (CoNb), ruthenium tantalum (RuTa), cobalt tantalum (CoTa), cobalt tantalum niobium (CoTaNb), cobalt ruthenium niobium (CoRuNb), cobalt ruthenium tantalum (CoRuTa), cobalt vanadium (CoV), zirconium cobalt (CoZr), or ruthenium tantalum (RuTa). In some embodiments, the first layer 318 comprises the alloy, and the second layer 320 comprises the alloy nitride. In some embodiments, the first layer 318 comprises the alloy nitride, and the second layer 320 comprises a metal, such as cobalt (Co), tantalum (Ta), ruthenium (Ru), or zirconium (Zr). The metal of the second layer 320 may be different from the metal of the subsequently formed conductive component 330. In some embodiments, the first layer 318 comprises a metal nitride, and the second layer 320 comprises the alloy nitride. The metal nitride may include tantalum nitride (TaN), niobium nitride (NbN), cobalt nitride (CoN), or zirconium nitride (ZrN). In some embodiments, the metal nitride is a nitride of a single metal.

[0038] In some embodiments, one of the first layer 318 and the second layer 320 comprises an alloy nitride, and the other of the first layer 318 and the second layer 320 comprises a metal, an alloy, or a metal nitride. The bilayer structure of the composite layer 314 can have improved barrier properties compared to a single-layer composite layer 314. The arrangement of the first layer 318 and the second layer 320 can enhance the adhesion between the conductive component 330 and the dielectric layer 305. For example, in some embodiments, a metal or alloy has better adhesion to the conductive component 330 than an alloy nitride. Therefore, the second layer 320 comprises a metal or alloy, and the first layer 318 comprises an alloy nitride. The second layer 320 is disposed between the first layer 318 and the conductive component 330. In some embodiments, an alloy nitride has better adhesion to the conductive component 330 than a metal nitride. Therefore, the second layer 320 comprises an alloy nitride, and the first layer 318 comprises a metal nitride.

[0039] In some embodiments, the first layer 318 and the second layer 320 are deposited via a single process. For example, the first layer 318 and the second layer 320 can be deposited via a physical vapor deposition (PVD) process in which two or more sputtering targets are used. For example, the first layer 318 may include an alloy nitride, and the second layer 320 may include a metal. In this embodiment, the first sputtering target includes a first metal, and the second sputtering target includes a metal nitride. During the physical vapor deposition (PVD) process, the first and second sputtering targets may utilize a first time period, and the alloy nitride is deposited. The second sputtering target can then be removed from the physical vapor deposition (PVD) process, and the first sputtering target utilizes a second time period. As a result, a metal layer is deposited on the alloy nitride layer. Because the metal layer and the alloy nitride layer are formed via a single physical vapor deposition (PVD) process, there may not be a distinct interface between the metal layer and the alloy nitride layer. The first and second time periods can be adjusted to control the thickness of the first and second layers. In some embodiments, the first and second time periods are the same. In some embodiments, the first and second time periods are different. The order of the sputtering targets used can also be switched, and the first layer 318 comprises a metal while the second layer 320 comprises an alloy nitride. In some embodiments, the first sputtering target comprises an alloy, and either the first layer 318 or the second layer 320 may comprise the alloy.

[0040] In some embodiments, a chemical vapor deposition (CVD) process is performed to form a first layer 318 and a second layer 320. During the CVD process, a nitrogen-containing precursor, a first metal-containing precursor, and a second metal-containing precursor may be introduced into the processing chamber for a first time period to deposit the first layer 318, which may be an alloy nitride layer. Subsequently, the nitrogen-containing precursor is stopped, while the first metal-containing precursor and / or the second metal-containing precursor continue to flow into the processing chamber for a second time period to deposit the second layer 320 on the alloy nitride layer, which may be an alloy layer or a metal layer. Similarly, since the alloy layer and the alloy nitride layer are formed by a single CVD process, there may not be a distinct interface between the alloy layer and the alloy nitride layer. The first and second time periods can be adjusted to control the thickness of the first layer 318 and the second layer 320. In some embodiments, the first and second time periods are the same. In some embodiments, the first and second time periods are different. The order in which the precursors flow into the processing chamber can be changed to form the corresponding first layer 318 and second layer 320.

[0041] In some embodiments, the composite layer 314 includes multiple layers, such as Figure 3C-2As shown. For example, composite layer 314 includes a first layer 322 disposed on dielectric layer 305, a second layer 324 disposed on the first layer 322, and a third layer 326 disposed on the second layer 324. In some embodiments, one of the first layer 322, the second layer 324, and the third layer 326 includes an alloy nitride, while the other two layers of the first layer 322, the second layer 324, and the third layer 326 include a metal, an alloy, a metal nitride, or a combination thereof. For example, in some embodiments, the first layer 322 includes a metal nitride, the second layer 324 includes an alloy nitride, and the third layer 326 includes a metal. In some embodiments, the first layer 322 includes an alloy nitride, the second layer 324 includes a metal nitride, and the third layer 326 includes an alloy. In some embodiments, the first layer 322 includes an alloy nitride, the second layer 324 includes a metal nitride, and the third layer 326 includes a metal. In some embodiments, the first layer 322 comprises an alloy nitride, the second layer 324 comprises a metal nitride, and the third layer 326 comprises an alloy. In some embodiments, the first layer 322 comprises an alloy, the second layer 324 comprises an alloy nitride, and the third layer 326 comprises a metal. In some embodiments, the first layer 322 comprises an alloy, the second layer 324 comprises an alloy nitride, and the third layer 326 comprises an alloy. In some embodiments, the first layer 322 comprises an alloy nitride, the second layer 324 comprises an alloy, and the third layer 326 comprises a metal. In some embodiments, the first layer 322 comprises an alloy nitride, the second layer 324 comprises a metal, and the third layer 326 comprises an alloy.

[0042] Similar to the arrangement of the first layer 318 and the second layer 320, the arrangement of the first layer 322, the second layer 324, and the third layer 326 can improve barrier and adhesion properties. In some embodiments, the total thickness of the first layer 322, the second layer 324, and the third layer 326 is in the range of about 5 angstroms to about 50 angstroms. In some embodiments, the individual layers of the first layer 318 and the second layer 320, or the first layer 322, the second layer 324, and the third layer 326, are deposited using different processes. For example, the first layer 318 is deposited using a first process, while the second layer 320 is deposited using a second process different from the first process.

[0043] In some embodiments, the composite layer 314 includes a gradient layer 328, such as Figure 3C-3 As shown. In some embodiments, gradient layer 328 comprises an alloy nitride having a gradient nitrogen concentration. For example, the nitrogen concentration varies in a direction away from dielectric layer 305. In some embodiments, the nitrogen concentration in gradient layer 328 may decrease in a direction away from dielectric layer 305. In some embodiments, a high nitrogen concentration improves barrier properties, while a low nitrogen concentration improves adhesion properties.

[0044] like Figure 3DAs shown, the conductive component 330 is deposited in the opening 312 on the composite layer 314. The conductive component 330 may include a conductive material, such as copper (Cu), silver (Ag), gold (Au), aluminum (Al), nickel (Ni), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), palladium (Pd), osmium (Os), tungsten (W), molybdenum (Mo), tantalum (Ta), graphene, or other suitable materials. In some embodiments, the conductive component 330 includes one or more metals. The conductive component 330 may be formed by any suitable process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or atomic layer deposition (ALD).

[0045] Next, as Figure 3E As shown, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove portions of the conductive components 330 and composite layer 314 formed on the dielectric layer 305. This exposes the dielectric layer 305.

[0046] Figure 4A and Figure 4B The cross-sectional side views of each stage are formed according to the composite layer 314 of an alternative embodiment. For example... Figure 4A As shown, an alloy layer 332 is first deposited in the opening 312. The alloy layer 332 may comprise two or more metals. In some embodiments, the alloy layer 332 comprises cobalt-niobium (CoNb), ruthenium-tantalum (RuTa), cobalt-tantalum (CoTa), cobalt-tantalum-niobium (CoTaNb), cobalt-ruthenium-niobium (CoRuNb), cobalt-ruthenium-tantalum (CoRuTa), cobalt-vanadium (CoV), cobalt-zirconium (CoZr), or ruthenium-tantalum (RuTa). The alloy layer 332 can be deposited using any suitable process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), wet coating, or electroplating. The deposition temperature can range from about 20 degrees Celsius to about 400 degrees Celsius.

[0047] Next, as Figure 4B As shown, a processing step is performed on alloy layer 332 to form composite layer 314. This processing step can be a nitriding process. The processing step may include plasma-based processes (e.g., inductively coupled plasma (ICP), microwave-assisted plasma, capacitively coupled plasma (CCP)), ion beam bombardment, or other suitable processes. The processing step may utilize a nitrogen-containing gas, such as N2, N2O, NO, other suitable nitrogen-containing gases, or combinations thereof. In some embodiments, alloy layer 332 is completely nitrided, and the resulting composite layer 314 contains nitrogen throughout its entire thickness. In some embodiments, due to this processing step, the nitrogen concentration decreases in the direction from opening 312 to dielectric layer 305, and composite layer 314 is... Figure 3C-2 The gradient layer 328 described herein.

[0048] Figure 5A and Figure 5B The cross-sectional side views of each stage are formed according to the composite layer 314 of an alternative embodiment. For example... Figure 5A As shown, an alloy layer 332 is deposited in the opening 312 on the dielectric layer 305. Next, a processing step is performed to partially nitride the alloy layer 332 to form a gradient layer 328, as... Figure 5B As shown, the gradient layer 328 comprises an alloy nitride layer having a nitrogen concentration that decreases in the direction away from the dielectric layer 305.

[0049] Figure 6A , Figure 6B and Figure 6C The cross-sectional side views of each stage are manufactured according to the interconnect structure 300 of an alternative embodiment. For example... Figure 6A As shown, a composite layer 314 is formed in the opening 312 on the dielectric layer 305. Next, an etching process is performed to remove portions of the composite layer 314 formed on the horizontal surface, as shown. Figure 6B As shown. This etching process can be an anisotropic etching process. As a result, dielectric layer 301 (and / or conductive components formed in dielectric layer 301) is exposed at the bottom of opening 312. Furthermore, this etching process is a selective etching process, which does not significantly remove dielectric layers 301 and 305. Next, as Figure 6C As shown, a conductive member 330 is formed in the opening 312. In some embodiments, the conductive member 330 contacts or bonds to a conductive member (not shown) formed in the dielectric layer 301, and the contact resistance is reduced.

[0050] Figure 7A , Figure 7B and Figure 7C The cross-sectional side views of each stage are manufactured according to the interconnect structure 300 of an alternative embodiment. For example... Figure 7A As shown, a first layer 318 and a second layer 320 are formed in an opening 312 on the dielectric layer 305. In some embodiments, the second layer 320 comprises an alloy nitride exposed in the opening 312, while the first layer 318 comprises an alloy bonded to the dielectric layer 305. Next, one or more etching processes are performed to remove portions of the first layer 318 and the second layer 320 formed on the horizontal surface, such as... Figure 7BAs shown. The one or more etching processes can be anisotropic etching processes. For example, in some embodiments, a first anisotropic etching process is performed to remove a portion of the second layer 320 formed on the horizontal surface, and then a second anisotropic etching process is performed to remove a portion of the first layer 318 formed on the horizontal surface. The first and second anisotropic etching processes are selective etching processes. The first anisotropic etching process does not significantly affect the first layer 318, and the second anisotropic etching process does not significantly affect the second layer 320 and the dielectric layers 301, 305. In some embodiments, a single anisotropic etching process is performed to remove a portion of the first layer 318 and the second layer 320. After one or more etching processes, the dielectric layer 301 (and / or the conductive components formed in the dielectric layer 301) is exposed at the bottom of the opening 312. Next, as Figure 7C As shown, a conductive member 330 is formed in the opening 312. In some embodiments, the conductive member 330 contacts or bonds to a conductive member (not shown) formed in the dielectric layer 301, and the contact resistance is reduced.

[0051] Figure 8A , Figure 8B and Figure 8C The cross-sectional side views of each stage are manufactured according to the interconnect structure 300 of an alternative embodiment. For example... Figure 8A As shown, a first layer 318 and a second layer 320 are formed in an opening 312 on the dielectric layer 305. In some embodiments, the second layer 320 comprises an alloy nitride exposed in the opening 312, while the first layer 318 comprises an alloy bonded to the dielectric layer 305. Next, an etching process is performed to remove portions of the second layer 320 formed on the horizontal surface, as shown. Figure 8B As shown. In some embodiments, the etching process is a selective anisotropic etching process, and the first layer 318 is not significantly affected by the selective anisotropic etching process. In some embodiments, the etching process that removes a portion of the first layer 318 formed on the horizontal surface ( Figure 7B The second layer 320 formed on the vertical surface (as described in the text) may be damaged or removed. Therefore, to minimize the risk of damaging the second layer 320 formed on the vertical surface, the first layer 318 formed on the horizontal surface is not removed, as... Figure 8B As shown. Next, as Figure 8C As shown, a conductive component 330 is formed in the opening 312. The conductive component 330 can be bonded to the first layer 318 and the second layer 320, as shown. Figure 8CAs shown. Because the resistance of the first layer 318 is less than that of the second layer 320, the contact resistance does not increase significantly due to the presence of the first layer 318 disposed below the conductive component 330. After depositing the conductive component 330, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove portions of the conductive component 330 and the first layer 318 formed above the dielectric layer 305.

[0052] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E The cross-sectional side views of each stage are manufactured according to the interconnect structure 300 of an alternative embodiment. For example... Figure 9A As shown, a conductive component 338 is disposed in a dielectric layer 301. The conductive component 338 may be formed in an opening formed in the dielectric layer 301. In some embodiments, the conductive component 338 includes a barrier layer 340, a pad layer 342, a conductive layer 344, and a cover layer 346. The barrier layer 340 may include a material that can prevent metal from diffusing from the conductive layer 344 into the dielectric layer 301. In some embodiments, the barrier layer 340 includes tantalum (Ta), zinc (Zn), manganese (Mn), zirconium (Zr), titanium (Ti), hafnium (Hf), niobium (Nb), vanadium (V), chromium (Cr), scandium (Sc), yttrium (Y), tungsten (W), molybdenum (Mo), aluminum (Al), ruthenium (Ru), manganese (Mn), cobalt (Co), tantalum nitride (TaNx), titanium nitride (TiNx), tungsten nitride (WNx), hafnium oxide (HfOx), or other suitable materials. The barrier layer 340 can be formed using any applicable process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The padding layer 342 can be an adhesive layer. In some embodiments, the padding layer 342 comprises cobalt (Co), ruthenium (Ru), tantalum (Ta), or cobalt-ruthenium (CoRu). The padding layer 342 can be formed using any applicable process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The conductive layer 344 can comprise the same material as the conductive component 330. The conductive layer 344 can be formed using any applicable process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, or electroless plating. The capping layer 346 can comprise the same material as the padding layer 342. In some embodiments, after forming the conductive layer 344, an etching process is performed to recess the conductive layer 344, and the capping layer 346 is deposited on the recessed conductive layer 344. The capping layer 346 can be formed by any applicable process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0053] After the conductive component 338 is formed, an etch stop layer (ESL) 348 is deposited on the dielectric layer 301 and the conductive component 338, and a dielectric layer 305 is deposited on the etch stop layer 348. The etch stop layer 348 may include a dielectric material such as alumina (Al2O3) or silicon carbide (SiC). x ), silicon nitride (SiN) x ), silicon carbonitride (SiC) x Nitrogen oxides (NiO) x N, aluminum oxide (AlO) x (Nᵧ) or aluminum nitride (AlN) x The dielectric material can be doped with hafnium (Hf), zirconium (Zr), or yttrium (Y). The etch stop layer 348 can be formed using any suitable process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Next, openings 312 are formed in the dielectric layer 305 and the etch stop layer 348 to expose the conductive components 338, such as... Figure 9A As shown. Figure 9B As shown, a barrier layer 350 is selectively formed on exposed portions of the conductive component 338. In some embodiments, the barrier layer 350 is selectively formed on exposed capping layer 346. In some embodiments, the barrier layer 350 comprises a self-assembled monolayer (SAM). Examples of SAM materials may include thiol-based compounds (e.g., dodecylthiol and / or alkylthiols), acid-based compounds (e.g., phosphonic acid and / or octadecylphosphonic acid), bicyclic nitrogen heterocyclic compounds (e.g., benzotriazole), or combinations thereof. The barrier layer 350 may be selectively formed on the metal surface of capping layer 346, but not on the dielectric surfaces of dielectric layer 305 and etch barrier layer 348. The barrier layer 350 may be deposited by any applicable process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, dip coating, or combinations thereof).

[0054] Next, as Figure 9C As shown, composite layer 314 is selectively deposited on dielectric layer 305 and etch stop layer 348. Composite layer 314 can be... Figure 3C , Figure 3C-1 , Figure 3C-2 and Figure 3C-3 The method described is used for deposition. A barrier layer 350 prevents the composite layer 314 from being deposited thereon. (As...) Figure 9D As shown, the barrier layer 350 is removed. The barrier layer 350 can be removed by any applicable process, such as heat treatment, electro-assisted desorption, plasma treatment, or a combination thereof. The process for removing the barrier layer 350 is a selective process that does not significantly affect the composite layer 314 and the capping layer 346. Figure 9EAs shown, a conductive member 330 is formed in the opening 312. In some embodiments, the conductive member 330 is coupled to the conductive member 338, and the contact resistance is reduced.

[0055] Figure 10A , Figure 10B and Figure 10C The cross-sectional side views of each stage are manufactured according to the interconnect structure 300 of an alternative embodiment. For example... Figure 10A As shown, after forming a barrier layer 350 on the exposed capping layer 346, an alloy layer 332 is selectively deposited on the dielectric layer 305 and the etch stop layer 348. The alloy layer 332 can be... Figure 4A The method described is used for deposition. A barrier layer 350 prevents the alloy layer 332 from being deposited thereon. Next, as... Figure 10B As shown, the process is performed to simultaneously form the composite layer 314 (or gradient layer 328) and remove the barrier layer 350. For example, in some embodiments, a nitrogen-containing plasma treatment process is performed. The nitrogen-containing plasma process partially or fully nitrides the alloy layer 332 to form the composite layer 314 or gradient layer 328 having alloy portions and alloy nitride portions. The nitrogen-containing plasma treatment process may also remove the barrier layer 350. Next, as Figure 10C As shown, a conductive component 330 is formed in the opening 312.

[0056] Figure 11A , Figure 11B , Figure 11C , Figure 11D and Figure 11E The cross-sectional side views of each stage are manufactured according to the interconnect structure 300 of an alternative embodiment. For example... Figure 11A As shown, in some embodiments, the cover layer 346 is absent, and the conductive component 338 includes a barrier layer 340, a padding layer 342, and a conductive layer 344. The conductive layer 344 is exposed at the bottom of the opening 312. Next, as... Figure 11B As shown, a barrier layer 350 is selectively formed on the exposed surface of the conductive layer 344. The barrier layer 350 may be formed on the metal surface of the conductive layer 344, but not on the dielectric surfaces of the dielectric layer 305 and the etch stop layer 348. Figure 11C As shown, composite layer 314 is selectively formed on dielectric layer 305 and etch stop layer 348. Barrier layer 350 prevents composite layer 314 from depositing thereon. After composite layer 314 is deposited, barrier layer 350 is removed, as shown. Figure 11D As shown. Next, a conductive component 330 is formed in the opening 312, as shown. Figure 11E As shown. In some embodiments, the conductive component 330 is bonded to the conductive layer 344, such as... Figure 11E As shown.

[0057] Figure 12A , Figure 12B and Figure 12C The cross-sectional side views of each stage are manufactured according to the interconnect structure 300 of an alternative embodiment. For example... Figure 12A As shown, after forming a barrier layer 350 on the exposed conductive layer 344, an alloy layer 332 is selectively deposited on the dielectric layer 305 and the etch stop layer 348. The alloy layer 332 can be... Figure 4A The method described is used for deposition. A barrier layer 350 prevents the alloy layer 332 from being deposited thereon. Next, as... Figure 12B As shown, the process is performed to simultaneously form the composite layer 314 (or gradient layer 328) and remove the barrier layer 350. For example, in some embodiments, a nitrogen-containing plasma treatment process is performed. The nitrogen-containing plasma process partially or fully nitrides the alloy layer 332 to form the composite layer 314 or gradient layer 328 having alloy portions and alloy nitride portions. The nitrogen-containing plasma treatment process may also remove the barrier layer 350. Next, as Figure 12C As shown, a conductive component 330 is formed in the opening 312.

[0058] Various embodiments of this disclosure provide interconnect structures and methods of forming the same. In some embodiments, the interconnect structure includes a dielectric layer 305, a conductive component 330 disposed in the dielectric layer 305, and a composite layer 314 disposed between the dielectric layer 305 and the conductive component 330. The composite layer 314 may include an alloy nitride layer. Some embodiments offer advantages. For example, the alloy nitride layer may simultaneously act as a barrier layer and an adhesive layer. The thickness of the alloy nitride layer may be small, which may result in an increase in the size of the conductive component 330. Therefore, the resistance is reduced.

[0059] The embodiments relate to a method. The method includes: depositing a first dielectric layer over a second dielectric layer, forming an opening in the first dielectric layer, and forming a composite layer on the first dielectric layer within the opening. The composite layer comprises an alloy nitride. The method further includes: depositing a conductive component on the composite layer, wherein the conductive component fills the opening.

[0060] Another embodiment relates to a method. The method includes: depositing a first dielectric layer over a second dielectric layer; forming an opening in the first dielectric layer to expose a first conductive component in the second dielectric layer; selectively depositing a barrier layer on the first conductive component; and forming a composite layer on the first dielectric layer within the opening. The composite layer comprises an alloy nitride. The method further includes: depositing a second conductive component on the composite layer, wherein the second conductive component fills the opening.

[0061] Another embodiment relates to a structure. This structure includes: a first dielectric layer disposed above a second dielectric layer, a first conductive component disposed in the first dielectric layer, and a composite layer disposed between the first conductive component and the first dielectric layer. The composite layer comprises an alloy nitride.

[0062] Some embodiments of this application provide a method for forming an interconnect structure, comprising: depositing a first dielectric layer over a second dielectric layer; forming an opening in the first dielectric layer; forming a composite layer on the first dielectric layer in the opening, wherein the composite layer comprises an alloy nitride; and depositing a conductive component on the composite layer, wherein the conductive component fills the opening.

[0063] In some embodiments, the composite layer is formed by a deposition process. In some embodiments, forming the composite layer includes: depositing an alloy layer; and nitriding the alloy layer. In some embodiments, the alloy layer is partially nitrided. In some embodiments, the alloy layer is fully nitrided. In some embodiments, the composite layer has a nitrogen concentration that varies in a direction away from the first dielectric layer. In some embodiments, the method further includes removing a portion of the composite layer formed on a horizontal surface before depositing the conductive component. In some embodiments, a portion of the composite layer is removed by an anisotropic etching process.

[0064] Other embodiments of this application provide a method for forming an interconnect structure, comprising: depositing a second dielectric layer over a first dielectric layer; forming an opening in the first dielectric layer to expose a first conductive component located in the second dielectric layer; selectively depositing a barrier layer on the first conductive component; forming a composite layer on the first dielectric layer in the opening, wherein the composite layer comprises an alloy nitride; and depositing a second conductive component on the composite layer, wherein the second conductive component fills the opening.

[0065] In some embodiments, the method further includes removing the barrier layer after forming the composite layer. In some embodiments, forming the composite layer includes: depositing an alloy layer; and nitriding the alloy layer. In some embodiments, the alloy layer is nitrided using a plasma process. In some embodiments, the barrier layer is removed using the plasma process. In some embodiments, the first conductive component includes a barrier layer, a pad, a conductive layer, and a capping layer. In some embodiments, the barrier layer is selectively deposited on the capping layer.

[0066] Some embodiments of this application provide an interconnect structure including: a first dielectric layer disposed above a second dielectric layer; a first conductive component disposed in the second dielectric layer; and a composite layer disposed between the first conductive component and the first dielectric layer, wherein the composite layer comprises an alloy nitride.

[0067] In some embodiments, the alloy nitride includes CoNbN, TaNbN, RuNbN, CoTaN, CoTaNbN, CoRuNbN, CoRuTaN, CoZrN, or CoVN. In some embodiments, the interconnect structure further includes a second conductive component disposed in the second dielectric layer, wherein the first conductive component is disposed above the second conductive component. In some embodiments, the thickness of the composite layer ranges from 5 angstroms to 50 angstroms. In some embodiments, the composite layer has a gradient nitrogen concentration.

[0068] The foregoing has outlined features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming an interconnect structure, comprising: A first dielectric layer is deposited over the second dielectric layer; An opening is formed in the first dielectric layer; A composite layer is formed on a first dielectric layer in the opening, wherein the composite layer comprises an alloy nitride; and A conductive component is deposited on the composite layer, wherein the conductive component fills the opening.

2. The method according to claim 1, wherein the composite layer is formed by a deposition process.

3. The method of claim 1, wherein forming the composite layer comprises: Deposited alloy layer; as well as The alloy layer is nitrided.

4. The method of claim 3, wherein the alloy layer is partially nitrided.

5. The method of claim 3, wherein the alloy layer is fully nitrided.

6. The method of claim 3, wherein the composite layer has a nitrogen concentration that varies in a direction away from the first dielectric layer.

7. The method of claim 1, further comprising removing a portion of the composite layer formed on the horizontal surface prior to depositing the conductive component.

8. The method of claim 7, wherein a portion of the composite layer is removed by an anisotropic etching process.

9. A method for forming an interconnect structure, comprising: A second dielectric layer is deposited over the first dielectric layer; An opening is formed in the first dielectric layer to expose a first conductive component located in the second dielectric layer; A barrier layer is selectively deposited on the first conductive component; A composite layer is formed on the first dielectric layer in the opening, wherein the composite layer comprises an alloy nitride; and A second conductive component is deposited on the composite layer, wherein the second conductive component fills the opening.

10. An interconnection structure, comprising: The first dielectric layer is disposed above the second dielectric layer; A first conductive component is disposed in the second dielectric layer; as well as A composite layer is disposed between the first conductive component and the first dielectric layer, wherein the composite layer comprises an alloy nitride.

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