GaN integrated passive device based on SiC substrate and preparation method thereof

Abstract

This invention discloses a GaN integrated passive device based on a SiC substrate and its fabrication method, comprising: a SiC substrate; a GaN buffer layer disposed on the SiC substrate; an AlGaN barrier layer disposed on the GaN buffer layer; thin-film resistors and MIM capacitors disposed on the AlGaN barrier layer; a dielectric isolation layer covering the thin-film resistors and MIM capacitors; and a planar spiral inductor disposed on the surface of the dielectric isolation layer. All components are electrically connected via a metal interconnect layer and monolithically integrated on the same SiC substrate. The integrated passive device of this invention replaces bonding wires and package interconnects with an on-chip metal interconnect layer, eliminating parasitic inductance and capacitance introduced by discrete assembly. The composite substrate balances high frequency, low loss, and efficient heat dissipation.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a GaN integrated passive device based on a SiC substrate and its fabrication method. Background Technology

[0002] With the development of 5G mobile communication and next-generation wireless communication systems, RF front-end modules are evolving towards miniaturization, higher frequency, and higher performance. The passive functions formed by the matching network, filtering network, and bias network within the module occupy a large amount of board area. The parasitic effects of discrete passive components restrict high-frequency performance. Therefore, integrated passive devices (IPDs), which integrate three types of passive components—thin-film resistors, capacitors, and inductors—on the same substrate, have become an important technical route for RF front-end integration.

[0003] Currently, most integrated passive devices are fabricated on silicon, glass, or gallium arsenide substrates. In the silicon carbide (SiC) and gallium nitride (GaN) system, patent application WO2023114975A1 discloses an integrated passive device assembly with a silicon carbide substrate. This assembly uses silicon carbide as the substrate, with a group III nitride intermediate layer, and can be configured with capacitors, resistors, and / or inductors. However, in this design, the integrated passive device assembly and the transistor die are separate dies, mounted on a metal base and connected via an interconnect structure. Furthermore, the industry has also fabricated integrated passive devices on semi-insulating SiC substrates, incorporating silicon nitride dielectric MIM capacitors, electroplated thick metal spiral inductors, thin-film resistors, and through-substrate vias. These devices have achieved a two-stage power amplifier with 20W output power, 23.3dB gain, and a power-added efficiency greater than 38% in the 3.4–3.8 GHz frequency band, validating the technical feasibility of SiC-based integrated passive devices.

[0004] In the aforementioned discrete assembly method, the chips are electrically connected by bonding wires and package interconnection. The bonding wires introduce additional parasitic inductance and parasitic capacitance, which exacerbate the degradation of circuit performance as the operating frequency increases, limiting further improvement of the device's high-frequency performance.

[0005] In view of this, there is a need for an integrated passive device and its fabrication scheme that can monolithically integrate passive components and eliminate the parasitic interconnections of bonding wires and packages. Summary of the Invention

[0006] The technical problem to be solved by the present invention is that in the existing passive GaN on SiC scheme, passive components and devices are assembled separately and interconnected by bonding wires and packages, which introduces additional parasitic inductance and capacitance, limiting high-frequency performance.

[0007] To address the aforementioned technical problems, in a first aspect, the present invention provides a GaN integrated passive device based on a SiC substrate, comprising: a SiC substrate; a GaN buffer layer disposed on the SiC substrate; an AlGaN barrier layer disposed on the GaN buffer layer; a thin-film resistor element disposed on the AlGaN barrier layer; a MIM capacitor element disposed on the AlGaN barrier layer, comprising a lower electrode metal layer, a dielectric insulating layer, and an upper electrode metal layer; a dielectric isolation layer covering the thin-film resistor element and the MIM capacitor element; a planar spiral inductor element disposed on the surface of the dielectric isolation layer; and a metal interconnect layer disposed on the surface of the dielectric isolation layer for realizing electrical connections between the thin-film resistor element, the MIM capacitor element, and the planar spiral inductor element; wherein the thin-film resistor element, the MIM capacitor element, and the planar spiral inductor element are monolithically integrated on the same SiC substrate.

[0008] Furthermore, the dielectric insulating layer comprises a first alumina layer, a silicon nitride layer, and a second alumina layer stacked from bottom to top.

[0009] Furthermore, a grounding shield is provided within the dielectric isolation layer. The grounding shield is located directly below the projection area of ​​the planar spiral inductor element and is connected to the AC ground potential.

[0010] Furthermore, the grounding shielding layer is a metal mesh structure or a complete metal plate structure.

[0011] Furthermore, it also includes a nucleation layer disposed between the SiC substrate and the GaN buffer layer.

[0012] Furthermore, the inner end of the planar spiral inductor is connected to the lower metal layer through a through-hole in the dielectric isolation layer, and the outer end is led out as an inductor port.

[0013] Furthermore, it also includes a surface passivation layer covering the surface of the device.

[0014] Secondly, the present invention provides a method for fabricating a GaN integrated passive device based on a SiC substrate, comprising the following steps: growing a GaN buffer layer on a SiC substrate, and growing an AlGaN barrier layer on the GaN buffer layer; sequentially depositing a lower electrode metal layer, fabricating a dielectric insulating layer, and depositing an upper electrode metal layer on the AlGaN barrier layer to form a MIM capacitor element; fabricating a thin-film resistor element on the AlGaN barrier layer; depositing a dielectric isolation layer on the device surface and etching vias in the dielectric isolation layer; fabricating a planar spiral inductor element on the surface of the dielectric isolation layer; and depositing a metal interconnect layer to realize the electrical connection between the thin-film resistor element, the MIM capacitor element, and the planar spiral inductor element.

[0015] Furthermore, the preparation of the dielectric insulating layer includes: sequentially depositing a first alumina layer, a silicon nitride layer, and a second alumina layer using an atomic layer deposition process.

[0016] Thirdly, the present invention provides a radio frequency front-end module, including the GaN integrated passive device based on SiC substrate described in the first aspect.

[0017] Beneficial effects: By monolithically integrating thin-film resistors, MIM capacitors, and planar spiral inductors on the same SiC substrate and directly interconnecting them with the on-chip metal interconnect layer, the parasitic inductance and parasitic capacitance introduced by bonding wires and package interconnects are eliminated. The composite substrate formed by the SiC substrate, GaN buffer layer, and AlGaN barrier layer simultaneously meets the requirements of high frequency, low loss, and high-efficiency heat dissipation. Attached Figure Description

[0018] Figure 1 This is a cross-sectional structural diagram of the integrated passive device of the present invention; Figure 2 This is a schematic diagram of the planar layout of the integrated passive components of the present invention; Figure 3 This is a partially enlarged schematic diagram of the dielectric insulating layer of the MIM capacitor element of the present invention; Figure 4 This is a partially enlarged schematic diagram of the planar spiral inductor and the grounding shielding layer of the present invention; Figure 5 This is a flowchart of the method for fabricating integrated passive devices according to the present invention.

[0019] Explanation of reference numerals in the attached figures: 1. SiC substrate; 11. AlN nucleation layer; 2. GaN buffer layer; 3. AlGaN barrier layer; 4. Thin film resistor; 5. MIM capacitor; 51. Lower electrode metal layer; 52. Dielectric insulating layer; 521. First alumina layer; 522. Silicon nitride layer; 523. Second alumina layer; 53. Upper electrode metal layer; 6. Dielectric isolation layer; 61. Through-hole; 7. Grounding shield layer; 8. Planar spiral inductor; 9. Metal interconnect layer; 10. Surface passivation layer. Detailed Implementation

[0020] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an integrated GaN passive device based on a SiC substrate and its fabrication method.

[0021] Example 1 This embodiment illustrates a first implementation of the present invention that integrates passive devices.

[0022] like Figure 1As shown, the GaN integrated passive device based on a SiC substrate in this embodiment includes: a SiC substrate 1, a GaN buffer layer 2, an AlGaN barrier layer 3, a thin-film resistor element 4, a MIM capacitor element 5, a dielectric isolation layer 6, a ground shielding layer 7, a planar spiral inductor element 8, a metal interconnect layer 9, and a surface passivation layer 10; wherein, the GaN buffer layer 2 is disposed on the SiC substrate 1, the AlGaN barrier layer 3 is disposed on the GaN buffer layer 2, the thin-film resistor element 4 and the MIM capacitor element 5 are disposed on the AlGaN barrier layer 3, the dielectric isolation layer 6 covers the thin-film resistor element 4 and the MIM capacitor element 5, the ground shielding layer 7 is disposed within the dielectric isolation layer 6, the planar spiral inductor element 8 is disposed on the surface of the dielectric isolation layer 6, and the passive components are isolated by the dielectric isolation layer 6 and electrically connected through the metal interconnect layer 9.

[0023] SiC substrate 1 is a semi-insulating 4H-SiC or 6H-SiC single crystal substrate with a resistivity of not less than 1×10⁻⁶. 5 The resistivity of the semi-insulating SiC substrate is higher than 1×10⁻⁶ Ω·cm, and the thickness is 100~500μm. 5 With a dielectric constant of Ω·cm, eddy current losses and parasitic capacitance effects within the substrate are suppressed to very low levels at high frequencies. Simultaneously, SiC's thermal conductivity reaches 490 W / (m·K), more than three times that of silicon, allowing for rapid dissipation of Joule heat generated during passive component operation. Therefore, the substrate simultaneously undertakes the two fundamental functions of high-frequency, low-loss load carrying and efficient heat dissipation. This is the direct reason for choosing SiC over high-resistivity silicon, glass, or GaAs substrates in this solution—high-resistivity silicon suffers from eddy current losses and has a thermal conductivity of only 150 W / (m·K), glass has a thermal conductivity of only 1 W / (m·K) and cannot be used in high-power-density applications, and GaAs is expensive with a thermal conductivity of 55 W / (m·K). Furthermore, the dielectric constant of semi-insulating SiC is 9.7, lower than silicon's 11.9, resulting in lower dielectric losses at high frequencies; while high-resistivity silicon is prone to forming parasitic conductive layers on its surface, affecting the stability of device performance.

[0024] An AlN nucleation layer 11, with a thickness of 20–50 nm, is disposed between the SiC substrate 1 and the GaN buffer layer 2. A 3.5% lattice mismatch exists between SiC and GaN. The AlN nucleation layer 11 buffers this mismatch, providing nucleation conditions for the subsequent gallium nitride epitaxial layer and ensuring the crystal quality of the epitaxial layer. This mismatch is much smaller than the 17% lattice mismatch between Si and GaN, which is a key advantage of SiC as a substrate for supporting high-quality gallium nitride epitaxial layers.

[0025] The GaN buffer layer 2 is disposed on the AlN nucleation layer 11, that is, on the SiC substrate 1 via the nucleation layer, with a thickness of 0.5~3μm. It is unintentionally doped or carbon doped, with a carbon doping concentration of 1×10⁻⁶. 17 ~1×1018 cm -3 The GaN buffer layer 2 serves three functions: first, it acts as a transition layer between the passive components and the SiC substrate 1, providing a smooth deposition surface for the upper components; second, GaN's thermal conductivity can reach 130 W / (m·K), forming a heat conduction channel from the components to the SiC substrate 1, conducting the heat generated by the thin-film resistor 4 and the MIM capacitor 5 downwards; third, it forms a heterostructure with the AlGaN barrier layer 3, influencing the temperature characteristics of the upper thin-film resistor through interfacial stress effects. Of these three functions, the first two are directly derived from the positional relationship of the GaN layer being sandwiched between the components and the high thermal conductivity substrate, while the third function ensures that the AlGaN barrier layer on top is not merely an appendage of the epitaxial stack, but rather a supporting surface for the components.

[0026] An AlGaN barrier layer 3 is disposed on top of the GaN buffer layer 2, with a thickness of 15~30 nm and an aluminum composition of 0.15~0.30. The AlGaN barrier layer 3 and the GaN buffer layer 2 together constitute an AlGaN / GaN heterostructure, providing a bearing surface for the thin-film resistor element 4, and controlling the temperature coefficient of the thin-film resistor through the interfacial stress effect of the heterostructure.

[0027] Thin-film resistive element 4 is disposed on the AlGaN barrier layer 3 and is formed by patterning a resistive metal layer. The resistive metal layer is made of NiCr, TaN, TiW, or TiN, with a thickness of 50~200nm. The resistive pattern is a serpentine, rectangular, or T-shaped structure. The desired resistance value is achieved by adjusting the width, length, and thickness of the resistive metal layer, typically ranging from 10Ω to 10kΩ. The thin-film resistive element 4 undergoes annealing treatment to achieve precise control of the resistance value. The annealing temperature is 300~500℃, and the atmosphere is nitrogen. The reason why the thin-film resistive element 4 is disposed on the AlGaN barrier layer 3 rather than directly on the dielectric layer is that: after the interfacial stress effect of the AlGaN / GaN heterostructure acts on the resistive metal layer, the temperature coefficient of resistance can be reduced to below ±50ppm / ℃, resulting in small resistance drift under high power operation and maintaining circuit accuracy; at the same time, the heat generated by the resistor is quickly dissipated through the heat conduction path connecting the AlGaN barrier layer to the SiC substrate 1 via the GaN buffer layer 2.

[0028] The MIM capacitor element 5 is a metal-insulator-metal capacitor element, including a lower electrode metal layer 51, a dielectric insulating layer 52, and an upper electrode metal layer 53. The lower electrode metal layer 51 is disposed on the AlGaN barrier layer 3, and is made of Ti / Pt / Au, TiN, or TaN, with a thickness of 100~300nm; the upper electrode metal layer 53 is disposed on the dielectric insulating layer 52, and is made of Ti / Pt / Au or TiN, with a thickness of 100~300nm; the upper electrode metal layer 53 and the lower electrode metal layer 51 form an overlapping region in the projection, and the overlapping region is the effective capacitance region.

[0029] The dielectric insulating layer 52 is disposed between the lower electrode metal layer 51 and the upper electrode metal layer 53. It is a multilayer composite structure, consisting of a first alumina layer 521, a silicon nitride layer 522, and a second alumina layer 523 stacked from bottom to top, i.e., an Al2O3 / SiN / Al2O3 stack. Each layer is prepared by atomic layer deposition at 200~300℃. The thickness of the first alumina layer 521 and the second alumina layer 523 is 5~15nm, the thickness of the silicon nitride layer 522 is 10~30nm, and the total thickness of the stack is 20~60nm. The reason for using a three-layer composite structure for the dielectric insulating layer 52 instead of a single silicon nitride dielectric is that: a single dielectric layer is prone to pinhole defects during thin-film formation. Once a pinhole penetrates, the upper and lower electrodes are directly connected, resulting in increased leakage current and decreased breakdown voltage. In the three-layer composite structure, the defect positions of each layer are staggered, and the defect connection path is blocked by the interlayer interface, so a pinhole in a single layer will not penetrate the entire dielectric. Atomic layer deposition (ALD) utilizes self-confined surface reactions to grow atomically layer by layer, resulting in dense, pinhole-free films with atomically controlled thickness. Of the three layers, the alumina layer provides a high dielectric constant (7–9), high breakdown field strength, and good interface properties, while the silicon nitride layer provides a high dielectric constant (6–7) and good step coverage. Thus, the dielectric insulating layer 52 simultaneously achieves a high capacitance density (2–5 fF / μm). 2 Low leakage current density (below 1×10) -8 A / cm 2 @1MV / cm) and high breakdown voltage (greater than 50V).

[0030] like Figure 3 The diagram shown is a partially enlarged schematic diagram of the dielectric insulating layer 52, illustrating the stacking relationship between the lower electrode metal layer 51, the first alumina layer 521, the silicon nitride layer 522, the second alumina layer 523, and the upper electrode metal layer 53.

[0031] A dielectric isolation layer 6 covers the thin-film resistor element 4 and the MIM capacitor element 5, and is made of silicon dioxide or silicon nitride with a thickness of 200~500nm. The dielectric isolation layer 6 isolates the passive components from each other and provides a bearing surface for the planar spiral inductor element 8. A through-hole 61 is formed in the dielectric isolation layer 6, which extends from the surface of the dielectric isolation layer 6 to the metal contact area of ​​the underlying layer for vertical interconnection between components.

[0032] A grounding shield 7 is disposed within the dielectric isolation layer 6, directly below the projected area of ​​the planar spiral inductor element 8, at a distance of 0.5~2μm from the planar spiral inductor element 8, and connected to AC ground potential. The grounding shield 7 is a metal mesh structure or a complete metal plate structure. After the inductor coil is energized, its electric field lines penetrate downwards towards the substrate. Without shielding, the electric field lines enter the SiC substrate 1, causing dielectric loss and reducing the inductance quality factor. With the grounding shield 7, the electric field lines terminate at the grounding shield 7 and no longer enter the substrate, thus blocking substrate loss and improving the inductance quality factor by 10~20%. The 0.5~2μm spacing between the shield and the inductor ensures that the shield is located in the near-field range of the inductor to fully intercept the electric field lines, while avoiding excessive spacing that could cause eddy currents at the metal edge to reverse and cancel the inductance flux, resulting in an excessive reduction in inductance.

[0033] like Figure 4 The diagram shown is a partially enlarged schematic of the planar spiral inductor 8 and the grounding shield 7, illustrating the coil cross-section of the dielectric isolation layer 6, the grounding shield 7, the through-hole 61, and the stacking and positional relationship of the metal interconnect layer 9.

[0034] A planar spiral inductor element 8 is disposed on the surface of the dielectric isolation layer 6. It is formed by patterning a thick metal layer into a planar spiral structure. The thick metal layer is made of Cu, Au, or Al, with a thickness of 2–10 μm, 2–10 turns, a linewidth of 10–50 μm, and a line spacing of 5–30 μm. The inner end of the planar spiral inductor element 8 is connected to the lower metal layer through a through-hole 61 in the dielectric isolation layer 6, and the outer end is led out as the inductor port. The thick metal layer controls the coil series resistance to a low level. Combined with the low-loss characteristics of the SiC substrate 1 and the field shielding effect of the grounding shielding layer 7, the inductance quality factor reaches over 30 in the 5 GHz band.

[0035] A metal interconnect layer 9, made of Ti / Au, is disposed on the surface of the dielectric isolation layer 6 and, after patterning, enables electrical connections between the thin-film resistor element 4, the MIM capacitor element 5, and the planar spiral inductor element 8. In this scheme, all connections between components are completed by the metal interconnect layer 9 within the chip, eliminating the need for bonding wires and package interconnects. This eliminates the parasitic inductance and capacitance introduced by bonding wires in discrete assembly schemes.

[0036] A surface passivation layer 10 is applied to the device surface. It is made of silicon nitride or polyimide and has a thickness of 300~1000nm. It covers and protects the interconnect layer and inductor, and isolates them from moisture and contaminants.

[0037] like Figure 2The diagram shows a planar layout of the aforementioned integrated passive device. The thin-film resistor element 4 has a serpentine shape. The upper electrode metal layer 53 and the lower electrode metal layer 51 of the MIM capacitor element 5 overlap in projection. The planar spiral inductor element 8 is a square spiral coil, and part of its projection covers the MIM capacitor element 5. The projection of the grounding shielding layer 7 covers the projection area of ​​the planar spiral inductor element 8. The inner end of the planar spiral inductor element 8 is led out through the through hole 61. Figure 2 The dashed lines represent the lower layer thin-film resistor element 4, lower electrode metal layer 51, upper electrode metal layer 53, and ground shield layer 7. The solid lines represent the top layer planar spiral inductor element 8, leads, and vias. The ports of the thin-film resistor element 4, MIM capacitor element 5, and planar spiral inductor element 8 are led out along the edge of the chip.

[0038] When the aforementioned integrated passive device operates as a complete IPD unit, the radio frequency signal enters the metal interconnect layer 9 through the port and is transmitted between the thin film resistor element 4, the MIM capacitor element 5, and the planar spiral inductor element 8, forming the resistance, capacitance, and inductance values ​​required for the matching network, filter network, or bias network. The heat generated by each element during operation is conducted to the SiC substrate 1 through the AlGaN barrier layer 3 and the GaN buffer layer 2 and dissipated through the substrate. The electric field lines of the planar spiral inductor element 8 are intercepted by the ground shielding layer 7 and do not enter the SiC substrate 1.

[0039] As a variation of this embodiment, the dielectric insulating layer 52 can also be replaced by an Al2O3 / SiN / Al2O3 stack using an HfO2 / SiN / HfO2, ZrO2 / SiN / ZrO2, or Al2O3 / HfO2 stack, each stack also prepared by atomic layer deposition. Thus, the dielectric material combination can be adjusted according to the requirements of capacitance density and leakage current: hafnium oxide and zirconium oxide have higher dielectric constants than aluminum oxide, and higher capacitance density can be obtained after replacement; this approach is also feasible, but aluminum oxide has better interface characteristics and breakdown field strength. This solution uses Al2O3 / SiN / Al2O3 as the base stack, achieving a balance between capacitance density and reliability.

[0040] As another variation of this embodiment, the grounding shield 7 can also be replaced with a grounding ring structure, that is, a ring-shaped grounding metal is only provided around the periphery of the planar spiral inductor element 8. This simplifies the patterning process of the shielding layer; this approach is also feasible, but the grounding ring can only intercept the electric field lines on the outside of the inductor, and the electric field lines directly below the inductor projection area will still enter the substrate. This solution exchanges a shielding layer that fully covers the area directly below the projection area for a higher quality factor gain.

[0041] As another variation of this embodiment, the GaN buffer layer 2 can also be replaced with an AlGaN gradient buffer layer or an AlN / GaN superlattice buffer layer. This further reduces the dislocation density of the buffer layer, thereby improving the uniformity and stability of the upper thin film resistance.

[0042] As another variation of this embodiment, the resistive metal layer of the thin-film resistive element 4 can also be made of chromium silicide (CrSi), titanium silicide (TiSi), or a cermet composite material. This allows for different combinations of resistivity and temperature coefficient of resistance, adapting to different resistance accuracy requirements.

[0043] As another variation of this embodiment, the planar spiral inductor element 8 can also adopt a circular spiral inductor, an octagonal spiral inductor, or a differential spiral inductor structure. This allows it to adapt to different circuit layouts and performance requirements.

[0044] As another variant of this embodiment, the SiC substrate 1 can also be a conductive SiC substrate for applications requiring substrate grounding; in this case, an insulating layer (AlN or SiO2) is added between the GaN buffer layer 2 and the SiC substrate 1 to prevent crosstalk between components caused by substrate conductivity.

[0045] As another variation of this embodiment, the passive components of this solution can be partially integrated as needed. This could involve integrating only thin-film resistors and MIM capacitors to form an RC network, integrating only MIM capacitors and planar spiral inductors to form an LC filter, or integrating only a single component to form a high-precision thin-film resistor or a high-quality factor inductor. This adapts to different circuit functional requirements, and the stacking relationships and fabrication methods under various partial integration forms are consistent with the complete integration solution described above.

[0046] In summary, this embodiment integrates thin-film resistors, MIM capacitors, and planar spiral inductors onto a single SiC substrate, eliminating the bonding wires and package interconnects required for discrete component assembly, and significantly reducing parasitic parameters. The high resistivity and high thermal conductivity of the SiC substrate, the thermal channel function of the GaN buffer layer, the pinhole-free characteristics of the atomic layer-deposited multilayer composite dielectric, and the field shielding effect of the grounding shielding layer work synergistically to enable the device to simultaneously achieve high-frequency, low-loss, efficient heat dissipation, and high-performance passive component monolithic integration. Leveraging the high-temperature stability of the SiC substrate, the device can operate within a temperature range of -55℃ to 200℃. Compared to discrete solutions requiring the assembly of gallium nitride active chips, passive device chips, and packaging substrates, this embodiment integrates all passive components on a single chip, reducing the number of components and assembly steps, and consequently shrinking the module size.

[0047] Example 2 This embodiment illustrates the fabrication method of the above-mentioned integrated passive device. The difference between this embodiment and Embodiment 1 is that Embodiment 1 describes the stacked structure of the device, while this embodiment describes the fabrication process of the structure.

[0048] The overall approach of this fabrication method is as follows: first, high-temperature epitaxial growth is completed, followed by lower-temperature component fabrication; first, a low aspect ratio planar structure is fabricated, followed by a high aspect ratio thick metal structure; three passive components are sequentially fabricated on the same substrate in the order of "MIM capacitor—thin-film resistor—dielectric isolation—shielding layer—inductor—interconnect," and all steps constitute a monolithic integrated circuit process. Figure 5 As shown, this preparation method includes steps S1 to S10.

[0049] Step S1: SiC substrate preparation and cleaning. A semi-insulating 4H-SiC substrate is selected and subjected to RCA standard cleaning and dilute hydrofluoric acid cleaning sequentially to remove surface organic matter and metallic contaminants, resulting in a clean substrate surface. The cleaning quality directly determines the nucleation quality of subsequent epitaxial layers.

[0050] Step S2: Epitaxial growth of GaN buffer layer and AlGaN barrier layer. Using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), an AlN nucleation layer (20-50 nm thick) and a GaN buffer layer (0.5-3 μm thick, carbon doping concentration 1×10⁻⁶) are sequentially grown on a SiC substrate. 17 ~1×10 18 cm -3 The composite substrate described in Example 1 was obtained by adding an AlGaN barrier layer (thickness 15~30nm, aluminum content 0.15~0.30).

[0051] Step S3: Fabrication of the lower electrode of the MIM capacitor. A lower electrode metal layer is deposited on the AlGaN barrier layer, using Ti / Pt / Au, TiN, or TaN, with a thickness of 100~300nm; the lower electrode metal layer is patterned using photolithography and etching processes to form the lower electrode of the MIM capacitor.

[0052] Step S4: Fabrication of the MIM capacitor dielectric layer. Using atomic layer deposition (ALD), a first Al₂O₃ layer (5-15 nm thick), a SiN layer (10-30 nm thick), and a second Al₂O₃ layer (5-15 nm thick) are sequentially deposited on the lower electrode surface at 200-300°C, forming a multilayer composite dielectric layer with a total thickness of 20-60 nm. The self-confined surface reaction characteristics of ALD allow for atomic-level control of the thickness of each layer, resulting in a dense film free of pinholes.

[0053] Step S5: Fabrication of the upper electrode of the MIM capacitor. A top electrode metal layer (Ti / Pt / Au or TiN) with a thickness of 100~300nm is deposited on the composite dielectric layer; the top electrode metal layer is patterned using photolithography and etching processes to form an overlapping region with the lower electrode, thus constituting the MIM capacitor.

[0054] Step S6: Fabrication of thin-film resistive elements. A resistive metal layer (NiCr, TaN, TiW, or TiN) with a thickness of 50–200 nm is deposited on the AlGaN barrier layer. The resistive metal layer is patterned using photolithography and etching processes to form a thin-film resistor with the desired resistance value and shape. Subsequently, it is annealed at 300–500 °C in a nitrogen atmosphere to achieve precise control of the resistance value. The resistive metal layer and the MIM capacitor electrode metal layer can use the same or different metal material systems. In this step, the thin-film resistor and the MIM capacitor are fabricated in the same layer and share the same photolithography platform, which reflects the compatibility of the three passive component processes.

[0055] Step S7: Dielectric isolation layer deposition and via etching. A dielectric isolation layer (silicon dioxide or silicon nitride) with a thickness of 200~500nm is deposited on the device surface; vias are made at the corresponding positions of the upper and lower electrodes of the resistor element and MIM capacitor using photolithography and etching processes to expose the metal contact area.

[0056] Step S8: Grounding Shielding Layer Preparation. A metallic grounding shielding layer (patterned metallic layer) is prepared directly below the projected area of ​​the planar spiral inductor within the dielectric isolation layer and connected to the AC ground potential. In this step, the shielding layer is embedded within the dielectric isolation layer, maintaining a dielectric gap of 0.5–2 μm between the shielding layer and the inductor.

[0057] Step S9: Fabrication of the planar spiral inductor. A seed layer is deposited on the dielectric isolation layer, followed by the deposition of a thick metal layer (Cu / Au stack or Al) with a thickness of 2–10 μm using electroplating or sputtering. A planar spiral inductor pattern is then formed using photolithography and etching, with 2–10 turns, a linewidth of 10–50 μm, and a line spacing of 5–30 μm. The inner end of the inductor is connected to the lower metal layer through vias, and the outer end is led out as the inductor port. This step is placed after the dielectric isolation layer and the shielding layer, ensuring that the high aspect ratio structure of the thick metal inductor is not affected by the preceding planarization.

[0058] Step S10: Metal interconnection and surface passivation. Deposit an interconnect metal layer (Ti / Au), pattern it, and realize the circuit connection between resistors, capacitors, and inductors; deposit the final passivation layer (silicon nitride or polyimide) with a thickness of 300~1000nm to complete the device fabrication.

[0059] The above-described fabrication method integrates the fabrication of three passive components into a single process flow: epitaxial growth is a high-temperature process performed first, while the component fabrication is a low-temperature process performed later, avoiding the risk of temperature damage to the preceding structure in the subsequent process; the MIM capacitor, thin-film resistor, dielectric isolation layer, shielding layer, and inductor are constructed layer by layer upwards, corresponding one-to-one with the stacked structure of Example 1. Thus, the three passive components are monolithically integrated on the same SiC substrate in a single step, eliminating the need for discrete component assembly, packaging, and interconnection.

[0060] Example 3 This embodiment illustrates one application of the aforementioned integrated passive device. The difference from Embodiment 1 is that Embodiment 1 describes the device's own stacked structure, while this embodiment describes its application within an RF front-end module. An RF front-end module includes the GaN integrated passive device based on a SiC substrate as described in Embodiment 1, and an RF active circuit electrically connected to the port of the integrated passive device. The integrated passive device serves as the matching network, filtering network, or bias network of the RF front-end module. Its thin-film resistors, MIM capacitors, and planar spiral inductors form an RF functional circuit connected to the RF active circuit via ports, forming a complete RF transceiver link in conjunction with the RF active circuit. Since the three passive components are monolithically integrated on the same SiC substrate, the RF front-end module eliminates the need for separate assembly and bonding of passive components, reducing internal interconnect parasitics and improving high-frequency performance and reliability.

[0061] The aforementioned integrated passive devices can be used in power amplifier matching networks, filters and duplexers, impedance transformers and baluns in RF front-end modules, passive networks in automotive radar (77GHz / 79GHz) RF front-ends, bias networks and bandwidth extension circuits for transimpedance amplifiers in optical communication modules, as well as electronic systems in high-temperature environments such as oil drilling and aerospace.

[0062] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the technical scope of the present invention. Therefore, any minor modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A GaN integrated passive device based on a SiC substrate, characterized in that, include: SiC substrate; GaN buffer layer disposed on the SiC substrate; An AlGaN barrier layer is disposed on top of the GaN buffer layer; A thin-film resistor element is disposed on the AlGaN barrier layer; a MIM capacitor element is disposed on the AlGaN barrier layer and includes a lower electrode metal layer, a dielectric insulating layer and an upper electrode metal layer. A dielectric isolation layer covers the thin-film resistor element and the MIM capacitor element; a planar spiral inductor element is disposed on the surface of the dielectric isolation layer; a metal interconnect layer is disposed on the surface of the dielectric isolation layer for realizing electrical connection between the thin-film resistor element, the MIM capacitor element and the planar spiral inductor element; the thin-film resistor element, the MIM capacitor element and the planar spiral inductor element are monolithically integrated on the same SiC substrate.

2. The GaN integrated passive device based on a SiC substrate according to claim 1, characterized in that, The dielectric insulating layer comprises a first alumina layer, a silicon nitride layer, and a second alumina layer stacked from bottom to top.

3. The GaN integrated passive device based on a SiC substrate according to claim 1, characterized in that, A grounding shield is provided inside the dielectric isolation layer. The grounding shield is located directly below the projection area of ​​the planar spiral inductor element and is connected to the AC ground potential.

4. The GaN integrated passive device based on a SiC substrate according to claim 3, characterized in that, The grounding shielding layer is a metal mesh structure or a complete metal plate structure.

5. The GaN integrated passive device based on a SiC substrate according to claim 1, characterized in that, It also includes a nucleation layer disposed between the SiC substrate and the GaN buffer layer.

6. The GaN integrated passive device based on a SiC substrate according to claim 1, characterized in that, The inner end of the planar spiral inductor is connected to the lower metal layer through a through-hole in the dielectric isolation layer, and the outer end is led out as an inductor port.

7. The GaN integrated passive device based on a SiC substrate according to claim 1, characterized in that, It also includes a surface passivation layer covering the surface of the device.

8. A method for fabricating GaN integrated passive devices based on SiC substrates, characterized in that, The process includes the following steps: growing a GaN buffer layer on a SiC substrate, and growing an AlGaN barrier layer on the GaN buffer layer; sequentially depositing a lower electrode metal layer, preparing a dielectric insulating layer, and depositing an upper electrode metal layer on the AlGaN barrier layer to form a MIM capacitor element; and preparing a thin film resistor element on the AlGaN barrier layer. A dielectric isolation layer is deposited on the surface of the device, and vias are etched in the dielectric isolation layer; a planar spiral inductor element is fabricated on the surface of the dielectric isolation layer; A metal interconnect layer is deposited to achieve electrical connection between the thin-film resistor element, the MIM capacitor element, and the planar spiral inductor element.

9. The method for fabricating GaN integrated passive devices based on SiC substrates according to claim 8, characterized in that, The preparation of the dielectric insulating layer includes: sequentially depositing a first alumina layer, a silicon nitride layer, and a second alumina layer using an atomic layer deposition process.

10. A radio frequency front-end module, characterized in that, Including GaN integrated passive devices based on SiC substrates as described in any one of claims 1 to 7.

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