Wafer alignment method, wafer bonding method, and wafer bonding apparatus

Abstract

This invention provides a wafer alignment method, a wafer bonding method, and a wafer bonding apparatus. The method includes: acquiring a first original image of a first wafer including a first flat edge as a positioning feature, and extracting geometric features of the first flat edge based on this image; acquiring a second original image of the first wafer including a first arc edge, and extracting a first alignment point located on the first arc edge based on this image; acquiring a third original image of a second wafer including a second flat edge as a positioning feature, and extracting geometric features of the second flat edge based on this image; acquiring a fourth original image of the second wafer including a second arc edge, and extracting a second alignment point located on the second arc edge based on this image; and aligning the second wafer with the first wafer according to the geometric features of the first and second flat edges and the first and second alignment points. This invention enables the alignment and bonding of multiple types of wafers using a single wafer bonding apparatus.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing, and particularly relates to a wafer alignment method, a wafer bonding method, a wafer bonding apparatus, a computer-readable storage medium, and a computer program product. Background Technology

[0002] In the semiconductor manufacturing process, wafers include notched wafers and flat-edge wafers. Figure 1 This is a layout diagram of the image acquisition equipment in existing wafer bonding equipment suitable for notched wafers. For example... Figure 1 As shown, in a wafer bonding device suitable for notched wafers, the mounting positions of the two image acquisition units, Cam1 and Cam2, are at an arc angle of 90° on the circumference of the wafer. Figure 2 This is a layout diagram of the image acquisition equipment in existing wafer bonding equipment suitable for flat-edge wafers. For example... Figure 2 As shown, in wafer bonding equipment suitable for flat-edge wafers, the two image acquisition units, Cam1 and Cam2, are typically mounted at the two ends of the flat edge of the wafer. Therefore, in the prior art, a single wafer bonding unit is only suitable for one type of wafer (notched wafer or flat-edge wafer). During manufacturing, when switching between flat-edge and notched wafer products, either the mounting positions of the image acquisition units need to be disassembled and changed, or a second set of image acquisition units for alignment needs to be added to the wafer bonding equipment. Disassembling and changing the mounting positions of the image acquisition units requires recalibrating the optical path of the image acquisition units, which is time-consuming and introduces assembly errors, affecting alignment stability. Adding a second set of image acquisition units increases the overall material cost and occupies internal installation space.

[0003] Therefore, there is an urgent need for a technical solution that allows the same wafer bonding equipment to be used for the alignment and bonding of both flat-edge and notched wafers. Summary of the Invention

[0004] This invention provides a wafer alignment method, a wafer bonding method, a wafer bonding apparatus, a computer-readable storage medium, and a computer program product, which can align and bond multiple types of wafers (such as flat-edge wafers and notched wafers) using a single wafer bonding apparatus.

[0005] In a first aspect, embodiments of the present invention provide a wafer alignment method. The wafer has positioning features. The wafer alignment method includes: Acquire a first original image of a first wafer containing positioning features, wherein the first wafer has a first flat edge as the positioning feature; Based on the first original image, extract the geometric features of the first flat edge; Obtain a second original image of the first wafer, including the first arc edge; Based on the second original image, extract the first alignment point located on the first arc edge and outside the first flat edge; A third original image of the second wafer containing positioning features is obtained, wherein the second wafer has a second flat edge as the positioning feature; Based on the third original image, extract the geometric features of the second flat edge; Obtain a fourth original image of the second wafer, including the second arc edge; Based on the fourth original image, extract the second alignment point located on the second arc edge and outside the second flat edge; The second wafer is aligned with the first wafer based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point, and the second alignment point.

[0006] In some embodiments of the present invention, the first alignment point is the intersection of the first arc edge and the first predetermined axis of the second original image, and the second alignment point is the intersection of the second arc edge and the second predetermined axis of the fourth original image.

[0007] In some embodiments of the present invention, the first predetermined axis is the central axis in the width direction of the second original image in the camera coordinate system where the image acquisition device for acquiring the second original image is located; the second predetermined axis is the central axis in the width direction of the fourth original image in the camera coordinate system where the image acquisition device for acquiring the fourth original image is located.

[0008] In some embodiments of the present invention, the geometric features of the first flat edge include a first starting point of the first flat edge and a first preset point on the first flat edge; the geometric features of the second flat edge include a second starting point of the second flat edge and a second preset point on the second flat edge.

[0009] In some embodiments of the present invention, aligning the second wafer with the first wafer based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point, and the second alignment point includes: Based on the first inclination angle of the first flat side determined by the first starting point and the first preset point, and the second inclination angle of the second flat side determined by the second starting point and the second preset point, the angle difference between the first inclination angle and the second inclination angle is obtained. Based on the angle difference, drive the second wafer to rotate until the angle difference meets a preset angle threshold; The difference between the first alignment point and the second alignment point in the first direction after the angle difference satisfies the preset angle threshold is used as the first offset of the second wafer in the first direction; Based on the first offset, the second wafer is driven to move in the first direction until the first offset satisfies a preset first offset threshold. The distance between the first flat edge and the second flat edge in the second direction after the first offset satisfies the preset first offset threshold is taken as the second offset of the second wafer in the second direction, wherein the second direction is perpendicular to the first direction; Based on the second offset, the second wafer is driven to move in the second direction until the second offset meets a preset second offset threshold, so as to align the second wafer with the first wafer.

[0010] In some embodiments of the present invention, the distance between the first flat edge and the second flat edge in the second direction is obtained based on the vertical distance between the first line segment and the second line segment, and the angle between the first flat edge and / or the second flat edge and the first direction after the first offset satisfies a preset first offset threshold.

[0011] In some embodiments of the present invention, the distance between the first flat edge and the second flat edge in the second direction is obtained based on the distance between the second starting point and the first line segment in the second direction.

[0012] In some embodiments of the present invention, the wafer alignment method further includes: A fifth original image of a third wafer containing positioning features is obtained, wherein the third wafer has a first notch as the positioning feature; Based on the fifth original image, extract the first gap image; The first wafer reference vector of the third wafer is obtained by performing the wafer reference vector determination process; A sixth original image of a fourth wafer containing positioning features is obtained, wherein the fourth wafer has a second notch as the positioning feature; Based on the sixth original image, extract the second gap image; The second wafer reference vector of the fourth wafer is obtained by performing the wafer reference vector determination process; Align the second wafer reference vector with the first wafer reference vector to align the fourth wafer with the third wafer. The wafer reference vector determination process includes: obtaining the geometric feature point of the notch as the first reference point; obtaining the second reference point at a predetermined position on the arc edge of one side of the wafer, so as to determine the vector pointing from one of the first reference point and the second reference point to the other as the wafer reference vector. The relative positional relationship between the first reference point and the second reference point of the third wafer is the same as that between the first reference point and the second reference point of the fourth wafer.

[0013] In some embodiments of the present invention, before obtaining the geometric feature points of the notch as the first reference point, the wafer reference vector determination process further includes: Based on the tilt angle of the notch determined from the notch image, the wafer is driven so that the notch is aligned with a standard orientation; The step of obtaining the geometric feature points of the notch as the first reference point includes: Obtain the geometric feature point of the notch aligned with the standard direction as the first reference point.

[0014] In some embodiments of the present invention, the step of extracting the first gap image based on the fifth original image includes: performing image adaptive enhancement on the fifth original image and delineating the region of interest where the first gap is located to obtain a first processed image; performing adaptive threshold segmentation on the first processed image to extract the first gap image; The step of extracting the second gap image based on the sixth original image includes: performing adaptive image enhancement on the sixth original image and delineating the region of interest where the second gap is located to obtain a second processed image; performing adaptive threshold segmentation on the second processed image to extract the second gap image.

[0015] In some embodiments of the present invention, driving the wafer to align the notch with a standard orientation based on the tilt angle of the notch determined from the notch image includes: Based on the gap image, determine the two target endpoints of the gap; Calculate the tilt angle of the gap based on the two target endpoints; Based on the tilt angle, the wafer is driven to rotate so that the notch is aligned with the standard direction.

[0016] In some embodiments of the present invention, the geometric feature point of the notch is the center of the largest inscribed circle of the notch. Alternatively, the geometric feature point of the notch is the center of the inscribed circle of the notch that passes through the vertex of the notch. Alternatively, the geometric feature point of the notch is the midpoint of the line connecting the two endpoints of the notch. Alternatively, the geometric feature points of the gap are the positions at which the distance between them and two specific straight lines of the gap image is a first preset distance and a second preset distance, respectively. The two specific straight lines are located on both sides of the vertex of the gap, and for each of the two specific straight lines, the specific straight line is the line that can pass through the target contour points on that side of the gap's contour with the largest number of points on the corresponding side of the gap's vertex.

[0017] In some embodiments of the present invention, the second reference point of the third wafer is the intersection of the arc edge of the third wafer and the predetermined axis of the fifth original image, and the second reference point of the fourth wafer is the intersection of the arc edge of the fourth wafer and the predetermined axis of the sixth original image.

[0018] In some embodiments of the present invention, the predetermined axis of the fifth original image is the central axis of the fifth original image in the width direction, and the predetermined axis of the sixth original image is the central axis of the sixth original image in the width direction.

[0019] In some embodiments of the present invention, the wafer alignment method is applied to a wafer bonding apparatus, the wafer bonding apparatus comprising: The first stage is used to hold the wafer to be bonded during the wafer bonding process; A second stage is used to hold another wafer to be bonded during the wafer bonding process, wherein the wafer to be bonded has positioning features; A first raw image acquisition unit is used to acquire a raw image of a first region of interest of the wafer to be bonded, held on the second stage. A second raw image acquisition device is used to acquire a raw image of the wafer to be bonded, which includes a second region of interest, held on the second stage. The angle between the arc of the first raw image acquisition device and the second raw image acquisition device on the wafer to be bonded is a preset angle, so that the raw image of the first region of interest of the wafer acquired by the first raw image acquisition device includes the positioning feature, and the raw image of the second region of interest includes a segment of the arc edge of the wafer. The wafer alignment method includes: The first wafer is placed on the second stage, wherein the first wafer has the first flat edge as the positioning feature; The first original image, including the first flat edge, is acquired by the first original image acquisition device and held on the second stage. Based on the first original image, extract the geometric features of the first flat edge; The second raw image, including the first arc edge, is acquired by the second raw image acquisition device on the first wafer held on the second stage; Based on the second original image, extract the first alignment point located on the first arc edge; The first wafer is transferred to the first stage, and the second wafer is placed on the second stage, wherein the second wafer includes a second flat edge as the positioning feature; The third raw image, including the second flat edge, is acquired by the first raw image acquisition device on the second wafer held on the second stage; Based on the third original image, extract the geometric features of the second flat edge; A fourth raw image, including the second arc edge, is acquired by the second raw image acquisition unit on the second stage of the second wafer. Based on the fourth original image, extract the second alignment point located on the edge of the second arc; Based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point, and the second alignment point, the first stage and the second stage are driven to move relative to each other to align the second wafer with the first wafer.

[0020] Secondly, embodiments of the present invention provide a wafer bonding method, comprising: aligning the second wafer and the first wafer using any of the above-described wafer alignment methods; and bonding the first wafer and the second wafer.

[0021] In some embodiments of the present invention, the wafer bonding method further includes: A third wafer is placed on a second stage, wherein the third wafer has a first notch as the positioning feature; A fifth raw image of the third wafer held on the second stage is acquired by the first raw image acquisition device to obtain a first notch image; Based on the tilt angle determined by the first notch image, the second stage holding the third wafer is driven so that the first notch is aligned with a standard orientation; With the first notch aligned with the standard direction, the geometric feature points of the first notch are obtained as the first reference point of the third wafer based on the image of the first notch. For the third wafer held on the second stage, the second raw image acquisition device acquires a sixth raw image of the third wafer including the third arc edge to obtain a second reference point of the third wafer and determine a first wafer reference vector of the third wafer, wherein the first wafer reference vector is pointed to by one of the first reference point and the second reference point of the third wafer. The third wafer is transferred to the first stage, and the fourth wafer is placed on the second stage, wherein the fourth wafer has a second notch as the positioning feature; A seventh raw image of the fourth wafer held on the second stage is acquired by the first raw image acquisition device to obtain a second notch image; Based on the tilt angle determined by the second notch image, the second stage holding the fourth wafer is driven so that the second notch is aligned with the standard orientation; With the second notch aligned with the standard direction, the geometric feature points of the second notch are obtained as the first reference point of the fourth wafer based on the image of the second notch; For the fourth wafer held on the second stage, the second raw image acquisition device acquires an eighth raw image of the fourth wafer including the fourth arc edge to obtain the second reference point of the fourth wafer and determine the second wafer reference vector of the fourth wafer, wherein the second wafer reference vector is pointed to by one of the first reference point and the second reference point of the fourth wafer. By driving the first stage and the second stage to move relative to each other, the second wafer reference vector of the fourth wafer is aligned with the first wafer reference vector of the third wafer, so as to align the fourth wafer held on the second stage with the third wafer held on the first stage. The third wafer and the fourth wafer are bonded together.

[0022] Thirdly, embodiments of the present invention provide a wafer bonding apparatus, comprising: The first stage is used to hold the wafer to be bonded during the wafer bonding process; A second stage is used to hold another wafer to be bonded during the wafer bonding process, wherein the wafer to be bonded has positioning features; A first raw image acquisition unit is used to acquire a raw image of a first region of interest of the wafer to be bonded, held on the second stage. A second raw image acquisition device is used to acquire a raw image of the wafer to be bonded, which includes a second region of interest, held on the second stage. The angle between the arc of the first raw image acquisition device and the second raw image acquisition device on the wafer to be bonded is a preset angle, so that the raw image of the first region of interest of the wafer acquired by the first raw image acquisition device includes the positioning feature, and the raw image of the second region of interest includes a segment of the arc edge of the wafer. A processor and a memory storing computer program instructions, wherein the processor reads and executes the computer program instructions to implement the wafer alignment method described in any of the preceding claims.

[0023] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement the wafer alignment method described in any one of the preceding claims.

[0024] Fifthly, embodiments of the present invention provide a computer program product, including a computer program that, when executed by a processor, implements the wafer alignment method described in any of the above embodiments.

[0025] The wafer alignment method, wafer bonding method, wafer bonding apparatus, computer-readable storage medium, and computer program product of this invention align the second wafer and the first wafer using the geometric features of the first flat edge of the first wafer, a first alignment point located on the first arc edge of the first wafer, the geometric features of the second flat edge of the second wafer, and a second alignment point located on the second arc edge of the second wafer. This achieves alignment of flat-edge wafers in a wafer bonding apparatus suitable for notched wafers. Since the above embodiments utilize not only the geometric features of the flat edge of the wafer but also alignment points on the wafer arc, the alignment accuracy of flat-edge wafers of the same size with different flat edge dimensions can be improved. Because the position of the flat edge of the flat-edge wafer relative to the lateral arc is substantially consistent with the position of the notch relative to the lateral arc of the notched wafer, this wafer alignment method can be applied to wafer bonding apparatus suitable for notched wafers, i.e., a single bonding apparatus can be used to align multiple types of wafers. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a layout diagram of the image acquisition device in a wafer bonding device applicable to notched wafers in the prior art; Figure 2 This is a layout diagram of the image acquisition device in a wafer bonding device suitable for flat-edge wafers in the prior art; Figure 3 This is a schematic flowchart of the wafer alignment method provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the wafer bonding equipment provided in an embodiment of the present invention; Figure 5 This is a schematic flowchart of a wafer alignment method provided in other embodiments of the present invention; Figure 6 yes Figure 5 The diagram shows the application of the wafer alignment method in a bonding device. Figure 7 yes Figure 3 A schematic diagram of step S90 in the wafer alignment method shown; Figure 8 This is a schematic flowchart of a wafer alignment method provided in other embodiments of the present invention; Figure 9 yes Figure 8 A schematic diagram of step S120 in the wafer alignment method shown; Figure 10 yes Figure 8 A schematic diagram of step S150 in the wafer alignment method shown. Figure 11 yes Figure 8 Another schematic diagram of step S120 in the wafer alignment method shown; Figure 12 yes Figure 8 Another schematic diagram of step S150 in the wafer alignment method shown; Figure 13 yes Figure 8 A schematic flowchart of step S110 in the wafer alignment method shown; Figure 14 yes Figure 8 A schematic diagram of step S140 in the wafer alignment method shown; Figure 15 yes Figure 11 A schematic diagram of step S1203 in the wafer alignment method shown; Figure 16 yes Figure 12 A schematic diagram of step S1503 in the wafer alignment method shown. Figure 17 This is a flowchart of the wafer bonding method provided in the embodiments of the present invention; Figure 18 This is a flowchart of a wafer bonding method provided in other embodiments of the present invention; Figure 19 A schematic diagram illustrating a wafer alignment method provided for other embodiments of the present invention; Figure 20 A flowchart of a wafer bonding method provided in another embodiment of the present invention. Detailed Implementation

[0028] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely intended to explain the present invention and not to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present invention by illustrating examples of the invention.

[0029] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0030] In the existing technology, a single wafer bonding equipment is only suitable for one type of wafer (notched wafer or flat-edge wafer).

[0031] Furthermore, in semiconductor processing, wafers of different sizes can use different physical positioning references. For example, wafers smaller than 6 inches can use a flat edge as the physical positioning reference, while 8-inch and 12-inch wafers can use a notch. Wafers of the same size may have different physical positioning references. For example, the flat edge of a 6-inch wafer has a dimension of 57.50 mm ± 2.5 mm. When two 6-inch wafers have different flat edges, aligning the two wafers using only points on the flat edges results in low alignment accuracy.

[0032] To address the problems of the prior art, embodiments of the present invention provide a wafer alignment method, a wafer bonding method, a wafer bonding apparatus, a computer-readable storage medium, and a computer program product.

[0033] The following describes a wafer alignment method provided by an embodiment of the present invention.

[0034] Figure 3 This is a schematic flowchart of a wafer alignment method provided in an embodiment of the present invention. The wafer alignment method provided in this embodiment is applicable to wafers with positioning features. For example... Figure 3 As shown, the wafer alignment method includes the following steps: S10: Obtain a first original image of a first wafer containing positioning features, wherein the first wafer has a first flat edge as the positioning feature; S20: Based on the first original image, extract the geometric features of the first flat edge; S30: Obtain a second original image of the first wafer containing the first arc edge; S40: Based on the second original image, extract the first alignment point located on the first arc edge and outside the first flat edge; S50: Obtain a third original image of the second wafer containing positioning features, wherein the second wafer has a second flat edge as the positioning feature; S60: Based on the third original image, extract the geometric features of the second flat edge; S70: Obtain a fourth original image of the second wafer containing the second arc edge; S80: Based on the fourth original image, extract the second alignment point located on the second arc edge and outside the second flat edge; S90: Align the second wafer with the first wafer based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point, and the second alignment point.

[0035] The wafer alignment method of this invention aligns the second wafer and the first wafer using the geometric features of the first flat edge of the first wafer, a first alignment point located on the first arc edge of the first wafer, the geometric features of the second flat edge of the second wafer, and a second alignment point located on the second arc edge of the second wafer, thus achieving the alignment of flat-edge wafers. Since the above embodiments not only utilize the geometric features of the flat edge of the wafer but also the alignment point on the arc edge, the alignment accuracy of flat-edge wafers of the same size with different flat edge dimensions can be improved. Because the position of the flat edge of the flat-edge wafer relative to the lateral arc edge is substantially consistent with the position of the notch relative to the lateral arc edge of the notched wafer, this wafer alignment method can be applied to wafer bonding equipment suitable for notched wafers, allowing the same bonding equipment to align multiple types of wafers. Therefore, when switching between flat-edge and notched wafers, no additional modifications to the wafer bonding equipment are required, such as disassembling and changing the installation position of the image acquisition unit, or adding a second set of image acquisition units for alignment.

[0036] The following describes specific embodiments of the wafer alignment method according to the present invention in conjunction with wafer bonding equipment. Figure 4 This is a schematic diagram of the structure of a wafer bonding device provided in an embodiment of the present invention. Figure 4 As shown, the wafer bonding apparatus may include a first stage 10, a second stage 20, a first raw image acquisition unit 30, and a second raw image acquisition unit 40.

[0037] The first stage 10 is used to hold the wafer to be bonded (such as the first wafer 50 including the first flat edge 51 and the first rounded edge 52) during the wafer bonding process.

[0038] The second stage 20 is used to hold another wafer to be bonded (such as a second wafer 60 including a second flat edge 61 and a second rounded edge 62) during the wafer bonding process, wherein the wafer to be bonded has positioning features. The wafer bonding process refers to the process of bonding the wafer to be bonded to the other wafer after aligning the wafer to be bonded (such as the first wafer 50) and the other wafer to be bonded (such as the second wafer 60) in the wafer bonding method.

[0039] The first raw image acquisition unit 30 is used to acquire raw images of the first region of interest of the wafer to be bonded, held on the second stage 20.

[0040] The second raw image acquisition unit 40 is used to acquire a raw image of the wafer to be bonded, which includes a second region of interest, held on the second stage 20. The mounting positions of the first raw image acquisition unit 30 and the second raw image acquisition unit 40 are such that the arc angle between their positions on the circumference of the wafer to be bonded is a preset angle, so that the raw image of the first region of interest of the wafer acquired by the first raw image acquisition unit includes the positioning feature, and the raw image of the second region of interest includes a segment of the arc edge of the wafer.

[0041] For a wafer with a notch as a positioning feature, the first region of interest is the image region where the notch is located, and the second region of interest is the image region where a point on a segment of the wafer's arc edge is located, which is outside the notch.

[0042] For a wafer with a flat edge as a positioning feature, the first region of interest is the image region where the flat edge is located, and the second region of interest is the image region where a point on a segment of the wafer's arc edge is located, which is outside the flat edge.

[0043] According to an embodiment of the present invention, for ease of explanation, the holding plane of the second stage 20 used to hold the wafer can be used as a reference plane, and the center point of the reference plane can be used as the origin to establish a reference coordinate system. This reference coordinate system can be a Cartesian coordinate system. In a Cartesian coordinate system, the X-axis and Y-axis are along the horizontal and vertical directions, respectively, and the Z-axis is along a direction perpendicular to the reference plane.

[0044] In some embodiments of the present invention, the preset angle is 90°. For example, the first raw image acquisition unit 30 is arranged on the Y-axis of the reference coordinate system, and the second raw image acquisition unit 40 is arranged on the X-axis of the reference coordinate system.

[0045] In some embodiments of the present invention, the first platform 10 is capable of at least one of X-axis motion, Y-axis motion, Z-axis motion, and rotation about the Z-axis, while the remaining dimensions of motion are achieved by the second platform 20. That is, the four dimensions of motion—X-axis motion, Y-axis motion, Z-axis motion, and rotation about the Z-axis—can be allocated to the first platform 10 and the second platform 20 as needed.

[0046] In some embodiments of the present invention, such as Figure 4 As shown, the first platform 10 can achieve Z-axis movement, and the second platform 20 can achieve X-axis and Y-axis movement as well as rotation around the Z-axis.

[0047] In other embodiments of the present invention, the first platform 10 is capable of X-axis and Y-axis movement and rotation about the Z-axis, and the second platform 20 is capable of Z-axis movement.

[0048] In other embodiments of the present invention, the first platform 10 is capable of X-axis movement, and the second platform 20 is capable of Y-axis movement, Z-axis movement, and rotation about the Z-axis.

[0049] In some embodiments of the present invention, the first stage 10 and the second stage 20 are chucks. Exemplarily, the first stage 10 and the second stage 20 can hold the wafer by adsorption.

[0050] In some embodiments of the present invention, such as Figure 4 As shown, the control device (such as a driver) of the first stage 10, the control device (such as a driver) of the second stage 20, the first raw image acquisition unit 30, the second raw image acquisition unit 40, the processor 70, and the memory 80 are connected to each other, for example, via a bus 90.

[0051] Bus 90 includes hardware, software, or both, that couples components of a wafer bonding device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association (VLB) bus, or other suitable buses, or a combination of two or more of these. Where appropriate, bus 90 may include one or more buses. Although specific buses are described and illustrated in the embodiments of the present invention, the present invention is contemplated by any suitable bus or interconnect.

[0052] Figure 5 This is a schematic flowchart of a wafer alignment method provided in other embodiments of the present invention. Figure 6 yes Figure 5The diagram illustrates the application of the wafer alignment method in a wafer bonding apparatus. Figures 4 to 6 The wafer alignment method applied to the wafer bonding equipment includes the following steps: S1000: Place the first wafer 50 on the second stage 20, wherein the first wafer 50 has the first flat edge 51 as the positioning feature, such as... Figure 6 As shown in state A; S1100: The first raw image Pic1, including the first flat edge 51, of the first wafer 50 held on the second stage 20 is acquired by the first raw image acquisition unit 30. Figure 6 As shown in state B; S1200: Based on the first original image Pic1, extract the geometric features of the first flat edge 51, such as... Figure 6 As shown in state C; S1300: The second raw image Pic2, including the first arc edge 52, of the first wafer 50 held on the second stage 20 is acquired by the second raw image acquisition unit 40, as shown. Figure 6 As shown in state D; S1400: Based on the second original image Pic2, extract the first alignment point P1 located on the first arc edge 52, as follows: Figure 6 As shown in state E; S1500: Transfer the first wafer 50 to the first stage 10, and place the second wafer 60 on the second stage 20, wherein the second wafer 60 includes a second flat edge 61 as the positioning feature, such as... Figure 6 As shown in state F; S1600: The third raw image Pic3, including the second flat edge 61, of the second wafer 60 held on the second stage 20, is acquired by the first raw image acquisition unit 30. Figure 6 As shown in state G; S1700: Based on the third original image Pic3, extract the geometric features of the second flat edge 61, such as... Figure 6 As shown in state H; S1800: The second raw image acquisition unit 40 acquires a fourth raw image Pic4 of the second wafer 60 held on the second stage 20, including the second arc edge 62. Figure 6 As shown in state I; S1900: Based on the fourth original image Pic4, extract the second alignment point P2 located on the second arc edge 62, as follows: Figure 6 As shown in state J; S2000: Based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point P1, and the second alignment point P2, drive the first stage 10 and the second stage 20 to move relative to each other to align the second wafer 60 with the first wafer 50, such as... Figure 6 The states K, L, M, and N are shown in the diagram.

[0053] The wafer alignment method of this invention aligns the second wafer and the first wafer using the geometric features of the first flat edge of the first wafer, a first alignment point located on the first arc edge of the first wafer, the geometric features of the second flat edge of the second wafer, and a second alignment point located on the second arc edge of the second wafer. This achieves alignment of flat-edge wafers in a wafer bonding apparatus suitable for notched wafers. Since the above embodiment utilizes not only the geometric features of the flat edge of the wafer but also the alignment point on the wafer arc, it can improve the alignment accuracy of flat-edge wafers of the same size with different flat edge dimensions. Because the position of the flat edge of the flat-edge wafer relative to the lateral arc is substantially consistent with the position of the notch relative to the lateral arc of the notched wafer, this wafer alignment method can be applied to wafer bonding apparatus suitable for notched wafers, i.e., using one bonding apparatus to align multiple types of wafers.

[0054] In some embodiments of the present invention, the geometric features of the first flat edge are any two points on the first flat edge, and the geometric features of the second flat edge are any two points on the second flat edge. That is, the geometric features of the flat edge are any two points on the flat edge that can determine the flat edge.

[0055] It should be noted that the relative positional relationship between the first alignment point and the second alignment point of the first wafer is essentially the same as that between the first alignment point and the second alignment point of the second wafer. Typically, during wafer loading, the relative positional deviation between the first and second wafers on the horizontal plane is small, and the misalignment of the arc edge included in the image acquired by the second raw image acquisition device for the arc edge is small. Therefore, the relative positional deviation of the physical contour points on the corresponding wafers, mapped from the intersection points of the arc edges of each wafer with their corresponding axes, on the horizontal plane can be ignored. Therefore, it can be considered that the relative position between the first alignment point and the second alignment point of the first wafer is consistent with the relative position between the first alignment point and the second alignment point of the second wafer.

[0056] In some embodiments of the present invention, the first alignment point is the intersection of the first arc edge and the first predetermined axis of the second original image, and the second alignment point is the intersection of the second arc edge and the second predetermined axis of the fourth original image.

[0057] In some embodiments of the present invention, such as Figure 6As shown in state E, the first predetermined axis is the central axis along the width direction of the second original image in the camera coordinate system where the image acquisition device that acquired the second original image is located; as shown in state E. Figure 6 As shown in state J, the second predetermined axis is the central axis in the width direction of the fourth original image in the camera coordinate system where the image acquisition device that acquired the fourth original image is located.

[0058] In the above embodiments, the image at the central axis of the width direction of the original image is relatively clear. Therefore, using the intersection of the central axis of the width direction of the original image and the arc edge can further improve the calibration accuracy.

[0059] In some embodiments of the present invention, the first predetermined axis is the axis located at 1 / 3 of the width direction of the second original image in the camera coordinate system where the image acquisition device for acquiring the second original image is located; the second predetermined axis is the axis located at 1 / 3 of the width direction of the fourth original image in the camera coordinate system where the image acquisition device for acquiring the fourth original image is located.

[0060] In some embodiments of the present invention, the first predetermined axis is the axis located at 1 / 4 of the width direction of the second original image in the camera coordinate system where the image acquisition device for acquiring the second original image is located; the second predetermined axis is the axis located at 1 / 4 of the width direction of the fourth original image in the camera coordinate system where the image acquisition device for acquiring the fourth original image is located.

[0061] In some embodiments of the present invention, the geometric features of the first flat edge include a first starting point of the first flat edge and a first preset point on the first flat edge; the geometric features of the second flat edge include a second starting point of the second flat edge and a second preset point on the second flat edge.

[0062] Preferably, the first preset point is the intersection of the edge of the edge-shaded region and the first flat edge, and the second preset point is the intersection of the edge of the edge-shaded region and the second flat edge. For example, see [link to example]. Figure 6 In state C, there is an edge shadow area in the upper right corner of the image. The intersection of this edge shadow area and the first flat edge 51 can be used as the first preset point; see [link to relevant documentation]. Figure 6In state H of the image, there is an edge shadow region in the upper right corner. The intersection of this edge shadow region and the second flat edge 61 can be used as the second preset point. It can be understood that the edge shadow region belongs to the noise in the image. In other words, because the pixel values ​​of the edge shadow region are relatively close to the pixel values ​​of the flat edge, it is easy to cause misidentification of the flat edge contour. By selecting the intersection of the edge shadow region and the flat edge as the aforementioned preset point, the boundary position affected by shadow noise can be marked, thereby accurately determining the preset point located on the flat edge.

[0063] In some embodiments of the present invention, such as Figure 6 As shown in state C, the geometric features of the first flat edge 51 include the first starting point s1 of the first flat edge 51 and the first preset point i1 on the first flat edge 51; as Figure 6 As shown in state H, the geometric features of the second flat edge 61 include the second starting point s2 of the second flat edge 61 and the second preset point i2 on the second flat edge 61. For example, the length of the first line segment s1i1 determined by the first starting point s1 and the first preset point i1 can be equal to the length of the second line segment s2i2 determined by the second starting point s2 and the second preset point i2.

[0064] Figure 7 yes Figure 3 The diagram shows a flow chart of step S90 in the wafer alignment method. In some embodiments of the present invention, such as... Figure 7 As shown, step S90: Aligning the second wafer with the first wafer based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point, and the second alignment point, includes: S901: Based on the first inclination angle of the first flat side determined by the first starting point and the first preset point and the second inclination angle of the second flat side determined by the second starting point and the second preset point, obtain the angle difference between the first inclination angle and the second inclination angle. S902: Drive the second wafer to rotate according to the angle difference until the angle difference meets the preset angle threshold; S903: Obtain the difference between the first alignment point and the second alignment point in the first direction after the angle difference satisfies the preset angle threshold, and use it as the first offset of the second wafer in the first direction; S904: Based on the first offset, drive the second wafer to move in the first direction until the first offset meets a preset first offset threshold; S905: Obtain the distance between the first flat edge and the second flat edge in the second direction after the first offset satisfies the preset first offset threshold, and use the distance as the second offset of the second wafer in the second direction, wherein the second direction is perpendicular to the first direction; S906: Based on the second offset, drive the second wafer to move in the second direction until the second offset meets a preset second offset threshold, so as to align the second wafer with the first wafer.

[0065] In the above embodiments of the present invention, the first flat edge and the second flat edge are adjusted to be substantially parallel according to the angle difference between the second flat edge and the first flat edge, and then the offset of the two wafers in the first direction and the second direction are adjusted sequentially, thereby improving the accuracy of wafer alignment.

[0066] In the above embodiments, the first direction can be the direction of the X-axis in the Cartesian coordinate system mentioned above, and the second direction can be the direction of the Y-axis.

[0067] In the above embodiment, step S902: driving the second wafer to rotate until the angle difference meets the preset angle threshold includes: driving the second wafer to rotate according to the angle deviation, and then continuing to acquire images to obtain a new angle deviation. If the new angle deviation meets the angle threshold, the second wafer is no longer rotated, and it can be assumed that the flat edge of the second wafer is parallel to the flat edge of the first wafer. If the new angle deviation does not meet the preset angle threshold, the second wafer is driven to rotate and images are acquired to obtain a new angle deviation until the acquired angle difference meets the preset angle threshold. In the above embodiment, step S904: driving the second wafer to move in the first direction according to the first offset until the first offset meets the preset first offset threshold includes: driving the second wafer to move in the first direction according to the first offset, and then continuing to perform image acquisition to obtain a new first offset; if the new first offset meets the preset first offset threshold, then the second wafer is no longer driven to move in the first direction; if the new first offset does not meet the preset first offset threshold, then the second wafer is continued to move in the first direction and image acquisition is performed to obtain a new first offset until the obtained first offset meets the preset first offset threshold.

[0068] In the above embodiment, step S906: driving the second wafer to move in the second direction according to the second offset until the second offset meets the preset second offset threshold includes: driving the second wafer to move in the second direction according to the second offset, and then continuing to perform image acquisition to obtain a new second offset; if the new second offset meets the preset second offset threshold, then the second wafer is no longer driven to move in the second direction; if the new second offset does not meet the preset second offset threshold, then the second wafer is continued to be driven to move in the second direction and image acquisition is performed to obtain a new second offset until the obtained second offset meets the preset second offset threshold.

[0069] It should be noted that, for the stage, there is a tilt angle between the Y-axis of the stage coordinate system and the wafer's flat edge. The displacement that needs to be compensated is the Y-axis displacement in the stage coordinate system. If the wafer is driven directly into position along the stage's Y-axis, it is necessary to calculate the projection components of the actual distance between the two flat edges in the stage's X and Y axes, which is quite complex. In this embodiment of the invention, X-axis alignment is performed first, and the X-axis movement compensates for the X-axis projection offset caused by the tilt angle. After completing X-axis alignment and eliminating the X-axis projection offset, only the Y-axis translation needs to be performed based on the projection distance of the two flat edges in the stage's Y-axis direction. XY component decomposition calculation is no longer required, making the control logic simpler.

[0070] In some embodiments of the present invention, the distance between the first flat edge and the second flat edge in the second direction is obtained based on the vertical distance between the first line segment and the second line segment, and the angle between the first flat edge and / or the second flat edge and the first direction after the first offset satisfies a preset first offset threshold.

[0071] For example, such as Figure 6 As shown in state N, the distance d between the first flat edge 51 and the second flat edge 61 in the second direction Y is obtained based on the vertical distance D between the first line segment s1i1 and the second line segment s2i2 and the angle θ between the first flat edge 51 and the first direction X after the first offset ΔX satisfies the preset first offset threshold Xpre, that is, d=D / cosθ.

[0072] In other embodiments of the present invention, the distance between the first flat edge and the second flat edge in the second direction is obtained based on the distance between the second starting point and the first line segment in the second direction.

[0073] For example, such as Figure 6As shown in state N, the distance d between the first flat edge 51 and the second flat edge 61 in the second direction Y is obtained based on the distance between the second starting point s2 and the first line segment s1i1 in the second direction Y. That is, the distance d between the first flat edge 51 and the second flat edge 61 in the second direction Y is equal to the distance between the second starting point s2 and the first line segment s1i1 in the second direction Y.

[0074] Figure 8 This is a schematic flowchart of a wafer alignment method provided in other embodiments of the present invention. In some embodiments of the present invention, such as... Figure 8 As shown, the wafer alignment method further includes: S100: Obtain a fifth original image of a third wafer containing positioning features, wherein the third wafer has a first notch as the positioning feature; S110: Extract the first gap image based on the fifth original image; S120: Obtain the first wafer reference vector of the third wafer by performing the wafer reference vector determination process; S130: Obtain a sixth original image of the fourth wafer containing positioning features, wherein the fourth wafer has a second notch as the positioning feature; S140: Extract the second notch image based on the sixth original image; S150: By performing the wafer reference vector determination process, the second wafer reference vector of the fourth wafer is obtained; S160: Align the second wafer reference vector with the first wafer reference vector to align the fourth wafer with the third wafer, wherein the wafer reference vector determination process includes: obtaining the geometric feature point of the notch as the first reference point; obtaining the second reference point at a predetermined position on the arc edge of one side of the wafer, so as to determine the vector pointing from one of the first reference point and the second reference point to the other as the wafer reference vector.

[0075] Wherein, the first reference point of the first wafer reference vector corresponds to the first reference point of the second wafer reference vector, and the second reference point of the first wafer reference vector corresponds to the second reference point of the second wafer reference vector. That is, the first wafer reference vector is a vector pointing from the first reference point of the first wafer to the second reference point, and the second wafer reference vector is a vector pointing from the first reference point of the second wafer to the second reference point.

[0076] In this design, the first reference point and the second reference point are located in two separate images. Through coordinate transformation, the first reference point and the second reference point are transformed to the same coordinate system. In this coordinate system, the vector pointing from one of the first reference point to the other is determined as the wafer reference vector. It can be understood that the wafer reference vector is a virtual reference vector, and there is no corresponding actual line segment on the wafer surface. The first reference point is extracted from the notch image of the wafer; the second reference point is a point determined on the arc edge of the wafer. Based on the positions of the two reference points in the same coordinate system, a virtual direction vector representing the wafer orientation can be obtained.

[0077] According to the above embodiments of the present invention, alignment of notched wafers can be achieved not only for parallel wafers but also for notched wafers in the same wafer bonding equipment. This means that when switching between flat-edge and notched wafers, no additional modifications to the wafer bonding equipment are required, such as disassembling and changing the installation position of the image acquisition unit or adding a second set of image acquisition units for alignment.

[0078] Furthermore, the wafer alignment method provided by the above embodiments of the present invention, based on the rigid body geometry two-point alignment principle, aligns the third and fourth wafers by introducing reference vectors of the third and fourth wafers, thereby providing a template-free adaptive alignment scheme that eliminates the need for template creation, storage, and iterative updates. On the other hand, the wafer alignment method provided by the embodiments of the present invention eliminates the susceptible interference of notch vertices and wafer center fitting, thereby improving alignment accuracy, stability, and anti-interference capability.

[0079] Figure 9 yes Figure 8 The diagram shows a flowchart of step S120 of the wafer alignment method. In some embodiments of the present invention, such as... Figure 9 As shown, step S120: obtaining the first wafer reference vector of the third wafer by performing the wafer reference vector determination process, including: S1201: Obtain the geometric feature points of the first notch as the first reference point; S1202: Obtain a second reference point at a predetermined position on the arc edge of one side of the third wafer, so as to determine the vector from one of the first reference point and the second reference point to the other as the first wafer reference vector.

[0080] Figure 10 yes Figure 8 The diagram shows a flowchart of step S150 of the wafer alignment method. In some embodiments of the present invention, such as... Figure 10As shown, step S150: By executing the wafer reference vector determination process, the second wafer reference vector of the fourth wafer is obtained, including: S1501: Obtain the geometric feature points of the second notch as the first reference point; S1502: Obtain a second reference point at a predetermined position on the arc edge of one side of the fourth wafer, and determine the vector pointing from one of the first reference point and the second reference point to the other as the second wafer reference vector.

[0081] In some embodiments of the present invention, before obtaining the geometric feature points of the notch as the first reference point, the wafer reference vector determination process further includes: Based on the tilt angle of the notch determined from the notch image, the wafer is driven so that the notch is aligned with a standard orientation; The step of obtaining the geometric feature points of the notch as the first reference point includes: Obtain the geometric feature point of the notch aligned with the standard direction as the first reference point.

[0082] The standard direction refers to a fixed direction pointing towards the center of the wafer on the wafer plane. For example, the standard direction may be a reference direction specified by the wafer bonding equipment.

[0083] Figure 11 yes Figure 8 Another schematic diagram of step S120 in the wafer alignment method shown. In some embodiments of the present invention, such as... Figure 11 As shown, before obtaining the geometric feature points of the first notch as the first reference point in S1201, step S120, obtaining the first wafer reference vector of the third wafer by performing the wafer reference vector determination process, further includes: Step S1203: Drive the third wafer to align the first notch with the standard direction according to the first tilt angle of the first notch determined by the first notch image; Step S1201: Obtaining the geometric feature points of the first notch as the first reference point includes: S12011: Obtain the geometric feature point of the first notch aligned with the standard direction as the first reference point.

[0084] Figure 12 yes Figure 8 Another schematic diagram of step S150 in the wafer alignment method shown. In some embodiments of the present invention, such as... Figure 12 As shown, before obtaining the geometric feature point of the second notch as the first reference point in S1501, step S150, obtaining the second wafer reference vector of the fourth wafer by performing the wafer reference vector determination process, further includes: Step S1503: Drive the fourth wafer to align the second notch with the standard orientation based on the second tilt angle of the second notch determined by the second notch image; Step S1501: Obtaining the geometric feature points of the second notch as the first reference point includes: S15011: Obtain the geometric feature point of the second notch aligned with the standard direction as the first reference point.

[0085] In the above embodiments of the present invention, before determining the first reference point of the wafer reference vector, the wafer is driven according to the tilt angle so that the notch is aligned with the standard direction, thereby avoiding the problem of asymmetric notch contour extraction caused by wafer tilt and improving the accuracy of wafer alignment.

[0086] Figure 13 yes Figure 8 The diagram shows a flow chart of step S110 in the wafer alignment method. In some embodiments of the present invention, such as... Figure 13 As shown, step S110: Based on the fifth original image, extract the first notch image, including: S1101: Perform adaptive image enhancement on the fifth original image and delineate the region of interest where the first gap is located to obtain the first processed image; S1102: Perform adaptive threshold segmentation on the first processed image to extract the first gap image.

[0087] Figure 14 yes Figure 8 The diagram shows a flow chart of step S140 in the wafer alignment method. In some embodiments of the present invention, such as... Figure 14 As shown, step S140: Based on the sixth original image, extract the second notch image, including: S1401: Perform adaptive image enhancement on the sixth original image and delineate the region of interest where the second gap is located to obtain the second processed image; S1402: Perform adaptive threshold segmentation on the second processed image to extract the second gap image.

[0088] In the above embodiments of the present invention, the fifth original image is an original image of the entire third wafer acquired by the first original image acquisition device, and the sixth original image is an original image of the entire fourth wafer acquired by the first original image acquisition device. Generally, the image color at the location of the notch in the original image is relatively dark.

[0089] In the above embodiments, for example, the region of interest in step S1101 where the first gap is located includes: delineating the region of interest where the first gap is located through blob localization analysis.

[0090] Similarly, for example, the region of interest in step S1401 includes: defining the region of interest in the second gap by means of blob localization analysis.

[0091] In the above embodiments of the present invention, by defining the region of interest where the notch is located, only the effective detection area is retained, reducing invalid calculations and background interference. At the same time, by using adaptive threshold segmentation, the dark area of ​​the wafer notch is stably extracted.

[0092] In some embodiments of the present invention, driving the wafer to align the notch with a standard orientation based on the tilt angle of the notch determined from the notch image includes: Based on the gap image, determine the two target endpoints of the gap; Calculate the tilt angle of the gap based on the two target endpoints; Based on the tilt angle, the wafer is driven to rotate so that the notch is aligned with the standard direction.

[0093] In the above embodiments of the present invention, the tilt angle of the notch is calculated based on two target endpoints, which simplifies the calculation process and improves the accuracy of wafer alignment.

[0094] Figure 15 yes Figure 11 The diagram shows a flow chart of step S1203 in the wafer alignment method. In some embodiments of the present invention, such as... Figure 15 As shown, step S1203: Based on the first tilt angle of the first notch determined from the first notch image, drive the third wafer to align the first notch with a standard direction, including: S12031: Determine the two target endpoints of the first gap based on the first gap image; S12032: Calculate the first tilt angle of the first gap based on the two target endpoints; S12033: Drive the third wafer to rotate according to the first tilt angle so that the first notch is aligned with the standard direction.

[0095] Figure 16 yes Figure 12 The diagram shows a flow chart of step S1503 in the wafer alignment method. In some embodiments of the present invention, such as... Figure 16As shown, step S1503: Based on the second tilt angle of the second notch determined by the second notch image, drive the fourth wafer to align the second notch with the standard direction, including: S15031: Determine the two target endpoints of the second gap based on the second gap image; S15032: Calculate the second tilt angle of the second notch based on the two target endpoints; S15033: Drive the fourth wafer to rotate according to the second tilt angle so that the second notch is aligned with the standard direction.

[0096] In some embodiments of the present invention, determining the two target endpoints of the notch based on the notch image includes: using Canny subpixel edge detection to extract the first contour lines on both sides of the notch in the notch image; expanding the notch in the notch image to obtain the second contour line of the expanded notch; and determining the intersection of the first contour line and the second contour line as the two target endpoints. The step of calculating the tilt angle of the gap based on the two target endpoints includes: calculating at least two parameters among the height difference between the two target endpoints, the width between the two target endpoints, and the distance between the two target endpoints; and calculating the tilt angle of the gap based on the at least two parameters.

[0097] In some embodiments of the present invention, the geometric feature point of the gap is the center of the largest inscribed circle of the gap, or the geometric feature point of the gap is the center of the inscribed circle of the gap passing through the vertex of the gap, or the geometric feature point of the gap is the midpoint of the line connecting the two endpoints of the gap, or the geometric feature point of the gap is a position point at a distance of a first preset distance and a second preset distance from two specific straight lines of the gap image, respectively. The two specific straight lines are located on both sides of the vertex of the gap, and for each of the two specific straight lines, the specific straight line is the line that can pass through the maximum number of target contour points on the contour of the gap on the corresponding side of the vertex of the gap.

[0098] In the above embodiments of the present invention, the first reference point is unique, which lays a good foundation for the determination of the reference vector and can improve the accuracy of wafer alignment.

[0099] In this embodiment of the invention, the geometric feature point of the notch (i.e., the first reference point) is a point that can be uniquely determined for the notch, and the third wafer and the fourth wafer both use the same type of first reference point. For example, the geometric feature point of the third wafer is the center of the largest inscribed circle of the first notch and the geometric feature point of the fourth wafer is the center of the largest inscribed circle of the second notch; the geometric feature point of the third wafer is the center of the inscribed circle of the first notch passing through the vertex of the first notch and the geometric feature point of the fourth wafer is the center of the inscribed circle of the second notch passing through the vertex of the first notch; or the geometric feature point of the third wafer is the midpoint of the line connecting the endpoints on both sides of the first notch and the geometric feature point of the fourth wafer is the midpoint of the line connecting the endpoints on both sides of the second notch.

[0100] In some embodiments, the endpoints on both sides of the notch are not limited to sharp inflection points where the curvature of the contour changes abruptly. When the root of the notch smoothly transitions to the contours on both sides without obvious sharp corners, the endpoints on both sides are the transition boundary points between the notch side contour and the wafer contour. In a specific embodiment, contour points can be traversed from the vertex of the notch along both sides, and the contour tangent angle or curvature can be calculated point by point. A curvature threshold or tangent angle threshold can be preset. If the tangent direction of multiple consecutive contour points traversed after a certain point tends to be consistent with the direction of the wafer body contour, then that point can be regarded as the corresponding side endpoint.

[0101] For example, the vertex of the notch can be understood as the contour point that is most deeply recessed into the wafer. Taking the vertex of the notch as the dividing point, the contour points on the notch contour can be divided into two sets of contour points on either side. For each set of contour points on that side, multiple target contour points can be determined, and then the straight line that passes through the most target contour points can be determined as the specific straight line on that side. There exists a point in the image that satisfies the following condition: the distance between this point and one of the specific straight lines is a first preset distance, and the distance between this point and the other specific straight line is a second preset distance. The first preset distance and the second preset distance can be equal or unequal. It is understood that for the first notch image and the second notch image, each of the two specific straight lines corresponds one-to-one. For ease of description and understanding, the two specific lines in the first gap image are denoted as the first specific line and the second specific line, respectively. The first specific line is located on the first side of the gap (e.g., the left side), and the second specific line is located on the second side of the gap (e.g., the right side). The two specific lines in the second gap image are denoted as the third specific line and the fourth specific line, respectively. The third specific line is located on the first side of the gap, and the fourth specific line is located on the second side of the gap. If the distance between the first reference point of the first gap image and the first specific line is a first preset distance, and the distance between the first reference point and the second specific line is a first preset distance, then the distance between the first reference point of the second gap image and the third specific line is a first preset distance, and the distance between the first reference point and the fourth specific line is a second preset distance.

[0102] In the above embodiments of the present invention, the tilt angle of the notch is calculated based on the two target endpoints determined by the first contour line and the second contour line, which can improve the accuracy of wafer alignment.

[0103] In this embodiment of the invention, when the first reference point is a position point at which the distance between it and two specific straight lines of the gap image is a first preset distance and a second preset distance, respectively, obtaining the geometric feature point of the gap as the first reference point based on the gap image includes: determining two target line segments in the gap image, each of the two target line segments being a partial outline of the gap in the gap image; for each of the two target line segments, determining the straight line that can pass through the most target outline points on the target line segment as the specific straight line corresponding to the target line segment, thereby determining the two specific straight lines in the gap image; and determining the point in the gap image at which the distance between the first specific straight line and the two specific straight lines is the first preset distance and the distance between the second specific straight line and the two specific straight lines is the second preset distance as the geometric feature point of the gap as the first reference point.

[0104] In some embodiments, a contour template can be used to match the gap image. The contour template is a pre-constructed matching template used to characterize the contour shape information of a standard gap. The contour template can be composed of local contour points of the standard gap, such as the shape of a local arc segment composed of partial contour points of the hypotenuse regions on both sides of the gap apex, without carrying the full contour information of the gap; or it can contain the complete contour shape information of the standard gap, while pre-marking the relative positions and contour segments of the two target line segments relative to the overall gap contour within the template, that is, marking the position range of the two target line segments on the standard gap contour on the template. The embodiments of the present invention do not specifically limit the type of contour template, and can flexibly select it according to the actual shape of the gap: when the contour features of the hypotenuses on both sides of the gap are clear and only two hypotenuse line segments need to be identified, a simplified template containing only local contour points of the gap can be selected to reduce the matching computation load; when the gap contour structure is complex and there are many interfering edges around the gap, a complete contour template carrying the complete gap contour and the position markings of the target line segments can be selected, thereby improving the accuracy of matching positioning and target line segment extraction. During matching, the contour template is translated, scaled, and rotated within the gap image for matching operations. The image region in the gap image with the highest shape similarity to the contour template is then found to obtain the matching result. Based on the positional mapping relationship between the contour template and the image in the matching result, two target line segments in the gap image can be obtained. These two target line segments are two contour line segments on the actual contour of the gap.

[0105] In other embodiments, the vertex of the gap can be obtained by traversing all contour points on the gap contour and filtering the position coordinates of each contour point. Using this vertex as a boundary, the gap contour can be divided into two sets of contour regions. For each side of the contour on both sides of the vertex, multiple candidate straight lines can be generated from all contour points on that side. The number of contour points covered by each candidate straight line on that side is counted, and the straight line that covers the most target contour points is selected as the specific straight line corresponding to that side. Thus, two specific straight lines are obtained on both sides of the gap vertex. In this case, the target contour points are all contour points on the corresponding side. In yet another embodiment, the user can manually draw two line segments on the gap contour of the gap image to mark the start and end points of the target line segment. In yet another embodiment, the curvature of each contour point of the gap contour in the gap image can also be calculated. When the curvature of a consecutive preset number of contour points is less than a preset curvature (the smaller the curvature, the closer to a straight line), the line segment formed by these contour points can be used as the target line segment. In some embodiments, after extracting the notch region, the minimum bounding rectangle of the notch region is solved; based on the center point of the minimum bounding rectangle and the minor axis, the measurement station positions and measurement angles of the measuring calipers corresponding to the two hypotenuses of the notch are determined; then, along the direction perpendicular to the minor axis, measurement sampling points are laid out on the left and right hypotenuses of the notch using the measuring calipers, and the laid-out sampling points are used as target contour points; a specific straight line can be obtained by performing line fitting on the target contour points. It can be understood that in this embodiment, the sampling area can be defined based on the measurement range of the measuring calipers, thereby determining the final target line segment.

[0106] It is understandable that for target contour points, either all contour points on the target line segment can be selected, or only a portion of the sampling points can be selected. Sampling points can be obtained by performing sub-pixel edge measurement using calipers, or by sub-pixel edge extraction, contour point selection, threshold boundary sampling, and other equivalent point-finding methods. A specific straight line can be fitted using the target contour points; this specific straight line is the one that passes through the maximum number of target contour points on the target line segment. "Passing through the target contour points on the target line segment" can be understood as the distance between the straight line and the target contour points being less than or equal to a preset distance threshold.

[0107] The above technical solution obtains a specific straight line representing the hypotenuse of the notch and solves for the first reference point based on the preset distance between the two specific straight lines. It does not rely on the tip of the notch and the stability of the obtained first reference point is high.

[0108] In some embodiments of the present invention, the second reference point of the third wafer is the intersection of the arc edge of the third wafer and the predetermined axis of the fifth original image, and the second reference point of the fourth wafer is the intersection of the arc edge of the fourth wafer and the predetermined axis of the sixth original image.

[0109] The above embodiments of the present invention can quickly and accurately obtain the second reference point.

[0110] In some embodiments of the present invention, the predetermined axis of the fifth original image is the central axis of the fifth original image in the width direction, and the predetermined axis of the sixth original image is the central axis of the sixth original image in the width direction.

[0111] Among them, the central axis in the width direction of the fifth original image and the sixth original image is the clearest part of the image field of view, so using this central axis can improve the accuracy of wafer alignment.

[0112] In other embodiments of the present invention, the predetermined axis of the fifth original image is the axis at 1 / 3 position or 1 / 4 position of the width direction of the fifth original image, and the predetermined axis of the sixth original image is the axis at 1 / 3 position or 1 / 4 position of the width direction of the sixth original image.

[0113] Another aspect of the present invention provides a wafer bonding method. Figure 17 This is a flowchart of the wafer bonding method provided in an embodiment of the present invention. Figure 17 As shown, the wafer bonding method includes: S3000: Align the second wafer and the first wafer according to the wafer alignment method provided in any of the above embodiments; S3100: Bond the first wafer and the second wafer.

[0114] Figure 18 This is a flowchart of a wafer bonding method provided in other embodiments of the present invention. In some embodiments of the present invention, such as... Figure 18 As shown, the wafer bonding method further includes: S3200: Place the third wafer on the second stage, wherein the third wafer has a first notch as the positioning feature; S3300: The first raw image acquisition unit acquires a fifth raw image of the third wafer held on the second stage to obtain a first notch image; S3400: Drive the second stage holding the third wafer according to the tilt angle determined by the first notch image, so that the first notch is aligned with the standard direction; S3500: With the first notch aligned with the standard direction, the geometric feature points of the first notch are obtained as the first reference point of the third wafer based on the first notch image; S3600: For the third wafer held on the second stage, the second raw image acquisition unit acquires a sixth raw image of the third wafer including the third arc edge to obtain a second reference point of the third wafer and determine a first wafer reference vector of the third wafer, wherein the first wafer reference vector is pointed to by one of the first reference point and the second reference point of the third wafer. S3700: The third wafer is transferred to the first stage, and the fourth wafer is placed on the second stage, wherein the fourth wafer has a second notch as the positioning feature; S3800: The first raw image acquisition unit acquires a seventh raw image of the fourth wafer held on the second stage to obtain a second notch image; S3900: Drive the second stage holding the fourth wafer according to the tilt angle determined by the second notch image, so that the second notch is aligned with the standard orientation; S4000: With the second notch aligned with the standard direction, the geometric feature points of the second notch are obtained as the first reference point of the fourth wafer based on the image of the second notch. S4100: For the fourth wafer held on the second stage, the second raw image acquisition unit acquires an eighth raw image of the fourth wafer including the fourth arc edge to obtain a second reference point of the fourth wafer and determine a second wafer reference vector of the fourth wafer, wherein the second wafer reference vector is pointed to by one of the first reference point and the second reference point of the fourth wafer. S4200: By driving the first stage and the second stage to move relative to each other, the second wafer reference vector of the fourth wafer is aligned with the first wafer reference vector of the third wafer, so as to align the fourth wafer held on the second stage with the third wafer held on the first stage; S4300: Bond the third wafer and the fourth wafer.

[0115] Figure 19This is a schematic diagram illustrating a wafer alignment method provided for other embodiments of the present invention. In some embodiments of the present invention, a wafer bonding method is used to perform alignment and bonding of two wafers. Bonding relies on a bonding apparatus, which typically includes a first stage for supporting a first wafer; a second stage for supporting a second wafer, wherein the first and second stages are opposite each other during bonding. The first stage has a Z-axis extension drive for applying bonding force, and the second stage has an X / Y / θ drive for adjusting the wafer angle; and two image acquisition units at fixed positions for acquiring two marking patterns on the wafer, respectively. The two marking patterns on the wafer are denoted as the first marking pattern and the second marking pattern, respectively. For a wafer with a notch, the first marking pattern is the notch, and the second marking pattern is the arc segment of the wafer; for a wafer with a flat edge, the first marking pattern is the inflection point of the flat edge (i.e., the intersection of the flat edge and the arc), and the second marking pattern is the arc segment of the wafer. The arc angle of the mounting positions of the two image acquisition units on the circumference of the wafer is 90°.

[0116] The wafer bonding method includes: loading a first wafer onto a second stage at a fixed angle, so that the first and second marker patterns on the first wafer are respectively located within the fields of view of two image acquisition devices; after image acquisition is completed, the first wafer is removed by adsorption through the first stage; then loading a second wafer onto the second stage, so that the first and second marker patterns on the second wafer are respectively located within the fields of view of two image acquisition devices. By comparing the image acquired on the first wafer with the image acquired in real time on the second wafer, the X / Y / θ angles of the second wafer are adjusted until a threshold is met; and then bonding the first and second wafers.

[0117] When bonding two flat-edge wafers, the flat-edge corner + flat edge + single side edge are used as markers. First, adjust the flat edges to be parallel, then adjust the x and y movements respectively through the flat-edge corner points (such as the first and second starting points mentioned above) and the single-side edge tangent points (such as the first and second alignment points mentioned above). Figure 19 As shown. The above method was used to test the alignment of the flat-edge wafer. The test results showed that the flat-edge alignment angle accuracy reached -0.004867554°, the flat-edge alignment X-axis accuracy reached 0.0009837891 mm, and the flat-edge alignment Y-axis accuracy reached -0.002908329 mm.

[0118] When bonding two notched wafers, the notch (specifically, the first reference point mentioned above) and a single side (specifically, the second reference point mentioned above) are used as marker points for adjustment.

[0119] Figure 20 A flowchart illustrating a wafer bonding method according to another embodiment of the present invention. In some embodiments of the present invention, such as... Figure 20The wafer bonding method is applicable to bonding two notched wafers and includes the following steps: S1. Adaptive Image Enhancement and Region of Interest (ROI) Cropping The original wafer images (the fifth and sixth original images in the aforementioned embodiments) are acquired, and edge contrast is maximized by power transformation and grayscale stretching. Morphological closing operations are used to smooth image noise. Blob localization analysis is used to delineate the local region of interest where the wafer notch is located, retaining only the effective detection area and reducing invalid operations and background interference.

[0120] S2, Adaptive Threshold Segmentation and Gap Region Purification Adaptive standard deviation local thresholding is used to obtain an image containing multiple connected components (i.e., multiple segmented regions). Area filtering is used to determine the connected component with the largest area, which includes the chamfered projection region of the notch location. Morphological opening and closing operations are performed on this connected component, and region differencing is performed on the operation results to determine the notch region. Specifically, adaptive standard deviation local thresholding is used to stably extract the dark region of the wafer notch; multiple rounds of circular opening and closing morphological operations are used to filter out interference from tiny dust particles and edge burrs; through region differencing and area filtering, the complete notch target region is accurately separated, and incomplete or excessively small interference regions are removed.

[0121] S3, Subpixel Edge Extraction and Initial Angle Coarse Calculation The purified Notch region is expanded; Canny subpixel edge detection is used to extract high-precision contour lines on both sides of the Notch; the intersection points of the high-precision contour lines and the expanded Notch region (the two target endpoints in the aforementioned embodiment) are determined; based on the intersection points, the horizontal width of the contour and the height difference between the two endpoints are determined, and the initial tilt angle of the Notch is calculated. This is used to reflect the current wafer placement angle.

[0122] S4, Angle Normalization Correction The calculated initial angles are corrected using interval constraints: When the angle is greater than 90°, subtract 180° from the angle. When the angle is less than -90°, add 180° to the angle; constrain all angles to the range of [-90°, 90°] to completely eliminate the problem of reverse jump between 0° and 180° in straight line angles; drive the platform to rotate slightly according to the corrected angle so that the Notch opening maintains a positive standard posture and eliminates the problem of asymmetric profile cutting caused by wafer tilt.

[0123] S5. Steady-state extraction of the center of the inscribed circle within the notch. After the notch orientation correction is completed (i.e., the wafer is aligned with the standard orientation), the notch profile in the standard orientation is smoothed and denoised. The inscribed circle of the notch is extracted by contour morphology transformation. The compliant inscribed circle radius range is screened and abnormal fitting results are eliminated. The center of the inscribed circle area is calculated as the first stable reference point M1.

[0124] S6, Construction of dual-point baseline Using the camera coordinate system with the equipment fixed in place as a reference, the image width axis is defined as a fixed reference axis; the feature of the arc edge (at 90° to the notch) on one side of the wafer is extracted, and the intersection of the arc edge and the fixed image axis is calculated as the second fixed reference point M2; the global reference line of the wafer is uniquely determined by the two points M1 (center of the inscribed circle of the notch) + M2 (intersection of the arc edge), without the need to fit the center of the outer circle of the wafer throughout the process, thus avoiding the systematic error caused by the full circle fitting.

[0125] S7, Wafer Alignment and Lamination The offset and angular deviation of the two reference lines are calculated in real time. By adjusting the X and Y translation and θ rotation of the motion platform, the reference lines of the upper and lower wafers are completely overlapped, and micron-level high-precision alignment and bonding are achieved.

[0126] The method provided in the above embodiments of the present invention achieves: (1) Template-free adaptation: completely abandons matching methods such as shape templates and NCC grayscale templates, eliminating the need for template creation, storage, and iterative updates, adapting to batch production of wafers of the same specifications, and reducing equipment maintenance costs; (2) Strong feature stability: abandons the easily disturbed Notch vertex, and uses the center of the inscribed circle as the core feature point, resisting interference from edge breakage, dust, and uneven edge grayscale, and significantly improving the positioning repeatability accuracy; (3) Angle control closed loop: a unique ±90° interval angle normalization strategy, fundamentally solving the angle problem. (3) Jump problem, combined with the process of first correction and then fitting, to ensure the accuracy of inscribed circle extraction; (4) Simplified error source: cancel the whole circle center fitting step of the wafer, reduce the first-level algorithm error, the algorithm process is simpler and the calculation speed is faster; (5) Mass production accuracy meets the standard: under normal workshop conditions, the alignment repeatability is stable at ≤20μm, which meets the requirements of 8-inch and 12-inch wafer bonding and advanced packaging process; (6) Rigorous and universal logic: based on the rigid body geometry double point line determination principle, the principle is self-consistent and without loopholes, and can be widely transferred to semiconductor equipment such as wafer thinning, cutting and testing.

[0127] Another aspect of the present invention provides a wafer bonding apparatus. The apparatus includes: The first stage is used to hold the wafer to be bonded during the wafer bonding process; A second stage is used to hold another wafer to be bonded during the wafer bonding process, wherein the wafer to be bonded has positioning features; A first raw image acquisition unit is used to acquire a raw image of a first region of interest of the wafer to be bonded, held on the second stage. A second raw image acquisition device is used to acquire a raw image of the wafer to be bonded, which includes a second region of interest, held on the second stage. The angle between the arc of the first raw image acquisition device and the second raw image acquisition device on the wafer to be bonded is a preset angle, so that the raw image of the first region of interest of the wafer acquired by the first raw image acquisition device includes the positioning feature, and the raw image of the second region of interest includes a segment of the arc edge of the wafer. A processor and a memory storing computer program instructions, wherein the processor reads and executes the computer program instructions to implement the method provided in any of the above embodiments.

[0128] In some embodiments of the present invention, the processor may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement embodiments of the present invention.

[0129] The memory may include a large-capacity storage device for data or instructions. For example, and not limitingly, the memory may include a hard disk drive (HDD), a floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or a Universal Serial Bus (USB) drive, or a combination of two or more of these. In one instance, the memory may include removable or non-removable (or fixed) media, or the memory may be non-volatile solid-state memory. The memory may be internal or external to the integrated gateway disaster recovery device.

[0130] In some embodiments of the present invention, the memory may be a read-only memory (ROM). The ROM may be a masked read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), an electrically erasable programmable read-only memory (EAROM), or flash memory, or a combination of two or more of these.

[0131] Some embodiments of the present invention are implemented using a computer-readable storage medium (such as a non-transitory computer-readable storage medium). The computer-readable storage medium stores computer program instructions; when executed by a processor, these computer program instructions implement any of the wafer alignment methods described in the above embodiments.

[0132] In another aspect, the present invention provides a computer program product, including a computer program that, when executed, implements the wafer alignment method in any of the above embodiments.

[0133] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0134] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this invention are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, read-only memory (ROM), flash memory, erasable read-only memory (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0135] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0136] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0137] The above description is merely a specific embodiment of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A wafer alignment method, wherein the wafer has positioning features, characterized in that, The method includes: Acquire a first original image of a first wafer containing positioning features, wherein the first wafer has a first flat edge as the positioning feature; Based on the first original image, extract the geometric features of the first flat edge; Obtain a second original image of the first wafer, including the first arc edge; Based on the second original image, extract the first alignment point located on the first arc edge and outside the first flat edge; A third original image of the second wafer containing positioning features is obtained, wherein the second wafer has a second flat edge as the positioning feature; Based on the third original image, extract the geometric features of the second flat edge; Obtain a fourth original image of the second wafer, including the second arc edge; Based on the fourth original image, extract the second alignment point located on the second arc edge and outside the second flat edge; The second wafer is aligned with the first wafer based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point, and the second alignment point.

2. The wafer alignment method according to claim 1, characterized in that, The first alignment point is the intersection of the first arc edge and the first predetermined axis of the second original image, and the second alignment point is the intersection of the second arc edge and the second predetermined axis of the fourth original image.

3. The wafer alignment method according to claim 2, characterized in that, The first predetermined axis is the central axis in the width direction of the second original image in the camera coordinate system where the image acquisition device that acquired the second original image is located; The second predetermined axis is the central axis in the width direction of the fourth original image within the camera coordinate system where the image acquisition device that acquired the fourth original image is located.

4. The wafer alignment method according to claim 1, characterized in that, The geometric features of the first flat edge include the first starting point of the first flat edge and the first preset point on the first flat edge; The geometric features of the second flat edge include the second starting point of the second flat edge and the second preset point on the second flat edge.

5. The wafer alignment method according to claim 4, characterized in that, Aligning the second wafer with the first wafer based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point, and the second alignment point includes: Based on the first inclination angle of the first flat side determined by the first starting point and the first preset point, and the second inclination angle of the second flat side determined by the second starting point and the second preset point, the angle difference between the first inclination angle and the second inclination angle is obtained. Based on the angle difference, drive the second wafer to rotate until the angle difference meets a preset angle threshold; The difference between the first alignment point and the second alignment point in the first direction after the angle difference satisfies the preset angle threshold is used as the first offset of the second wafer in the first direction; Based on the first offset, the second wafer is driven to move in the first direction until the first offset satisfies a preset first offset threshold. The distance between the first flat edge and the second flat edge in the second direction after the first offset satisfies a preset first offset threshold is taken as the second offset of the second wafer in the second direction, wherein the second direction is perpendicular to the first direction; Based on the second offset, the second wafer is driven to move in the second direction until the second offset meets a preset second offset threshold, so as to align the second wafer with the first wafer.

6. The wafer alignment method according to claim 5, characterized in that, The distance between the first flat edge and the second flat edge in the second direction is obtained based on the perpendicular distance between the first line segment determined by the first starting point and the first preset point and the second line segment determined by the second starting point and the second preset point, and the angle between the first flat edge and / or the second flat edge and the first direction after the first offset satisfies a preset first offset threshold; or The distance between the first flat edge and the second flat edge in the second direction is obtained based on the distance between the second starting point and the first line segment in the second direction.

7. The wafer alignment method according to claim 1, characterized in that, The method further includes: A fifth original image of a third wafer containing positioning features is obtained, wherein the third wafer has a first notch as the positioning feature; Based on the fifth original image, extract the first gap image; The first wafer reference vector of the third wafer is obtained by performing the wafer reference vector determination process; A sixth original image of a fourth wafer containing positioning features is obtained, wherein the fourth wafer has a second notch as the positioning feature; Based on the sixth original image, extract the second gap image; The second wafer reference vector of the fourth wafer is obtained by performing the wafer reference vector determination process; Align the second wafer reference vector with the first wafer reference vector to align the fourth wafer with the third wafer. The wafer reference vector determination process includes: Obtain the geometric feature points of the notch as the first reference point; A second reference point is obtained at a predetermined position on the arc edge of one side of the wafer, and the vector pointing from one of the first reference point and the second reference point to the other is determined as the wafer reference vector.

8. The wafer alignment method according to claim 7, characterized in that, Before obtaining the geometric feature points of the notch as the first reference point, the wafer reference vector determination process further includes: Based on the tilt angle of the notch determined from the notch image, the wafer is driven so that the notch is aligned with a standard orientation; The step of obtaining the geometric feature points of the notch as the first reference point includes: Obtain the geometric feature point of the notch aligned with the standard direction as the first reference point.

9. The wafer alignment method according to claim 7, characterized in that, The step of extracting the first gap image based on the fifth original image includes: The fifth original image is subjected to adaptive image enhancement, and the region of interest where the first gap is located is defined to obtain the first processed image; Adaptive threshold segmentation is performed on the first processed image to extract the first gap image; The step of extracting the second gap image based on the sixth original image includes: The sixth original image is subjected to adaptive image enhancement, and the region of interest where the second gap is located is defined to obtain the second processed image; Adaptive thresholding is performed on the second processed image to extract the second gap image.

10. The wafer alignment method according to claim 8, characterized in that, The step of driving the wafer to align the notch with a standard orientation based on the tilt angle of the notch determined from the notch image includes: Based on the gap image, determine the two target endpoints of the gap; Calculate the tilt angle of the gap based on the two target endpoints; Based on the tilt angle, the wafer is driven to rotate so that the notch is aligned with the standard direction.

11. The wafer alignment method according to claim 7, characterized in that, The geometric feature point of the notch is the center of the largest inscribed circle of the notch. Alternatively, the geometric feature point of the notch is the center of the inscribed circle of the notch that passes through the vertex of the notch. Alternatively, the geometric feature point of the notch is the midpoint of the line connecting the two endpoints of the notch. Alternatively, the geometric feature points of the gap are the positions at which the distance between them and two specific straight lines of the gap image is a first preset distance and a second preset distance, respectively. The two specific straight lines are located on both sides of the vertex of the gap, and for each of the two specific straight lines, the specific straight line is the line that can pass through the target contour points on that side of the gap's contour with the largest number of points on the corresponding side of the gap's vertex.

12. The wafer alignment method according to claim 7, characterized in that, The second reference point of the third wafer is the intersection of the arc edge of the third wafer and the predetermined axis of the fifth original image, and the second reference point of the fourth wafer is the intersection of the arc edge of the fourth wafer and the predetermined axis of the sixth original image.

13. The wafer alignment method according to claim 12, characterized in that, The predetermined axis of the fifth original image is the central axis of the fifth original image in the width direction, and the predetermined axis of the sixth original image is the central axis of the sixth original image in the width direction.

14. The wafer alignment method according to any one of claims 1-13, characterized in that, The wafer alignment method is applied to a wafer bonding apparatus, the wafer bonding apparatus comprising: The first stage is used to hold the wafer to be bonded during the wafer bonding process; A second stage is used to hold another wafer to be bonded during the wafer bonding process, wherein the wafer to be bonded has positioning features; A first raw image acquisition unit is used to acquire a raw image of a first region of interest of the wafer to be bonded, held on the second stage. A second raw image acquisition device is used to acquire a raw image of the wafer to be bonded, held on the second stage, containing a second region of interest. The mounting positions of the first and second raw image acquisition devices are such that the included angle between the arcs on the circumference of the wafer to be bonded is a preset angle, so that the raw image of the first region of interest acquired by the first raw image acquisition device includes the positioning feature, and the raw image of the second region of interest includes a segment of the arc edge of the wafer. The wafer alignment method includes: The first wafer is placed on the second stage, wherein the first wafer has the first flat edge as the positioning feature; The first original image, including the first flat edge, is acquired by the first original image acquisition device and held on the second stage. Based on the first original image, extract the geometric features of the first flat edge; The second raw image, including the first arc edge, is acquired by the second raw image acquisition device on the first wafer held on the second stage; Based on the second original image, extract the first alignment point located on the first arc edge; The first wafer is transferred to the first stage, and the second wafer is placed on the second stage, wherein the second wafer includes a second flat edge as the positioning feature; The third raw image, including the second flat edge, is acquired by the first raw image acquisition device on the second wafer held on the second stage; Based on the third original image, extract the geometric features of the second flat edge; A fourth raw image, including the second arc edge, is acquired by the second raw image acquisition unit on the second stage of the second wafer. Based on the fourth original image, extract the second alignment point located on the edge of the second arc; Based on the geometric features of the first flat edge, the geometric features of the second flat edge, the first alignment point, and the second alignment point, the first stage and the second stage are driven to move relative to each other to align the second wafer with the first wafer.

15. A wafer bonding method, characterized in that, include: The second wafer and the first wafer are aligned using the wafer alignment method according to any one of claims 1-13; The first wafer and the second wafer are bonded together.

16. The wafer bonding method according to claim 15, characterized in that, Also includes: A third wafer is placed on a second stage, wherein the third wafer has a first notch as the positioning feature; A fifth raw image of the third wafer held on the second stage is acquired by the first raw image acquisition device to obtain a first notch image; Based on the tilt angle determined by the first notch image, the second stage holding the third wafer is driven so that the first notch is aligned with a standard orientation; With the first notch aligned with the standard direction, the geometric feature points of the first notch are obtained as the first reference point of the third wafer based on the image of the first notch. For the third wafer held on the second stage, the second raw image acquisition device acquires a sixth raw image of the third wafer including the third arc edge to obtain a second reference point of the third wafer and determine a first wafer reference vector of the third wafer, wherein the first wafer reference vector is pointed to by one of the first reference point and the second reference point of the third wafer. The third wafer is transferred to the first stage, and the fourth wafer is placed on the second stage, wherein the fourth wafer has a second notch as the positioning feature; A seventh raw image of the fourth wafer held on the second stage is acquired by the first raw image acquisition device to obtain a second notch image; Based on the tilt angle determined by the second notch image, the second stage holding the fourth wafer is driven so that the second notch is aligned with the standard orientation; With the second notch aligned with the standard direction, the geometric feature points of the second notch are obtained as the first reference point of the fourth wafer based on the image of the second notch; For the fourth wafer held on the second stage, the second raw image acquisition device acquires an eighth raw image of the fourth wafer including the fourth arc edge to obtain the second reference point of the fourth wafer and determine the second wafer reference vector of the fourth wafer, wherein the second wafer reference vector is pointed to by one of the first reference point and the second reference point of the fourth wafer. By driving the first stage and the second stage to move relative to each other, the second wafer reference vector of the fourth wafer is aligned with the first wafer reference vector of the third wafer, so as to align the fourth wafer held on the second stage with the third wafer held on the first stage. The third wafer and the fourth wafer are bonded together.

17. A wafer bonding apparatus, characterized in that, The device includes: The first stage is used to hold the wafer to be bonded during the wafer bonding process; A second stage is used to hold another wafer to be bonded during the wafer bonding process, wherein the wafer to be bonded has positioning features; A first raw image acquisition unit is used to acquire a raw image of a first region of interest of the wafer to be bonded, held on the second stage. A second raw image acquisition device is used to acquire a raw image of the wafer to be bonded, which includes a second region of interest, held on the second stage. The angle between the arc of the first raw image acquisition device and the second raw image acquisition device on the wafer to be bonded is a preset angle, so that the raw image of the first region of interest of the wafer acquired by the first raw image acquisition device includes the positioning feature, and the raw image of the second region of interest includes a segment of the arc edge of the wafer. A processor and a memory storing computer program instructions, wherein the processor reads and executes the computer program instructions to implement the wafer alignment method as described in any one of claims 1-14.

18. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, implement the wafer alignment method as described in any one of claims 1-14.

19. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the wafer alignment method as described in any one of claims 1-14.

Images