Array substrate, display panel and display device
Patent Information
- Application Number
- CN202580000252.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-11-06
AI Technical Summary
Existing dual-gate pixel architectures are prone to poor color mixing in DLG mode, and the high data line density leads to high material costs, making it difficult to apply effectively in large-size products.
By employing a staggered transistor design, the width of data lines and gate lines is reduced, and the connection method is optimized through branch lines to ensure that transistors connected to the same data line are staggered in the row direction, thereby reducing the number of data lines and lowering material costs.
It effectively solves the problem of poor color mixing in DLG mode, reduces data line density, reduces the number of driver chips, reduces material costs, and improves pixel aperture ratio and refresh rate.
Smart Images
Figure CN123057428A_ABST
Abstract
Description
Array substrate, display panel and display device Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology
[0002] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their small size, low power consumption, high image quality, no radiation, and portability. They have experienced rapid development in recent years and have gradually replaced traditional cathode ray tube (CRT) displays, dominating the current flat panel display market. Currently, TFT-LCDs are widely used in products of various sizes, covering almost all major electronic products in today's information society, such as LCD TVs, high-definition digital TVs, computers (desktops and laptops), mobile phones, tablets, navigation systems, in-vehicle displays, projection displays, cameras, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention
[0003] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:
[0004] On one hand, embodiments of this disclosure provide an array substrate, including:
[0005] Substrate;
[0006] Multiple pixel electrodes are arranged in an array on the substrate, and each pair of four pixel electrodes in two adjacent rows and two columns constitutes a pixel electrode group.
[0007] Multiple gate lines are provided, with two gate lines between two adjacent rows of pixel electrodes, and the pixel electrodes in the same row correspond to the two gate lines. The gate lines corresponding to the odd-numbered pixel electrodes in the same row and the gate lines corresponding to the even-numbered pixel electrodes in the same row are located on both sides of the pixel electrodes in that row.
[0008] Multiple data lines are provided, with one data line between two adjacent columns of pixel electrode groups. Multiple pixel electrode groups in the same column correspond to two data lines, and the data lines corresponding to the odd-numbered pixel electrode groups and the data lines corresponding to the even-numbered pixel electrode groups in the same column are located on both sides of the pixel electrode groups in that column.
[0009] A plurality of transistors, wherein the gate of the transistor is electrically connected to the gate line, the first electrode of the transistor is electrically connected to the data line, and the second electrode of the transistor is electrically connected to the pixel electrode; in at least a portion of the row gaps of the pixel electrode, two transistors connected to the same data line are at least partially staggered along the row direction.
[0010] In some embodiments, in the array substrate provided in the present disclosure, in the row gap between the pixel electrode groups, two transistors connected to the same data line are located on opposite sides of the data line.
[0011] In some embodiments, in the array substrate provided in the present disclosure, the two transistors between adjacent data lines in the row gaps between the pixel electrode groups are arranged in a direction that intersects both the row direction and the column direction.
[0012] In some embodiments, the array substrate provided in the present disclosure further includes a first branch line located in the row gap between the pixel electrode groups. The first branch line is led out from the data line and extends along the row direction between the two gate lines before being electrically connected to the first electrode of the transistor.
[0013] In some embodiments, in the array substrate provided in the present disclosure, the two first branch lines between two adjacent data lines extend along the row direction between the two gate lines and then bend to be electrically connected to the first electrode of the transistor; or, the two first branch lines between two adjacent data lines extend along the row direction between the two gate lines and then are directly electrically connected to the first electrode of the transistor.
[0014] In some embodiments, in the array substrate provided in the present disclosure, in the row gap between the pixel electrode groups, two first branch lines are drawn from the middle data lines of every three adjacent data lines at a first position and a second position that are staggered from each other in the column direction; two first branch lines are drawn from the data lines near the first position at two positions that are substantially collinear with the second position in the row direction; and two first branch lines are drawn from the data lines near the second position at two positions that are substantially collinear with the first position in the row direction.
[0015] In some embodiments, the array substrate provided in this disclosure further includes a common electrode overlapping the pixel electrode and a connecting line integrally disposed with the common electrode.
[0016] Within one of the row gaps between two adjacent groups of the pixel electrode group: the orthographic projections of the two first branch lines derived from the middle data line of every three adjacent data lines on the substrate and the orthographic projection of the connecting line on the substrate do not overlap; the orthographic projections of the first branch lines derived from the data lines on both sides near the middle data line on the substrate and the connecting line on the substrate do not overlap; the orthographic projections of the first branch lines derived from the data lines on both sides away from the middle data line on the substrate and the connecting line on the substrate overlap. Within the other group: the orthographic projections of the two first branch lines derived from the middle data line of every three adjacent data lines on the substrate and the connecting line on the substrate overlap; the orthographic projections of the first branch lines derived from the data lines on both sides near the middle data line on the substrate and the connecting line on the substrate overlap; the orthographic projections of the first branch lines derived from the data lines on both sides away from the middle data line on the substrate and the connecting line on the substrate do not overlap.
[0017] In some embodiments, in the array substrate provided in the present disclosure, in the row gaps within the pixel electrode group, two transistors connected to the same data line are staggered along the row direction on one side of the data line.
[0018] In some embodiments, in the array substrate provided in the present disclosure, between two adjacent data lines, the arrangement direction of the two transistors in the row gap within the pixel electrode group is approximately the same as the arrangement direction of the two transistors in the row gap between the pixel electrode groups.
[0019] In some embodiments, the array substrate provided in the present disclosure further includes a second branch line located in the row gap within the pixel electrode group. The second branch line is led out from the data line and extends along the row direction between the two gate lines before being electrically connected to the first poles of the two transistors respectively.
[0020] In some embodiments, the array substrate provided in this disclosure further includes a common electrode overlapping the pixel electrode and a connecting line integrally disposed with the common electrode.
[0021] The orthographic projection of the second branch line on the substrate overlaps with the orthographic projection of the connecting line on the substrate.
[0022] In some embodiments, the array substrate provided in the present disclosure further includes a third branch line within the row gap between the pixel electrode groups, the third branch line being led out from the side of the same data line away from the second branch line and extending between the two gate lines.
[0023] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projection of the third branch line of the same data line leading out from one of the row gaps between two adjacent pixel electrode groups on the substrate overlaps with the orthographic projection of the connecting line on the substrate, while the orthographic projection of the third branch line leading out from the other does not overlap with the orthographic projection of the connecting line on the substrate.
[0024] In some embodiments, in the array substrate provided in the present disclosure, the orthographic projections of each of the third branch lines on the substrate overlap with the orthographic projections of the connecting lines on the substrate, or the orthographic projections of each of the third branch lines on the substrate do not overlap with the orthographic projections of the connecting lines on the substrate.
[0025] In some embodiments, the array substrate provided in this disclosure further includes a common electrode overlapping the pixel electrodes, a connecting line integrally formed with the common electrode, and a first common electrode line within the column gaps of the pixel electrode group; wherein...
[0026] The first common electrode line is on the same layer as the data line, and the first common electrode line is connected between adjacent connection lines in the column direction.
[0027] In some embodiments, the array substrate provided in the present disclosure further includes a fourth branch line located in the row gap between the pixel electrode groups, the fourth branch line being inclinedly led out from the data line to be electrically connected to the first electrode of the transistor.
[0028] In some embodiments, in the array substrate provided in the present disclosure, in the row gap between the pixel electrode groups, the data line leads out two fourth branch lines at two positions that are staggered from each other in the direction of intersection with the fourth branch line.
[0029] In some embodiments, in the array substrate provided in the present disclosure, two transistors connected to the same data line are arranged side by side along the column direction on one side of the data line in the row gap within the pixel electrode group.
[0030] In some embodiments, the array substrate provided in this disclosure further includes a first lead;
[0031] The transistor includes a first transistor, which is electrically connected to the pixel electrode spaced apart from the data line connected to it via the first lead.
[0032] In some embodiments, the array substrate provided in the present disclosure further includes a second common electrode line extending between the pixel electrode groups, wherein the orthographic projection of the first lead on the substrate overlaps with the orthographic projection of the second common electrode line on the substrate.
[0033] In some embodiments, in the array substrate provided in the present disclosure, the transistor further includes a second transistor, which is electrically connected to the pixel electrode adjacent to the data line to which it is connected;
[0034] The array substrate further includes a second lead in the same layer as the first lead. The second lead is integrally disposed with the pixel electrode connected to the second transistor, and the orthogonal projection of the second lead on the substrate overlaps with the orthogonal projection of the second common electrode line on the substrate.
[0035] In some embodiments, the array substrate provided in this disclosure further includes a common electrode overlapping the pixel electrode, a connecting line integrally disposed with the common electrode, and a second common electrode line extending in the inter-row gap of the pixel electrode group, wherein the second common electrode line and the connecting line are electrically connected between two gate lines in the same row gap.
[0036] In some embodiments, in the array substrate provided in the present disclosure, the gate line includes a groove opening toward the pixel electrode, and the orthographic projection of the second electrode of the transistor on the substrate overlaps with the orthographic projection of the gate line on both sides of the groove column direction on the substrate.
[0037] On the other hand, this disclosure provides a display panel including the array substrate provided in this disclosure and a counter substrate disposed opposite to the array substrate.
[0038] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description
[0039] Figure 1 shows a dual-gate pixel architecture of a related technology;
[0040] Figure 2 shows the dual-gate pixel architecture provided in an embodiment of this disclosure;
[0041] Figure 3 is an enlarged structural diagram of region Z1 in Figure 2;
[0042] Figure 4 is a schematic diagram of the cross-sectional structure along line I-I' in Figure 2;
[0043] Figure 5 is a schematic diagram of the structure of the layer where the pixel electrode is located in Figure 3;
[0044] Figure 6 is a schematic diagram of the structure of the layer containing the grid lines in Figure 3;
[0045] Figure 7 is a schematic diagram of the active layer in Figure 3;
[0046] Figure 8 is a schematic diagram of the structure of the layer where the data line is located in Figure 3;
[0047] Figure 9 is a schematic diagram of the structure of the layer where the vias are located in Figure 3;
[0048] Figure 10 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 3;
[0049] Figure 11a is a schematic diagram of the stacked structure of the layer containing the data line and the layer containing the common electrode in Figure 3;
[0050] Figure 11b is a schematic diagram of another stacked structure of the data line layer and the common electrode layer provided in the embodiments of this disclosure;
[0051] Figure 11c is a schematic diagram of another stacked structure of the data line layer and the common electrode layer provided in the embodiments of this disclosure;
[0052] Figure 12 is a magnified structural diagram of region Z2 in Figure 3;
[0053] Figure 13 is an enlarged structural diagram of region Z3 in Figure 2;
[0054] Figure 14 is a schematic diagram of the cross-sectional structure along line II-II' in Figure 13;
[0055] Figure 15 is a schematic diagram of the structure of the layer where the pixel electrode is located in Figure 13;
[0056] Figure 16 is a schematic diagram of the structure of the layer containing the grid lines in Figure 13;
[0057] Figure 17 is a schematic diagram of the active layer in Figure 13;
[0058] Figure 18 is a schematic diagram of the structure of the layer where the data line is located in Figure 13;
[0059] Figure 19 is a schematic diagram of the structure of the layer where the vias are located in Figure 13;
[0060] Figure 20 is a schematic diagram of the structure of the layer where the common electrode is located in Figure 13;
[0061] Figure 21 is an enlarged structural diagram of region Z4 in Figure 13;
[0062] Figure 22 is a schematic diagram of a display panel provided in an embodiment of this disclosure;
[0063] Figure 23 is a schematic diagram of another structure of the display panel provided in an embodiment of this disclosure;
[0064] Figure 24 is a schematic diagram of another structure of the display panel provided in an embodiment of this disclosure;
[0065] Figure 25 is a schematic diagram of the structure of the display device provided in the embodiment of this disclosure. Detailed Implementation
[0066] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.
[0067] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0068] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.
[0069] With the continuous development of display technology, LCD displays have become dominant in the display industry. Products using the ADS (Adaptive Digital Switching) structure have become the mainstream display mode due to their advantages such as wide viewing angles, fast response times, and high contrast.
[0070] In recent years, while improving product specifications, companies have also continuously developed products to reduce costs. Taking pixel structure as an example, the technology has evolved from single gate to dual gate. Compared to the single gate solution, which uses one data line to drive one column of sub-pixels, the dual gate solution uses one data line to drive multiple columns of sub-pixels. This reduces the number of data lines, the total number of driver chips (ICs), and significantly reduces material costs, making it particularly suitable for medium and large-sized products such as automotive displays and televisions.
[0071] Figure 1 shows a dual-gate pixel architecture of the related technology. When the DLG (Dual Line Gate) function is enabled, each cycle can be 4 rows of gates. Within a cycle, the gates are enabled in the order of the 1st and 3rd rows of gates being enabled simultaneously, followed by the 2nd and 4th rows of gates being enabled simultaneously. Since the sub-pixels connected by the two rows of gates that are enabled simultaneously have different colors through the same data line, color mixing problems will occur in DLG mode.
[0072] To address the aforementioned technical problems, this disclosure provides an array substrate. Figure 2 is a schematic diagram of the pixel structure of the array substrate, Figure 3 is an enlarged schematic diagram of the Z1 region in Figure 2, Figure 4 is a schematic diagram of the cross-sectional structure along line I-I' in Figure 2, and Figures 5 to 10 are schematic diagrams of the structures of different film layers in Figure 3. Referring to Figures 1 to 10, the array substrate of this disclosure may include:
[0073] The substrate 101 includes a display area AA, which may have an array of red sub-pixels R, green sub-pixels G, and blue sub-pixels B. The substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, or plastic.
[0074] Multiple pixel electrodes 102 are arranged in an array in the display area AA, and four pixel electrodes 102 in every two adjacent rows and two columns can form a pixel electrode group P. Optionally, the pixel electrodes 102 can be made of transparent conductive materials such as indium tin oxide (ITO) and indium zinc oxide (IZO).
[0075] Multiple gate lines 103 are provided, with two gate lines 103 between two adjacent rows of pixel electrodes 102. Each row of pixel electrodes 102 corresponds to one of the two gate lines 103 (corresponding here means that the gate of the transistor electrically connected to the pixel electrode is electrically connected to the gate line). The gate lines 103 corresponding to odd-numbered pixel electrodes 102 and even-numbered pixel electrodes 102 are located on opposite sides of the row of pixel electrodes 102, thus forming a dual-gate pixel structure. Optionally, the material of the gate lines 103 may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The gate lines 103 can be a single-layer structure or a multilayer structure; for example, the gate lines 103 can be a single-layer structure composed of a copper metal layer.
[0076] In some embodiments, a transparent conductive layer for fabricating pixel electrode 102 and a metal conductive layer for fabricating gate line 103 can be formed sequentially. The patterns of the layer containing pixel electrode 102 and the layer containing gate line 103 can be fabricated using a mask. In this case, as shown in Figures 5 and 6, there is a first similar pattern GT' in the layer containing pixel electrode 102 that is similar to the layer containing gate line 103. Due to the influence of process factors such as exposure diffraction, the first similar pattern GT' will expand outward relative to the pattern of the layer containing gate line 103.
[0077] Multiple data lines 104 are provided, with one data line 104 between two adjacent columns of pixel electrode groups P. Multiple pixel electrode groups P in the same column correspond to two data lines 104, and the data lines 104 corresponding to odd-numbered pixel electrode groups P and even-numbered pixel electrode groups P in the same column are located on opposite sides of that column. In other words, the data lines 104 can be located within the column gap V-GP1 between adjacent pixel electrode groups P arranged along the row direction X, and the same data line 104 can correspond to the odd-numbered pixel electrode group P in its left adjacent column and the even-numbered pixel electrode group P in its right adjacent column. In some embodiments, the material of the data lines 104 may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), and nickel (Ni). The data lines 104 can be a single-layer structure or a multilayer structure; for example, the data lines 104 can be a multilayer structure composed of a titanium metal layer / an aluminum metal layer / a titanium metal layer.
[0078] Multiple transistors 105 are provided. The gate g of transistor 105 is electrically connected to gate line 103, the first terminal s of transistor 105 is electrically connected to data line 104, and the second terminal d of transistor 105 is electrically connected to pixel electrode 102. In this disclosure, gate line 103 corresponds to pixel electrode 102, which can be understood as the gate g of transistor 105 electrically connected to pixel electrode 102 being electrically connected to gate line 103. Data line 104 corresponds to pixel electrode group P, which can be understood as data line 104 being electrically connected to pixel electrode 102 of pixel electrode group P through transistor 105.
[0079] As can be seen from Figures 2 and 3, in this disclosure, the sub-pixels connected to the n&(n+2)th gate lines 103 and the same data line 104 via transistor 105 have the same color (for example, the sub-pixels connected to the 1st and 3rd gate lines 103 and the 2nd data line 104 from the left via transistor 105 are all red sub-pixels R). Therefore, DLG mode can be supported without color mixing problems. In DLG mode, both rows of gates are turned on simultaneously, doubling the data transmission time and the refresh rate.
[0080] In some embodiments, this disclosure may further provide that at least a portion of the row gaps (e.g., row gaps H-GP2 within pixel electrode group P) of the pixel electrode 102 are at least partially offset along the row direction X of the two transistors 105 connected to the same data line 104. Compared to the two transistors 105 connected to the same data line 104 at a row gap (e.g., row gap H-GP2 within pixel electrode group P) being vertically aligned along the column direction Y, this disclosure provides that the two transistors 105 connected to the same data line 104 at a row gap (e.g., row gap H-GP1 between pixel electrode groups P) are at least partially offset along the row direction X, which helps to reduce the width of the row gap (e.g., row gap H-GP1 between pixel electrode groups P), and correspondingly reduces the width of the black matrix BM covering the row gap (e.g., row gap H-GP2 within pixel electrode group P), thereby improving the pixel aperture ratio.
[0081] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 3, 5 to 8, in the row gap H-GP2 within the pixel electrode group P, two transistors 105 connected to the same data line 104 are located on opposite sides of the data line 105. This is equivalent to the two transistors 105 connected to the same data line 104 being staggered left and right along the row direction X in the row gap H-GP2 within the pixel electrode group P. Optionally, in the row gap H-GP2 within the pixel electrode group P, two transistors 105 between two adjacent data lines 104 are arranged obliquely along a direction intersecting both the row direction X and the column direction Y. This can minimize the width of the row gap H-GP1 between pixel electrode groups P, effectively improving the pixel aperture ratio.
[0082] In some embodiments, the array substrate provided in the present disclosure, as shown in FIG3, FIG6 and FIG8, may further include a first branch line 106 located in the row gap H-GP1 between pixel electrode groups P. The first branch line 106 may be led out from the data line 104 and extended along the row direction X between two gate lines 103 and electrically connected to the first electrode s of the transistor 105. This allows the transistor 105 in the H-GP1 row gap to be designed obliquely, and the width of a single gate line 103 can be compressed to 9μm to 13μm, for example 11μm or 12μm. Correspondingly, the width of the black matrix BM in the column direction Y can be reduced to 90μm to 110μm, for example 95μm, 99μm, 100μm, 102μm, 105μm, etc.
[0083] Referring again to Figures 3 and 8, in order to make full use of the row gap H-GP1 between pixel electrode groups P, in this disclosure, the middle data line 104 (e.g., the third data line 104 from the left) of every three adjacent data lines 104 (e.g., the second, third, and fourth data lines 104 from the left) can have two first branch lines 106 drawn from the first position L1 and the second position L2, which are staggered in the column direction Y. The data line 104 near the first position L1 (e.g., the second data line 104 from the left) has two first branch lines 106 drawn from two positions L3 & L4 that are approximately collinear with the second position L2 in the row direction X. The data line 104 near the second position L2 (e.g., the fourth data line 104 from the left) has two first branch lines 106 drawn from two positions L5 & L6 that are approximately collinear with the first position L1 in the row direction X. It should be understood that, in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, the above-mentioned "approximately collinear" may be on a straight line extending along the row direction X, or may be offset vertically along the column direction Y. Therefore, as long as the "approximately collinear" relationship between the above-mentioned features satisfies the allowable deviation, it falls within the protection scope of this disclosure.
[0084] In some embodiments, as shown in Figures 3 and 8, within the row gap H-GP1 between pixel electrode groups P, two first branch lines 106 between adjacent data lines 104 can extend between two gate lines 103 and then bend to electrically connect with transistor 105, thereby achieving a short connection with pixel electrode 102; the short-connected first branch lines 106 can not overlap with the connection line 108 of common electrode 107. Optionally, the two first branch lines 106 between adjacent data lines 104 can also extend between two gate lines 103 and directly connect with transistor 105, thereby achieving a long connection with pixel electrode 102; the long-connected first branch lines 106 can overlap with the connection line 108 of common electrode 107.
[0085] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 3, 8, and 10, may further include a common electrode 107 overlapping with the pixel electrode 102, and a connecting line 108 integrally formed with the common electrode 107. Optionally, the layer containing the common electrode 107 may be fabricated using a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). In this disclosure, one of the common electrode 107 and the pixel electrode 102 may be a slit electrode within a sub-pixel, and the other may be a block electrode within a sub-pixel. This disclosure illustrates the example of the common electrode 107 being a slit electrode and the pixel electrode 102 being a block electrode. To ensure that adjacent transistors 105 are not short-circuited and are staggered left and right, this disclosure can configure the following within one of the two adjacent inter-group row gaps H-GP1 of the pixel electrode group P (e.g., the second inter-group row gap H-GP1 from top to bottom): the orthographic projection of the two first branch lines 106 extending from the middle data line 104 (e.g., the third data line 104 from the left) of every three adjacent data lines 104 (e.g., the second, third, and fourth data lines 104 from the left) onto the substrate 101 is not parallel to the orthographic projection of the connecting line 108 onto the substrate 101. The orthographic projections of the first branch line 106 extending from the data lines 104 on both sides (e.g., the 2nd and 4th data lines 104 from the left) closer to the middle data line 104 (e.g., the 3rd data line 104 from the left) on the substrate 101 do not overlap with the orthographic projections of the connecting line 108 on the substrate 101. The orthographic projections of the first branch line 106 extending from the data lines 104 on both sides (e.g., the 2nd and 4th data lines 104 from the left) further away from the middle data line 104 (e.g., the 3rd data line 104 from the left) on the substrate 101 are also not overlapping. The projections of the connecting line 108 onto the substrate 101 overlap; in another group (e.g., the first inter-row spacing H-GP1 from top to bottom): the projections of the two first branch lines 106 extending from the middle data line 104 (e.g., the third data line 104 from the left) of every three adjacent data lines 104 (e.g., the second, third, and fourth data lines 104 from the left) onto the substrate 101 overlap with the projections of the connecting line 108 onto the substrate 101, and the projections of the two side data lines 104 (e.g., the second, third, and fourth data lines 104 from the left) onto the substrate 101 overlap. 04) The orthographic projection of the first branch line 106 leading out from the middle data line 104 (e.g., the third data line 104 from the left) on the substrate 101 overlaps with the orthographic projection of the connecting line 108 on the substrate 101. The orthographic projection of the first branch line 106 leading out from the data lines 104 on both sides (e.g., the second and fourth data lines 104 from the left) away from the middle data line 104 (e.g., the third data line 104 from the left) on the substrate 101 does not overlap with the orthographic projection of the connecting line 108 on the substrate 101.Optionally, Figure 11a shows a stacking diagram of the layer where the first branch line 106 is located and the layer where the connecting line 108 is located in Figure 3, and the overlapping position O1 of the first branch line 106 and the connecting line 108 is marked in Figure 11a.
[0086] In some embodiments, as shown in FIG3, FIG5 to FIG8, in the row gap H-GP2 within the pixel electrode group P, two transistors 105 connected to the same data line 104 can be staggered along the row direction X on one side of the data line 104. This facilitates the data line 104 to be electrically connected to the upper and lower pixel electrodes 102 of adjacent rows and adjacent columns within the pixel electrode group P through the two transistors 105 respectively, while also ensuring that the row gap H-GP2 within the pixel electrode group P is relatively narrow.
[0087] Referring to Figures 3, 5 to 8, it can be seen that in this disclosure, the arrangement direction of the two transistors 105 at the row gap H-GP2 within the pixel electrode group P is approximately the same as the arrangement direction of the two transistors 105 at the row gap H-GP1 between pixel electrode groups P. For example, between the first and second data lines 104 from the left, the transistors 105 at the inter-group row gap H-GP1 and the intra-group row gap H-GP2 are both arranged at an angle from lower left to upper right; between the second and third data lines 104 from the left, the transistors 105 at the inter-group row gap H-GP1 and the intra-group row gap H-GP2 are both arranged at an angle from upper left to lower right. This is beneficial because the widths of the inter-group row gap H-GP1 and the intra-group row gap H-GP2 are comparable, and the corresponding black matrix BM has comparable widths in the inter-group row gap H-GP1 and the intra-group row gap H-GP2, which helps to improve the uniformity of the black matrix BM.
[0088] In some embodiments, as shown in FIG3, 6, and 8, the array substrate provided in the present disclosure may further include a second branch line 109 located in the row gap H-GP2 within the pixel electrode group P. The second branch line 109 may be led out from the data line 104 and extend along the row direction X between the two gate lines 103, and then electrically connected to the first electrode s of two transistors 105 respectively. Optionally, after extending along the row direction X between the two gate lines 103, the second branch line 109 bends to be electrically connected to the first electrode s of a transistor 105 (i.e., a transistor 105 electrically connected to the adjacent pixel electrode 102 from which the data line 104 leads out the second branch line 109), and is electrically connected to the first electrode s of the two gate lines 104. After extending along the row direction X between 3, it is directly connected to the first pole s of another transistor 105 (i.e., the transistor 105 that is electrically connected to the data line 104 that leads out the second branch line 109 at the pixel electrode 102), so that the transistor 105 in the row gap H-GP2 in the pixel electrode group P can be designed obliquely, and the width of a single gate line 103 can be compressed to 9μm to 13μm, such as 9μm, 10μm, 11μm, 12μm, 13μm, etc. Correspondingly, the width of the black matrix BM in the column direction Y can be reduced to 90μm to 110μm, such as 90μm, 95μm, 99μm, 100μm, 105μm, 110μm, etc.
[0089] Considering that the second branch line 109 needs to achieve short and long connections with two pixel electrodes 102 in adjacent rows and columns of the pixel electrode group P, respectively, and the connecting line 108 can be located at the column gap (also called the intra-group column gap V-GP2 of the pixel electrode group P) between two adjacent pixel electrodes 102 in the row direction X of the pixel electrode group P, the second branch line 109 in this disclosure can cross the connecting line 108 to facilitate its electrical connection with two pixel electrodes 102 in adjacent rows and columns of the pixel electrode group P. That is, the orthographic projection of the second branch line 109 on the substrate 101 can overlap with the orthographic projection of the connecting line 108 on the substrate 101, as shown in Figures 3, 6, and 8. Figure 11a is a stacked diagram of Figures 8 and 10, where O2 represents the overlap position of the second branch line 109 and the connecting line 108.
[0090] In some embodiments, as shown in FIG3, FIG6, FIG8 and FIG11a, the array substrate provided in the present disclosure may further include a third branch line 110 within the row gap H-GP2 of the pixel electrode group P. The third branch line 110 may be led out from the side of the same data line 104 away from the second branch line 109 and extend between the two gate lines 103. This not only ensures that the load of the gate lines 103 is similar or even the same, but also helps to improve the etching uniformity of the layer pattern where the data line 104 is located.
[0091] Optionally, as shown in Figures 3, 6, 8, and 11a, the orthographic projection of the third branch line 110 of the same data line 104 (e.g., the second data line 104 from the left) extending into one of the row gaps H-GP2 within two adjacent pixel electrode groups P (e.g., the first row gap H-GP2 from the top) on the substrate 101 overlaps with the orthographic projection of the connecting line 108 on the substrate 101, while the orthographic projection of the third branch line 110 extending into the other (e.g., the second row gap H-GP2 from the top) on the substrate 101 does not overlap with the orthographic projection of the connecting line 108 on the substrate 101. In other words, one of the two third branch lines 110 extending from the same data line 104 within the row gaps H-GP2 within two adjacent pixel electrode groups P intersects with the connecting line 108, and the other intersects with the connecting line 108.
[0092] Figure 11a shows that in one of the row gaps H-GP2 within two adjacent pixel electrode groups P (e.g., the first row gap H-GP2 from top to bottom): the orthographic projection of the third branch line 110 extending from the first data line 104 (e.g., the second data line 104 from the left) of every three adjacent data lines 104 (e.g., the second, third, and fourth data lines 104 from the left) onto the substrate 101 overlaps with the orthographic projection of the connecting line 108 onto the substrate 101; the orthographic projection of the third branch line 110 extending from the second data line 104 and the third data line (e.g., the third and fourth data lines 104 from the left) onto the substrate 101 does not overlap with the orthographic projection of the connecting line 108 onto the substrate 101; in the other (e.g., the first row gap H-GP2 from top to bottom)... Within the two groups of row gaps (H-GP2), the orthographic projection of the third branch line 110 derived from the first data line 104 (e.g., the second data line 104 from the left) of every three adjacent data lines 104 (e.g., the second, third, and fourth data lines 104 from the left) on the substrate 101 does not overlap with the orthographic projection of the connecting line 108 on the substrate 101. The orthographic projection of the third branch line 110 derived from the second data line 104 and the third data line (e.g., the third and fourth data lines 104 from the left) on the substrate 101 overlaps with the orthographic projection of the connecting line 108 on the substrate 101 (for clarity, Figure 12 shows an enlarged structure of region Z2 in Figure 3). The overlap position of the third branch line 110 and the connecting line 108 is marked as O3.
[0093] In short, in Figure 11a, three adjacent data lines 104 (e.g., the 2nd, 3rd, and 4th data lines 104 from the left) are grouped together. Within each group, the three third branch lines 110 extending from one of the row gaps H-GP2 within the adjacent two pixel electrode groups P (e.g., the first row gap H-GP2 from the top) intersect, do not intersect, and do not intersect with the connecting line 108 in sequence. In the other group (e.g., the first row gap H-GP2 from the top), the three third branch lines 110 extending from the other group (e.g., the first row gap H-GP2 from the top) intersect, do not intersect, and intersect with the connecting line 108 in sequence. Of course, in some embodiments, the three third branch lines 110 extending from one of the row gaps H-GP2 within two adjacent pixel electrode groups P (e.g., the first row gap H-GP2 from top to bottom) can sequentially not overlap with the connecting line 108, and the three third branch lines 110 extending from the other (e.g., the first row gap H-GP2 from top to bottom) can sequentially overlap with the connecting line 108; or, in other embodiments, the three data lines 104 within two adjacent pixel electrode groups P... The three third branch lines 110 drawn from one of the row gaps H-GP2 (e.g., the first row gap H-GP2 from the top down) can overlap with the connecting line 108 in sequence, while the three third branch lines 110 drawn from the other (e.g., the first row gap H-GP2 from the top down) do not overlap with the connecting line 108 in sequence; or, the three data lines 104 within the group can be drawn from one of the row gaps H-GP2 in the adjacent two pixel electrode groups P (e.g., the first row gap H-GP2 from the top down). Line 110 can also sequentially overlap, overlap, and not overlap with connecting line 108. In another (e.g., the first row gap H-GP2 from the top down), three third branch lines 110 can sequentially not overlap, not overlap, and overlap with connecting line 108. Alternatively, the three third branch lines 110 of the three data lines 104 within a group can sequentially not overlap, not overlap, and overlap with connecting line 108 in one of the row gaps H-GP2 within two adjacent pixel electrode groups P (e.g., the first row gap H-GP2 from the top down). In another (e.g., the first group from the top down)... The three third branch lines 110 drawn from the inner row gap H-GP2 overlap, overlap, and do not overlap with the connecting line 108 in sequence; or, the three data lines 104 in the group can also overlap, not overlap, and overlap with the connecting line 108 in sequence in one of the inner row gaps H-GP2 of two adjacent pixel electrode groups P (e.g., the first inner row gap H-GP2 from top to bottom), while the three third branch lines 110 drawn from the other (e.g., the first inner row gap H-GP2 from top to bottom) do not overlap, overlap, and do not overlap with the connecting line 108 in sequence.The goal is to ensure that one of the two third branch lines 110 extending from a single data line 104 within the inter-row spacing H-GP1 between two adjacent groups overlaps with the connecting line 108, while the other does not overlap with the connecting line 108.
[0094] Referring to Figures 3, 8, and 11a, in every four adjacent row gaps (e.g., the first inter-group row gap H-GP1, the first intra-group row gap H-GP2, the second inter-group row gap H-GP1, and the second intra-group row gap H-GP2 from top to bottom), the first data line 104 (e.g., the second data line 104 from the left) of every three adjacent data lines 104 (e.g., the second, third, and fourth data lines 104 from the left) has four branch lines overlapping with the connecting line 108: a first branch line 106 extending to the right from the first inter-group row gap H-GP1, a second branch line 109 extending to the right from the first intra-group row gap H-GP2, a first branch line 106 extending to the left from the second inter-group row gap H-GP1, and a second branch line 109 extending to the left from the second intra-group row gap H-GP2. Data line 104 (e.g., the third data line from the left) has four branch lines that overlap with the connecting line 108: two first branch lines 106 extending to the left and right from the first inter-group row gap H-GP1, one second branch line 109 extending to the right from the first intra-group row gap H-GP2, and one second branch line 109 extending to the left from the second intra-group row gap H-GP2. Data line 104 (e.g., the fourth data line from the left) has four branch lines that overlap with the connecting line 108: one first branch line 106 extending to the left from the first inter-group row gap H-GP1, one second branch line 109 extending to the right from the first intra-group row gap H-GP2, one first branch line 106 extending to the right from the second inter-group row gap H-GP1, and one second branch line 109 extending to the left from the second intra-group row gap H-GP2. Combining the above-mentioned first data line 104 (e.g., the second data line 104 from the left) with a third branch line 110 extending to the left of the first group's row gap H-GP2 that overlaps with the connecting line 108, and the second and third data lines 104 (e.g., the third and fourth data lines 104 from the left) with a third branch line 110 extending to the right of the second group's row gap H-GP2 that overlaps with the connecting line 108, it can be seen that in this disclosure, at every four adjacent row gaps, any one of every three adjacent data lines 104 has five intersecting branch lines with the connecting line 108. This ensures that the overlap capacitance between different data lines 104 and connecting lines 108 is similar or even the same.
[0095] Since only the first branch line 106 and the second branch line 109 serve as electrical connections in this disclosure, and there are four first branch lines 106 and four second branch lines 109 intersecting with the connecting line 108 at every four adjacent row gaps, the overlapping capacitance between different data lines 104 and the connecting line 108 is approximately the same. Therefore, capacitance compensation is not required. Based on this, the third branch line 110 led from the same data line 104 in this disclosure can overlap with the connecting line 108 in one of the two row gaps H-GP2 within the two groups, as shown in FIG11a, and not overlap with the connecting line 108 in the other. In some embodiments, the third branch line 110 led from the same data line 104 in this disclosure can also completely not overlap with the connecting line 108, as shown in FIG11b; or the third branch line 110 led from the same data line 104 can also completely overlap with the connecting line 108, as shown in FIG11c.
[0096] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 3, 4, and 8 to 10, may further include a first common electrode line 111 at the column gap V-GP2 within the pixel electrode group P. The first common electrode line 111 may be in the same layer and material as the data line 104, and the first common electrode line 111 is connected between adjacent connection lines 108 in the column direction Y. Optionally, a first insulating layer 112 is provided between the layer containing the first common electrode line 111 and the layer containing the connection line 108. The two ends of the first common electrode line 111 can be electrically connected to the connection line 108 through a first via V1 penetrating the first insulating layer 112. At least a portion of the first common electrode line 111 is covered by a common electrode 107 and electrically connected to the connection line 108, which is equivalent to the first common electrode line 111 being connected in parallel with the common electrode 107, so that the layer containing the common electrode 107 forms a mesh structure, which helps to reduce the resistance of the common electrode 107 and improve the uniformity of the common electrode signal. In some embodiments, in order to reduce the overlap capacitance between the common electrode 107 and the data line 104, the present disclosure may hollow out the common electrode 107 in the area between every two pixel electrodes 102 to partially expose the data line 104.
[0097] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 3 to 5 and Figures 8 to 10, may further include a transition electrode 113 and a second insulating layer 114. The transition electrode 113 is in the same layer and made of the same material as the common electrode 107. The pixel electrode 102 and the second electrode d of the transistor 105 are electrically connected to the transition electrode 113 through a second via V2 penetrating the first insulating layer 112 and the second insulating layer 114, thereby achieving electrical connection between the pixel electrode 102 and the second electrode d of the transistor 105. Furthermore, by using the transition electrode 113 to connect the pixel electrode 102 and the second electrode d of the transistor 105, the first via V1 and the second via V2 can be fabricated using the same mask, thereby avoiding the need to separately fabricate a via penetrating the second insulating layer 114 (which would enable electrical connection between the pixel electrode 102 and the second electrode d of the transistor 105), saving a masking process and reducing costs.
[0098] In some embodiments, in the array substrate provided in the present disclosure, FIG13 shows an enlarged structure of the Z3 region in FIG2, FIG14 is a cross-sectional view along line II-II' in FIG13, and FIG15 to FIG20 are schematic diagrams of the structures of different film layers in FIG13. As can be seen from FIG13 to FIG20, the array substrate of the present disclosure may further include a fourth branch line 115 located in the row gap H-GP1 between pixel electrode groups P. The fourth branch line 115 may be inclinedly led out from the data line 104 to be electrically connected to the first electrode s of the transistor 105, thereby enabling the two transistors 105 connected to the same data line 104 to be staggered in the row direction X in the row gap H-GP1 between pixel electrode groups P. Optionally, in the row gap H-GP1 between pixel electrode groups P, the data line 104 may lead out two fourth branch lines 115 at two positions L7 & L8 that are staggered from each other in the direction of intersection with the fourth branch line 115, so that the two transistors 105 between two adjacent data lines 104 are inclinedly arranged in a direction that intersects both the row direction X and the column direction Y. This effectively reduces the width of the row gap H-GP1 between pixel electrode groups P, thereby increasing the pixel aperture ratio.
[0099] In some embodiments of the array substrate provided in this disclosure, as shown in Figures 13 and 18, in the row gap H-GP1 within the pixel electrode group P, two transistors 105 connected to the same data line 104 can be arranged side-by-side along the column direction Y on one side of the data line 104 (the projections of the two transistors 105 in the direction of the data line 104 overlap, and the gate lines 103 electrically connected to the two transistors 105 are located between adjacent rows of pixel electrodes 102). This facilitates the data line 104 to be electrically connected to the upper and lower pixel electrodes 102 of adjacent rows and columns within the pixel electrode group P through the two transistors 105 respectively. Optionally, the data line 104 of this disclosure may include a widened portion WP between two adjacent gate lines 103 in the row gaps H-GP1 and H-GP2. The widened portion WP may overlap with the projection of the spacer ps to support the spacer ps. The spacer ps may be disposed on the array substrate and / or the opposing substrate (also called the color filter substrate), which is not limited in this disclosure.
[0100] In some embodiments, the array substrate provided in the present disclosure, as shown in Figures 13, 16, and 18, may further include first leads 116 located in inter-group row gaps H-GP1 and intra-group row gaps H-GP2. These first leads 116 may be in the same layer and material as the gate lines 103. Furthermore, if the layer containing the gate lines 103 and the layer containing the pixel electrodes 102 are fabricated using the same mask, a pattern overlapping with the first leads 116 may also exist in the layer containing the pixel electrodes 102. In some embodiments, the transistor 105 may include a first transistor 1051 and a second transistor 1052. The first transistor 1051 is electrically connected to the pixel electrodes 102 spaced apart from its connected data lines 104 via the first leads 116, and the second transistor 1052 is electrically connected to the pixel electrodes 102 adjacent to its connected data lines 104.
[0101] In some embodiments, as shown in Figures 13, 16, and 18 to 20, this disclosure may further include a second common electrode line 117 that penetrates the inter-row gap V-GP1 of the pixel electrode group P and is in the same layer and material as the data line 104. The second common electrode line 117 and the connecting line 108 are electrically connected via a transition electrode 113 through a third via V3 (penetrating the first insulating layer 112 and the second insulating layer 114). Optionally, the third via V3 is located between two gate lines 103 within the same row gap (including the inter-group row gap H-GP1 and the intra-group row gap H-GP2). In some embodiments, the orthographic projection of the first lead 116 on the substrate 101 overlaps with the orthographic projection of the second common electrode line 117 on the substrate 101, thereby causing the load of the pixel electrode 102 connected to the first transistor 1051 through the first lead 116 to be different from the load of the pixel electrode 102 directly connected to the second transistor 1052. To ensure that the load on different pixel electrodes 102 is the same, this disclosure can provide a second lead 118 that is in the same layer and made of the same material as the first lead 116. The second lead 118 is integrally disposed with the pixel electrode 102 connected to the second transistor 1052, and the orthographic projection of the second lead 118 on the substrate 101 overlaps with the orthographic projection of the second common electrode line 117 on the substrate 101. For clarity, FIG21 shows the enlarged structure of the Z4 region in FIG13.
[0102] In some embodiments, in the array substrate provided in this disclosure, as shown in FIG12 and FIG21, the gate line 103 may include a groove GV opening toward the pixel electrode 102. The orthogonal projection of the second electrode d of the transistor 105 on the substrate 101 may overlap with the orthogonal projections of the gate line 103 on the substrate 101 on both sides of the groove GV column direction Y (i.e., the left and right sides in the figure). In this way, regardless of the process fluctuations in the process where the second electrode d of the transistor 105 is offset to the left or right relative to the gate line 103, it can be ensured that the Cgs of each transistor 105 is similar or even the same, where Cgs is the overlap capacitance between the gate g and the source drain s&d of the transistor 105, Cgs=εS / 4πkd, ε is a constant, S is the area of the gate g and the source drain d&s facing each other, d is the distance between the gate g and the source drain d&s, and k is an electrostatic constant.
[0103] In some embodiments, in the array substrate provided in the present disclosure, a semiconductor layer (including but not limited to amorphous silicon layer, polycrystalline silicon layer, indium gallium zinc oxide layer, etc.) for fabricating the active layer act of the transistor 105 and a metal conductive layer for fabricating the data line 104 can be formed sequentially. The patterns of the active layer act and the layer where the data line 104 is located can be prepared using a mask. In this case, as shown in FIG7, FIG8, FIG17 and FIG18, there is a second similar pattern SD' in the active layer act that is similar to the layer where the data line 104 is located. Due to the influence of process factors such as exposure diffraction, the second similar pattern SD' will expand outward relative to the pattern of the layer where the data line 104 is located.
[0104] Based on the same inventive concept, this disclosure provides a display panel, as shown in Figures 22 to 25, including an array substrate 001 and a counter substrate 002 placed opposite each other. The array substrate 001 is the same as described in this disclosure, and the counter substrate 002 may include a black matrix BM, a red color resist CF-R, a green color resist CF-G, a blue color resist CF-B, and spacers ps. In some embodiments, the black matrix BM, red color resist CF-R, green color resist CF-G, blue color resist CF-B, and spacers ps may also be disposed on the array substrate 001; this disclosure does not specifically limit this. Since the principle by which this display panel solves the problem is similar to that of the array substrate described above, the implementation of this display panel can refer to the embodiments of the array substrate described above, and repeated details will not be elaborated further.
[0105] In some embodiments, as shown in FIG25, the display panel provided in this disclosure may further include a liquid crystal layer 003 between an array substrate 001 and a counter substrate 002, a first polarizer 004 on the side of the array substrate 001 away from the counter substrate 002, and a second polarizer 005 on the side of the counter substrate 002 away from the array substrate 001, wherein the polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are those which should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.
[0106] Based on the same inventive concept, this disclosure provides a display device, as shown in FIG25, including the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature light-emitting diodes (Mini LEDs, Micro LEDs, etc.).
[0107] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.
[0108] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, or personal digital assistant. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as a radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.
[0109] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.
[0110] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.
Claims
1. An array substrate, wherein, include: Substrate; Multiple pixel electrodes are arranged in an array on the substrate, and each pair of four pixel electrodes in two adjacent rows and two columns constitutes a pixel electrode group. Multiple gate lines are provided, with two gate lines between two adjacent rows of pixel electrodes, and the pixel electrodes in the same row correspond to the two gate lines. The gate lines corresponding to the odd-numbered pixel electrodes in the same row and the gate lines corresponding to the even-numbered pixel electrodes in the same row are located on both sides of the pixel electrodes in that row. Multiple data lines are provided, with one data line between two adjacent columns of pixel electrode groups. Multiple pixel electrode groups in the same column correspond to two data lines, and the data lines corresponding to the odd-numbered pixel electrode groups and the data lines corresponding to the even-numbered pixel electrode groups in the same column are located on both sides of the pixel electrode groups in that column. Multiple transistors, wherein the gate of each transistor is electrically connected to the gate line, the first electrode of each transistor is electrically connected to the data line, and the second electrode of each transistor is electrically connected to the pixel electrode; In at least a portion of the row gaps of the pixel electrodes, two transistors connected to the same data line are at least partially offset along the row direction.
2. The array substrate as claimed in claim 1, wherein, In the row gaps between the pixel electrode groups, the two transistors connected to the same data line are located on opposite sides of the data line.
3. The array substrate as described in claim 1 or 2, wherein, In the row gaps between the pixel electrode groups, the two transistors between two adjacent data lines are arranged in a direction that intersects both the row direction and the column direction.
4. The array substrate as described in claim 2 or 3, wherein, It also includes a first branch line located in the row gap between the pixel electrode groups, the first branch line being led out from the data line and extending along the row direction between the two gate lines before being electrically connected to the first electrode of the transistor.
5. The array substrate as claimed in claim 4, wherein, The two first branch lines between two adjacent data lines extend along the row direction between the two gate lines and then bend to be electrically connected to the first electrode of the transistor; or, the two first branch lines between two adjacent data lines extend along the row direction between the two gate lines and then are directly electrically connected to the first electrode of the transistor.
6. The array substrate as claimed in claim 4 or 5, wherein, In the row gaps between the pixel electrode groups, two first branch lines are drawn from the middle data lines of every three adjacent data lines at a first position and a second position that are staggered from each other in the column direction. Two first branch lines are drawn from the data lines near the first position at two positions that are approximately collinear with the second position in the row direction. Two first branch lines are drawn from the data lines near the second position at two positions that are approximately collinear with the first position in the row direction.
7. The array substrate according to any one of claims 4 to 6, wherein, It also includes a common electrode that overlaps with the pixel electrode, and a connecting line integrally formed with the common electrode; Within one of the row gaps between two adjacent groups of the pixel electrode group: the orthographic projections of the two first branch lines derived from the middle data line of every three adjacent data lines on the substrate and the orthographic projection of the connecting line on the substrate do not overlap; the orthographic projections of the first branch lines derived from the data lines on both sides near the middle data line on the substrate and the connecting line on the substrate do not overlap; the orthographic projections of the first branch lines derived from the data lines on both sides away from the middle data line on the substrate and the connecting line on the substrate overlap. Within the other group: the orthographic projections of the two first branch lines derived from the middle data line of every three adjacent data lines on the substrate and the connecting line on the substrate overlap; the orthographic projections of the first branch lines derived from the data lines on both sides near the middle data line on the substrate and the connecting line on the substrate overlap; the orthographic projections of the first branch lines derived from the data lines on both sides away from the middle data line on the substrate and the connecting line on the substrate do not overlap.
8. The array substrate according to any one of claims 1 to 7, wherein, In the row spacing within the pixel electrode group, two transistors connected to the same data line are staggered along the row direction on one side of the data line.
9. The array substrate according to any one of claims 1 to 8, wherein, Between two adjacent data lines: the arrangement direction of the two transistors in the row gap within the pixel electrode group is approximately the same as the arrangement direction of the two transistors in the row gap between the pixel electrode groups.
10. The array substrate as claimed in claim 8 or 9, wherein, It also includes a second branch line located in the row gap within the pixel electrode group. The second branch line is led out from the data line and extends along the row direction between the two gate lines before being electrically connected to the first poles of the two transistors respectively.
11. The array substrate as claimed in claim 10, wherein, It also includes a common electrode that overlaps with the pixel electrode, and a connecting line integrally formed with the common electrode; The orthographic projection of the second branch line on the substrate overlaps with the orthographic projection of the connecting line on the substrate.
12. The array substrate as claimed in claim 11, wherein, It also includes a third branch line within the row gap between the pixel electrode groups, the third branch line being drawn from the side of the same data line away from the second branch line and extending between the two gate lines.
13. The array substrate as claimed in claim 12, wherein, The orthographic projection of the third branch line drawn from one of the row gaps in two adjacent pixel electrode groups on the substrate overlaps with the orthographic projection of the connecting line on the substrate; the orthographic projection of the third branch line drawn from the other does not overlap with the orthographic projection of the connecting line on the substrate.
14. The array substrate as claimed in claim 12, wherein, The orthographic projections of each of the third branch lines on the substrate overlap with the orthographic projections of the connecting lines on the substrate, or the orthographic projections of each of the third branch lines on the substrate do not overlap with the orthographic projections of the connecting lines on the substrate.
15. The array substrate according to any one of claims 1 to 14, wherein, It also includes a common electrode overlapping the pixel electrode, a connecting line integrally formed with the common electrode, and a first common electrode line within the column gaps of the pixel electrode group; wherein... The first common electrode line is on the same layer as the data line, and the first common electrode line is connected between adjacent connection lines in the column direction.
16. The array substrate as claimed in claim 2 or 3, wherein, It also includes a fourth branch line located in the row gap between the pixel electrode groups, the fourth branch line being led out obliquely from the data line to be electrically connected to the first electrode of the transistor.
17. The array substrate as claimed in claim 16, wherein, In the row gap between the pixel electrode groups, the data line leads out two fourth branch lines at two positions that are staggered from each other in the direction of intersection with the fourth branch line.
18. The array substrate according to any one of claims 1 to 3, 16, and 17, wherein, In the row gaps within the pixel electrode group, two transistors connected to the same data line are arranged side-by-side along the column direction on one side of the data line.
19. The array substrate according to any one of claims 16 to 18, wherein, It also includes the first lead; The transistor includes a first transistor, which is electrically connected to the pixel electrode spaced apart from the data line connected to it via the first lead.
20. The array substrate as claimed in claim 19, wherein, It also includes a second common electrode line extending between the pixel electrode groups, wherein the orthographic projection of the first lead on the substrate and the orthographic projection of the second common electrode line on the substrate overlap each other.
21. The array substrate as claimed in claim 20, wherein, The transistor further includes a second transistor, which is electrically connected to the pixel electrode adjacent to the data line to which it is connected; The array substrate further includes a second lead in the same layer as the first lead. The second lead is integrally disposed with the pixel electrode connected to the second transistor, and the orthogonal projection of the second lead on the substrate overlaps with the orthogonal projection of the second common electrode line on the substrate.
22. The array substrate according to any one of claims 16 to 21, wherein, It also includes a common electrode that overlaps with the pixel electrode, a connecting line integrally formed with the common electrode, and a second common electrode line extending between the row gaps of the pixel electrode group, wherein the second common electrode line and the connecting line are electrically connected between two gate lines in the same row gap.
23. The array substrate according to any one of claims 1 to 22, wherein, The gate line includes a groove opening toward the pixel electrode, and the orthographic projection of the second electrode of the transistor on the substrate overlaps with the orthographic projection of the gate line on both sides of the groove row direction on the substrate.
24. A display panel, wherein, It includes the array substrate as described in any one of claims 1 to 23, and a counter substrate positioned opposite to the array substrate.
25. A display device, wherein, It includes the display panel as described in claim 24, and a backlight module located on the light-incident side of the display panel.