Artificial intelligence system and method for flattening transistor-level layout and wiring of digital circuits

Abstract

In integrated circuits, a method for flattening and / or routing multiple transistors using an artificial intelligence (AI) model includes the following steps: receiving input consisting of a circuit schematic and features; performing supervised or unsupervised learning of the AI ​​model to generate layouts and / or routings predicted by the AI ​​model; and using a cost function to optimize the transistor layouts and / or routings. Optimal layouts and / or routings are generated by: iteratively running a loop of layouts and / or routings based on the AI ​​model; assigning values ​​to each layout and / or routing combination according to the cost function, and recording layout and / or routing and value information during the executed iterations until a predetermined metric is met, a predetermined number of iterations is exceeded, or time has elapsed; ranking each generated layout and / or routing combination according to the cost function; and selecting the top k (k=1,2,....) layout and / or routing combinations.

Description

[0001] References

[0002] U.S. Patent Documents

[0003] USP 11,087,060. System, method, and computer program product for the integration of machine learning predictors in an automatic placement associated with an electronic design.

[0004] USP 11,275,882. System, method, and computer program product for group and isolation prediction using machine learning and applications in analog placement and sizing.

[0005] USP 11,348,000. System, method, and computer program product for routing in an electronic design using deep learning.

[0006] USP 11,386,322. System, method, and computer program product for routing in an electronic design using deep learning.

[0007] Other References

[0008] W. T. J. Chan et al., "BEOL stack-aware routability prediction from placement using data mining techniques," in 2016 IEEE 34th International Conference on Computer Design (ICCD). IEEE, 2016, pp. 41–48.

[0009] R. Liang et al., “DRC hotspot prediction at sub-10nm process nodesusing customized convolutional network,” in Proceedings of the 2020International Symposium on Physical Design, 2020, pp. 135–142.

[0010] H. Wang et al., “GCN-RL Circuit Designer: Transferable TransistorSizing with Graph Neural Networks and Reinforcement Learning, ” 2020 57thACM / IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2020,pp. 1-6, doi: 10.1109 / DAC18072.2020.9218757.

[0011] H. Liao et al., “Attention routing: track-assignment detailed routingusing attention-based reinforcement learning,” in ASME 2020 InternationalDesign Engineering Technical Conferences and Computers and Information inEngineering Conference. American Society of Mechanical Engineers DigitalCollection, 2020.

[0012] H. Liao et al., “A deep reinforcement learning approach for globalrouting,” Journal of Mechanical Design, vol. 142, no. 6, 2020.

[0013] A. Mirhoseini et al., “A graph placement methodology for fast chipdesign,” Nature, vol. 594, no. 7862, pp. 207–212, 2021.

[0014] Placement Optimization via PPA-Directed Graph Clustering. Yi-Chen Luet al., MLCAD '22: Proceedings of the 2022 ACM / IEEE Workshop on MachineLearning for CAD. September 2022. Pages 1–6, 2021.

[0015] NVCell: Standard Cell Layout in Advanced Technology Nodes withReinforcement Learning. H. Ren et al., 2021 58th ACM / IEEE Design AutomationConference (DAC), pp. 1291-1294, 2021.

[0016] Towards Machine Learning for Placement and Routing in Chip Design: aMethodological Overview. arXiv,Pub Date: 2022-02-28 , DOI:arxiv-2202.13564.J. Yan et al.,

[0017] AI / ML Algorithms and Applications in VLSI Design and Technology. D.Amuru et al., https: / / arxiv.org / abs / 2202.10015, 2022.

[0018] Hu J. and Sachin S. Sapatnekar, A survey on multi-net global routing for integrated circuits, Integration. Volume 31, Issue 1, November 2001, pp.1-49.

[0019] R. Luo et al., AlphaTruss : Monte Carlo Tree Search for Optimal TrussLayout Design Buildings, Volume 12, Issue 5, 641 (2022)

[0020] Silver, D., Schrittwieser, J., Simonyan, K. et al. Mastering the game of Go without human knowledge. Nature 550, 354–359 (2017). https: / / doi.org / 10.1038 / nature24270

[0021] Schrittwieser, J., Antonoglou, I., Hubert, T. et al. Mastering Atari,Go, chess and shogi by planning with a learned model. Nature 588, 604–609(2020). https: / / doi.org / 10.1038 / s41586-020-03051-4 Technical Field

[0022] This invention relates to the field of digital circuits. More specifically, this invention relates to the use of artificial intelligence (AI) systems and methods in the automated transistor-level placement and routing of flattened digital circuits comprising a large number of transistors, wherein no domain expert information is required and the work exceeds human capabilities. Background Technology

[0023] Modern processors consist of blocks that perform different functions, such as input / output (I / O), memory, internet connectivity, video processing, audio processing, and arithmetic calculations. These blocks are designed in a hierarchical structure using standard cells, custom circuits, or both.

[0024] Hierarchical design (a standard practice in processor design) refers to an integrated circuit or a portion thereof (i.e., a block of (one or more) standard cells) consisting of multiple sub-circuits (i.e., groups of multiple standard cells) or standard cells used as building blocks, where global placement is performed by locating and interconnecting the standard cells or sub-circuits. This is the opposite of flattened design, which has no hierarchy and where transistors themselves serve as building blocks. Hierarchical design is often practiced to circumvent the exponentially increasing complexity of digital circuits (i.e., as the number of transistors increases).

[0025] The described systems and methods are particularly applicable to standard cells and flattened digital circuits comprising a large number of transistors, resulting in a vast number of possible layout and routing combinations that exceed human capabilities. Most existing transistor-level layout and routing systems and methods are limited to manual layout (i.e., by human layout editors) or to automated tools designed to improve productivity rather than power-to-apply (PPA). Existing automated tools use symbolic layout presets for grouping p-type or n-type transistors with different np row pattern alternatives (where n and p represent n-type and p-type transistors, respectively). These methods are based on presets of pre-layouts of commonly used patterns and are designed to simplify layout editing tasks rather than optimize them. They typically begin by providing the layout editor with an initial layout and a limited set of row layout arrangements (e.g., np, pn, nppn, pnnp, npnp, etc.) to choose from, allowing for further manual modification of the layout to improve the initially proposed layout. However, this approach is limited to a relatively small number of transistors and does not utilize artificial intelligence methods. Furthermore, the results depend heavily on the layout editor's skill, experience, and creativity, and it does not span the entire set of possible layouts and routings.

[0026] The artificial intelligence methods disclosed in the context of this invention focus on die-level optimization rather than standard cell or circuit-level optimization. USP 11,087,060 describes a method for training a machine learning system to predict the layout of a second processor's schematic and layout under various constraints using schematics and layouts of existing processors.

[0027] USP 11,275,882 extends USP 11,087,060 for analog circuit systems and describes machine learning methods (such as genetic algorithms or random forests) applied to schematics and layouts of existing processors to classify (i.e., predict) whether two transistors of a second processor can be grouped together, resized, and oriented to automatically generate an analog layout of the second processor based on the schematic of the second processor. However, the reported recall (86%) and precision (86%) are insufficient for practical implementations.

[0028] USP 11,348,000 and USP 11,386,322 further extend the prior invention by using a deep neural network to perform global routing of a processor. They describe a method for training a deep neural network using a schematic of an existing processor and its global routing data to generate detailed routing data, at least in part, based on the global routing data. The deep neural network is trained using the schematic of an existing processor and its global routing data to generate features. Then, when a schematic of a second processor is fed into the neural network, the neural network generates detailed global routing for the second processor.

[0029] Recent literature is filled with research papers on using AI methods for processor design, and commercial products (at the processor level) are already available. WTJ Chan et al., “BEOL stack-aware routability prediction from placement using data mining techniques”, discusses, but is not publicly available, a machine learning model for predicting (i.e., classifying the effectiveness of processor placement and routing schemes) whether a processor-level placement solution is routerble without experimentation or the use of early global routing for the global placement and interconnection of standard cells. This paper focuses primarily on congestion and violations of post-routing design rule checking (DRC – verifying whether a particular design meets the constraints imposed by the process technology to be used in its manufacture). Given a netlist, clock cycles, area utilization, aspect ratio, and back-end processes (BEOL is a stage in the design process that focuses on the placement and routing of various components on the chip), the amount of metal, and a stack-specific placement, their model predicts whether the processor placement is routerble. The reported results for 28nm and 45nm CMOS technology processors are 91% precision and 86% recall, which still require human intervention because there are still a large number of false positives and a small number of false negatives in the classification results of their test dataset.

[0030] R. Liang et al. presented “DRC hotspot prediction at sub-10nm process nodes using customized convolutional network” at the 2020 International Symposium on Physical Design. This is a convolutional neural network (CNN) that predicts DRC hotspots at sub-10nm technology nodes in the early stages of routing; that is, for global routing congestion or blockage (i.e., pin access issues). They trained a modified version of the public domain segmentation CNN (U-Net) for 27 hours on 166 layout instances across twelve 7nm designs and pin images. The inference used to predict Design Rule Check (DRC) violation hotspots in early-stage routing resulted in a true confidence rate (TPR) of 78% and a false confidence rate (FPR) of 9%, which is insufficient for fully automated DRC.

[0031] Wang et al., “GCN-RL Circuit Designer: Transferable Transistor Sizingwith Graph Neural Networks and Reinforcement Learning,” discloses a graph convolutional neural network (GCN) combined with reinforcement learning to perform automatic transistor sizing by fully leveraging reinforcement learning's knowledge of transfer between different technology nodes and circuit topologies used in mixed-signal integrated circuits, for migrating analog circuits from one technology node to another. The GCN is used to handle the connectivity relationships between components in analog circuits. The model is designed for mixed-signal ICs, thus using a variety of transistor parameters as well as capacitors and resistors as features. However, as they report, their model is suitable for older planar CMOS transistors (e.g., migrating analog designs from 180nm to 45nm) but not for advanced digital FinFET technologies, such as where transistor width is quantized as fins. Furthermore, the model is limited by the fixed topology of the transistors, as their goal is to migrate specific analog circuits from older technologies (e.g., 250nm) to more advanced nodes (e.g., 65nm). Interestingly, R. Luo et al., in “AlphaTruss: Monte Carlo Tree Search for Optimal Truss Layout Design,” describe a reinforcement learning algorithm for optimizing truss layouts, which bears some resemblance to transistor interconnects. Jiang Hu and Sachin S. Sapatnekar, in “A Survey on Multi-net Global Routing for Integrated Circuits,” Integration, volume 31, Issue 1, November 2001, pp. 1-49, discuss global routing methods that address a set (i.e., blocks / macros) N = {N1, N2, ..., Nk} of networks to be routed on an acyclic directed graph, and can be simplified to finding the shortest path connecting two pins in the presence of wiring congestion and blocking. They review traditional methods such as sequential routing and hierarchical routing techniques, as well as other techniques such as move-based heuristics and iterative deletion. While most traditional routing techniques focus on congestion, new objectives such as timing and crosstalk emerge on top of congestion.

[0032] As can be seen, most existing technologies describe the use of AI systems and methods for chip-level placement and routing, focusing on the global placement of digital blocks and / or standard cells throughout a finite die area (i.e., on a canvas) in a hierarchical design, where constraints are at the macro level; that is, cell-to-cell or block-to-block design rules, or in some cases, for analog circuits. Hierarchical design (standard practice) refers to an integrated circuit or a portion thereof (i.e., a block of (one or more) standard cells) consisting of multiple sub-circuits (i.e., groups of multiple standard cells) or standard cells used as building blocks, such that global placement is performed by locating and interconnecting the standard cells or sub-circuits. This contrasts with flattened designs where there is no hierarchy and the transistors themselves serve as building blocks. Hierarchical design is commonly practiced to circumvent the exponentially increasing complexity of digital circuits as the number of transistors increases.

[0033] Commercial tools using AI approaches optimize chip design flows by automating the entire design process, replacing the common manual tuning (iterative) process, with a focus on improving productivity and runtime. Machine learning-driven RTL-to-GDS (Register Transfer Level (RTL) design defines the logical functionality of a digital design at an abstract level before the physical layout of a specified circuit. Graphical Data Stream (GDS) is a binary file representing layout data in a hierarchical format. End-to-end optimization tools that concurrently optimize chip layout planning with (block or cell level) routing can also improve PPA, but are implemented at the chip level, not the transistor level.

[0034] Therefore, the objective of this invention is to provide a system and method for transistor layout and / or wiring within standard cells or flattened digital circuits to optimize power consumption, performance, and area (PPA).

[0035] Another objective of this invention is to provide a system and method for transistor placement and / or wiring within standard cells or flattened digital circuits, applicable to standard cells or any digital circuits comprising a large number of transistors characterized by a vast array of placement and / or wiring combinations beyond human capability; for optimizing PPA. Summary of the Invention

[0036] In integrated circuits, a method for flattening and / or routing multiple transistors using an artificial intelligence (AI) model includes the following steps: a) Receives an input consisting of a circuit schematic and features; b) Perform supervised or unsupervised learning of the AI ​​model to generate layout and / or wiring predicted by the AI ​​model; c) Use cost functions to optimize transistor placement and / or routing; d) Generate optimal layout and / or routing through the following operations: d.1) Based on the AI ​​model, iteratively run a loop for layout and / or routing; d.2) Assign values ​​to each layout and / or routing combination according to the cost function, and record layout and / or routing and value information during the executed iterations until a predetermined metric is met or a predetermined number of iterations is exceeded or time has elapsed; d.3) Rank each generated layout and / or routing according to the cost function; and d.4) Select the first k (k=1,2,....) layout and / or routing combinations.

[0037] In an embodiment, the method may include the following steps: a) Provide neural networks (NN); b) Provide Monte Carlo Tree (MCT); c) Provide a cost function; d) Receive input consisting of a circuit schematic, transistor characteristics, and a set of design rules; e) Generate a set of layout and / or wiring predictions for training the neural network (NN); f) Train the neural network with the generated set to produce predicted policies and values; g) Based on the predicted strategies and values ​​generated by the neural network (NN), the optimal layout and / or routing are generated by iteratively running the MCT in a loop as an iteration of the Monte Carlo Tree (MCT); h) Generate optimal layout and / or routing through the following operations: d.1) Based on the AI ​​model, iteratively run a loop for layout and / or routing; d.2) Assign values ​​to each layout and / or routing combination according to the cost function, and record layout and value information during the executed iterations until a predetermined metric is met or a predetermined number of iterations is exceeded or time has elapsed; d.3) Rank each generated layout and / or routing according to the cost function; and d.4) Select the first k (k=1,2,....) layout and / or routing combinations.

[0038] In an embodiment, any sequence of nodes representing a path down to a leaf in a Monte Carlo tree (MCT) can be a layout combination.

[0039] In the embodiments, only layout combinations that satisfy the design rules after M iterations are allowed.

[0040] Cost (reward) function L It could be:

[0041] in , and It is a normalization constant. It is the total length of the connecting lines. It is the total number of intersections of the lines, and It is the total area of ​​the layout.

[0042] Cost functions can be used, including different function forms and different measures, or any combination of area, line length, line intersection and other measures.

[0043] The method may also include the following steps: a) Store the best layout or the top k layouts (k > 1, any); b) Perform another loop for M iterations and prune nodes that have been visited in previous iterations; c) Retrain the NN on the newly pruned tree with pruned nodes to generate policies and values; and d) The layout and / or routing process is performed iteratively, and the process is terminated after a predetermined number of M derivations.

[0044] The optimal layout and / or routing process may terminate when certain criteria are met, or after a predetermined number of iterations, or after a predetermined runtime has elapsed.

[0045] Acyclic directed graphs can be used instead of tree structures, thereby reducing memory size and increasing speed.

[0046] A neural network can be a single neural network or a combination of multiple neural networks of the same or different types.

[0047] Neural networks can be selected from the following groups: - Graph neural networks used for input embeddings; - Convolutional neural networks used for layout embeddings; - Dense neural networks for feature embedding; - Dense neural networks for policy and value generation.

[0048] Netlists or RTL code can be used as input for synthesizing netlists.

[0049] The cost function can reflect the total area, total wiring, or both, and is any function that minimizes the layout area and / or wiring length.

[0050] The cost function can be any of the following functional forms: - Circuit area; - Length of the connection; - The lines intersect; - Specific design rules; - Transistor characteristics.

[0051] In an embodiment, the method may include the following steps: a) Input the circuit netlist and the characteristics of its transistors into a graph neural network (GNN), which generates a two-dimensional (2D) feature array of size N×h, where N is the total number of transistors and h is the hidden layer size; b) Flatten a 2D array of size N×h by reducing its dimension, and feed the flattened 2D array into MLP1, which outputs a vector of size m. c) Feed a vector of unique identifiers (UINs) for the location of each transistor in the previous layout and / or wiring predictions into the convolutional neural network and generate an output vector of size n; d) Combine vectors of size m and n and feed the concatenated vectors into a dense neural network to generate new policies and values.

[0052] In this embodiment, the outputs of the neural network MLP1 and CNN can be concatenated.

[0053] The output of a neural network can be a single output.

[0054] Neural networks can either generate policies to infer policies that maximize rewards, or generate values ​​to infer values ​​for predicted layouts.

[0055] Transistor characteristics can include a unique identifier (UIN) for the location, transistor type, threshold voltage, number or width of fins, gate length, or number of gate fingers.

[0056] A partial list of transistor characteristics, or an extended list with additional characteristics, can be used as input to a neural network.

[0057] The input to a neural network can be a concatenated vector of transistor UINs, a two-dimensional array of the X and Y positions of transistors, or any type of data format containing transistor position information, such as an image file.

[0058] The initial weights of a neural network can be pre-trained on a smaller circuit with fewer transistors, uniformly distributed, or determined according to AI-related methods.

[0059] UIN can be a decimal or binary representation of the transistor location in the layout, or a one-hot encoded representation of the transistor location in the layout, where any unique representation can be used as UIN.

[0060] Each type of transistor can have a variable channel width, including different numbers of fins in a FinFET, or a stack of all-around gate or complementary FETs.

[0061] The predetermined score can be the standard confidence upper limit (UCB) score.

[0062] This document discloses systems and methods for flattening transistor-level placement and / or routing of digital circuits using artificial intelligence. Specifically, reinforcement learning (RL) placement and / or routing of transistors within a flattened circuit is described. An RL agent interacts with the environment of a standard cell or circuit and performs the placement and / or routing of transistors. An optimal transistor placement and / or routing is generated corresponding to the minimum cost function subject to manufacturing design rules (DR). The embodiments herein particularly relate to transistor-level design of standard cells and circuits. This invention is applicable to any type of field-effect transistor structure, such as planar CMOS, FinFET, gate all-around (GAA), complementary field-effect transistors, etc. A FinFET is a type of FET where the conductive channel is a thin vertical fin, rather than the surface-buried plane of a planar CMOS FET. A gate all-around (GAA) FET is a modified transistor structure where the gate surrounds a linear conductive channel. A complementary field-effect transistor (CFET) is a device type where nMOS and pMOS GAA transistors are stacked on top of each other, thereby allowing for further maximization of the effective channel width.

[0063] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. While similar or equivalent methods and materials to those described herein may be used in the practice or testing of embodiments of the invention, exemplary methods and / or materials are described below. In the event of conflict, the patent specification (including its limitations) shall prevail. Furthermore, materials, methods, and examples are merely illustrative and not intended to be necessarily limiting. The terms wire, wiring, and interconnection are used interchangeably. Attached Figure Description

[0064] Referring to the accompanying drawings, the above and other features and advantages of the invention will be better understood from the following illustrative and non-limiting detailed description of its preferred embodiments, wherein: Figure 1 It is a simplified general block diagram of conventional implementations of reinforcement learning systems and methods; Figure 2 This is a block diagram embodiment of the reinforcement learning system and method of the present invention; Figure 3 This is a block diagram embodiment of the neural network system of the present invention; Figure 4It represents the circuit netlist as an acyclic graph, where A and B are the circuit inputs and Out is the circuit output; gray transistors are p-type and white transistors are n-type. Figure 5a The illustration shows an implementation of the type grouping design rule for the single-track transistor of the present invention; the gray transistor is p-type and the white transistor is n-type; Figure 5b The illustration shows an implementation of the type grouping design rule for the dual-track transistor of the present invention; the gray transistor is p-type and the white transistor is n-type; Figure 6 The illustration shows an implementation of the transistor type and threshold voltage design rules of the present invention; the gray transistor is p-type and the white transistor is n-type; Figures 7a-7b The illustrations depict different design rules for embodiments of the transistor's fins and fill cells (specified as 1 grid); Figure 7c The illustration shows an embodiment of the transistor fin with a fill-free design rule according to the present invention; and Figure 7d The illustration shows the transistor layout design rules of the present invention following the fill cell implementation. Detailed Implementation

[0065] This invention describes a system and method for flattening, transistor-level, placement, and / or routing standard cells and digital circuits using artificial intelligence (AI) methods, performed by an AI model conducting supervised or unsupervised learning. The system and method described in this invention generate multiple possible placement and / or routing solutions subject to DR constraints, ranked by a cost function, from which a human circuit layout editor can select based on various metric considerations.

[0066] The systems and methods described in this paper relate to optimizing standard cells and flattened digital circuits at the transistor level using artificial intelligence (AI) methods, and particularly to reinforcement learning (RL) for transistor placement and / or routing within standard cells or flattened digital circuits to optimize power consumption, performance, and area (PPA).

[0067] The proposed system and method provide local placement and / or routing of transistors within standard cells and flattened digital circuits (with or without canvas constraints). The proposed transistor flattening placement and / or routing methods are subject to local, cell / circuit-level design rules, such as minimum distances between transistors with different threshold voltages, adjacency constraints, etc. (thousands of design rules must be satisfied in modern CMOS technology nodes). The embodiments described herein depict local routing methods that solve for a set of vertices V (i.e., transistors) to be routed through an acyclic directed graph, where V = {V1, V2, ..., Vk}, to find the minimum sum of the total lengths of all pin (edge) connections, the minimum area subject to design rules, or any other metric or combination of metrics. The proposed inventive method enables optimal placement and / or routing on flattened circuits with high transistor counts (beyond human capability due to the numerous possible layouts and / or combinations), significantly saving manpower and time and exceeding human capabilities. The described invention is particularly effective for large designs (i.e., those containing many transistors) and numerous design rules, even with complex trade-offs. Furthermore, this invention allows the complex hierarchical structure of digital integrated circuits, comprising a large number of standard cells and circuits, to be flattened into a single-layer transistor, which undergoes layout and / or wiring as a single circuit; to improve PPA. The proposed method is applicable to any type of field-effect transistor (FET) structure, such as planar CMOS, FinFET (a type of FET where the conductive channel is a thin vertical fin rather than a surface-buried plane), gate-all-around FET (GAA, a modified transistor structure where the gate surrounds a linear conductive channel), complementary field-effect transistor (CFET, an architecture where nmos and pmos GAA transistors are stacked on top of each other, thereby allowing for further maximization of the effective channel width), and any future FET architecture.

[0068] Figure 1A general block diagram of a reinforcement learning system for unsupervised learning of layout and / or wiring is presented, designed to save area and / or power consumption or improve any other metric or combination of metrics. Layout determines where to place transistors in a generally finite amount of space. Next is wiring, which determines how to connect the laid-out transistors; no domain expert information or dataset is required. First, circuit information is fed into a Monte Carlo Tree (MCT); MCT search (MCTS) is a heuristic search algorithm that allows searching for the best move to “play” (i.e., instead of systematically checking all possible moves and examining each move) by relying on statistics rather than full exploration, as described by Silver, D., Schrittwieser, J., Simonyan, K. et al. in “Mastering the game of Go without human knowledge,” Nature 550, 354–359 (2017). Compared to exhaustive search, it allows for efficient navigation of large state spaces.

[0069] In embodiments of the invention, MCTS is implemented to search for potentially permissible transistor layouts subject to design rule constraints. Based on intermediate results generated by MCT, a neural network 3 is trained to learn optimal layouts and / or routing. The training phase uses layout and / or routing data from previous MCT runs (i.e., simulations) to predict policies (i.e., the probability distribution of potential actions in a given state) and values ​​(i.e., the expected reward for selecting a sequence of states). A state is a unique configuration of the positions (x-position and y-position) of transistors in 2D space. Once trained, the neural network 3 is integrated into new MCT runs during the iteration process. The neural network 3 also evaluates states by providing policy and value estimates, which are used for tree search (to select more promising paths in the search space). In embodiments of the invention, an upper confidence limit (UCB) formula is used to select actions, which uses uncertainty in action value estimates to balance exploration and exploitation. The UCB formula balances exploitation (i.e., selecting the known best action) with exploration (i.e., exploring new actions).

[0070] In another embodiment of the invention, a neural network (NN) is used to select actions.

[0071] In yet another embodiment, other algorithms may be implemented for action selection. The layout and / or routing generation process is performed iteratively, thereby recording and evaluating layout and / or routing and value information in each iteration until it ends (e.g., after a predetermined metric is met or a predetermined number of iterations is exceeded or time has elapsed), thereby producing a ranked set of optimized transistor layouts and / or routings.

[0072] Neural networks can be graph neural networks for input embedding (e.g., described in Khemani, B., Patil, S., Kotecha, K. et al. A review of graph neural networks: concepts, architectures, techniques, challenges, datasets, applications, and future directions. J Big Data 11, 18 (2024)); convolutional neural networks for layout embedding (e.g., described in Zhao, X., Wang, L., Zhang, Y. et al. A review of convolutional neural networks in computer vision. Artificial Intelligence Review 57, 99 (2024)); dense neural networks for feature embedding (e.g., described in Leonardo FS Scabini and Odemir M. Bruno, Structure and performance of fully connected neural networks: Emerging complex network properties, Physica A: Statistical Mechanics and its Applications, Volume 615, (2023)); or dense neural networks for policy and value generation.

[0073] In another embodiment of the invention, one or more neural networks are implemented to learn the dynamics of the “game” itself (i.e., a neural network for approximating the dynamics of the environment) to estimate the quality of a move and the consequences of taking that move. The neural network is configured to represent the dynamics of the environment without training or constraints, as described by Schrittwieser, J., Antonoglou, I., Hubert, T. et al. Mastering Atari, Go, chess and shogi byplanning with a learned model. Nature 588, 604–609 (2020). https: / / doi.org / 10.1038 / s41586-020-03051-4

[0074] For a circuit containing N transistors, the depth of the MCT tree is N, which is the total number of transistors. Each sequence of child nodes in tree 2 (i.e., the path (downward to the leaf)) represents a possible layout. For n ≤ N leaves, there can be 2^N MCT trees. n A combination of layouts. In embodiments of the invention, reinforcement learning is used hierarchically in several steps, or in a single step that includes an environment, task, agent, and experiment for laying out and / or routing multiple transistors.

[0075] Figure 2 Embodiments according to the present invention are given. Figure 1 The implementation of the block diagram. Circuit schematics, transistor characteristics, and a set of design rules are used as input 6. Output 13 is the optimal layout and / or wiring, or the layout of a top-ranked set of transistors (i.e., the location and interconnection of transistors on the semiconductor wafer) and / or their interconnections. In embodiments of the invention, a netlist is used as input (a netlist is an abstract representation of a digital circuit). In another embodiment, RTL code (Register Transfer Level - Design Abstraction, which models synchronous digital circuits based on the flow of digital signals (data) between hardware registers and the logical operations performed on those signals) is used as input to synthesize the netlist. In yet another embodiment, any data file (e.g., an image file) containing schematics and features of the digital circuit can be used. The cost function (i.e., reward 9) is the total circuit area, the total number of interconnects, or both. In yet another embodiment, the cost function is any functional form of circuit area, interconnect length, interconnect crossovers, and specific design rules and transistor characteristics.

[0076] An initialization process, including M deductions (i.e., M iterations of the MCT), is used to create a dataset for training neural network 12. Neural network 12 is trained on the generated dataset to produce policy and value 11.

[0077] Subsequently, based on the strategies and values ​​predicted by the neural network (12), MCT7 is iteratively run (in M iterations) to generate optimal layout and / or routing. Any sequence of nodes (paths) leading down to the leaves is a layout combination. Of all the layout combinations in the M iterations, only those that satisfy the design rules are permissible. The AI ​​model is configured to provide predicted layout and / or routing.

[0078] Each layout in the generated layout is filtered and selected according to the constraints of the design rules 8, and is assigned a value (reward) according to the cost function 9.

[0079] In one embodiment, the cost (i.e., reward) function 9 is: [Equation 1] in , and It is a normalization constant. It is the total length of the connecting lines. It is the total number of intersections of the lines, and This refers to the total area of ​​the layout. In another embodiment of the invention, any function that minimizes the layout area and / or connection length can be used. In yet another embodiment, other cost functions can be used, including different function forms and different metrics, or any combination of area, connection length, connection intersection, and other metrics.

[0080] The system records layout and / or routing information and reward information in M ​​iterations. For an MCT (7) of depth d < N, d child nodes are repeatedly selected using a standard upper confidence (UCB) score or some other score until a leaf node is reached and a layout is generated. In another embodiment of the invention, a genetic algorithm or any other combinatorial optimization selection algorithm is used to select child nodes that descend to the leaf. The best layout or the top k (ranked) layouts (k > 1, e.g., k = 1, 2, 3, ...) are stored, and another loop of M iterations is performed after pruning nodes that have been visited in previous iterations, thereby reducing runtime. The neural network 12 is retrained on the newly pruned tree to generate policies and values ​​11. The process is performed iteratively until termination (e.g., until a predetermined metric is met or a predetermined number of iterations or elapsed time is exceeded), where the top k (k = 1, 2, ...) layout and / or routing combinations are selected. In an embodiment of the invention, the process terminates when a predetermined number of M iterations are reached. In another embodiment of the invention, the process is terminated based on a metric comparing the optimal layout result with the suboptimal layout result. In yet another embodiment, the process terminates when a specific criterion is met, or after performing a predetermined number of iterations, or after a predetermined running time has elapsed. In yet another embodiment, the process terminates after a predetermined number of iterations or after a predetermined elapsed time.

[0081] In an embodiment of the present invention, an acyclic directed graph is used instead of tree structure 7 to reduce memory size and shorten runtime.

[0082] In embodiments of the present invention, the neural network (12) includes one or more neural networks of the same or different types.

[0083] Figure 3 A block diagram of a neural network 12 according to an embodiment of the present invention is provided.

[0084] The circuit netlist 15 and the characteristics 14 of its transistors are input into a graph neural network (GNN) 17, which generates a two-dimensional (2D) feature array of size N×h, where N is the total number of transistors and h is the hidden layer size (i.e., h is a hyperparameter of the GNN).

[0085] A 2D array of size N×h is flattened and fed into MLP1 18, which outputs a vector of size m. Convolutional neural network 19 is fed a vector of unique identifiers (UINs) for the location of each transistor and generates an output vector of size n. Netlist 15 is an acyclic directed graph comprising N vertices (i.e., N transistors). Each transistor has 3 pins (gate, source, drain), and every two pins of different transistors are interconnected. Therefore, edges are described by an array of size [3N, 2], which is fed into GNN 17.

[0086] The outputs of neural networks MLP1 (18) and CNN (19) are combined and fed into MLP2 (20), whose output is the policy and the value. In an embodiment of the invention, the outputs of neural networks 19 and 18 are concatenated. In another embodiment of the invention, other functions that combine the outputs of neural networks 19 and 18 may be applied.

[0087] In embodiments of the invention, the output of the neural network 20 is a single output. In a single-output embodiment, the neural network 20 generates only a policy, inferring a policy that maximizes the reward; or it generates only values ​​to infer predicted layout and / or wiring values.

[0088] In an embodiment of the present invention, the transistor feature 14 is a unique identifier for the x and y positions, the transistor type, the threshold voltage, the number or width of the fins, and the gate length or the number of gate fingers.

[0089] In another embodiment of the invention, a partial list of the characteristics of the transistors or an extended list with additional characteristics is used as input to the neural network 17.

[0090] In an embodiment of the invention, the input to the neural network 19 is a concatenated vector of transistor UINs. The concatenated vector can be fed into a dense NN to generate new policies and values.

[0091] In another embodiment, the input to the neural network 19 is a two-dimensional array of transistor positions (i.e., X and Y positions). In yet another embodiment, the input to the neural network 19 is any type of data format containing transistor position information, such as an image file.

[0092] In embodiments of the present invention, the initial weights of the neural networks 17-20 are pre-trained on a smaller circuit (i.e., comprising fewer transistors), uniformly distributed, or determined according to AI-related methods known to those skilled in the art (e.g., random, normal distribution, etc.) or based on domain expert information.

[0093] In embodiments of the invention, UIN is a binary representation of the transistor positions in the layout (e.g., transistor numbers 5, 8, 24, 101, etc.). In another embodiment, it uses numbers such as Klimo, M., Luká The one-hot encoded UIN described in P. and Tarábek, P., “Deep Neural Networks Classification via Binary Error-Detecting Output Codes” in Applied Sciences, 11(8), (2021) (https: / / doi.org / 10.3390 / app11083563), serves as a representation of transistor locations in the layout. In yet another embodiment of the invention, any unique representation can be used as the UIN.

[0094] In an embodiment of the invention, MLP1 (18) is a dense neural network (i.e., a fully connected neural network), MLP2 (20) is a dense neural network, and CNN (19) is a convolutional neural network. In yet another embodiment of the invention, any known type of neural network is implemented for neural networks 17-20.

[0095] Figure 4 This is a diagram of a circuit consisting of six transistors of two types. Each transistor is represented by a rectangle. Gray transistors 24-26 are p-type and white transistors 27-29 are n-type. Each transistor has three pins (gate, source, drain). For clarity, only the gate pin is labeled. The circuit's inputs and outputs are A (21) and B (22), and the output is (23).

[0096] In embodiments of the present invention, only p-type, only n-type, or both types of transistors constitute the circuit.

[0097] In embodiments of the invention, the number of transistors is unlimited (subject to the limitations of modern memory). In embodiments of the invention, the circuit may include a single type of transistor or two types of transistors in equal or different numbers. In embodiments of the invention, the circuit may include multiple inputs and outputs, i.e., two or more; inputs or outputs.

[0098] In another embodiment, the transistor is a functionally inactive dummy transistor, or the terminals of the transistor are connected to act as a dummy diode, resistor, or capacitor.

[0099] Figure 5a Examples of single-track, in-track, and same-type transistor layout design rules are given. Gray rectangles 30-32 and rows 37-38 are p-type transistors, and white rectangles 33-35 and rows 36 and 40 are n-type transistors. For clarity, transistor pins and interconnections are omitted. Manufacturing DR specifies that transistors of the same type (e.g., 30-32, rows 37, 38) are limited to the same row (i.e., the same diffusion). Furthermore, p-type and n-type transistors should be laid out in groups. The smallest group consists of two transistors. Stacking two or more tracks is possible. Figure 5b In the dual-stack embodiment shown, the tracks are inverted to save space. In yet another embodiment, the tracks are not inverted. Figure 5b The design rules for a dual-track layout are given, in which a mirror-like inverted layout is implemented to save area.

[0100] Figure 6 An example of threshold voltage layout DR constraint is given. For clarity, transistor pins and interconnections are omitted. Transistors of the same type and the same threshold voltage are laid out side by side (e.g., p-type 41-42, 43-45, and n-type 48-50, 51-53). In embodiments of the invention, a minimum group of two transistors with the same threshold voltage (Vt) is implemented (e.g., 41-42). The layout of a single Vt transistor (e.g., 46) must be followed by a fill gap (47, 54) or a dummy transistor with the same Vt (e.g., to the right of HVt transistor 46, where HVt specifies a high threshold voltage transistor, SVt is a standard threshold voltage transistor, and LVt is a low threshold voltage transistor).

[0101] In embodiments of the present invention, any type of transistor can be manufactured with one of different threshold voltage (Vt) options (e.g., high Vt, standard Vt, low Vt, ultra-low Vt, etc.) and laid out according to relevant design rule constraints.

[0102] Figure 7 illustrates the fin-based DR layout of the present invention (e.g., for FinFET technology). For clarity, transistor pins and interconnections have been omitted. Figure 7a and Figure 7b Transistors 55-56 and 59-60, of the same type (n-type) and the same Vt but with different fins, are depicted. When transistors with different fins are arranged side by side (i.e., 55-56 or 59-60, adjacent to each other), fill cells (57, 58, a grid) or dummy transistors are laid out before any additional transistors are laid out from the left (58) or right (57).

[0103] Figure 7c The diagram illustrates the optimal DR scenario for generating the best layout relative to... Figure 7a The diagram depicts the arrangement of transistors 62-63 with the same fins on the right side.

[0104] Figure 7d Another layout DR scenario is given, in which transistors 65 and 67 with different fins are arranged next to the fill cell (66).

[0105] In embodiments of the invention, each type of transistor may have a variable channel width (including different numbers of fins for FinFETs, or stacks of all-around gates or complementary FETs). In embodiments of the invention, transistors with different gate lengths (including multi-gate transistors (i.e., multiple gate fingers)) are laid out and wired.

[0106] In embodiments of the invention, photolithographic design rules (e.g., "cutting") are implemented as additional constraints on layout and / or wiring. In yet another embodiment of the invention, wiring is implemented on several metal layers (e.g., M0, M1, M2...).

[0107] It should be recognized that certain features of the invention described in the context of a single embodiment for clarity may also be provided in combination in a single embodiment. Conversely, various features of the invention described in the context of a single embodiment for brevity may also be provided individually or in any suitable sub-combination, or suitably in any other described embodiment of the invention. Certain features described in the context of various embodiments should not be considered essential features of those embodiments unless the embodiments would not be operable without these elements.

[0108] Although the invention has been described in conjunction with specific embodiments thereof, it will be apparent to those skilled in the art that many substitutions, modifications, and variations will be readily apparent. Accordingly, it is intended to cover all such substitutions, modifications, and variations falling within the spirit and broad scope of the appended claims.

[0109] All publications, patents, and patent applications mentioned in this specification are incorporated herein by reference in their entirety, as if each individual publication, patent, or patent application were specifically and individually indicated to be incorporated herein by reference. Furthermore, any reference or identification of any reference in this application should not be construed as an admission that such reference is available as prior art to the invention. The use of section headings should not be construed as necessarily limiting.

Claims

1. A method for flattening and / or routing multiple transistors in an integrated circuit using an artificial intelligence (AI) model, comprising the following steps: a) Receives an input consisting of a circuit schematic and features; b) Perform supervised or unsupervised learning of the AI ​​model to generate layout and / or wiring predicted by the AI ​​model; c) Use cost functions to optimize transistor placement and / or routing; d) Generate optimal layout and / or routing through the following operations: d.1) Based on the AI ​​model, iteratively run a loop for layout and / or routing; d.2) Assign values ​​to each layout and / or routing combination according to the cost function, and record layout and / or routing and value information during the executed iterations until a predetermined metric is met or a predetermined number of iterations is exceeded or time has elapsed; d.3) Rank each generated layout and / or routing according to the cost function; as well as d.4) Select the first k (k=1,2,....) layout and / or routing combinations.

2. The method according to claim 1, comprising the following steps: a) Provide neural networks (NN); b) Provide Monte Carlo Tree (MCT); c) Provide a cost function; d) Receive input consisting of a circuit schematic, transistor characteristics, and a set of design rules; e) Generate a set of layout and / or wiring predictions for training the neural network (NN); f) Train the neural network (NN) with the generated set to produce predicted policies and values; g) Based on the predicted strategies and values ​​generated by the neural network (NN), the optimal layout and / or routing are generated by iteratively running the MCT in a loop as an iteration of the Monte Carlo Tree (MCT); h) Generate optimal layout and / or routing through the following operations: d.1) Based on the AI ​​model, iteratively run a loop for layout and / or routing; d.2) Assign values ​​to each layout and / or routing combination according to the cost function, and record layout and value information during the executed iterations until a predetermined metric is met or a predetermined number of iterations is exceeded or time has elapsed; d.3) Rank each generated layout and / or routing according to the cost function; as well as d.4) Select the first k (k=1,2,....) layout and / or routing combinations.

3. The method of claim 2, wherein any sequence of nodes representing a path down to a leaf in a Monte Carlo tree (MCT) is a layout combination.

4. The method according to claim 2, wherein only the layout combination of M derivations that satisfy the design rules is permissible.

5. The method of claim 2, wherein the cost (reward) function L is: wherein , and are normalization constants, is the total length of the lines, is the total number of intersections of the lines, and is the total area of the layout.

6. The method of claims 1 and 2, wherein a cost function is used, comprising different functional forms and different metrics, or any combination of area, line length, line intersection and other metrics.

7. The method according to claim 2, further comprising: e) Store the best layout or the top k layouts (k > 1, any); f) Perform another loop for M iterations and prune nodes that have been visited in previous iterations; g) Retrain the NN on the newly pruned tree with pruned nodes to produce policies and values; as well as h) The placement and / or routing process is performed iteratively, and the process is terminated after a predetermined number of M derivations.

8. The method of claim 2, wherein the process of optimal layout and / or routing terminates when a specific criterion is met, or terminates after performing a predetermined number of iterations, or terminates after a predetermined running time has elapsed.

9. The method of claim 2, wherein an acyclic directed graph is used instead of a tree structure, thereby reducing memory size and increasing speed.

10. The method according to claims 1 and 2, wherein the neural network is a single neural network or a combination of multiple neural networks of the same or different types.

11. The method according to claims 1 and 2, wherein the neural network (NN) is selected from the group consisting of: - Graph neural networks used for input embeddings; - Convolutional neural networks used for layout embeddings; - Dense neural networks for feature embedding; - Dense neural networks for policy and value generation.

12. The method of claims 1 and 2, wherein the netlist or RTL code is used as input to synthesize the netlist.

13. The method according to claims 1 and 2, wherein the cost function reflects the total area, total wiring, or both, and the cost function is any function that minimizes the layout area and / or wiring length.

14. The method according to claims 1 and 2, wherein the cost function is any functional form of one or more of the following: - Circuit area; - Length of the connection; - The lines intersect; - Specific design rules; - Transistor characteristics.

15. The method according to claim 2, comprising: a) Input the circuit netlist and the characteristics of its transistors into a graph neural network (GNN), which generates a two-dimensional (2D) feature array of size N×h, where N is the total number of transistors and h is the hidden layer size; b) Flatten a 2D array of size N×h by reducing its dimension, and feed the flattened 2D array into MLP1, which outputs a vector of size m. c) Feed a vector of unique identifiers (UINs) for the location of each transistor in the previous layout and / or wiring predictions into the convolutional neural network and generate an output vector of size n; d) Combine vectors of size m and n and feed the concatenated vectors into a dense neural network to generate new policies and values.

16. The method of claim 2, wherein the outputs of the neural network MLP1 and CNN are concatenated.

17. The method of claim 2, wherein the output of the neural network is a single output.

18. The method of claim 2, wherein the neural network generates only policies, infers policies that maximize rewards, or generates only values ​​to infer values ​​for predicted layouts.

19. The method of claim 2, wherein the characteristics of the transistor are a unique identifier (UIN) of the location, transistor type, threshold voltage, number or width of fins, gate length or number of gate fingers.

20. The method of claim 2, wherein a partial list of transistor characteristics or an extended list with additional characteristics is used as input to the neural network.

21. The method of claim 2, wherein the input to the neural network is a concatenated vector of transistor UINs.

22. The method according to claims 1 and 2, wherein the input to the neural network is a two-dimensional array of the X and Y positions of the transistors.

23. The method of claims 1 and 2, wherein the input to the neural network is any type of data format containing transistor location information, such as an image file.

24. The method of claims 1 and 2, wherein the initial weights of the neural network are pre-trained on a smaller circuit comprising fewer transistors, uniformly distributed, or determined according to an AI-related method.

25. The method of claim 2, wherein UIN is a decimal or binary representation of the transistor position in the layout, or a one-hot encoded representation of the transistor position in the layout, wherein any unique representation can be used as UIN.

26. The method of claims 1 and 2, wherein each type of transistor has a variable channel width, including different numbers of fins for a FinFET, or a stack of all-around gate or complementary FETs.

27. The method of claim 2, wherein the predetermined score is the standard confidence upper limit (UCB) score.

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