Display panel, driving method and display device

Abstract

A display panel, driving method, and display device are disclosed. The display panel includes a display control circuit (10) and a multi-row, multi-column pixel circuit, a multi-row gate line, and a multi-column data line. The pixel circuit includes a switching transistor and a pixel electrode. The gate of the switching transistor is electrically connected to the corresponding gate line, the first electrode of the switching transistor is electrically connected to the corresponding data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode. The display control circuit (10) is electrically connected to the data line and is used to provide a set voltage to the data line during a blank time period set between two frames, which can improve the problem of screen flicker caused by brightness changes due to low-frequency leakage.

Description

Display panel, driving method and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel, driving method, and display device. Background Technology

[0002] In related technologies, the display panel may include multi-row and multi-column pixel circuits, multi-row gate lines, and multi-column data lines; the pixel circuit includes a switching transistor and a pixel electrode; the gate of the switching transistor is electrically connected to the corresponding gate line, the first electrode of the switching transistor is electrically connected to the corresponding data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode.

[0003] When the potential of the gate drive signal provided by each row of gate lines rises high enough to turn on the switching transistor, the data voltage signal provided by the data line flows into each pixel electrode through the switching transistor. When the potential of the gate drive signal drops to a certain value, the switching transistor turns off, and the pixel electrode voltage is maintained. However, the complete shutdown of the switching transistor is only an ideal state. In reality, a small amount of leakage current will leak into the data line through the switching transistor. The lower the refresh rate of the display panel, the longer the frame time, and the longer the holding time after the pixel electrode is fully charged, that is, the longer the blank period lasts, the more leakage current the switching transistor will have, the greater the voltage drop of the pixel electrode, and the easier it is for the human eye to detect the flickering phenomenon caused by the change in brightness. Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a display panel including a display control circuit and a multi-row, multi-column pixel circuit, a multi-row gate line, and a multi-column data line; the pixel circuit includes a switching transistor and a pixel electrode; the gate of the switching transistor is electrically connected to a corresponding gate line, the first electrode of the switching transistor is electrically connected to a corresponding data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode;

[0005] The display control circuit is electrically connected to the data line and is used to provide a set voltage to the data line during the blank time period set between two frames.

[0006] Optionally, during the blank time period, the absolute value of the difference between the voltage value of the set voltage and the voltage value of the pixel voltage on the pixel electrode is less than the threshold voltage.

[0007] Optionally, the display control circuit includes a first control circuit and a data voltage supply circuit;

[0008] The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0009] The first control circuit is electrically connected to the multiplexing control terminal and the data voltage supply terminal respectively, and is used to control the multiplexing control terminal to provide an effective multiplexing control signal and control the data voltage supply terminal to provide a corresponding set voltage during the blank time period, so that the data voltage supply circuit writes the set voltage to the corresponding data line under the control of the multiplexing control signal.

[0010] Optionally, the display control circuit includes a first control circuit and a data voltage supply circuit;

[0011] The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0012] The first control circuit is electrically connected to the multiplexing control terminal and the data voltage supply terminal respectively, and is used to control the multiplexing control signal to be provided to the multiplexing control terminal during the blank time period, and to control the data voltage supply terminal to provide a corresponding set voltage; the multiplexing control signal is a square wave control signal.

[0013] Optionally, the display control circuit includes a first control circuit and a data voltage supply circuit;

[0014] The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0015] The first control circuit is electrically connected to the data voltage providing terminal and is used to control the data voltage providing terminal to provide a corresponding set voltage during the blank time period.

[0016] The first control circuit is also electrically connected to the multiplexing control terminal, and is also used to control the supply of a multiplexing control signal to the multiplexing control terminal during the start time period included in the blank time period and the end time period included in the blank time period; the multiplexing control signal is a square wave control signal.

[0017] Optionally, the data voltage providing circuit is used to write the set voltage to the corresponding data line under the control of the multiplexing control signal when the multiplexing control signal is a valid multiplexing control signal during the blank time period, and to control the data voltage providing terminal to disconnect from the corresponding data line under the control of the multiplexing control signal when the multiplexing control signal is an invalid multiplexing control signal during the blank time period.

[0018] Optionally, the display control circuit includes a first control circuit and a data voltage supply circuit;

[0019] The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0020] The first control circuit is electrically connected to the multiplexing control terminal and the data voltage supply terminal respectively, and is used to control the multiplexing control terminal to provide an invalid multiplexing control signal during the blank time period, and to control the data voltage supply terminal to provide a corresponding set voltage, so that the data voltage supply circuit controls the data voltage supply terminal to disconnect from the corresponding data line under the control of the multiplexing control signal.

[0021] The data voltage providing circuit includes transistors with a channel width-to-length ratio greater than 60.

[0022] Optionally, the data voltage providing circuit includes a plurality of first transistors;

[0023] The gate of the 4n-3rd first transistor is electrically connected to the first multiplexing control terminal, the first electrode of the 4n-3rd first transistor is electrically connected to the 2n-1th data voltage supply terminal, and the second electrode of the 4n-3rd first transistor is electrically connected to the 4n-3rd column data line.

[0024] The gate of the 4n-2nd first transistor is electrically connected to the first multiplexing control terminal, the first electrode of the 4n-2nd first transistor is electrically connected to the 2nth data voltage supply terminal, and the second electrode of the 4n-2nd first transistor is electrically connected to the 4n-2nd column data line;

[0025] The gate of the 4n-1th first transistor is electrically connected to the second multiplexing control terminal, the first terminal of the 4n-1th first transistor is electrically connected to the 2n-1th data voltage supply terminal, and the second terminal of the 4n-1th first transistor is electrically connected to the 4n-1th column data line.

[0026] The gate of the 4nth first transistor is electrically connected to the second multiplexing control terminal, the first electrode of the 4nth first transistor is electrically connected to the 2nth data voltage supply terminal, and the second electrode of the 4nth first transistor is electrically connected to the 4nth column data line.

[0027] n is a positive integer.

[0028] Optionally, the display control circuit includes a test control circuit and a second control circuit;

[0029] The test control circuit is electrically connected to the test control terminal, the test voltage supply terminal and the data line respectively, and is used to control the connection or disconnection between the test voltage supply terminal and the data line under the control of the test control signal provided by the test control terminal;

[0030] The second control circuit is used to provide a valid test control signal to the test control terminal during the blank time period, and control the test voltage supply terminal to provide a corresponding set voltage, so that the test control circuit writes the set voltage to the corresponding data line under the control of the test control signal.

[0031] Optionally, the display panel includes a first test voltage supply terminal and a second test voltage supply terminal;

[0032] The test control circuit is electrically connected to the first test voltage providing terminal and the second test voltage providing terminal respectively, and is used to control the first test voltage providing terminal to connect or disconnect with the data lines located in the odd-numbered columns, and to control the second test voltage providing terminal to connect or disconnect with the data lines located in the even-numbered columns, under the control of the test control signal.

[0033] The second control circuit is used to control the first test voltage providing terminal to provide a first set voltage and control the second test voltage providing terminal to provide a second set voltage during the blank time period, so that the test control circuit, under the control of the test control signal, writes the first set voltage to the data line located in the odd column and writes the second set voltage to the data line located in the even column.

[0034] Optionally, the first set voltage is a positive voltage signal and the second set voltage is a negative voltage signal; or, the first set voltage is a negative voltage signal and the second set voltage is a positive voltage signal.

[0035] Optionally, the test control circuit includes a plurality of second transistors;

[0036] The gate of the (2n-1)th second transistor is electrically connected to the test control terminal, the first terminal of the (2n-1)th second transistor is electrically connected to the first test voltage supply terminal, and the second terminal of the (2n-1)th second transistor is electrically connected to the (2n-1)th column data line;

[0037] The gate of the 2nth second transistor is electrically connected to the test control terminal, the first terminal of the 2nth second transistor is electrically connected to the second test voltage supply terminal, and the second terminal of the 2nth second transistor is electrically connected to the 2nth column data line.

[0038] n is a positive integer.

[0039] In a second aspect, embodiments of this disclosure provide a driving method for a display panel, applied to the aforementioned display panel, the driving method for the display panel comprising:

[0040] During the blank time period set between two frames, the display control circuit provides a set voltage to the data line.

[0041] Optionally, during the blank time period, the absolute value of the difference between the voltage value of the set voltage and the voltage value of the pixel voltage on the pixel electrode is less than the threshold voltage.

[0042] In a third aspect, embodiments of this disclosure provide a display device including the display panel described above. Attached Figure Description

[0043] Figure 1 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0044] Figure 2 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0045] Figure 3 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0046] Figure 4 is a timing diagram of at least one embodiment of the display panel shown in Figure 3;

[0047] Figure 5 is a timing diagram of at least one embodiment of the display panel shown in Figure 3;

[0048] Figure 6 is a timing diagram of at least one embodiment of the display panel shown in Figure 3;

[0049] Figure 7 is a timing diagram of at least one embodiment of the display panel shown in Figure 3;

[0050] Figure 8 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0051] Figure 9 is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0052] Figure 10 is a timing diagram of at least one embodiment of the display panel shown in Figure 9. Detailed Implementation

[0053] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0054] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0055] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0056] The display panel described in this embodiment includes a display control circuit, a multi-row and multi-column pixel circuit, a multi-row gate line, and a multi-column data line; the pixel circuit includes a switching transistor and a pixel electrode; the gate of the switching transistor is electrically connected to the corresponding gate line, the first electrode of the switching transistor is electrically connected to the corresponding data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode.

[0057] The display control circuit is electrically connected to the data line and is used to provide a set voltage to the data line during the blank time period set between two frames.

[0058] In a specific implementation, the display panel may include a display control circuit. During the blank period, the display control circuit provides a set voltage to the data line, and the potential of the data line is well maintained. The first terminal of the switching transistor in the pixel circuit is electrically connected to the corresponding data line, and the second terminal of the switching transistor is electrically connected to the pixel electrode. Although the corresponding gate controls the switching transistor to turn off during the blank period, the voltage difference between the first terminal and the second terminal of the switching transistor is small. During the blank period, the leakage current of the pixel electrode voltage is reduced, and the pixel electrode voltage is maintained, thereby improving the problem of screen flicker caused by brightness changes due to low-frequency leakage current.

[0059] In at least one embodiment of this disclosure, during the blank time period, the absolute value of the difference between the voltage value of the set voltage and the voltage value of the pixel voltage on the pixel electrode is less than the threshold voltage.

[0060] In specific implementation, during the blank time period, the absolute value of the difference between the set voltage and the pixel voltage on the pixel electrode is less than the threshold voltage, so as to control that the voltage difference between the first electrode and the second electrode of the switching transistor is very small during the blank time period, thereby reducing the leakage current of the switching transistor and maintaining the pixel electrode voltage well, thus improving the low-frequency flicker phenomenon.

[0061] Optionally, the threshold voltage may be less than or equal to 0.5V, for example, the threshold voltage may be equal to 0.5V, 0.4V, 0.3V, 0.2V, 0.1V or 0.05V, but is not limited thereto.

[0062] Currently, the market demands wide-frequency compatibility for display panels, such as dynamic switching between 30Hz and 240Hz, or 15Hz and 120Hz. This places strict requirements on the display panel itself regarding low-frequency screen flicker. Because the human eye is more sensitive to low refresh rate screens, such as 15Hz, a significant flickering phenomenon occurs when the display is running at 15Hz. This flickering is mainly due to the human eye perceiving changes in screen brightness, which are primarily caused by leakage current in the pixels within the panel at low frequencies. In practical implementation, the extended blank periods in both wide-frequency compatibility and low-frequency modes further exacerbate the low-frequency flicker problem in related display products. Based on the above issues, this embodiment of the present disclosure provides a set voltage to the data line during the blank period through the display control circuit. This ensures that the potential of the data line is well maintained. During the blank period, the leakage current of the pixel electrode voltage is reduced, and the pixel electrode voltage is maintained, thereby improving the screen flickering problem caused by brightness changes due to low-frequency leakage current.

[0063] As shown in Figure 1, the display panel described in at least one embodiment of this disclosure may include a display control circuit 10 and a multi-row, multi-column pixel circuit, a multi-row gate line, and a multi-column data line;

[0064] In Figure 1, the pixel electrode labeled PX11 is the first row and first column, the pixel electrode labeled PX12 is the first row and second column, the pixel electrode labeled PX13 is the first row and third column, the pixel electrode labeled PX14 is the first row and fourth column, the pixel electrode labeled PX15 is the first row and fifth column, and the pixel electrode labeled PX16 is the first row and sixth column.

[0065] The pixel electrode labeled PX21 is the first row and first column pixel electrode, the pixel electrode labeled PX22 is the first row and second column pixel electrode, the pixel electrode labeled PX23 is the first row and third column pixel electrode, the pixel electrode labeled PX24 is the first row and fourth column pixel electrode, the pixel electrode labeled PX25 is the first row and fifth column pixel electrode, and the pixel electrode labeled PX26 is the first row and sixth column pixel electrode.

[0066] The pixel electrode labeled PX31 is the first pixel electrode in the third row, the pixel electrode labeled PX32 is the second pixel electrode in the third row, the pixel electrode labeled PX33 is the third pixel electrode in the third row, the pixel electrode labeled PX34 is the fourth pixel electrode in the third row, the pixel electrode labeled PX35 is the fifth pixel electrode in the third row, and the pixel electrode labeled PX36 is the sixth pixel electrode in the third row.

[0067] The pixel electrode labeled PX41 is the first pixel electrode in the fourth row, the second pixel electrode in the fourth row, the third pixel electrode in the fourth row, the fourth pixel electrode in the fourth row, the fourth pixel electrode in the fourth row, the fifth pixel electrode in the fourth row, and the sixth pixel electrode in the fourth row.

[0068] The pixel electrode labeled PXN-11 is the first pixel electrode in the N-1 row; the pixel electrode labeled PXN-12 is the second pixel electrode in the N-1 row; the pixel electrode labeled PXN-13 is the third pixel electrode in the N-1 row; the pixel electrode labeled PXN-14 is the fourth pixel electrode in the N-1 row; the pixel electrode labeled PXN-15 is the fifth pixel electrode in the N-1 row; and the pixel electrode labeled PXN-16 is the sixth pixel electrode in the N-1 row.

[0069] The pixel electrode labeled PXN1 is the first pixel electrode in the Nth row, the second pixel electrode in the Nth row, the third pixel electrode in the Nth row, the fourth pixel electrode in the Nth row, the fifth pixel electrode in the Nth row, and the sixth pixel electrode in the Nth row; N is an integer greater than 6.

[0070] The transistor labeled TK11 is the switching transistor in the first row and first column; the transistor labeled TK12 is the switching transistor in the first row and second column; the transistor labeled TK13 is the switching transistor in the first row and third column; the transistor labeled TK14 is the switching transistor in the first row and fourth column; the transistor labeled TK15 is the switching transistor in the first row and fifth column; and the transistor labeled TK16 is the switching transistor in the first row and sixth column.

[0071] The transistor labeled TK21 is the first switch transistor in the first row and first column; the transistor labeled TK22 is the first switch transistor in the second row and second column; the transistor labeled TK23 is the first switch transistor in the third row and third column; the transistor labeled TK24 is the first switch transistor in the fourth row and fourth column; the transistor labeled TK25 is the first switch transistor in the fifth row and fifth column; and the transistor labeled TK26 is the first switch transistor in the sixth row and sixth column.

[0072] The transistor labeled TK31 is the switching transistor in the first column of the third row; the transistor labeled TK32 is the switching transistor in the second column of the third row; the transistor labeled TK33 is the switching transistor in the third column of the third row; the transistor labeled TK34 is the switching transistor in the fourth column of the third row; the transistor labeled TK35 is the switching transistor in the fifth column of the third row; and the transistor labeled TK36 is the switching transistor in the sixth column of the third row.

[0073] The transistor labeled TK41 is the switching transistor in the first column of the fourth row; the transistor labeled TK42 is the switching transistor in the second column of the fourth row; the transistor labeled TK43 is the switching transistor in the third column of the fourth row; the transistor labeled TK44 is the switching transistor in the fourth column of the fourth row; the transistor labeled TK45 is the switching transistor in the fifth column of the fourth row; and the transistor labeled TK46 is the switching transistor in the sixth column of the fourth row.

[0074] The transistor labeled TKN-11 is the switching transistor in the first column of row N-1; the transistor labeled TKN-12 is the switching transistor in the second column of row N-1; the transistor labeled TKN-13 is the switching transistor in the third column of row N-1; the transistor labeled TKN-14 is the switching transistor in the fourth column of row N-1; the transistor labeled TKN-15 is the switching transistor in the fifth column of row N-1; and the transistor labeled TKN-16 is the switching transistor in the sixth column of row N-1.

[0075] The transistor labeled TKN1 is the switching transistor in the first column of the Nth row; the transistor labeled TKN2 is the switching transistor in the second column of the Nth row; the transistor labeled TKN3 is the switching transistor in the third column of the Nth row; the transistor labeled TKN4 is the switching transistor in the fourth column of the Nth row; the transistor labeled TKN5 is the switching transistor in the fifth column of the Nth row; and the transistor labeled TKN6 is the switching transistor in the sixth column of the Nth row.

[0076] The first row of gate lines is labeled GT1, the second row of gate lines is labeled GT2, the third row of gate lines is labeled GT3, the fourth row of gate lines is labeled GT4, the (N-1)th row of gate lines is labeled GTN, and the Nth row of gate lines is labeled GTN.

[0077] The data line labeled DL1 is the first column, the data line labeled DL2 is the second column, the data line labeled DL3 is the third column, the data line labeled DL4 is the fourth column, the data line labeled DL5 is the fifth column, and the data line labeled DL6 is the sixth column.

[0078] The gate of TK11 is electrically connected to GT1, the source of TK11 is electrically connected to DL1, and the drain of TK11 is electrically connected to PX11; the gate of TK12 is electrically connected to GT1, the source of TK12 is electrically connected to DL2, and the drain of TK12 is electrically connected to PX12; the gate of TK13 is electrically connected to GT1, the source of TK13 is electrically connected to DL3, and the drain of TK13 is electrically connected to PX13; the gate of TK14 is electrically connected to GT1, the source of TK14 is electrically connected to DL4, and the drain of TK14 is electrically connected to PX14; the gate of TK15 is electrically connected to GT1, the source of TK15 is electrically connected to DL5, and the drain of TK15 is electrically connected to PX15; the gate of TK16 is electrically connected to GT1, the source of TK16 is electrically connected to DL6, and the drain of TK16 is electrically connected to PX16.

[0079] The gate of TK21 is electrically connected to GT2, the source of TK21 is electrically connected to DL1, and the drain of TK21 is electrically connected to PX21; the gate of TK22 is electrically connected to GT2, the source of TK22 is electrically connected to DL2, and the drain of TK22 is electrically connected to PX22; the gate of TK23 is electrically connected to GT2, the source of TK23 is electrically connected to DL3, and the drain of TK23 is electrically connected to PX23; the gate of TK24 is electrically connected to GT2, the source of TK24 is electrically connected to DL4, and the drain of TK24 is electrically connected to PX24; the gate of TK25 is electrically connected to GT2, the source of TK25 is electrically connected to DL5, and the drain of TK25 is electrically connected to PX25; the gate of TK26 is electrically connected to GT2, the source of TK26 is electrically connected to DL6, and the drain of TK26 is electrically connected to PX26.

[0080] The gate of TK31 is electrically connected to GT3, the source of TK31 is electrically connected to DL1, and the drain of TK31 is electrically connected to PX31; the gate of TK32 is electrically connected to GT3, the source of TK32 is electrically connected to DL2, and the drain of TK32 is electrically connected to PX32; the gate of TK33 is electrically connected to GT3, the source of TK33 is electrically connected to DL3, and the drain of TK33 is electrically connected to PX33; the gate of TK34 is electrically connected to GT3, the source of TK34 is electrically connected to DL4, and the drain of TK34 is electrically connected to PX34; the gate of TK35 is electrically connected to GT3, the source of TK35 is electrically connected to DL5, and the drain of TK35 is electrically connected to PX35; the gate of TK36 is electrically connected to GT3, the source of TK36 is electrically connected to DL6, and the drain of TK36 is electrically connected to PX36.

[0081] The gate of TK41 is electrically connected to GT4, the source of TK41 is electrically connected to DL1, and the drain of TK41 is electrically connected to PX41; the gate of TK42 is electrically connected to GT4, the source of TK42 is electrically connected to DL2, and the drain of TK42 is electrically connected to PX42; the gate of TK43 is electrically connected to GT4, the source of TK43 is electrically connected to DL3, and the drain of TK43 is electrically connected to PX43; the gate of TK44 is electrically connected to GT4, the source of TK44 is electrically connected to DL4, and the drain of TK44 is electrically connected to PX44; the gate of TK45 is electrically connected to GT4, the source of TK45 is electrically connected to DL5, and the drain of TK45 is electrically connected to PX45; the gate of TK46 is electrically connected to GT4, the source of TK46 is electrically connected to DL6, and the drain of TK46 is electrically connected to PX46.

[0082] The gate of TKN-11 is electrically connected to GTN-1, the source of TKN-11 is electrically connected to DL1, and the drain of TKN-11 is electrically connected to PXN-11; the gate of TKN-12 is electrically connected to GTN-1, the source of TKN-12 is electrically connected to DL2, and the drain of TKN-12 is electrically connected to PXN-12; the gate of TKN-13 is electrically connected to GTN-1, the source of TKN-13 is electrically connected to DL3, and the drain of TKN-13 is electrically connected to PXN-13. The gate of TKN-14 is electrically connected to GTN-1, the source of TKN-14 is electrically connected to DL4, and the drain of TKN-14 is electrically connected to PXN-14; the gate of TKN-15 is electrically connected to GTN-1, the source of TKN-15 is electrically connected to DL5, and the drain of TKN-15 is electrically connected to PXN-15; the gate of TKN-16 is electrically connected to GTN-1, the source of TKN-16 is electrically connected to DL6, and the drain of TKN-16 is electrically connected to PXN-16.

[0083] The gate of TKN1 is electrically connected to GTN, the source of TKN1 is electrically connected to DL1, and the drain of TKN1 is electrically connected to PXN1; the gate of TKN2 is electrically connected to GTN, the source of TKN2 is electrically connected to DL2, and the drain of TKN2 is electrically connected to PXN2; the gate of TKN3 is electrically connected to GTN, the source of TKN3 is electrically connected to DL3, and the drain of TKN3 is electrically connected to PXN3; the gate of TKN4 is electrically connected to GTN, the source of TKN4 is electrically connected to DL4, and the drain of TKN4 is electrically connected to PXN4; the gate of TKN5 is electrically connected to GTN, the source of TKN5 is electrically connected to DL5, and the drain of TKN5 is electrically connected to PXN5; the gate of TKN6 is electrically connected to GTN, the source of TKN6 is electrically connected to DL6, and the drain of TKN6 is electrically connected to PXN6.

[0084] The display control circuit 10 is electrically connected to the first column data line DL1, the second column data line DL2, the third column data line DL3, the fourth column data line DL4, the (N-1)th column data line DLN-1, and the Nth column data line DLN, respectively, and is used to provide a set voltage to the first column data line DL1, the second column data line DL2, the third column data line DL3, the fourth column data line DL4, the (N-1)th column data line DLN-1, and the Nth column data line DLN during the blank time period set between two frames.

[0085] In at least one embodiment of this disclosure, the display control circuit includes a first control circuit and a data voltage supply circuit;

[0086] The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0087] The first control circuit is used to control the multiplexing control terminal to provide a valid multiplexing control signal during the blank time period, and to control the data voltage supply terminal to provide a corresponding set voltage, so that the data voltage supply circuit writes the set voltage to the corresponding data line under the control of the multiplexing control signal.

[0088] In a specific implementation, the display control circuit may include a first control circuit and a data voltage supply circuit; under the control of a multiplexing control signal, the data voltage supply circuit controls the connection or disconnection between the data voltage supply terminal and the corresponding data line; during the blank time period, the first control circuit controls the multiplexing control terminal to provide a valid multiplexing control signal and controls the data voltage supply terminal to provide a corresponding set voltage, so that the data voltage supply circuit writes the set voltage to the corresponding data line under the control of the multiplexing control signal.

[0089] In at least one embodiment of this disclosure, the number of reset control terminals is two, as an example for illustration.

[0090] As shown in Figure 2, based on at least one embodiment of the display panel shown in Figure 1, the display control circuit may include a first control circuit 21 and a data voltage supply circuit 22;

[0091] The data voltage providing circuit 22 is electrically connected to the first multiplexing control terminal MUX1, the second multiplexing control terminal MUX2, the first data voltage providing terminal S1, the second data voltage providing terminal S2, the third data voltage providing terminal S3, the fourth data voltage providing terminal S4, the first column data line DL1, the second column data line DL2, the third column data line DL3, the fourth column data line DL4, the fifth column data line DL5, and the sixth column data line DL6, respectively. It is used to control the first data voltage providing terminal S1 and the first column data line DL6 under the control of the first multiplexing control signal provided by the first multiplexing control terminal MUX1. The connection or disconnection between DL1 controls the connection or disconnection between the second data voltage supply terminal S2 and the second column data line DL2, controls the connection or disconnection between the third data voltage supply terminal S3 and the fifth column data line DL5, controls the connection or disconnection between the fourth data voltage supply terminal S4 and the sixth column data line DL6, and under the control of the second multiplexing control signal provided by the second multiplexing control terminal MX2, controls the connection or disconnection between the first data voltage supply terminal S1 and the third column data line DL3, and controls the connection or disconnection between the second data voltage supply terminal S2 and the fourth column data line DL4;

[0092] The first control circuit 21 is electrically connected to the first multiplexing control terminal MUX1, the second multiplexing control terminal MUX2, the first data voltage supply terminal S1, the second data voltage supply terminal S2, the third data voltage supply terminal S3, and the fourth data voltage supply terminal S4, respectively. During the blank time period, it controls the first multiplexing control terminal MUX1 to provide a valid first multiplexing control signal, controls the second multiplexing control terminal MUX2 to provide a valid second multiplexing control signal, and controls the first data voltage supply terminal S1, the second data voltage supply terminal S2, the third data voltage supply terminal S3, and the fourth data voltage supply terminal S4 to provide corresponding set voltages. This allows the data voltage supply circuit 22, under the control of the first multiplexing control signal and the second multiplexing control signal, to write the set voltages onto the first column data line DL1, the second column data line DL2, the third column data line DL3, the fourth column data line DL4, the fifth column data line DL5, and the sixth column data line DL6.

[0093] Optionally, the data voltage providing circuit includes a plurality of first transistors;

[0094] The gate of the 4n-3rd first transistor is electrically connected to the first multiplexing control terminal, the first electrode of the 4n-3rd first transistor is electrically connected to the 2n-1th data voltage supply terminal, and the second electrode of the 4n-3rd first transistor is electrically connected to the 4n-3rd column data line.

[0095] The gate of the 4n-2nd first transistor is electrically connected to the first multiplexing control terminal, the first electrode of the 4n-2nd first transistor is electrically connected to the 2nth data voltage supply terminal, and the second electrode of the 4n-2nd first transistor is electrically connected to the 4n-2nd column data line;

[0096] The gate of the 4n-1th first transistor is electrically connected to the second multiplexing control terminal, the first terminal of the 4n-1th first transistor is electrically connected to the 2n-1th data voltage supply terminal, and the second terminal of the 4n-1th first transistor is electrically connected to the 4n-1th column data line.

[0097] The gate of the 4nth first transistor is electrically connected to the second multiplexing control terminal, the first electrode of the 4nth first transistor is electrically connected to the 2nth data voltage supply terminal, and the second electrode of the 4nth first transistor is electrically connected to the 4nth column data line.

[0098] n is a positive integer.

[0099] As shown in Figure 3, based on at least one embodiment of the display panel shown in Figure 2, the data voltage supply circuit may include a first first transistor T11, a second first transistor T21, a third first transistor T31, a fourth first transistor T41, a fifth first transistor T51, and a sixth first transistor T61.

[0100] The gate of T11 is electrically connected to MUX1, the source of T11 is electrically connected to S1, and the drain of T11 is electrically connected to DL1.

[0101] The gate of T21 is electrically connected to MUX1, the source of T21 is electrically connected to S2, and the drain of T21 is electrically connected to DL2.

[0102] The gate of T31 is electrically connected to MUX2, the source of T31 is electrically connected to S1, and the drain of T31 is electrically connected to DL3.

[0103] The gate of T41 is electrically connected to MUX2, the source of T41 is electrically connected to S2, and the drain of T41 is electrically connected to DL4.

[0104] The gate of T51 is electrically connected to MUX1, the source of T51 is electrically connected to S3, and the drain of T51 is electrically connected to DL5.

[0105] The gate of T61 is electrically connected to MUX1, the source of T61 is electrically connected to S4, and the drain of T61 is electrically connected to DL6.

[0106] In at least one embodiment shown in Figure 3, T11, T21, T31, T41, T51, and T61 can all be n-type transistors, but are not limited thereto. In specific implementations, T11, T21, T31, T41, T51, and T61 can also be p-type transistors.

[0107] In at least one embodiment shown in Figure 3, the data voltage providing circuit may include a first transistor T11, a second first transistor T21, a third first transistor T31, a fourth first transistor T41, a fifth first transistor T51, and a sixth first transistor T61, which can reduce the number of data voltage channels and thus reduce the number of Source Driver ICs. In related technologies, during idle periods, each first transistor is generally turned off, and leakage current may occur in each first transistor, thus posing a problem of voltage maintenance in low-frequency scenarios.

[0108] As shown in Figure 4, in at least one embodiment of the display panel shown in Figure 3 of this disclosure, during the blank time period TB between the m-th frame time Fm and the (m+1)-th frame time Fm+1, MUX1 and MUX2 provide high voltage signals, T11, T21, T31, T41, T51 and T61 are all turned on, and S1, S2, S3 and S4 provide set voltages to write the set voltages to DL1, DL2, DL3, DL4, DL5 and DL6; m is a positive integer.

[0109] As shown in Figure 4, in at least one embodiment of the display panel shown in Figure 3 of this disclosure, during the blank time period TB, S1, S2, S3 and S4 can provide a grayscale 127 voltage signal, that is, the set voltage can be a grayscale 127 voltage signal. At this time, each data line will be continuously charged with a grayscale 127 voltage signal, and the potential of each data line is well maintained. At the same time, the source and drain terminals of the switching transistor are electrically connected to the corresponding pixel electrode and data line, respectively. Although the gate lines of each row are not turned on during the blank time period TB, the voltage difference between the source and drain terminals of the switching transistor is very small. For example, the pixel electrode voltage can be 3V and the data line voltage can be 2.5V. The long-term leakage caused by the switching transistor will be greatly reduced, and the pixel electrode voltage is maintained, thereby improving the screen flickering problem caused by brightness changes due to low-frequency leakage.

[0110] In Figure 4, the first clock signal is labeled CK1, the second clock signal is labeled CK2, the third clock signal is labeled CK3, and the fourth clock signal is labeled CK4.

[0111] In at least one embodiment of this disclosure, the display control circuit includes a first control circuit and a data voltage supply circuit;

[0112] The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0113] The first control circuit is used to control the supply of a multiplexing control signal to the multiplexing control terminal during the blank time period, and to control the data voltage supply terminal to supply a corresponding set voltage; the multiplexing control signal is a square wave control signal.

[0114] As shown in Figure 5, in at least one embodiment of the display panel shown in Figure 3, during the blank time period TB between the m-th time Fm and the (m+1)-th frame time Fm+1, both MUX1 and MUX2 provide square wave control signals. When MUX1 provides a high voltage signal, T11, T21, T51, and T61 are all turned on, and S1, S2, S3, and S4 provide set voltages to write the set voltages to DL1, DL2, DL5, and DL6. When MUX2 provides a high voltage signal, T31 and T41 are both turned on, and S1 and S2 provide set voltages to write the set voltages to DL3 and DL4.

[0115] At least one embodiment shown in Figure 5 can address the situation where the IC does not support adjustment of the multiplexing control terminal when it is constantly high during the blank time period. In at least one embodiment shown in Figure 5, MUX1 and MUX2 can provide square wave control signals at frame time Fm and frame time Fm+1 (m+1). In at least one embodiment of this disclosure, the display control circuit includes a first control circuit and a data voltage supply circuit.

[0116] The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0117] The first control circuit is used to control the data voltage providing terminal to provide a corresponding set voltage during the blank time period;

[0118] The first control circuit is further configured to control the supply of a multiplexing control signal to the multiplexing control terminal during the start time period included in the blank time period and the end time period included in the blank time period; the multiplexing control signal is a square wave control signal.

[0119] As shown in Figure 6, in at least one embodiment of the display panel shown in Figure 3, a blank time period TB is provided between the m-th time Fm and the (m+1)-th frame time Fm+1. The blank time period TB includes a start time period TS and an end time period TE. The first multiplexing control terminal MUX1 provides a square wave control signal, and the second multiplexing control terminal MUX2 provides a square wave control signal.

[0120] As shown in Figure 6, in at least one embodiment of the display panel shown in Figure 3, during operation, the first multiplexing control terminal MUX1 can provide a square wave control signal and the second multiplexing control terminal MUX2 can provide a square wave control signal during the blank time period TB, which includes the start and end time periods. This setting can also ensure that during the blank time period TB, the potential of each data line and the potential of each pixel electrode can be applied to situations where the display panel needs to reduce power consumption.

[0121] In at least one embodiment of this disclosure, during the switching time period and the ending time period, the reset control signal may have one square wave pulse or two square wave pulses, but is not limited thereto, and the number of square wave pulses in the reset control signal is not limited.

[0122] In at least one embodiment of this disclosure, the data voltage providing circuit is used to write the set voltage to the corresponding data line under the control of the multiplexing control signal when the multiplexing control signal is a valid multiplexing control signal during the blank time period, and to control the data voltage providing terminal to disconnect from the corresponding data line under the control of the multiplexing control signal when the multiplexing control signal is an invalid multiplexing control signal during the blank time period.

[0123] In specific implementation, during the blank time period, when the multiplexing control signal is a valid multiplexing control signal, the set voltage is written to the corresponding data line under the control of the multiplexing control signal.

[0124] During the blank time period, when the multiplexing control signal is an invalid multiplexing control signal, the data voltage supply terminal is disconnected from the corresponding data line under the control of the multiplexing control signal.

[0125] In at least one embodiment of this disclosure, when each of the first transistors included in the data voltage supply circuit is an n-type transistor, the effective multiplexing control signal can be a high voltage signal, and the invalid multiplexing control signal can be a low voltage signal.

[0126] When the first transistors included in the data voltage supply circuit are p-type transistors, the valid multiplexing control signal is a low voltage signal, and the invalid multiplexing control signal is a high voltage signal.

[0127] In at least one embodiment of this disclosure, the display control circuit includes a first control circuit and a data voltage supply circuit;

[0128] The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal.

[0129] The first control circuit is used to control the multiplexing control terminal to provide an invalid multiplexing control signal during the blank time period, and to control the data voltage supply terminal to provide a corresponding set voltage, so that the data voltage supply circuit controls the data voltage supply terminal to disconnect from the corresponding data line under the control of the multiplexing control signal.

[0130] The data voltage providing circuit includes transistors with a channel width-to-length ratio greater than 60.

[0131] As shown in Figure 7, at least one embodiment of the display panel shown in Figure 3 has a blank time period TB between the m-th time Fm and the (m+1)-th frame time Fm+1 during operation.

[0132] During the blank period TB, MUX1 and MUX2 provide low voltage signals, while S1, S2, S3, and S4 provide set voltages.

[0133] In at least one embodiment shown in FIG7, the channel width-to-length ratio of each first transistor included in at least one embodiment of the display panel shown in FIG3 is usually set to be very large, for example, it can be 240 / 3. This results in a large leakage current of the first transistor itself. During a long blank period, the voltage signal of each data voltage supply terminal will slowly leak into each data line, thereby maintaining the data line voltage and pixel electrode voltage.

[0134] In at least one embodiment of this disclosure, the display control circuit includes a test control circuit and a second control circuit;

[0135] The test control circuit is electrically connected to the test control terminal, the test voltage supply terminal and the data line respectively, and is used to control the connection or disconnection between the test voltage supply terminal and the data line under the control of the test control signal provided by the test control terminal;

[0136] The second control circuit is used to provide a valid test control signal to the test control terminal during the blank time period, and control the test voltage supply terminal to provide a corresponding set voltage, so that the test control circuit writes the set voltage to the corresponding data line under the control of the test control signal.

[0137] Optionally, the display panel includes a first test voltage supply terminal and a second test voltage supply terminal;

[0138] The test control circuit is electrically connected to the first test voltage providing terminal and the second test voltage providing terminal respectively, and is used to control the first test voltage providing terminal to connect or disconnect with the data lines located in the odd-numbered columns, and to control the second test voltage providing terminal to connect or disconnect with the data lines located in the even-numbered columns, under the control of the test control signal.

[0139] The second control circuit is used to control the first test voltage providing terminal to provide a first set voltage and control the second test voltage providing terminal to provide a second set voltage during the blank time period, so that the test control circuit, under the control of the test control signal, writes the first set voltage to the data line located in the odd column and writes the second set voltage to the data line located in the even column.

[0140] In at least one embodiment of this disclosure, the first set voltage is a positive voltage signal and the second set voltage is a negative voltage signal; or, the first set voltage is a negative voltage signal and the second set voltage is a positive voltage signal.

[0141] As shown in Figure 8, based on at least one embodiment of the display panel shown in Figure 2, the display control circuit may further include a test control circuit 81 and a second control circuit 82.

[0142] The test control circuit 81 is electrically connected to the test control terminal CSTW, the first test voltage providing terminal CTD_1, the second test voltage providing terminal CTD_2, the first column data line DL1, the second column data line DL2, the third column data line DL3, the fourth column data line DL4, the fifth column data line DL5, and the sixth column data line DL6, respectively. Under the control of the test control signal provided by the test control terminal CSTW, it controls the connection or disconnection between the first test voltage providing terminal CTD_1 and the first column data line DL1, the connection or disconnection between the second test voltage providing terminal CTD_2 and the second column data line DL2, the connection or disconnection between the first test voltage providing terminal CTD_1 and the third column data line DL3, the connection or disconnection between the second test voltage providing terminal CTD_2 and the fourth column data line DL4, the connection or disconnection between the first test voltage providing terminal CTD_1 and the fifth column data line DL5, and the connection or disconnection between the second test voltage providing terminal CTD_2 and the sixth column data line DL6.

[0143] The second control circuit 82 is electrically connected to the test control terminal CSTW, the first test voltage providing terminal CTD_1, and the second test voltage providing terminal CTD_2. During the blank time period, it provides a valid test control signal to the test control terminal CSTW, provides a first set voltage to the first test voltage providing terminal CTD_1, and provides a second set voltage to the second test voltage providing terminal CTD_2, so that the test control circuit 81, under the control of the test control signal, writes the first set voltage to DL1, DL3, and DL5, and writes the second set voltage to DL2, DL4, and DL6.

[0144] In at least one embodiment of the display panel shown in Figure 8, during operation, the CSTW provides effective test control signals during blank periods to write a first set voltage to DL1, DL3 and DL5, and a second set voltage to DL2, DL4 and DL6.

[0145] In practical implementation, when the transistors included in the test control circuit are n-type transistors, the effective test control signal is a high-voltage signal; when the transistors included in the test control circuit are p-type transistors, the effective test control signal is a low-voltage signal.

[0146] Optionally, the test control circuit includes a plurality of second transistors;

[0147] The gate of the (2n-1)th second transistor is electrically connected to the test control terminal, the first terminal of the (2n-1)th second transistor is electrically connected to the first test voltage supply terminal, and the second terminal of the (2n-1)th second transistor is electrically connected to the (2n-1)th column data line;

[0148] The gate of the 2nth second transistor is electrically connected to the test control terminal, the first terminal of the 2nth second transistor is electrically connected to the second test voltage supply terminal, and the second terminal of the 2nth second transistor is electrically connected to the 2nth column data line.

[0149] n is a positive integer.

[0150] As shown in Figure 9, based on at least one embodiment shown in Figure 8, the test control circuit includes a first second transistor T12, a second second transistor T22, a third second transistor T32, a fourth second transistor T42, a fifth second transistor T52, and a sixth second transistor T62.

[0151] The gate of T12 is electrically connected to the test control terminal CTSW, the source of T12 is electrically connected to the first test voltage supply terminal CTD_1, and the drain of T12 is electrically connected to the first column data line DL1.

[0152] The gate of T22 is electrically connected to the test control terminal CTSW, the source of T22 is electrically connected to the second test voltage supply terminal CTD_2, and the drain of T22 is electrically connected to the second column data line DL2.

[0153] The gate of T32 is electrically connected to the test control terminal CTSW, the source of T32 is electrically connected to the first test voltage supply terminal CTD_1, and the drain of T32 is electrically connected to the third column data line DL3.

[0154] The gate of T42 is electrically connected to the test control terminal CTSW, the source of T42 is electrically connected to the second test voltage supply terminal CTD_2, and the drain of T42 is electrically connected to the fourth column data line DL4.

[0155] The gate of T52 is electrically connected to the test control terminal CTSW, the source of T52 is electrically connected to the first test voltage supply terminal CTD_1, and the drain of T52 is electrically connected to the fifth column data line DL5.

[0156] The gate of T62 is electrically connected to the test control terminal CTSW, the source of T62 is electrically connected to the second test voltage supply terminal CTD_2, and the drain of T62 is electrically connected to the sixth column data line DL6.

[0157] In at least one embodiment of FIG9, T12, T22, T32, T42, T52 and T62 are all n-type transistors, but are not limited thereto.

[0158] As shown in Figure 10, in at least one embodiment of the display panel shown in Figure 9 of this disclosure, during the blank time period TB between the m-th time Fm and the (m+1)-th frame time Fm+1, CTSW provides a high voltage signal, CTD_1 provides a first set voltage, CTD_2 provides a second set voltage, and T12, T22, T32, T42, T52 and T62 are all turned on, writing the first set voltage to DL1, DL3 and DL5, and writing the second set voltage to DL2, DL4 and DL6, so as to maintain the voltage signal on the data line and the pixel electrode voltage;

[0159] During the blank period TB, both MUX1 and MUX2 provide low voltage signals, and T11, T21, T31, T41, T51 and T61 are all turned off.

[0160] In at least one embodiment shown in Figure 10, the first set voltage is a positive voltage signal and the second set voltage is a negative voltage signal, to be applied to the column flip architecture.

[0161] In at least one embodiment of the display panel shown in FIG9 of this disclosure, during Cell Test (cell test phase), each second transistor can be turned on to provide test signals to each data line for cell test.

[0162] At least one embodiment of this disclosure can reduce pixel leakage in broadband and low-frequency scenarios, thereby improving image flicker. It can be applied to a wide range of small and medium-sized TPCs (touch tablets), NBs (notebook computers), mobile devices, and automotive displays.

[0163] The display panel driving method described in this disclosure embodiment is applied to the aforementioned display panel, and the display panel driving method includes:

[0164] During the blank time period set between two frames, the display control circuit provides a set voltage to the data line.

[0165] In at least one embodiment of this disclosure, during the blank time period, the absolute value of the difference between the voltage value of the set voltage and the voltage value of the pixel voltage on the pixel electrode is less than the threshold voltage.

[0166] The display device described in this disclosure includes the display panel described above.

[0167] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display panel, comprising a display control circuit and a multi-row, multi-column pixel circuit, a multi-row gate line, and a multi-column data line; the pixel circuit includes a switching transistor and a pixel electrode; the gate of the switching transistor is electrically connected to a corresponding gate line, the first electrode of the switching transistor is electrically connected to a corresponding data line, and the second electrode of the switching transistor is electrically connected to the pixel electrode; The display control circuit is electrically connected to the data line and is used to provide a set voltage to the data line during a blank time period set between two frames.

2. The display panel as claimed in claim 1, wherein, During the blank time period, the absolute value of the difference between the set voltage and the pixel voltage on the pixel electrode is less than the threshold voltage.

3. The display panel as claimed in claim 1, wherein, The display control circuit includes a first control circuit and a data voltage supply circuit; The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal. The first control circuit is electrically connected to the multiplexing control terminal and the data voltage supply terminal respectively, and is used to control the multiplexing control terminal to provide an effective multiplexing control signal and control the data voltage supply terminal to provide a corresponding set voltage during the blank time period, so that the data voltage supply circuit writes the set voltage to the corresponding data line under the control of the multiplexing control signal.

4. The display panel as claimed in claim 1, wherein, The display control circuit includes a first control circuit and a data voltage supply circuit; The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal. The first control circuit is electrically connected to the multiplexing control terminal and the data voltage supply terminal respectively, and is used to control the multiplexing control signal to be provided to the multiplexing control terminal during the blank time period, and to control the data voltage supply terminal to provide a corresponding set voltage; the multiplexing control signal is a square wave control signal.

5. The display panel as claimed in claim 1, wherein, The display control circuit includes a first control circuit and a data voltage supply circuit; The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal. The first control circuit is electrically connected to the data voltage providing terminal and is used to control the data voltage providing terminal to provide a corresponding set voltage during the blank time period. The first control circuit is also electrically connected to the multiplexing control terminal, and is also used to control the supply of a multiplexing control signal to the multiplexing control terminal during the start time period included in the blank time period and the end time period included in the blank time period; the multiplexing control signal is a square wave control signal.

6. The display panel as claimed in claim 4 or 5, wherein, The data voltage providing circuit is used to write the set voltage to the corresponding data line under the control of the multiplexing control signal when the multiplexing control signal is a valid multiplexing control signal during the blank time period, and to control the data voltage providing terminal to disconnect from the corresponding data line under the control of the multiplexing control signal when the multiplexing control signal is an invalid multiplexing control signal during the blank time period.

7. The display panel as claimed in claim 1, wherein, The display control circuit includes a first control circuit and a data voltage supply circuit; The data voltage supply circuit is electrically connected to at least two multiplexing control terminals, multiple data voltage supply terminals, and the multiple rows of data lines, respectively, and is used to control the connection or disconnection between the data voltage supply terminals and the corresponding data lines under the control of the multiplexing control signal provided by the multiplexing control terminal. The first control circuit is electrically connected to the multiplexing control terminal and the data voltage supply terminal respectively, and is used to control the multiplexing control terminal to provide an invalid multiplexing control signal during the blank time period, and to control the data voltage supply terminal to provide a corresponding set voltage, so that the data voltage supply circuit controls the data voltage supply terminal to disconnect from the corresponding data line under the control of the multiplexing control signal. The data voltage providing circuit includes transistors with a channel width-to-length ratio greater than 60.

8. The display panel as claimed in claim 3, 4, 5 or 7, wherein, The data voltage supply circuit includes a plurality of first transistors; The gate of the 4n-3rd first transistor is electrically connected to the first multiplexing control terminal, the first electrode of the 4n-3rd first transistor is electrically connected to the 2n-1th data voltage supply terminal, and the second electrode of the 4n-3rd first transistor is electrically connected to the 4n-3rd column data line. The gate of the 4n-2nd first transistor is electrically connected to the first multiplexing control terminal, the first electrode of the 4n-2nd first transistor is electrically connected to the 2nth data voltage supply terminal, and the second electrode of the 4n-2nd first transistor is electrically connected to the 4n-2nd column data line; The gate of the 4n-1th first transistor is electrically connected to the second multiplexing control terminal, the first terminal of the 4n-1th first transistor is electrically connected to the 2n-1th data voltage supply terminal, and the second terminal of the 4n-1th first transistor is electrically connected to the 4n-1th column data line. The gate of the 4nth first transistor is electrically connected to the second multiplexing control terminal, the first electrode of the 4nth first transistor is electrically connected to the 2nth data voltage supply terminal, and the second electrode of the 4nth first transistor is electrically connected to the 4nth column data line. n is a positive integer.

9. The display panel as claimed in claim 1, wherein, The display control circuit includes a test control circuit and a second control circuit; The test control circuit is electrically connected to the test control terminal, the test voltage supply terminal and the data line respectively, and is used to control the connection or disconnection between the test voltage supply terminal and the data line under the control of the test control signal provided by the test control terminal; The second control circuit is used to provide a valid test control signal to the test control terminal during the blank time period, and control the test voltage supply terminal to provide a corresponding set voltage, so that the test control circuit writes the set voltage to the corresponding data line under the control of the test control signal.

10. The display panel as claimed in claim 9, wherein, The display panel includes a first test voltage supply terminal and a second test voltage supply terminal; The test control circuit is electrically connected to the first test voltage providing terminal and the second test voltage providing terminal respectively, and is used to control the first test voltage providing terminal to connect or disconnect with the data lines located in the odd-numbered columns, and to control the second test voltage providing terminal to connect or disconnect with the data lines located in the even-numbered columns, under the control of the test control signal. The second control circuit is used to control the first test voltage providing terminal to provide a first set voltage and control the second test voltage providing terminal to provide a second set voltage during the blank time period, so that the test control circuit, under the control of the test control signal, writes the first set voltage to the data line located in the odd column and writes the second set voltage to the data line located in the even column.

11. The display panel as claimed in claim 10, wherein, The first set voltage is a positive voltage signal, and the second set voltage is a negative voltage signal; or, the first set voltage is a negative voltage signal, and the second set voltage is a positive voltage signal.

12. The display panel as claimed in claim 10, wherein, The test control circuit includes multiple second transistors; The gate of the (2n-1)th second transistor is electrically connected to the test control terminal, the first terminal of the (2n-1)th second transistor is electrically connected to the first test voltage supply terminal, and the second terminal of the (2n-1)th second transistor is electrically connected to the (2n-1)th column data line; The gate of the 2nth second transistor is electrically connected to the test control terminal, the first terminal of the 2nth second transistor is electrically connected to the second test voltage supply terminal, and the second terminal of the 2nth second transistor is electrically connected to the 2nth column data line. n is a positive integer.

13. A driving method for a display panel, applied to the display panel as described in any one of claims 1 to 12, the driving method for the display panel comprising: During the blank time period set between two frames, the display control circuit provides a set voltage to the data line.

14. The driving method for a display panel as described in claim 13, wherein, During the blank time period, the absolute value of the difference between the set voltage and the pixel voltage on the pixel electrode is less than the threshold voltage.

15. A display device comprising a display panel as claimed in any one of claims 1 to 12.

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