Data communication system, encoder logic and decoder logic arranged therein, and encoding method and decoding method using the same

Abstract

A data communication system, encoder logic and decoder logic disposed therein, and encoding and decoding methods utilizing them are disclosed. An encoder logic, disposed in the data communication system, wherein each link unit consisting of four transmission lines is driven by PAM4 signals, and using graph coloring theory, 24 state symbols whose sum of PAM4 signals is 0 and whose results from six comparators are non-repeating are used for communication. The encoder logic generates signals for the PHY driving the communication unit, and the communication unit receives data to be transmitted and encodes it to transmit state symbol signals. The encoder logic includes: a transmission initial position setting module, which sets a specific position set as the initial position as a new position in a state transition diagram having 24 state symbols, where the relative distance between each state symbol is defined by transition symbols X, Y, and Z; a data input module, which receives transmitted data from the transmitted data stream; and a transmission state judgment module, configured to check whether the transmitted data satisfies any of a plurality of transmission conditions, determine the corresponding state, and set the new position.

Description

Technical Field

[0001] This invention relates to a data communication system, encoder logic and decoder logic disposed therein, and encoding and decoding methods using them. More specifically, it relates to a data communication system for controlling the DC level characteristics of a transmission line in order to mitigate transmission line impedance variations in a link unit transmitting PAM4 signals and improve overall response characteristics, encoder logic and decoder logic disposed therein, and encoding and decoding methods using them. Background Technology

[0002] In wired high-speed communication, the most significant challenges lie in the parasitic capacitance between the transmission line and the ground signal, as well as the matching capacitance between the transmission lines. The inductance and resistance components of the transmission line also have an impact, but due to advancements in ultra-high-speed transmission line manufacturing technology, inductance and resistance are relatively negligible. Because the signal is transmitted using voltage changes occurring on the high-speed transmission line, the increased capacitance significantly increases the time constant and capacitive load, leading to numerous difficulties in high-speed data transmission or long-distance data communication.

[0003] Typically, when the signal voltage containing signal pulse period or phase information is referred to as Vpp, the capacitance of the transmission line is a factor that causes signal distortion, attenuation, phase delay, and other effects, thereby interfering with communication.

[0004] The known wired high-speed serial communication technologies (MIPI, LVDS, USB 2.0, USB 3.0, SATA, etc.) reduce the impact of capacitive loads by reducing the amplitude of the signal voltage, thereby increasing the speed through high-speed serial signal transmission.

[0005] The current (i) required for signal transmission can be defined by i = C × (dv / dt). That is, as dv / dt (the change in voltage over time), which is the frequency component, increases, the current (i) required for signal transmission will increase even if the value of C, representing the same capacitive load, remains constant. Furthermore, the impedance on the signal transmission line also acts as resistance, increasing the time constant and thus interfering with high-speed signal transmission.

[0006] At the same time, due to the emergence of big data applications such as artificial intelligence (AI), virtual reality, and media streaming, the amount of data being computed and transmitted is increasing dramatically. In computing systems, the energy cost of DRAM access continues to increase as system performance becomes more sophisticated.

[0007] [Existing Technical Documents] [Patent Literature] (Patent Document 0001) Korean Patent Registration No. 10-2543177 (Published on June 14, 2023) (Invention Title: High-bandwidth memory device and system device including the device) (Patent Document 0002) Korean Patent Registration No. 10-0817031 (Published on March 20, 2008) (Invention Title: Single-Wire Serial Communication Module) (Patent Document 0003) Korean Patent Publication No. 2017-0024223 (Published on March 7, 2017) (Invention Title: Device including a single-wire interface and data processing system including the device). Summary of the Invention

[0008] Technical issues Therefore, the technical problem addressed by the present invention is this: the object of the present invention is to provide a data communication system that suppresses the frequency of the same electrical state (symbol level) when transmitting PAM4 signals, thereby preventing impedance variations caused by the DC level bias of the four transmission lines of the link unit based on PAM4 signals, and optimizing the overall signal response characteristics of the system.

[0009] Another object of the present invention is to provide encoder logic for the above-mentioned data communication system.

[0010] Another object of the present invention is to provide a decoder logic disposed in the above-mentioned data communication system.

[0011] Another object of the present invention is to provide an encoding method utilizing the above-described encoder logic.

[0012] Another object of the present invention is to provide a decoding method utilizing the above-described decoder logic.

[0013] Solution to the problem To achieve the aforementioned objectives of the present invention, a data communication system according to one embodiment includes: a link unit comprising four transmission lines and driven by a PAM4 signal; a first communication unit including a first PHY unit connected to one side of the link unit and performing the transmission / reception of the PAM4 signal, and a first encoding / decoding unit connected to the first PHY unit; and a second communication unit including a second PHY unit connected to the other side of the link unit and performing the transmission / reception of the PAM4 signal, and a second encoding / decoding unit connected to the second PHY unit, wherein the first encoding / decoding unit and the second encoding / decoding unit... Each of the code units includes: encoder logic, which assigns signal pairs that satisfy the following conditions to vertices and line segments of the graphics shading theory, defines the signal pairs as state symbols according to a determined relationship, matches the transmitted data to the state symbol, encodes and transmits the data to the link unit using a definition of the relationship between the previous state symbol and the current state symbol: the sum of the PAM4 signals of each of the transmission lines is 0, and the PAM values ​​of the simultaneously driven transmission lines have different signal levels; and decoder logic, which decodes the signals received through the link unit and recovers them as data using a definition of the relationship between the previous state symbol and the current state symbol.

[0014] In one embodiment, the number of data transmitted using the PAM4 signal used for transmission / reception is 23, of which 21 are actual communication data and 2 may include transmission control signals.

[0015] In one embodiment, the encoder logic may include: a transmission initial position setting module, which sets a specific position set as the initial position as a new position in a state transition diagram having 24 state symbols and the relative distance between each state symbol being defined by transition symbols X, Y, and Z; a data input module, which receives transmission data from a transmission data stream; and a transmission status judgment module, which is configured to check whether the transmission data satisfies any of a plurality of transmission conditions, determine the corresponding status, and set the new position.

[0016] In one embodiment, the state transition diagram includes: Group A with 12 state symbols arranged corresponding to the inner circle, and Group B with 12 state symbols arranged corresponding to the outer circle. In the state transition diagram, transition symbols X, Y, and Z define the relative distance between each state symbol. Transition symbol X represents the exchange between state symbols belonging to Group A and state symbols belonging to Group B, and represents the exchange between state symbols with the same index. Transition symbol Y represents the movement of a state symbol belonging to Group A or Group B within the same group by one step. Transition symbol Z represents the movement of a state symbol belonging to Group A or Group B by one step towards a state symbol belonging to Group B or Group A.

[0017] In one embodiment, the decoder logic may include: a receiving initial position setting module, which sets a specific position set as the initial position as a new position in the state transition diagram and sets 0 as new data; a data analysis module, which, as receiving data from the received data stream, sets new data as old data, sets the received data as new data, then calculates the data difference between the set old data and the set new data, and analyzes the number of X, Y, and Z respectively; and a receiving state judgment module, which, based on the analyzed number of X, Y, and Z and the received data, checks any of a plurality of receiving conditions and judges the corresponding state.

[0018] In one embodiment, the state can be any of the following: a swap (S) in which the state symbols of group A and group B are transferred to the opposite group without increasing in order, only exchanging positions; an end of data communication (END, E); a rotation (R) in which the group is not changed in the previous state symbol of group A or group B, but only moves in a circular direction within the same group; and a rotation-swap (RS) in which the group is swapped to another group in the previous state symbol of group A or group B, and rotation occurs in the swapped group.

[0019] In one embodiment, the first encoding / decoding unit may receive transmitted data during signal transmission to form a status symbol based on the TX signal and the TX enable signal, and provide the formed status symbol to the first PHY unit. During signal reception, the status symbol may be recovered based on the RX signal provided by the first PHY unit.

[0020] In one embodiment, the first PHY unit includes: one or more DRV blocks that convert TX signals of externally input voltage levels into current and output them to the transmission line via I / O pads; and one or more RCV blocks that receive PAM4 signals transmitted through the link unit and can send / receive PAM4 signals.

[0021] In one embodiment, the second encoding / decoding unit may recover a state symbol based on the RX signal provided by the second PHY unit when receiving a signal, and receive transmission data to form a state symbol based on the TX signal and the TX enable signal when transmitting a signal, and provide the formed state symbol to the second PHY unit.

[0022] In one embodiment, the second PHY unit includes: one or more DRV blocks that convert TX signals of externally input voltage levels into current and output them to the transmission line via I / O pads; and one or more RCV blocks that receive PAM4 signals transmitted through the link unit and can send / receive PAM4 signals.

[0023] To achieve another objective of the present invention, according to one embodiment, an encoder logic is provided in a data communication system. The data communication system uses PAM4 signals to drive link units consisting of four transmission lines. Utilizing graph coloring theory, 24 state symbols whose sum of PAM4 signals is 0 and whose results from the six comparators are non-repeating are used for communication. The encoder logic generates signals for the PHY driving the communication unit. The communication unit receives data to be transmitted and encodes it to transmit state symbol signals. The encoder logic includes: a transmission initial position setting module, which sets a specific position set as the initial position as a new position in a state transition diagram with 24 state symbols, where the relative distance between each state symbol is defined by transition symbols X, Y, and Z; a data input module, which receives transmitted data from the transmitted data stream; and a transmission state judgment module, configured to check whether the transmitted data satisfies any of a plurality of transmission conditions, determine the corresponding state, and set the new position.

[0024] In one embodiment, the transmission status determination module may include: a first transmission condition processing unit, which, when the transmitted data satisfies a first transmission condition of 22, determines the meaning of the transmitted data as an idle state, sets the new position as the old position, and sets the position in the old position converted to X as the new position; a second transmission condition processing unit, which, when the transmitted data satisfies a second transmission condition greater than or equal to 0 and less than or equal to 10, determines the meaning of the transmitted data as a rotation (R) state, sets the new position as the old position, and sets the position in the old position plus Y(D+1) as the new position; and a third transmission condition processing unit. The first part, when the transmitted data satisfies the third transmission condition of being greater than or equal to 11 and less than or equal to 20, determines the meaning of the transmitted data as a rotation-swap (RS) state, sets the new position as the old position, applies rotation-swap (RS) to the old position, and sets the position that has moved by Y (D-11) as the new position; and the second part, when the transmitted data satisfies the fourth transmission condition of 21, determines the meaning of the transmitted data as an end state, sets the new position as the old position, applies rotation-swap (RS) to the old position, and sets the position that has moved by Y (D-11) as the new position.

[0025] In one embodiment, the transmission status judgment module may further include: a transmission error judgment unit, which judges the transmission data as an error state when the transmission data does not meet the first to fourth transmission conditions.

[0026] To achieve another objective of the present invention, according to one embodiment, a decoder logic is provided, which is configured in a data communication system. The data communication system uses PAM4 signals to drive link units consisting of four transmission lines each. Utilizing graph coloring theory, 24 state symbols whose sum of PAM4 signals is 0 and whose results from the six comparators are non-repeating are used for communication. The decoder logic receives six PAM4 comparison signals output from the PHY of the communication unit and recovers the 24 state symbols. The decoder logic includes: a receiving initial position setting module, which, in the case of 24 state symbols and each state... The relative distance between symbols is defined in the state transition diagram by the transition symbols X, Y, and Z. A specific position set as the initial position is set as the new position, and 0 is set as the new data. The data analysis module receives data from the received data stream, sets the new data as the old data, sets the received data as the new data, calculates the data difference between the set old data and the set new data, and analyzes the number of X, Y, and Z respectively. The receiving state judgment module checks any of the multiple receiving conditions based on the analyzed number of X, Y, and Z and the received data, and judges the corresponding state.

[0027] In one embodiment, the receiving state determination module may include: a first receiving condition processing unit, which determines the received data as idle and stores the received data when the result of analyzing the received data satisfies a first receiving condition that the number of X is 1, the number of Y is 0, and the number of Z is 0; a second receiving condition processing unit, which determines the received data as corresponding to the position Y-1 and stores the received data when the result of analyzing the received data satisfies a second receiving condition that the number of X is 0, the number of Y is 1 to 11, and the number of Z is 0; a third receiving condition processing unit, which determines the received data as corresponding to the position 11+Y and stores the received data when the result of analyzing the received data satisfies a third receiving condition that the number of X is 0, the number of Y is 0 to 9, and the number of Z is 1; and a fourth receiving condition processing unit, which determines the received data as ending and stores the received data when the result of analyzing the received data satisfies a fourth receiving condition that the number of X is 0, the number of Y is 10, and the number of Z is 1.

[0028] In one embodiment, the receiving status judgment module may further include: a receiving error judgment unit, which judges the received data as an error state when the first to fourth receiving conditions are not met.

[0029] To achieve another objective of the present invention, an encoding method according to one embodiment includes: (a) in a state transition diagram having 24 state symbols, where the relative distance between each state symbol is defined by transition symbols X, Y, and Z, setting a specific position set as the initial position as a new position; (b) receiving transmission data from a transmission data stream; (c) when the transmission data satisfies a first transmission condition of 22, determining the meaning of the transmission data as an idle state, setting the new position as the old position, and setting the position in the old position that is converted to X as the new position; (d) transmitting the PAM4 value of the data corresponding to the new position to the transmission line via PHY, and then returning to step (b); (e) when the transmission data satisfies a second transmission condition greater than or equal to 0 and less than or equal to 10, determining the meaning of the transmission data as a rotated (ROTATE, R) state, setting the new position as the old position, setting the position of the old position plus Y(D+1) as the new position, and then returning to step (d); (f) When the transmitted data satisfies the third transmission condition of being greater than or equal to 11 and less than or equal to 20, the meaning of the transmitted data is determined to be a rotation-swap (RS) state, the new position is set as the old position, after applying rotation-swap (RS) to the old position, the position that has moved by Y (D-11) is set as the new position, and then the process returns to step (d); and (g) when the transmitted data satisfies the fourth transmission condition of 21, the meaning of the transmitted data is determined to be an end state, the new position is set as the old position, after applying rotation-swap (RS) to the old position, the position that has moved by Y (D-11) is set as the new position, and then the process returns to step (a).

[0030] In one embodiment, it may further include: (h) when the transmitted data does not meet the first to fourth transmission conditions, after determining that it is an error state, returning to step (a).

[0031] To achieve another objective of the present invention, a decoding method according to one embodiment includes: (a) in a state transition diagram having 24 state symbols, where the relative distance between each state symbol is defined by transition symbols X, Y, and Z, setting a specific position set as the initial position as a new position, and setting 0 as new data; (b) as receiving data from the received data stream, setting the new data as old data, calculating the data difference between the set old data and the set new data after setting the received data as new data, and analyzing the number of each of X, Y, and Z; (c) when the result of analyzing the received data satisfies a first reception condition where the number of X is 1, the number of Y is 0, and the number of Z is 0, determining the received data as idle, storing the received data, and returning to step (b); (d) when the result of analyzing the received data satisfies a second reception condition where the number of X is 0, the number of Y is 1 to 11, and the number of Z is 0, determining the received data as corresponding to the position Y-1, storing the received data, and returning to step (b); (e) When the result of analyzing the received data satisfies the third receiving condition that the number of X is 0, the number of Y is 0 to 9, and the number of Z is 1, the received data is determined to correspond to the position 11+Y, the received data is stored, and the process returns to step (b); and (f) when the result of analyzing the received data satisfies the fourth receiving condition that the number of X is 0, the number of Y is 10, and the number of Z is 1, the received data is determined to be finished, the received data is stored, and the process returns to step (a).

[0032] In one embodiment, it may further include: (g) when the received data does not meet the first to fourth receiving conditions, after determining that it is an error state, returning to step (a).

[0033] Invention Effects According to this invention, by controlling the DC level characteristics of the four transmission lines transmitting PAM4 signals, the frequency at which a specific symbol level is maintained for an extended period can be minimized. This suppression of the continuation of the same electrical state mitigates transmission line impedance variations in link units, resulting in improved overall system response characteristics. Attached Figure Description

[0034] Figure 1 This is a block diagram used to schematically illustrate the data communication system according to the present invention.

[0035] Figure 2 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are three transmission lines constituting a link unit.

[0036] Figure 3 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are four transmission lines constituting a link unit.

[0037] Figure 4 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are 5 transmission lines constituting a link unit.

[0038] Figure 5 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are 6 transmission lines constituting a link unit.

[0039] Figure 6 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are 6 transmission lines constituting a link unit.

[0040] Figure 7 yes Figure 1 The electrical equivalent modeling circuit of a transmission line is shown.

[0041] Figure 8 It is used for explanation Figure 7 The transmission line shown is a circuit symbol for a link unit consisting of four lines.

[0042] Figure 9 It is used for explanation Figure 8 The diagram shown illustrates the concept of a link consisting of n link units.

[0043] Figure 10 This is a block diagram illustrating a data communication system according to an embodiment of the present invention.

[0044] Figure 11 It is used for explanation Figure 10 The diagram shows the first PHY unit, the link unit, and the second PHY unit.

[0045] Figure 12 It is used for explanation Figure 11 The circuit diagram shown is an example of a DRV block.

[0046] Figure 13 It is used for explanation Figure 11 The circuit diagram shows another example of a DRV block.

[0047] Figure 14 It is used for explanation Figure 11 The circuit diagram shows another example of a DRV block.

[0048] Figure 15 It is used for explanation Figure 14 The circuit diagram shown is an example of a current transmitter.

[0049] Figure 16 It is used for explanation Figure 11 The circuit diagram shown is an example of an RCV block.

[0050] Figure 17 It is used for explanation Figure 11 The circuit diagram shows another example of an RCV block.

[0051] Figure 18 It is used for explanation Figure 16 or Figure 17 The circuit diagram shown is an example of a voltage comparator.

[0052] Figure 19 It is used for explanation Figure 18 The circuit diagram of the first differential voltage comparator of the voltage comparator module is shown.

[0053] Figure 20 It is used for explanation Figure 16 or Figure 17 The circuit diagram shown is an example of a voltage comparator module.

[0054] Figure 21 It is used for explanation Figure 20 The circuit diagram of the first differential voltage comparator of the voltage comparator module is shown.

[0055] Figure 22 It is used for explanation Figure 11 The circuit diagram shows another example of a DRV block.

[0056] Figure 23 It is used for explanation Figure 14 The circuit diagram shows another example of a current transmitter.

[0057] Figure 24 It is used for explanation Figure 16 The circuit diagram shown is an example of a voltage generation unit.

[0058] Figure 25 It is used for explanation Figure 16 The circuit diagram shows another example of a voltage generation unit.

[0059] Figure 26 It is used for explanation Figure 11 The circuit diagram shows another example of an RCV block.

[0060] Figure 27 It is used for explanation Figure 11 The circuit diagram shows another example of an RCV block.

[0061] Figure 28a , Figure 28b and Figure 28c It shows the basis Figure 27 The graph shows the signal amplitude of the output impedance at the X port of the RCV block.

[0062] Figure 29a and Figure 29b It is used for explanation Figure 16 or Figure 17 The circuit diagram shows another example of a current comparator module.

[0063] Figure 30 It is used for explanation Figure 26 Or the circuit diagram of the first differential current comparator of the current comparator module shown in Figure 29.

[0064] Figure 31 It is used for explanation Figure 26 Or the circuit diagram of the first differential current comparator of the current comparator module shown in Figure 29.

[0065] Figure 32 The eye diagram of the PAM4 signal received by the PAM4 signal-based communication system according to the comparative example is shown.

[0066] Figure 33 An eye diagram of the PAM4 signal received by the PAM4 signal-based communication system according to the present invention is shown.

[0067] Figure 34 It is used for explanation Figure 10 The block diagram shown is of the first encoding / decoding unit.

[0068] Figure 35 It is used for explanation Figure 10 The diagram shows the state symbol recovery process performed by the first or second communication unit.

[0069] Figure 36 This is a diagram used to illustrate a signal transmission state transition diagram in which state symbols are arranged in a ring shape according to the definition of the present invention.

[0070] Figure 37 It is a diagram used to illustrate the process of allocating and receiving decimal transmitted data.

[0071] Figure 38 This is a block diagram illustrating the encoder logic according to an embodiment of the present invention.

[0072] Figure 39 This is a block diagram illustrating the decoder logic according to an embodiment of the present invention.

[0073] Figure 40 This is a flowchart illustrating an encoding method according to an embodiment of the present invention.

[0074] Figure 41 This is a flowchart illustrating a decoding method according to an embodiment of the present invention. Detailed Implementation

[0075] The invention will now be described in more detail with reference to the accompanying drawings. The invention can be modified and taken in various forms; therefore, specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the invention to the specific forms disclosed, and it should be understood to include all modifications, equivalents, and even substitutions falling within the spirit and technical scope of the invention.

[0076] Similar reference numerals are used for similar structural elements in the description of the accompanying drawings. In the drawings, the dimensions of the structures are shown enlarged for clarity of the invention.

[0077] The terms "first," "second," etc., can be used to describe various structural elements, but the structural elements should not be limited by these terms. These terms are used only to distinguish one structural element from others. For example, without departing from the scope of the invention, a first structural element can be named a second structural element, and similarly, a second structural element can be named a first structural element. Singular expressions include plural expressions unless explicitly indicated in the context.

[0078] In this application, terms such as “comprising” or “having” are intended to specify the presence of features, figures, steps, operations, structural elements, components or combinations thereof as described in the specification, and should be understood to not preclude the presence or additional possibility of one or more other features, figures, steps, operations, structural elements, components or combinations thereof.

[0079] Furthermore, unless otherwise defined, all terms used herein, including technical or scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms identical to those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be construed as having an idealized or overly formalized meaning unless expressly defined in this application.

[0080] First, the terms described in this specification are defined as follows.

[0081] A "processor unit" is an IC that is responsible for logical operations, such as an AI processor, GPU, CPU, and SoC.

[0082] A "processor module" is a board or assembly consisting of high-bandwidth memory (HBM) and processor units.

[0083] "DDR RAM" includes DDR4, DDR5, DDR6, GDDR5, GDDR6, etc.

[0084] "TSV-link" is a signal transmission line (transmission line) used to connect the internal DRAM die and the interface die of HBM through a through-silicon via (TSV).

[0085] A "T-link" is a signal transmission line (transmission line) used to connect the processor unit and the HBM via a silicon interposer or PCB.

[0086] The Physical Layer (PHY) is the layer that transmits and receives data as electrical signals per bit unit; it is the layer that transmits and receives electrical signals to and from the actual transmission line. This invention relates to the configuration of a PHY unit and the contents of an encoder / decoder for transmitting and receiving data through the PHY unit.

[0087] A “link unit” is defined by multiple transmission lines.

[0088] A “communication link” is defined by multiple link units.

[0089] A transmission line unit (e.g., link unit, T-link unit, TSV-link unit) refers to the smallest communication unit composed of PAM signals, consisting of 3, 4, 5, or other transmission lines. A communication link is formed by expanding a link unit by N units. This communication link, as the signal transmission medium, can be constructed from T-links, TSV-links, PCB patterns, wires, etc.

[0090] "Communication system" refers to a two-way communication system implemented by a first communication module (or first communication unit), a transmission line (or link unit) bundle, and a second communication module (or second communication unit).

[0091] A “communication system module” refers to a system consisting of at least two communication systems, with the number of transmission lines adjusted to be an integer multiple of 4 (4×N), such as 8, 16, 32, 64, 128, 256, ..., 1024, 2048.

[0092] "Communication subject" refers to a semiconductor system that, in a communication system or communication system module consisting of one or more components, governs one or the other side and performs data transmission (i.e., sending and receiving), functions as a host, device, server, or client. In this embodiment, in a structure where a memory device and a processor unit are connected, the communication subject can refer to both the memory device and the processor unit. Alternatively, in a structure where processor units are connected, the communication subject can refer to the processor units on both sides.

[0093] "Non-Return-to-Zero (NRZ) signal" refers to a signal modulation method that converts the meaning of "0" and "1" of data into two different amplitude electrical signals. For example, when the NRZ signal value corresponding to the value of 1 bit is 0V or 1V, bit value 0 is simply converted into a 0V signal, and bit value 1 is converted into a 1V signal.

[0094] Pulse Amplitude Modulation (PAM) signals refer to encoding / decoding techniques that convert two or more bits into electrical signals with at least three amplitudes. For example, PAM4 uses four signal levels per transmission line. For 2-bit data (00, 01, 10, 11), it encodes the data using relative voltages (-3, -1, +1, +3) and represents this value through a single transmission line. PAM4 can transmit 2 bits of data using only one transmission line, thus transmitting twice the amount of data compared to NRZ (Noise, Transmission, and Reduction) transmission. Generally, PAM has disadvantages compared to NRZ, including higher power consumption, lower signal-to-noise ratio (SNR), and higher probability of error (BER). However, PAM, through the application of sophisticated signal processing and error correction techniques, is commonly used for high-speed data transmission.

[0095] PAM4 is a signal modulation technique that uses four different signal levels for high-speed signal transmission. To represent the digital logic signals 1 and 0, PAM4 signals use two more levels than the comparative NRZ signal, which uses only high and low signal levels. NRZ signals can only transmit one bit of information within one state symbol period. In contrast, PAM4 signals use four different signal levels (00, 01, 10, 11) to transmit signals, thus allowing two bits of logic information to be transmitted within one state symbol period. Therefore, compared to NRZ, PAM4 has the advantage of doubling the bit transmission rate at a given baud rate.

[0096] Bit Error Ratio (BER) is an indicator used in digital communication to evaluate the degree to which digital signals are affected by changes in analog characteristics such as noise and distortion. It is usually referred to as the proportion of erroneous bits relative to the total number of bits transmitted.

[0097] "Encoding" is the process of converting data to be transmitted into state symbols of specific signals that have the physical meaning of electrical signals.

[0098] "Decoding" is the process of recovering data from the physically meaningful state symbols of a received electrical signal.

[0099] Graph coloring theory is a method in graph theory for assigning colors to vertices of the same color to prevent them from being adjacent. It can be used to define the invariants of a graph.

[0100] A "state symbol" is the basic transmission unit used to transmit digital data in a communication system. A state symbol is a signal unit represented by a specific state, waveform, frequency, phase, amplitude, etc., of a transmission line. A state symbol can represent the meaning of one or more bits at a time. For example, in the case of PAM2, one bit is transmitted each time using two state symbols (0 and 1 respectively). In the case of PAM4, two bits are transmitted each time using four state symbols (00, 01, 10, and 11 respectively). In the case of PAM8, three bits are transmitted each time using eight state symbols (000, 001, 010, 011, 100, 101, 110, and 111 respectively). Specifically, a "state symbol" refers to a state symbol representing 24 different transmission line state values, defined according to the present invention (graphic shading theory and the condition that the sum of the signal lines is 0), in a system with a link unit having four transmission lines implemented based on graphic shading theory and each transmission line using PAM4 signals. The 24 state symbols are divided into group A and group B, each group containing 12 state symbols. The state symbols with the same number in groups A and B have an inverse relationship where the symbols are opposite to each other and the absolute values ​​are the same. For example, A0 and B0, A1 and B1, and A11 and B11 are corresponding pairs and constitute this relationship.

[0101] A "data symbol" is a value calculated based on the difference between the previous state symbol and the current state symbol, and it represents the data value used in communication. In this embodiment, the data value is defined as 21 cases from 0 to 20.

[0102] A "control symbol" is a state symbol representing the control value used in communication, calculated from the difference between the previous state symbol and the current state symbol. In this embodiment, the IDLE and END state values ​​are used as control symbols. On the other hand, in a system that performs control functions such as start, end, and wait for data communication through a separate communication line, the "IDLE" and "END" control symbols can be redefined as two data symbols added to the existing 21 data symbols for transmission and reception. This can increase the overall data transmission capacity of the link unit (i.e., the transmission line).

[0103] "Movement value" represents the positional difference between the previous state symbol and the current state symbol. It refers to the distance the state symbol has moved, calculated based on the positional movement definition of this invention, according to the rotation (ROTATE, R) or rotation-swap (ROTATE-SWAP, RS) of the state symbol.

[0104] The "State Transition Diagram" consists of 12 state symbols each in groups A and B, arranged in a circular pattern. The 0th and 11th state symbols are connected to each other. The groups are arranged clockwise in the order 0 → 1 → 2 → ... → 11 → 0, with group A on the inside and group B on the outside. The state symbols in both groups are arranged in the same order, forming 12 pairs. State transitions are based on the difference between the previous and current state symbols, categorized as X, Y, and Z, thus representing the method and distance of movement. Even during clockwise rotation or group transitions, the value of the current state symbol should always be less than or equal to the value of the previous state symbol, maintaining the circular structure.

[0105] "Swap (S)" defines the case where the state symbols of groups A and B are transferred to the opposite group without increasing their order, only exchanging positions. The swap state is defined as the control symbol value IDLE.

[0106] "Rotate (R)" is defined as a movement within the same group (A or B) along a circular direction without changing the group itself, based on a previous state symbol. The rotation value, which can be represented solely by rotation, is a decimal value from 1 to 11. In this case, the data symbol value is assigned a decimal value from 0 to 10. The value of a data symbol is defined as the sum of the rotation values ​​minus 1, as shown in the following formula.

[0107] The value of the data symbol = (overall rotation value) - 1 "Rotate-Swap (RS)" defines a situation where a group (A or B) is swapped to another group in its previous state symbol, and a rotation occurs within the swapped group. In Rotate-Swap (RS), Swap (S) is defined as a movement value of decimal +12 that can only occur once in a single data transfer, and Rotation (R) is defined as a movement value of decimal 0 to 10. Therefore, the movement values ​​that can be represented by Rotate-Swap (RS) are decimal 12 to 22. When the movement value is decimal 12 to 21, the value of the data symbol is assigned to decimal 11 to 20 as shown in the following relation (R-1 relation). The value of the data symbol = (overall rotation - value of the swap) - 1 When the movement value is 22 in decimal, it is defined as the control signal END.

[0108] A "data transfer bundle (or data transfer unit)" refers to the basic unit used in data transfer between memory elements (DRAM, Flash Memory, SRAM, etc.) and processor units, or between processor units themselves. It is equivalent to a page size or a Direct Memory Access (DMA) transfer unit, and can be defined as 512 bytes, 1KB, 2KB, or a maximum of 1024KB, depending on the application environment. In other words, it is an optimized transfer unit composed of multiple data sets determined according to the data transfer protocol between memory elements and processor units.

[0109] Figure 1 This is a block diagram used to schematically illustrate the data communication system according to the present invention.

[0110] Reference Figure 1 According to an embodiment of the present invention, a data communication system includes: a transmission line 10, a first processor unit 21 disposed on one side of the transmission line 10, a first encoder / decoder 22 connected to the output of the first processor unit 21, a first transmit / receive buffer 23 connected to the output of the first encoder / decoder 22 and one side of the transmission line 10, a second transmit / receive buffer 31 connected to the other side of the transmission line 10, a second encoder / decoder 32 connected to the output of the second transmit / receive buffer 31, and a second processor unit 33 connected to the output of the second encoder / decoder 32.

[0111] In this embodiment, the first processor unit 21, the first encoder / decoder 22, and the first transmit / receive buffer 23 can define a first chip, and the second transmit / receive buffer 31, the second encoder / decoder 32, and the second processor unit 33 can define a second chip. Here, the first chip and the second chip refer to a complete chip formed by combining modular components in semiconductor design. Traditional methods focus on designing a large chip, but chip-count technology combines multiple small chips (chips) to form a system. 2.5D and 3D packaging technologies can be used to improve the integration performance between chip-counts. That is, chip-count systems are developed to overcome the limitations of traditional monolithic chips. Dies within the package can be connected through a silicon interposer, and chip-counts within the chip-count system can communicate with each other according to die-to-die communication standards such as Universal Chiplet Interconnect Express (UCIe).

[0112] This invention does not use serializers / deserializers (hereinafter SerDes) and PLLs. Instead, it uses encoding / decoding of parallel data to transmit / receive data in units of defined state symbols, thereby simplifying the circuit configuration.

[0113] Furthermore, this invention determines the received value by comparing the difference between transmission lines, which not only improves the BER value, but also minimizes the silicon area and the energy consumption required for data transmission by minimizing the number of comparators.

[0114] Furthermore, the present invention uses a method that immediately converts parallel data into state symbols and transmits them via parallel transmission lines without overhead or parallel-to-serial data conversion. Therefore, it does not use flip-flops for temporary data storage in the separate SerDes data conversion process, and there is no time latency associated with the SerDes process.

[0115] Table 1 shows an example of a portion of the code for 8B10B code conversion.

[0116] [Table 1]

[0117] Referring to Table 1, the technique of converting 8-bit parallel data into 10-bit serial data is used to achieve reliable data transmission in high-speed data communication technologies such as USB 3.0, 1Gbit LAN, and PCI-Express (PCIe).

[0118] USB 3.0 uses a serial data transmission method for high-speed data transfer. USB 3.0 can transmit data at SuperSpeed ​​(5Gbps) and transmit data securely using 8b / 10b encoding and other methods.

[0119] 1Gbit LAN is a standard for high-speed data transmission over a network, which encapsulates data into Ethernet frames for transmission.

[0120] PCIe is an interface within a computer that transmits data between various devices (such as graphics cards and network cards). PCIe uses serial data transmission to maximize data transfer speed and efficiency. Data transmission is performed using 8b / 10b encoding in each channel.

[0121] This invention can solve various problems that arise in a system when the speed of parallel data generated in the system is faster than the signal transmission speed achievable in the transmission lines between systems (e.g., TSV-links, T-links) due to the development of semiconductor manufacturing and design technologies.

[0122] To this end, at least three transmission lines are bundled together into a link unit, and the number of link units is expanded according to the amount of data to be transmitted, so as to operate in the form of a T-link or TSV-link.

[0123] As an example, when 3 transmission lines are bundled into one link unit, the required transmission lines for the link are 3 × N. Here, N is an integer. As another example, when 4 transmission lines are bundled into one link unit, the required transmission lines for the link are 4 × N. In this way, more than 5 transmission lines can be bundled together to implement a link unit as needed. When 64 transmission lines are allocated to the link, 16 link units consisting of 4 transmission lines are used (i.e., 64 / 4 = 16).

[0124] The individual transmission lines that make up each link unit (i.e., the bundle of transmission lines) use PAM signals. Typically, signal levels (signal values) such as PAM3, PAM4, PAM5, PAM6, and PAM7 are used. PAM signal levels can be implemented in various forms depending on the interface voltage or current used by the transmission line, and are therefore defined as relative values ​​as shown in Table 2 below.

[0125] [Table 2]

[0126] Referring to Table 2, the PAM3 signal has 3 signal levels: (-1, 0, +1). The PAM4 signal has 4 signal levels: (-3, -1, +1, +3). The PAM5 signal has 5 signal levels: (-2, -1, 0, +1, +2). The PAM6 signal has 6 signal levels: (-5, -3, -1, +1, +3, +5). The PAM7 signal has 7 signal levels: (-3, -2, -1, 0, +1, +2, +3).

[0127] Using the number M of transmission lines constituting a link unit and the number N of PAM signal levels, the number of state symbols (i.e., signal types) that can be represented by a single link unit is M. N Here, M and N can be expanded to 3, 4, 5, 6, 7, etc., as needed.

[0128] The number of PAM signal levels can be defined as the same as or greater than the number of transmission lines. For example, if there are 3 PAM signal levels, then PAM3 is defined, which has 3 signal levels (-1, 0, +1). If there are 4 PAM signal levels, then PAM4 is defined, which has 4 signal levels (-3, -1, +1, +3). If there are 5 PAM signal levels, then PAM5 is defined, which has 5 signal levels (-2, -1, 0, +1, +2).

[0129] However, to improve BER, the optimal number is preferably the same as the number of PAM signal levels.

[0130] The following describes the process of specifying the number and form of state symbols used in this invention.

[0131] In having the above M N Among the state symbols generated by the combination of all possible cases, graph coloring theory is applied to construct polygons with the same number of vertices as the number of transmission lines used in each link unit. For example, if the number of transmission lines is 3, 4, 5, and 6, then triangles, quadrilaterals, pentagons, and hexagons are constructed.

[0132] Transmission lines are assigned to the vertices of the polygon (e.g., triangles, quadrilaterals, etc.), and line segments (or differences) of graph theory are assigned to the line segments connecting the vertices. The assigned line segment values ​​do not overlap with each other.

[0133] When the sum of the PAM values ​​in the transmission line that constitutes the link unit is "0", and all non-repeating line segments connecting each vertex (transmission line) are connected, only the state symbol corresponding to the case where the value of the connected line segment is different from that of the two ends (vertices) connected is selected and defined as the final state symbol.

[0134] In the final state symbols selected, the values ​​at both ends of the vertex (transmission line) of the line segment (PAM value of the transmission line) are all different from each other. Therefore, in the process of sending / receiving state symbols, there is a differential value for all state symbols ("a value that is not 0, and the result in the comparator circuit is clearly 0 or 1").

[0135] Therefore, the transmission / reception of the selected final state symbols has the same effect as communication methods using differential signals. In the field of communication for data transmission, this differential signal transmission method also has excellent signal transmission characteristics in the presence of noise on the transmission line, power supply noise, low-level transmission lines, etc., so the result can be expected to improve the BER (Bit Error Rate).

[0136] Furthermore, in the status symbols, only signals whose sum of PAM values ​​of the transmission lines constituting the link unit is "0" are used as status symbols for communication. This allows the energy consumption of the link required for signal transmission to remain constant regardless of the status symbol, thus simplifying the power management and design of the communication system and reducing EMI radiated noise.

[0137] This will be explained in detail below along with examples.

[0138] Example 1) When the link unit consists of three transmission lines (A, B, C) and uses PAM3 signals, the number of state symbols that can be represented by the link unit is M. N There are a total of 27 (i.e., 3) 3 =27). Here, PAM4, PAM5, etc., which have more signal levels than PAM3, can also be used. However, in order to improve BER and maximize the signal level difference between transmission lines, PAM3 signals are used.

[0139] Figure 2 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are three transmission lines constituting a link unit.

[0140] Reference Figure 2 Assign transmission lines A, B, and C to the vertices of the triangle as is done in graphics coloring theory, and define line segments that do not overlap with each other and connect all vertices. Here, the defined line segments are RX[0], RX[1], and RX[2].

[0141] When the PAM3 values ​​of transmission lines A, B, and C are all added together, the sum of the transmission lines is "0" (A+B+C=0). If only the two ends (vertices) of all segments RX[0], RX[1], and RX[2] are selected to have different values ​​from each other, then only 6 state symbols remain out of all 27 state symbols. In this embodiment, these 6 state symbols are defined as the final state symbols used in communication. As shown in Table 3 below, the 6 state symbols are defined as the final state symbols.

[0142] [Table 3]

[0143] Referring to Table 3, there are 3 transmission lines (A, B, C) that constitute a link unit. The final state symbol using PAM3 signal is defined, and the allocation of state symbol and PAM3 value for each transmission line is indicated.

[0144] This is defined as assigning a 1:1 numerical value (e.g., decimal 0-5) to each of the six state symbols. Based on this definition, communication is achieved by encoding during data transmission and decoding during data reception.

[0145] Example 2) When the link unit consists of four transmission lines (A, B, C, and D) and uses PAM4 signals, the number of state symbols that can be represented by the link unit is M. N There are a total of 256 (i.e., 4)4 =256).

[0146] Figure 3 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are four transmission lines constituting a link unit.

[0147] Reference Figure 3 Assign each transmission line A, B, C, and D to the vertices of the quadrilateral as is done in graphics coloring theory, and define line segments that do not repeat each other and connect all vertices. Here, the defined line segments are RX[0], RX[1], RX[2], RX[3], RX[4], and RX[5].

[0148] When the PAM4 values ​​of transmission lines A, B, C, and D are all added together, the sum of the transmission lines is "0" (A+B+C+D=0). If only the two ends (vertices) of all segments RX[0], RX[1], RX[2], RX[3], RX[4], and RX[5] are selected, all of which have different values, then only 24 state symbols remain out of the total 256 state symbols. In this embodiment, these 24 state symbols are defined as the final state symbols used in communication. As shown in Table 4 below, these 24 state symbols are defined as the final state symbols.

[0149] [Table 4]

[0150] Referring to Table 4, there are 4 transmission lines (A, B, C and D) that constitute a link unit. The final state symbol using PAM4 signal is defined, and the allocation of state symbol and PAM4 value for each transmission line is indicated.

[0151] This is defined as assigning 24 state symbols to 24 numerical values ​​(e.g., decimal 0-23) in a 1:1 ratio. Based on this definition, communication is achieved by encoding during data transmission and decoding during data reception.

[0152] Example 3) When the link unit consists of 5 transmission lines (A, B, C, D, and E) and uses PAM5 signals, the number of state symbols that can be represented by the link unit is M. N The total is 3125 (i.e., 5 5 =3125).

[0153] Figure 4 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are 5 transmission lines constituting a link unit.

[0154] Reference Figure 4The transmission lines A, B, C, D, and E are assigned to the vertices of the pentagon as used in graphical coloring theory, and line segments that are unique to each other and connect all vertices are defined. Here, the defined line segments are RX[0], RX[1], RX[2], RX[3], RX[4], RX[5], RX[6], RX[7], RX[8], and RX[9]. The number of state symbols inferred from the 10 comparators selected by PAM5's graphical coloring theory is 120.

[0155] Figure 4 The detailed explanation of the reasoning using diagrams can be found in... Figure 2 and Figure 3 The content described herein can be easily deduced, therefore detailed explanations are omitted.

[0156] Example 4) Figure 5 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are 6 transmission lines constituting a link unit.

[0157] Reference Figure 5 In the case of using PAM6 signals and the link unit being implemented by 6 transmission lines, a graphical pattern for inference using graphical coloring theory to select the state symbol is shown, which consists of 12 line segments (comparators).

[0158] Figure 5 The detailed explanation of the reasoning using diagrams can be found in... Figure 2 and Figure 3 The content described herein can be easily deduced, therefore detailed explanations are omitted.

[0159] Example 5) Figure 6 It is a diagram used to illustrate the reasoning using graphic coloring theory when there are 6 transmission lines constituting a link unit.

[0160] Reference Figure 6 In the case of using PAM6 signals and the link unit being implemented with 6 transmission lines, a graphical pattern for inference using graphical coloring theory to select state symbols is shown, consisting of 15 line segments (comparators). The number of state symbols inferred from the 15 comparators selected by the graphical coloring theory of PAM6 is 720.

[0161] Figure 6 Detailed graphical descriptions can be found from Figure 2 and Figure 3 The content described herein can be easily deduced, therefore detailed explanations are omitted.

[0162] In parallel data communication using the aforementioned PAM signals, the state symbols used to represent PAM signal pairs in each transmission line as electrical signals can be selected by a program, based on the principle of a graphic coloring algorithm.

[0163] Refer again Figure 1 A system that is located at both ends of a transmission line, generates data, and sends / receives the generated data as the main body of communication can be a structure with two processor units connected together, or a structure in which processor units and memory devices such as HBM are arranged on one side, and DRAM dies and base logic dies of HBM are arranged on the other side.

[0164] The physical signal connection between communication entities includes a data link and a control link. The data link performs data transmission and reception. The control link includes functions such as enable / disable, direction control, data read / write, idle, start, stop, error check, built-in test, and loopback test.

[0165] In this specification, the data link will be the primary focus of the description. The control link will not be described separately, but will be provided as a condition where sufficient control is required to enable communication. Hereinafter, the data link will be referred to as the link.

[0166] This invention is based on supporting bidirectional communication, but this specification mainly describes sending data from one side and receiving data from the other side. Sending data from the other side and receiving data from one side is the reverse of the above process, therefore detailed description is omitted.

[0167] Figure 7 yes Figure 1 The electrical equivalent modeling circuit of a transmission line is shown.

[0168] Reference Figure 7 L0 represents the inductance component, RS represents the impedance component (series resistance), L1 represents the reactance component, and CS0~CS2 represent the transmission line model based on the parasitic capacitance component. The inductance component L0 and the impedance component RS are relatively small values ​​and have a relatively minor impact on high-speed signal transmission. Conversely, although the parasitic capacitance components Cs0~Cs3 are also relatively small values, they are the factors with the greatest impact on high-speed parallel signal transmission.

[0169] When the transmission line model consists of multiple components, there is also cross-coupling capacitance between the transmission lines, but this will not be described separately in this invention.

[0170] In some embodiments, transmission lines are used to couple adjacent chips. In one aspect, transmission lines can increase the available peripheral space for inter-chip connectivity and overall capacity. In another aspect, transmission lines can provide increased bandwidth for inter-chip communication with reduced latency.

[0171] In some embodiments, the transmission line can be used as a transmission line between logic chips. The transmission line can be oriented towards communication, meeting bandwidth, power, latency, and cost objectives. Logic chips such as system-on-a-chip (SoC) may include a central processing unit (CPU) or a graphics processing unit (GPU). Furthermore, the peripheral portion of the logic chip can be formatted to enable memory integration and other input / output (I / O) connections to other devices.

[0172] Transmission lines can support metal stacks and logic (e.g., transistor types) compatible with communication functions. Transmission lines can be packaged in various configurations, including chip-on-wafer (CoW) and 2.5D packaging technologies. CoW can also be, for example, a 2.5D or 3D arrangement. Here, individual chips are bonded together (i.e., chip-to-chip) or bonded to an interposer (i.e., chip-interposer-chip). Bonding technologies can be microbumps (high-density I / O), or ACF, or hybrid bonding (metal-to-metal) supporting very high-density I / O, or even optics. Instead of individual chips, wafer-to-wafer (W2W) bonding is also possible and can be used depending on the application. For example, CoW can involve a single area of ​​a support wafer or panel larger than the chip mounted on the support wafer, while W2W can involve the same area of ​​a single wafer or panel. 2.5D packaging can use smaller, high-density interconnects between two chips. The chip used for 2.5D packaging can be a short-length passive bridge or a longer length as a transmission line arrangement. These transmission lines provide options for balancing bandwidth, power, complexity, heat and power delivery, and other architectural requirements. Furthermore, the transmission lines can be active silicon (or other device technologies such as GaAs). Transmission lines can also be encapsulated in a molding compound and optionally include multiple component connections via bridges. Therefore, transmission lines for 2.5D packaging can also be individually formed and packaged using 2.5D packaging. Larger transmission lines can also impose special requirements on managing mechanical stress and other assembly issues when assembled to a substrate. Connections between the chip and the transmission line can be achieved using solder (microbumps), or ACF, and hybrid bonding (metal-to-metal). In some exemplary implementations, CoW integration can use microbumps or even higher density hybrid bonding for high-performance logic with high-density I / O. In some implementations, CoW integration can include hybrid bonding of an interposer and a silicon chip. In some embodiments, CoW integration can include silicon chips connected to back-end-of-the-line (BEOL) interconnects in a chip-like manner. For example, the silicon chip may have a partial BEOL (Block Interconnect) structure and interconnects, with a subsequent second-level BEOL structure connecting the silicon chip in a chip-like manner. The silicon chip may be embedded in an inorganic gap filler (e.g., oxide) material on which the second-level BEOL structure is formed. In some embodiments, 2.5D packaging can be used for chipset optical functions with moderate bandwidth and latency requirements.

[0173] In one implementation, a transmission line can serve as a memory strip to couple a memory chipset to a logic chip. The memory chipset can be laterally separated. Furthermore, the laterally separated memory chips can be individually packaged or may be part of a die stack having multiple dies or modules. Therefore, according to embodiments, the laterally separated chips can be part of a laterally separated package, die stack, or module. In one aspect, the transmission line enables the logic chip to communicate with various types of DRAM chips, including LPDDR-x, DDR, HMB, etc. According to embodiments, the memory chip is not limited to DRAM, or variations of LPDDR-x, DDR, HBM, etc. Similarly, the logic chip can include various functions (but not limited to) such as a SOC, CPU, GPU, cache, signal processor, glue logic, etc., and can be based on silicon or other technologies (e.g., GaAs). The transmission line can include a memory-compatible physical interface (PHY) (e.g., PHY analog and PHY digital controllers) and a local controller compatible with the memory type. In some implementations, the memory strip is packaged in 2.5D packaging, multi-chip modules (MCMs), and MCMs with bridges, etc. Furthermore, memory modules can be packaged in various shapes for wiring, such as L-shapes.

[0174] Figure 8 It is used for explanation Figure 7 The transmission line shown is a circuit symbol for a link unit consisting of four lines.

[0175] Reference Figure 8 Four transmission lines form a bundle, defining a link unit. Figure 8 The diagram shows a link unit defined by four transmission lines, but a transmission line consisting of four can also define a T-link, TSV-link, PCB pattern, physical connection line, etc.

[0176] Link units can be further bundled into 16 to 32 bundles, expanding into links with 64 to 128 transmission lines. That is, multiple transmission lines define a link unit, and multiple link units define a link. As needed, it can be expanded into links with 256, 512, 1024, 2048, or more transmission lines.

[0177] The communication units connected at both ends of the link are also extended in the same number as the bundle of link units defining the link, forming a communication module. In this specification, multiple communication units are defined as a communication module.

[0178] Figure 9 It is used for explanation Figure 8 The diagram shown illustrates the concept of a link consisting of n link units.

[0179] Reference Figure 9A bundle of n link units defines a link. When the number of link units is expanded to two or more, a mapping module for data transmission and a remapping module for data reception can be added to each communication module.

[0180] Specifically, for data transmission in the communication module, a mapping module is used. This module converts the binary (BIN) or hexadecimal (HEX) data used by the processor unit (or computing system) into a number system according to the number of status symbols for each communication unit using a numeral system. The converted number system values ​​are then assigned as status symbol signals according to the definitions specified by each communication unit. In the case of a PAM4 system with four transmission lines, each communication unit can transmit 24 status symbols.

[0181] For example, when converting 64-bit data (e.g., binary 64-bit or hexadecimal 16-bit) to base 24 14-bit, a logic block is used to assign the converted base 24 values ​​to status symbols for each communication unit. This logic block, composed of combinational logic circuits that determine the result based on the input value, can be designed to perform base conversions at a 1-clock speed (data transfer rate) with minimal overhead using current advanced semiconductor manufacturing technology.

[0182] In addition, a remapping module is used for data reception of the communication module. This module converts the received data of the communication unit into status symbols and then converts the converted status symbols into a number system according to the binary (BIN) or hexadecimal (HEX) system used by each processor unit (or computing system), thereby restoring the original data.

[0183] For example, a logic block can be used to convert received data into status symbols, then convert the status symbols into base-24 14 bundles, and finally convert the bases into 64-bit data (e.g., binary 64 bundles, hexadecimal 16 bundles) and pass it to the processor unit. This logic block, composed of combinational logic, can be designed to perform base conversions at 1-clock speed (data transfer rate) with minimal overhead using current advanced semiconductor manufacturing technology.

[0184] The following example illustrates a scenario where there is one link unit (m=1), four transmission lines constituting the link unit, and PAM4 signaling.

[0185] The following examples illustrate the link unit unit representing the number of transmission lines. Implementing a link unit as a bundle of n (where n is an integer greater than 1) is an extended concept of the link unit, and therefore detailed descriptions are omitted.

[0186] Figure 10 This is a block diagram illustrating a data communication system according to an embodiment of the present invention.

[0187] Reference Figure 10 A first communication unit 200 and a second communication unit 300 are respectively arranged on one side and the other side of a link unit 100 consisting of four transmission lines. In this embodiment, the first communication unit 200 can define a first chip module, and the second communication unit 300 can define a second chip module. A chip is a method of constructing a whole chip by dividing it into multiple small modules. The first chip module and the second chip module are independent small chips that can perform different functions, combining multiple chips to define a system instead of a large chip.

[0188] In this embodiment, when the first communication unit 200 sends a signal, the second communication unit 300 receives a signal, and when the second communication unit 300 sends a signal, the first communication unit 200 receives a signal.

[0189] The first communication unit 200 includes: a first PHY unit 210 connected to one side of the link unit 100 and performing PAM signal transmission / reception; a first encoding / decoding unit 220 connected to the first PHY unit 210; a first pre-encoder 230 connected to the first encoding / decoding unit 220; and a first post-decoder 240 connected to the first encoding / decoding unit 220.

[0190] The first PHY unit 210 includes: one or more DRV blocks that convert TX signals of externally input voltage levels into current and output them to the transmission line through I / O pads; and one or more RCV blocks that receive PAM signals transmitted through the link unit 100 and send / receive PAM signals.

[0191] When transmitting a signal, the first encoding / decoding unit 220 receives the transmission data (TXA_DATA[n:0]) provided by the first pre-encoder 230, forms a status symbol based on the TX signal (TX[7:0]) and the TX enable signal (TX_EN[7:0]), and provides the formed status symbol to the first PHY unit 210. Furthermore, when receiving a signal, the first encoding / decoding unit 220 recovers the status symbol based on the RX signal (RX[5:0]) provided by the first PHY unit 210 and provides it to the first post-decoder 240.

[0192] When a signal is transmitted, the first pre-encoder 230 receives the data to be transmitted from the processor unit or memory device and performs pre-encoding processing.

[0193] The first post-decoder 240 performs post-decoding processing on the received data during data reception.

[0194] The second communication unit 300 includes: a second PHY unit 310 connected to the other side of the link unit 100 and performing PAM signal transmission / reception; a second encoding / decoding unit 320 connected to the second PHY unit 310; a second pre-encoder 330 connected to the second encoding / decoding unit 320; and a second post-decoder 340 connected to the second encoding / decoding unit 320.

[0195] The second PHY unit 310 includes: one or more DRV blocks that convert TX signals of externally input voltage levels into current and output them to the transmission line through I / O pads; and one or more RCV blocks that receive PAM signals transmitted through the link unit 100 and send / receive PAM signals.

[0196] When receiving a signal, the second encoding / decoding unit 320 recovers a status symbol based on the RX signal (RX[5:0]) provided by the second PHY unit 310 and provides it to the second post-decoder 340. Furthermore, when transmitting a signal, the second encoding / decoding unit 320 receives transmission data (TXB_DATA[n:0]) provided by the second pre-encoder 330, forms a status symbol based on the TX signal (TX[7:0]) and the TX enable signal (TX_EN[7:0]), and provides the formed status symbol to the second PHY unit 310.

[0197] When a signal is transmitted, the second pre-encoder 330 receives the data to be transmitted from the processor unit or memory device and performs pre-encoding processing.

[0198] The second post-decoder 340 performs post-decoding processing on the received data during data reception.

[0199] The comparators used in the first PHY unit 210 and the second PHY unit 310 may include voltage comparators. When using a clock (RXA_CLK or RXB_CLK), the voltage comparators used in the first PHY unit 210 and the second PHY unit 310 may include ARM (Analog Re-generative Memory) latched voltage comparators.

[0200] Figure 10 The first PHY unit 210, link unit 100, and second PHY unit 310 can be configured as follows: Figure 11 As shown.

[0201] Figure 11 It is used for explanation Figure 10 The diagram shows the first PHY unit 210, the link unit 100, and the second PHY unit 310.

[0202] Reference Figure 11 A first PHY unit 210 is arranged on one side of the link unit 100, and a second PHY unit 310 is arranged on the other side of the link unit 100.

[0203] Link unit 100 includes four transmission lines. In this embodiment, since there are four transmission lines, PAM4 signals are used as the TX signals to drive each transmission line. In this embodiment, the number of data transmitted using the PAM4 signals used for transmission / reception is 23, of which 21 are actual communication data and 2 include transmission control signals.

[0204] The first PHY unit 210 and the second PHY unit 310 each include four DRV blocks 400 and four RCV blocks 500.

[0205] Each DRV block 400 is configured to drive a PAM4 signal on a single transmission line. Each RCV block 500 uses four input circuits to receive signals received from the single transmission line. The circuitry consists of six comparators, constructed using graphics shading theory, that compare these four inputs and output the result.

[0206] In order to process the drive signal (i.e., TX signal) of the first transmission line, the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD of the first DRV block 400 are respectively connected to the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD[0] of the first PHY unit 210.

[0207] In order to process the drive signal (i.e., TX signal) of the second transmission line, the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD of the second DRV block 400 are respectively connected to the TX_EN[3], TX_EN[2], TX[3], TX[2] and PAD[1] of the first PHY unit 210.

[0208] In order to process the drive signal (i.e., TX signal) of the third transmission line, the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD of the third DRV block 400 are respectively connected to the TX_EN[5], TX_EN[4], TX[5], TX[4] and PAD[2] of the first PHY unit 210.

[0209] In order to process the drive signal (i.e., TX signal) of the fourth transmission line, the TX_EN[1], TX_EN[0], TX[1], TX[0] and PAD of the fourth DRV block 400 are respectively connected to the TX_EN[7], TX_EN[6], TX[7], TX[6] and PAD[3] of the first PHY unit 210.

[0210] The applicable DRV block 400 in this embodiment can be achieved through the following... Figure 12 , Figure 13 and Figure 14 Various circuits are implemented.

[0211] Figure 12 It is used for explanation Figure 11 The circuit diagram shown is an example of a DRV block 400. In particular, the voltage mode driver (DRV) circuit is shown.

[0212] Reference Figure 12 According to an example, the DRV block 400 includes a first TX buffer (ATX0), a first TX resistor (RTX0), a second TX buffer (ATX1), and a second TX resistor (RTX1), which converts the TX signal of the externally input voltage level into current and outputs it to the transmission line of the link unit 100 through the I / O pads.

[0213] In this embodiment, the first TX resistor (RTX0) and the second TX resistor (RTX1) preferably have a resistance value between 300Ω and 10kΩ. Alternatively, the first TX resistor (RTX0) and the second TX resistor (RTX1) can be set to use a current between 50μA and 300μA as a data transmission signal, depending on the voltage (VDD) of the output circuit.

[0214] Conventional signal transmission driver (TX or DRV) circuits model the ideal output buffer (output impedance or Ron of 0Ω) and the Ron (ON resistance value) of the PMOS and NMOS FETs constituting the output buffer terminals as a virtual resistance (RT). The resistance (RT) is set to a value of approximately 10Ω to 300Ω in order to match the impedance of the transmission line.

[0215] Conversely, in this invention, the output resistor, namely the first TX resistor (RTX0) (or the first TX resistor (RTX0) and the second TX resistor (RTX1)), serves to convert the voltage generated in the output buffer into current, thereby generating the transmission current. The purpose of this resistor is to generate a constant current regardless of the transmission line impedance; it typically has a resistance value in the range of 300Ω to 10kΩ, or is set to generate a current level of 50μA to 300μA depending on the VDD and VCOM voltages. This is an important feature distinguishing it from the prior art.

[0216] For example, when VDD is 1.0V and VCOM is 0.5V, if the signal transmission current is set to -25μA, then RTX0 (i.e., using only RTX0) is 20kΩ according to [Mathematical Formula 4] and [Mathematical Formula 5]. If the current is set to 100μA, 150μA, 200μA, and 300μA, then the resistance values ​​of RTX0 are calculated to be 5kΩ, 3.333kΩ, 2.5kΩ, and 1.667kΩ, respectively.

[0217] A first TX buffer (ATX0) and a first TX resistor (RTX0) with a first TX signal (TX[0]) and a first TX enable signal (TX_EN[0]) are connected in series to the I / O pads. A second TX buffer (ATX1) and a second TX resistor (RTX1) with a second TX signal (TX[1]) and a second TX enable signal (TX_EN[1]) are connected in series to the I / O pads.

[0218] exist Figure 12 The document describes how two TX buffers and two resistors are configured in the DRV block 400 to represent four relative current values. Similarly, if three or more TX buffers and three or more resistors are configured in the DRV block 400, more relative current values ​​can be represented, but this is omitted in this specification.

[0219] Figure 13 It is used for explanation Figure 11 The circuit diagram shows another example of a DRV block. In particular, it shows a current-mode driver (DRV) circuit in the current source (reference) mode.

[0220] Reference Figure 13 According to another example, the DRV block 400 includes a PAM encoding unit 410, a first buffer 420, and a voltage-to-current converter 430, which converts the TX signal of the externally input voltage level into current and outputs it to the transmission line through the I / O pads.

[0221] The PAM encoding unit 410 encodes the TX signal based on the TX_EN signal. In this embodiment, if there are 3 transmission lines, the TX signal of each transmission line is driven using the PAM3 signal; if there are 4 transmission lines, the TX signal of each transmission line is driven using the PAM4 signal.

[0222] The first buffer 420 includes a front-end inverter (BU1) enabled by the TX_EN signal and inverting the TX signal, and a back-end inverter (BU2) connected to the front-end inverter (BU1) and enabled by the TX_EN signal to invert the signal inverted by the front-end inverter (BU1), thus buffering the PAM4 signal of voltage level encoded by the PAM encoding unit 410.

[0223] The voltage-to-current converter 430 includes a pull-up current source (PUC), a pull-down current source (PDC), a pull-up switch (PUS), and a pull-down switch (PDS) to convert a PAM4 signal with a voltage level buffered by the first buffer 420 into current. The pull-up current source (PUC) and the pull-down current source (PDC) generate a first current. The pull-up current source (PUC) and the pull-down current source (PDC) may include a current source or a current mirror. The pull-up switch (PUS) responds to a signal output from the inverter (BU2) at the back end of the first buffer 420 and controls the output of the first current generated in the pull-up current source (PUC). The pull-down switch (PDS) responds to a signal output from the inverter (BU1) at the front end of the buffer 310 and controls the output of the first current generated in the pull-down current source (PDC).

[0224] Therefore, a current corresponding to the transmitted voltage signal, i.e., the first current, is applied to the transmission line connected through the I / O pads. That is, in order to convert the input voltage signal into current, a pull-up current source (PUC) and a pull-down current source (PDC) connected to a current switch with a pull-up switch (PUS) and a pull-down switch (PDS) can be used.

[0225] Figure 14 It is used for explanation Figure 11 The circuit diagram shows another example of a DRV block. In particular, it shows a current-mode driver (DRV) circuit in the form of a current transmitter.

[0226] Reference Figure 14 According to another example, the DRV block 400 includes a first TX buffer (ATX0), a first TX resistor (RTX0), a second TX buffer (ATX1), a second TX resistor (RTX1), and a current transmitter (CC) that converts the input voltage signal into current and provides it to the transmission line through the I / O pads.

[0227] A first TX buffer (ATX0) and a first TX resistor (RTX0) with a first TX signal (TX[0]) and a first TX enable signal (TX_EN[0]) are connected in series to the X port of the current transmitter (CC). A second TX buffer (ATX1) and a second TX resistor (RTX1) with a second TX signal (TX[1]) and a second TX enable signal (TX_EN[1]) are connected in series to the X port of the current transmitter (CC).

[0228] The current transmitter (CC) includes an X port connected to the common terminal of the first TX resistor (RTX0) and the second TX resistor (RTX1), a Y port on which a common-mode voltage (VCOM) is applied to the transmission line, and a ZP port connected to the I / O pads. The Y port receives the common-mode voltage (VCOM) on the transmission line, the X port receives the current, and the ZP port mirrors the input current and outputs it through the I / O pads. The current transmitter (CC) may also include an EN port (not shown) with an EN signal that enables / disables the operation of the current transmitter.

[0229] The relationship between the input and output signals of a current transmitter (CC) can be defined by the following matrix.

[0230]

[0231] according to Figure 14 The state symbols of the current transmitter (CC) shown are defined in relation to the above signal input and output matrix. The current transmitter (CC) has the following characteristics.

[0232] - The Y port is a high-impedance port where the input current is "0" and the voltage signal is received.

[0233] The voltage at port X is the same as that at port Y, making it a low-impedance port for receiving current signals.

[0234] - The ZP port mirrors the input (or output) current of the X port 1:1 and has the same current output as the X port. High-impedance port for output value.

[0235] Figure 15 It is used for explanation Figure 14 The circuit diagram shows an example of a current conveyor (CC). In this embodiment, the current conveyor (CC) is shown as a balanced output rail-to-rail current conveyor (Balanced Output Rail-to-rail Current Conveyor ±).

[0236] Reference Figure 15 The current transmitter (CC) consists of a core block (CORE) and a drive block (D2).

[0237] The core block (CORE) includes an upper differential input terminal 1110, a lower differential input terminal 1120, an upper current mirror terminal 1130, a lower current mirror terminal 1140, a switch terminal 1150, a first capacitor (C1), and a second capacitor (C2). It receives VBP0, VBP1, and VBP2 from a bias circuit block (not shown) as bias voltages for the PMOS devices, and receives VBN0, VBN1, and VBN2 as bias voltages for the NMOS devices. Figure 15 The bias circuit block is omitted from the diagram of the balanced output rail-to-rail second-generation current transmitter (CC).

[0238] The core block (CORE) achieves rail-to-rail input and output through the upper differential input terminal 1110 and the lower differential input terminal 1120, which are connected to the Y port and the X port. Based on the voltage of the Y port and the voltage of the X port, the current applied by the bias voltage is mirrored and the first drive voltage (P_DRV) and the second drive voltage (N_DRV) are output to the driver block (D2).

[0239] The upper differential input terminal 1110 is composed of p-MOSFET MP0 and p-MOSFET MP1 connected in series and p-MOSFET MP2 and p-MOSFET MP3 connected in parallel. p-MOSFET MP0 has a source with an applied first power supply voltage (VDD), a gate with an applied bias voltage (VBP0), and a drain connected to the source of p-MOSFET MP1. p-MOSFET MP1 has a source connected to the drain of p-MOSFET MP0, a gate with an applied bias voltage (VBP1), and a drain connected to the sources of p-MOSFET MP2 and p-MOSFET MP3. p-MOSFET MP2 has a source connected to the drain of p-MOSFET MP1, a gate connected to the Y port, and a drain connected to the lower current mirror terminal 1140. p-MOSFET MP3 has a source connected to the drain of p-MOSFET MP1, a gate connected to the X port, and a drain connected to the lower current mirror terminal 1140. p-MOSFET MP2 and p-MOSFET MP3 are responsible for the input, comparing the voltage at the Y port with the voltage at the X port, thus directing the current applied by the bias voltage (tail current) (Ip) to the gate side where a lower input voltage has been applied. Here, the operable input signal voltage (Common mode voltage) ranges from approximately 0.8V to 0V, assuming the first supply voltage (VDD) is approximately 1.0V.

[0240] The lower differential input terminal 1120 is composed of n-MOSFETs MN0 and MN1 connected in series and n-MOSFETs MN2 and MN3 connected in parallel. n-MOSFET MN0 has a drain connected to the source of n-MOSFET MN1, a gate with an applied bias voltage (VBN0), and a source with an applied second supply voltage (VSS). n-MOSFET MN1 has a drain connected to the sources of n-MOSFET MN2 and n-MOSFET MN3, a gate with an applied bias voltage (VBN1), and a source connected to the drain of n-MOSFET MN0. n-MOSFET MN2 has a drain connected to the upper current mirror terminal 1130, a gate connected to the Y port, and a source connected to the drain of n-MOSFET MN1. n-MOSFET MN3 has a drain connected to the upper current mirror terminal 1130, a gate connected to the X port, and a source connected to the drain of n-MOSFET MN1. n-MOSFETs MN2 and MN3 are responsible for the input, comparing the voltage at the Y port with the voltage at the X port, thus directing the current (In) applied by the bias voltage towards the gate side where a higher voltage has been applied. Here, the operable input signal voltage (Common mode voltage) ranges from approximately 0.2V to 1.0V, assuming the first supply voltage (VDD) is approximately 1.0V.

[0241] Because the input stage of the current transmitter (CC) is equipped with upper differential input terminal 1110 and lower differential input terminal 1120, rail-to-rail input can be achieved. That is, when the power supply is 1.0V, the tail current (Ip, In) can flow, so that the range of the input voltage (Common Mode Voltage) covers the entire range of the power supply voltage (first power supply voltage (VDD)).

[0242] The rail-to-rail input covers the entire range of input signals from 0V to VDD, thus offering the advantage of operating on a wider range of input voltages compared to conventional circuits that receive either upper or lower inputs.

[0243] The upper current mirror terminal 1130 is composed of p-MOSFET MP4, p-MOSFET MP5, p-MOSFET MP6, and p-MOSFET MP7, defining a current mirror. p-MOSFET MP4 has a source to which a first power supply voltage (VDD) is applied, a gate connected to the drain of p-MOSFET MP5 and the gate of p-MOSFET MP6, and a drain connected to the source of p-MOSFET MP5. Furthermore, the drain of p-MOSFET MP4 is connected to the source of n-MOSFET MN3 at the lower differential input terminal 1120. p-MOSFET MP5 has a source connected to the drain of p-MOSFET MP4, a gate connected to the gate of p-MOSFET MP7, and a drain connected to the gate of p-MOSFET MP4. Furthermore, the source of p-MOSFET MP5 is connected to the source of n-MOSFET MN3 at the lower differential input terminal 1120. The p-MOSFET MP6 has a source to which a first power supply voltage (VDD) is applied, a gate connected to the drain of p-MOSFET MP5 and the gate of p-MOSFET MP4, and a drain connected to the source of p-MOSFET MP7. Furthermore, the drain of p-MOSFET MP6 is connected to the source of n-MOSFET MN2 at the lower differential input terminal 1120. The p-MOSFET MP7 has a source connected to the drain of p-MOSFET MP6, a gate connected to the gate of p-MOSFET MP5, and a drain connected to the drive block (D2) and the switch terminal 1150. Here, p-MOSFET MP5 and p-MOSFET MP7 are biased by a bias voltage (VBP1), and the bias voltages of p-MOSFET MP4 and p-MOSFET MP6 have the circuit characteristic of applying the drain voltage of p-MOSFET MP5.

[0244] If the gate area of ​​p-MOSFET MP4 is the same as that of p-MOSFET MP6, and the gate area of ​​p-MOSFET MP5 is the same as that of p-MOSFET MP7, then the current flowing through p-MOSFET MP6 and p-MOSFET MP7 is the same as the current flowing through p-MOSFET MP4 and p-MOSFET MP5. In this case, the saturation voltage of p-MOSFET MP5 is higher than the threshold voltage (Vth) of p-MOSFET MP4, thereby supplying current to the drain of p-MOSFET MP7. Therefore, it features a wider operable voltage range than a typical current mirror structure.

[0245] At this time, if the current is applied to the drains of p-MOSFET MP4 and p-MOSFET MP6 with different values ​​due to the difference in input voltage at the lower differential input terminal 1120, the final output current (I(MP7)) flowing through p-MOSFET MP7 is determined by the bias current ±@IN caused by the bias voltage (VBP1). Here, @ is the proportion of the current (In) relative to the difference in input voltage obtained from the upper differential input terminal 1110 and the lower differential input terminal 1120, which are current transmitters (CC).

[0246] The lower current mirror terminal 1140 is composed of n-MOSFET MN4, n-MOSFET MN5, n-MOSFET MN6, and n-MOSFET MN7, defining a current mirror. n-MOSFET MN4 has a drain connected to the source of n-MOSFET MN5, a gate connected to the gate of n-MOSFET MN6, and a source to which a second power supply voltage (VSS) is applied. Furthermore, the drain of n-MOSFET MN4 is connected to the source of p-MOSFET MP3 at the upper differential input terminal 1110. n-MOSFET MN5 has a drain connected to the switch terminal 1150, a gate connected to the gate of n-MOSFET MN7, and a source connected to the drain of n-MOSFET MN4. Furthermore, the source of n-MOSFET MN5 is connected to the source of p-MOSFET MP2 at the upper differential input terminal 1110. n-MOSFET MN6 has a drain connected to the source of n-MOSFET MN7, a gate connected to the gate of n-MOSFET MN4, and a source to which a second power supply voltage (VSS) is applied. n-MOSFET MN7 has a drain connected to switch terminal 1150, a gate connected to the gate of n-MOSFET MN5, and a source connected to the drain of n-MOSFET MN6. Furthermore, the drain of n-MOSFET MN7 is connected to the source of p-MOSFET MP2 at the upper differential input terminal 1110. Here, n-MOSFET MN5 and n-MOSFET MN7 are biased by a bias voltage (VBN1), and the bias voltages of n-MOSFET MN4 and n-MOSFET MN6 have circuit characteristics that apply the source voltage of n-MOSFET MN5.

[0247] If the gate area of ​​n-MOSFET MN4 is the same as that of n-MOSFET MN6, and the gate area of ​​n-MOSFET MN5 is the same as that of n-MOSFET MN7, then the current flowing through n-MOSFET MN6 and n-MOSFET MN7 is the same as the current flowing through n-MOSFET MN4 and n-MOSFET MN5. In this case, the saturation voltage of n-MOSFET MN5 is higher than the threshold voltage (Vth) of n-MOSFET MN4, thereby supplying current to the source of n-MOSFET MN7. Therefore, it features a wider operable voltage range than a typical current mirror structure.

[0248] At this time, if the current is applied to the sources of n-MOSFET MN4 and n-MOSFET MN6 with different values ​​due to the difference in input voltage at the upper differential input terminal 1110, the final output current (I(MN7)) flowing through n-MOSFET MN7 is determined by the bias current ±@IP caused by VBN1. Here, @ is the proportion of the current (Ip) relative to the difference in input voltage obtained from the upper differential input terminal 1110 and lower differential input terminal 1120, which are the input stages of the current transmitter (CC).

[0249] In this embodiment, the upper current mirror terminal 1130 and the lower current mirror terminal 1140 are high-compliance current mirrors.

[0250] The driver block (D2) includes a first driver 1210 and a second driver 1220, and outputs normal output current through the ZP port in response to the first drive voltage (P_DRV) and the second drive voltage (N_DRV).

[0251] The first driver 1210 consists of a p-MOSFET MP10 and an n-MOSFET MN10 connected in series. The p-MOSFET MP10 has a source to which a first power supply voltage (VDD) is applied, a gate connected to the upper current mirror terminal 1130, and a drain connected to both the n-MOSFET MN10 and the X port. The n-MOSFET MN10 has a source to which a second power supply voltage (VSS) is applied, a gate connected to the lower current mirror terminal 1140, and a drain connected to both the p-MOSFET MP10 and the X port. The first driver 1210 serves to connect the output to the X port of the input stage to suit the structure of a second-generation current transmitter.

[0252] The second driver 1220 has the same structure as the first driver 1210, consisting of a p-MOSFET MP11 and an n-MOSFET MN11 connected in series. The p-MOSFET MP11 has a source with applied VDD, a gate connected to the gate of the p-MOSFET MP10 in the first driver 1210, a drain connected to the n-MOSFET MN11, and a drain connected to the ZP port. The n-MOSFET MN11 has a source with applied VSS, a gate connected to the lower current mirror terminal 1140 and the gate of the n-MOSFET MN10, and a drain connected to the p-MOSFET MP11 and the ZP port. Unlike the first driver 1210, which is connected to the X port of the differential input stage (upper differential input terminal 1110 and lower differential input terminal 1120), the second driver 1220 is connected to the ZP port for output driving.

[0253] Refer again Figure 14 The first TX buffer (ATX0) is enabled according to the first TX enable signal (TX_EN[0]) and provides the first TX signal (TX[0]) to the first TX resistor (RTX0). The second TX buffer (ATX1) is enabled according to the second TX enable signal (TX_EN[1]) and provides the second TX signal (TX[1]) to the second TX resistor (RTX1). The operating voltage of the first TX buffer (ATX0) and the second TX buffer (ATX1) can be the first power supply voltage (VDD).

[0254] The first TX resistor (RTX0) is arranged between the first TX buffer (ATX0) and the X port of the current transmitter (CC), which can simply convert the voltage of TX[0], which is a logic signal, into two currents applied to the X port of the current transmitter (CC). That is, for the values ​​of 0 and 1, which are logic signal voltages, the values ​​of currents of relative magnitude -1 and +1 can be applied to the X port of the current transmitter (CC).

[0255] Furthermore, the second TX resistor (RTX1) is arranged between the second TX buffer (ATX1) and the X port of the current transmitter (CC), which can easily convert the voltage of TX[0] as a logic signal into two currents applied to the X port of the current transmitter (CC). That is, for the values ​​of 0 and 1 as logic signal voltages, the values ​​of currents of relative magnitude -1 and +1 can be applied to the X port of the current transmitter (CC).

[0256] In this embodiment, when the power supply voltage of the logic core that generates the transmitted signal and the power supply voltage of the interface used for signal transmission are different from each other, or when different voltages are required for the quality of the communication signal, the first TX buffer (ATX0) can use a buffer including a voltage level shifter. The operating voltage of the voltage level shifter is the VDD power supply voltage. At this time, when the value of the first TX resistor (RTX0) is RTX, the voltage of the first TX buffer (ATX0) is the first power supply voltage (VDD), the common mode voltage (VCOM) is 1 / 2VDD, and the value of the first TX buffer (ATX0) is 1, the current applied to the X port of the current transmitter (CC) is as shown in the following mathematical formula (1).

[0257] [Mathematical Expression 1]

[0258] On the other hand, when the value of the first TX buffer (ATX0) is 0, the current applied to the X port of the current transmitter (CC) is as shown in the following mathematical formula (2).

[0259] [Mathematical Expression 2]

[0260] Since the common-mode voltage (VCOM) is 1 / 2VDD, the currents are (1 / 2VDD) / RTX and -(1 / 2VDD)RTX, which can be expressed as +1 and -1 respectively in relative terms.

[0261] When the first TX buffer (ATX0) is disabled, its output floats, and the current applied to the X port of the current transmitter (CC) is "0". Furthermore, the current mirrored to the ZP port of the current transmitter (CC) is also "0". This signal state is also applied to transmission lines with a relative value of 0.

[0262] The above illustrates an example of a first TX signal (TX[0]) being applied to the X port of a current transmitter (CC) via a first TX buffer (ATX0) and a first TX resistor (RTX0) and converted into current. Similarly, a second TX signal (TX[1]) can be applied to the X port of a current transmitter (CC) via a second TX buffer (ATX1) and a second TX resistor (RTX1) and converted into current.

[0263] exist Figure 14The document describes how two TX buffers and two resistors are configured in the DRV block to represent four relative current values. Similarly, if three or more TX buffers and three or more resistors are configured in the DRV block, more relative current values ​​can be represented, but this is omitted in this specification.

[0264] Hereinafter, in this specification, DRV block 400 will be referred to as... Figure 14 The following description is based on a current mode driver (DRV) circuit using the current transmitter method shown.

[0265] exist Figure 14 In order to receive the PAM4 signal transmitted through the link unit, the RCV block 500 of the PHY unit can be composed of a voltage generation unit and a voltage comparator module for the four transmission lines.

[0266] Figure 16 It is used for explanation Figure 11 The circuit diagram shown is an example of an RCV block 500. In particular, the voltage mode comparator (OPAMP) circuit is shown.

[0267] Reference Figure 16 According to an example, the RCV block 500 includes: a voltage generation unit 510 that converts the current of a PAM4 signal provided through a transmission line into a voltage; and a voltage comparator module 530 that performs differential comparison on the PAM4 signal converted into a voltage by the voltage generation unit 510.

[0268] The voltage generation unit 510 includes multiple RC parallel circuits arranged between the transmission line and the voltage comparator module 530. Each RC parallel circuit includes a resistor (RRX) and a capacitor (CRX), one end of which is connected to a PAD connected to the transmission line and the other end of which is connected to a common-mode voltage (or common-ground voltage). The resistor (RRX) converts the current of the PAM4 signal provided through the transmission line into a voltage, and the capacitor (CRX) improves signal quality by bypassing high-frequency components or adjusting the frequency response. The capacitor (CRX) can work together with the resistor (RRX) to perform high-frequency noise removal and equalization functions.

[0269] exist Figure 16 The diagram shows that the voltage generation unit 510 includes multiple RC parallel circuits, but the capacitor (CRX) connected between the PAD and the common-mode voltage (or common-ground voltage) can be selectively used. That is, the capacitor (CRX) can be omitted in the voltage generation unit 510.

[0270] The voltage comparator module 530 includes six voltage comparators that perform differential comparisons on the PAM4 signal converted into voltage by the voltage generation unit 510. The CLK input used in the voltage comparator module 530 can be selectively used as needed, depending on the type of voltage comparator.

[0271] Specifically, the four transmission lines are named A, B, C, and D. When each transmission line is connected to PAD[0], PAD[1], PAD[2], and PAD[3] of the receiver, the voltage comparator module 530 compares the PAD signals RX[0]=(AB), RX[1]=(BC), RX[2]=(CD), RX[3]=(DA), RX[4]=(AC), and RX[5]=(BD) respectively, and outputs the values ​​of RX[0:5] as the input values ​​of the decoder circuit. Figure 16 In the diagram, A represents PAD[0], B represents PAD[1], C represents PAD[2], and D represents PAD[3].

[0272] Figure 16 The voltage comparator module 530 shown may include an analog comparator that compares the voltages at the differential inputs by current bias or a clock-based latch comparator.

[0273] Figure 17 It is used for explanation Figure 11 The circuit diagram shows another example of the RCV block 500. In particular, it shows the circuit utilizing the input of the X port of the current transmitter (CC) and the comparator.

[0274] Reference Figure 17 According to another example, the RCV block 500 includes: a voltage generation unit 520 that converts the current of the PAM4 signal provided through the transmission line into a voltage; and a voltage comparator module 530 that performs differential comparison on the PAM4 signal converted into a voltage by the voltage generation unit 520.

[0275] The voltage generation unit 520 includes multiple current transmitters (CCs) connected to the transmission line and multiple RC parallel circuits arranged between the current transmitters (CCs) and the voltage comparator module 530.

[0276] Each current transmitter (CC) is connected to one of the four transmission lines of the link unit in a one-to-one manner.

[0277] Each RC parallel circuit includes a resistor (RRX) and a capacitor (CRX), one end of which is connected to the ZP port of the current transmitter (CC), and the other end of which is connected to the common-mode voltage (or common-ground voltage). The resistor (RRX) converts the current supplied through the ZP port of the current transmitter (CC) into a voltage, while the capacitor (CRX) improves signal quality by bypassing high-frequency components or adjusting the frequency response. The capacitor (CRX) can work together with the resistor (RRX) to perform high-frequency noise removal and equalization functions.

[0278] Specifically, to generate the voltage value of the transmitted signal (RXA[3:0]), a resistor (RRX) is placed between the ZP port of the current transmitter (CC) and the common-mode voltage (VCOM) to convert the current, which is the transmitted signal, into a voltage. Furthermore, a capacitor (CRX) is placed between the ZP port of the current transmitter (CC) and the common-mode voltage (VCOM), and in the process of converting the current, which is the transmitted signal, into a voltage, it works in conjunction with the resistor (RRX) as a passive filter for high-frequency noise removal or equalization.

[0279] exist Figure 17 The diagram shows that the voltage generation unit 520 includes multiple RC parallel circuits, but the capacitor (CRX) connected between the PAD and the common-mode voltage (or common-ground voltage) can be selectively used. That is, the capacitor (CRX) can be omitted in the voltage generation unit 510.

[0280] The voltage comparator module 530 includes a comparator (or OPAMP) with six differential input terminals for distinguishing PAM4 signals from four RXA[3:0] outputs. When the four transmission lines are named A, B, C, and D, and each transmission line is connected to PAD[0], PAD[1], PAD[2], and PAD[3] of the receiver, the voltage comparator module 530 compares the PAD signals RX[0]=(AB), RX[1]=(BC), RX[2]=(CD), RX[3]=(DA), RX[4]=(AC), and RX[5]=(BD), respectively, and outputs the values ​​of RX[0:5] as the input values ​​of the decoder circuit. In this embodiment, A represents RXA[0], B represents RXA[1], C represents RXA[2], and D represents RXA[3].

[0281] The CLK input used in voltage comparator module 530 is selectively used as needed, depending on the type of voltage comparator. A voltage comparator is a circuit that detects a differential signal, i.e., the difference between the positive and negative input voltages, and converts it into a digital signal [High(1) or Low(0)].

[0282] Figure 18 It is used for explanation Figure 16 or Figure 17 The circuit diagram shown is an example of a voltage comparator module 530.

[0283] Reference Figure 18 According to an example, the voltage comparator module 530 includes a first differential voltage comparator (COP1), a second differential voltage comparator (COP2), a third differential voltage comparator (COP3), a fourth differential voltage comparator (COP4), a fifth differential voltage comparator (COP5), and a sixth differential voltage comparator (COP6), for voltage generation unit (510, Figure 17 (as shown) (520, Figure 20 The transmitted signal voltage values ​​(RXA[3:0]) are differentially compared. The first to sixth comparators (COP1, COP2, COP3, COP4, COP5, COP6) include differential voltage comparators that receive current bias and detect the gate input voltage difference.

[0284] The first differential voltage comparator (COP1) outputs a first differential voltage (OUT[0]) that performs a differential comparison between the first voltage (IN[0]) and the second voltage (IN[1]) provided from the voltage generation unit (510:520). The second differential voltage comparator (COP1) outputs a second differential voltage (OUT[1]) that compares the second voltage (IN[1]) and the third voltage (IN[2]) provided from the voltage generation unit (510:520). Furthermore, the third differential voltage comparator (COP3) outputs a third differential voltage (OUT[2]) that compares the third voltage (IN[2]) and the fourth voltage (IN[3]) provided from the voltage generation unit (510:520). The fourth differential voltage comparator (COP4) outputs a fourth differential voltage (OUT[3]) that compares the first voltage (IN[0]) and the fourth voltage (IN[3]) provided from the voltage generation unit (510:520). In addition, the fifth differential voltage comparator (COP5) outputs a fifth differential voltage (OUT[4]) that compares the first voltage (IN[0]) and the third voltage (IN[2]) provided from the voltage generation unit (510:520), and the sixth differential voltage comparator (COP6) outputs a sixth differential voltage (OUT[5]) that compares the second voltage (IN[1]) and the fourth voltage (IN[3]) provided from the voltage generation unit (510:520).

[0285] The encoder and decoder, connected to the four transmission lines, transmit / receive data at specific position values ​​as differential signals. For the received signal, six differential voltage comparators are used to compare the signals input from the four transmission lines. Encoding logic (used during transmission) and decoding logic (used during reception) are required to select the non-repeating valid values ​​from the results of these differential voltage comparators for transmission and reception.

[0286] Figure 19 It is used for explanation Figure 18 The circuit diagram of the first differential voltage comparator of the voltage comparator module 530 is shown. Figure 19 The first differential voltage comparator is shown, but the second through sixth differential voltage comparators have the same configuration.

[0287] Reference Figure 19 The first differential voltage comparator (COP1) of the voltage comparator module 530 includes a first comparator circuit (VCC1), a second comparator circuit (VCC2), and a buffer drive circuit (BDC), which compares the voltage at the differential voltage input terminal by current bias.

[0288] The first comparator circuit (VCC1) has a current bias circuit connected to the lower end of the FET that receives the differential input, which supplies the operating current to the FET.

[0289] The second comparator circuit (VCC2) rapidly amplifies the signal from the first comparator circuit.

[0290] The buffer drive circuit (BDC) is connected to the second comparator circuit, which enhances fast operation and drive characteristics even when the output is connected to a logic block with a large load.

[0291] The output of this differential amplifier is affected by any input voltage applied to VIN(+) and VIN(-) because the transistors are connected with their drains together. That is, the drain current of the two transistors must always be equal to the sum of the current flowing through transistor T1 and the current flowing through transistor T2. Therefore, the output voltage decreases when the voltage on one side increases, thus performing differential operation.

[0292] Figure 20 It is used for explanation Figure 16 or Figure 17 The circuit diagram shown is an example of a voltage comparator module 530.

[0293] Reference Figure 20The voltage comparator module 530 includes a first differential voltage comparator (COP21), a second differential voltage comparator (COP22), a third differential voltage comparator (COP23), a fourth differential voltage comparator (COP24), a fifth differential voltage comparator (COP25), and a sixth differential voltage comparator (COP26) that operate in response to a clock (CLK) cycle, for voltage generation unit (510, Figure 16 (as shown) (520, Figure 17 The transmitted signal voltage values ​​(RXA[3:0]) are compared differentially. The first to sixth voltage comparators (COP21, COP22, COP23, COP24, COP25, COP26) are differential ARM (Analog Re-generative Memory) latch voltage comparators that use a comparison clock to detect the gate input voltage difference.

[0294] The first differential voltage comparator (COP21) responds to the clock (CLK) and outputs a first differential voltage (OUT[0]) that performs a differential comparison between the first voltage (IN[0]) and the second voltage (IN[1]) provided from the voltage generation unit (510:520). The second differential voltage comparator (COP22) responds to the clock (CLK) and outputs a second differential voltage (OUT[1]) that compares the second voltage (IN[1]) and the third voltage (IN[2]) provided from the voltage generation unit (510:520). Furthermore, the third differential voltage comparator (COP23) responds to the clock (CLK) and outputs a third differential voltage (OUT[2]) that compares the third voltage (IN[2]) and the fourth voltage (IN[3]) provided from the voltage generation unit (510:520). The fourth differential voltage comparator (COP24) responds to the clock (CLK) and outputs a fourth differential voltage (OUT[3]) that compares the first voltage (IN[0]) and the fourth voltage (IN[3]) provided from the voltage generation unit (510:520). Furthermore, the fifth differential voltage comparator (COP25) responds to the clock (CLK) and outputs a fifth differential voltage (OUT[4]) that compares the first voltage (IN[0]) and the third voltage (IN[2]) provided from the voltage generation unit (510:520). The sixth differential voltage comparator (COP26) responds to the clock (CLK) and outputs a sixth differential voltage (OUT[5]) that compares the second voltage (IN[1]) and the fourth voltage (IN[3]) provided from the voltage generation unit (510:520).

[0295] The encoders and decoders of the four transmission lines transmit and receive data as differential signals, specifying specific positioning values. For the received signal, six differential voltage comparators are used to compare the signals input from the four transmission lines. Encoding logic (used during transmission) and decoding logic (used during reception) are required to select the non-repeating valid values ​​from the results of these differential voltage comparators for transmission and reception.

[0296] Figure 21 It is used for explanation Figure 20 The circuit diagram of the first differential voltage comparator of the voltage comparator module 530 is shown.

[0297] Reference Figure 21 The first differential voltage comparator (COP21) is a circuit that operates together with a differential voltage comparator (ALC) and an SR latch (SRL), using a comparison clock to detect the difference in gate input voltages. The first differential voltage comparator (COP21) includes a differential analog regenerative memory (ARM) latch voltage comparator.

[0298] A differential voltage comparator (ALC) compares two input signals to determine the output signal, amplifies the difference, and determines the output signal based on the amplified difference.

[0299] When the output of the differential voltage comparator (ALC) is determined, the SR latch (SRL) stores it. The output of the SR latch (SRL) memorizes the output state of the differential voltage comparator (ALC) and retains it for a period of time.

[0300] Compared to comparators using the aforementioned bias application method, this invention does not require a separate bias voltage (or current), which is highly advantageous in power-sensitive systems like this one. Furthermore, the time required from the input signal to the comparison result output is relatively short, which is highly beneficial for high-speed operation. In addition, the comparison result is output quickly via the comparison clock or trigger signal, thereby allowing for precise control of sampling timing. Furthermore, it has a storage function that holds the output until the comparison clock or trigger signal changes. Moreover, by adding an SR latch to both ends of the output of the ARM latch voltage comparator, a differential voltage comparator is constructed and used, so that the comparison value is generated and updated only at the rising (or falling) edge of the comparison clock or trigger signal each time.

[0301] In the detailed embodiments described in this specification, the RCV block is based on the differential ARM latch voltage comparator in the circuit described above, which uses a comparison clock to detect the difference in gate input voltage.

[0302] In this invention, when transmitting / receiving PAM4 signals through a link unit with 4 transmission lines, the maximum number of status symbols used in communication is 24 (refer to the values ​​in Table 4 above).

[0303] As described above, since the sum of the values ​​of the PAM4 signals applied to the four transmission lines is 0, the sum of the energy required to drive that state symbol to the transmission line (i.e., the case where the energy consumed in VDD is calculated as positive and the energy consumed in GND is calculated as negative) is 0 regardless of which of the 24 state symbols is transmitted.

[0304] Therefore, since the signals applied to the four transmission lines are configured to have values ​​that are complementary (opposite polarities) to each other, the electromagnetic energy released from the transmission lines cancels each other out, resulting in the characteristics of not requiring separate GND shielding wiring and very low electromagnetic interference (EMI) radiation.

[0305] Furthermore, since the signals transmitted through the four transmission lines (link units) are transmitted in a form that can be distinguished as differential signals, the communication signals have a better SNR (signal-to-noise ratio) and less jitter or skew compared to the single-ended method of the comparative example where each transmission line transmits signals independently.

[0306] Furthermore, since the transmission line consumes the same current under any of the 24 state symbols, the difference between the average power consumption required during data transmission and the maximum peak-to-peak power consumption (maximum power consumption - minimum power consumption) can be minimized, thereby reducing the complexity of the power supply system. It also provides convenience for link (transmission line) design and improves the overall BER by equally controlling the total energy of each signal in the cross coupling on the transmission line.

[0307] Because the link unit with the comparative example NRZ signal form can represent more status symbols in data transmission, the present invention can utilize the remaining number of redundant status symbols to reduce the number of link units used, or maximize the data transmission volume by using all conventional link units, or designate some status symbols as status symbols that can control communication (e.g., start, end, idle state of data communication, etc.) or check the transmission line (e.g., error correction signal, error judgment signal, transmission line quality check signal such as ECC, or control signal for improving quality, etc.).

[0308] As a method for improving transmission line quality, a specific value from a predefined signal control mode or status symbol representation is specified. Using information about the values ​​of information transmitted from one PHY unit and the expected values ​​of signals received from the other PHY unit, the driving and receiving values ​​of the PHY units are calibrated, taking into account the respective load conditions of the transmission line. This calibration is performed on both sides of the PHY unit during signal transmission and data reception, as described below.

[0309] The DRV block of the PHY unit on one side, which performs data transmission, optimizes the drive characteristics by minimizing signal jitter and maximizing the area of ​​the eye pattern through pre-emphasis. The RCV block of the PHY unit on the other side performs a series of actions to improve communication quality by measuring and adjusting the receiver sensitivity and the data timing of the received signal through adaptive equalization processing.

[0310] The pre-emphasis used in this invention emphasizes the high-frequency components of the signal at the transmitting end, which can compensate for high-frequency attenuation (loss) generated in the transmission channel. It is particularly useful for addressing the problem of high-frequency component attenuation caused by high data rates. Typically, during data transmission, the signal strength is temporarily increased in data sequences with large signal variations and decreased in data sequences with small signal variations to compensate for the effects of signal attenuation from the transmission line.

[0311] Figure 22 It is used for explanation Figure 11 The circuit diagram shows another example of a DRV block. Specifically, it is shown in... Figure 14 The DRV block shown includes a pre-emphasis circuit.

[0312] Reference Figure 22 According to another example, the DRV block 500 includes a first TX buffer (ATX0), a first TX resistor (RTX0), a second TX buffer (ATX1), a second TX resistor (RTX1), a pre-emphasis circuit (PEC), and a current transmitter (CC) to convert the input voltage signal into current and provide it to the transmission line through the I / O pads.

[0313] The first TX resistor (RTX0) and the second TX resistor (RTX1) have resistance values ​​ranging from 300Ω to 10kΩ. Alternatively, the first TX resistor (RTX0) and the second TX resistor (RTX1) are set according to the voltage (VDD) of the output circuit to generate a current between 50μA and 300μA as a data transmission signal.

[0314] Figure 22The first TX buffer (ATX0), the first TX resistor (RTX0), the second TX buffer (ATX1), the second TX resistor (RTX1), and the current transmitter (CC) shown have been... Figure 14 As shown in the figure, the same reference numerals are therefore given and their detailed descriptions are omitted.

[0315] The pre-emphasis circuit (PEC) includes a pre-emphasis buffer (PTX) enabled by TX_EN[1:0] and buffering the pre-emphasis (PEMP) signal, a variable resistor (RPH), and a variable capacitor (CPH), which temporarily increase or decrease the strength of the TX signal applied to the X port of the current transmitter (CC). Here, the variable resistor (RPH) and variable capacitor (CPH) introduce artificial distortion into the TX signal, thereby improving the signal characteristics on the receiving side. At least one of the variable resistor (RPH) and variable capacitor (CPH) can be omitted.

[0316] Preemphasis circuits (PECs) can be one or more per transmission line. The degree of distortion caused by the preemphasis circuit (PEC) can be variably adjusted according to the characteristics of the transmission line. Here, the characteristics of the transmission line can include frequency response characteristics, transmission line impedance, cross-coupling characteristics of adjacent signals, etc.

[0317] Figure 23 It is used for explanation Figure 14 The circuit diagram shows another example of a current transmitter.

[0318] Reference Figure 23 The current transmitter (CC) consists of a core block (CORE) and a drive block (D2).

[0319] Core block (CORE) and Figure 15 The core block (CORE) shown is the same, therefore it is given the same reference numerals and its detailed description is omitted.

[0320] The driver block (D2) includes a first driver 1210 and a second driver 2220, and in response to a first driving voltage (P_DRV) and a second driving voltage (N_DRV), outputs a first normal output current and a second normal output current through a first ZP port (IZPP) and a second ZP port (IZPN).

[0321] The first driver 1210 consists of a p-MOSFET MP10 and an n-MOSFET MN10 connected in series. The p-MOSFET MP10 has a source to which a first power supply voltage (VDD) is applied, a gate connected to the upper current mirror terminal 1130, and a drain connected to both the n-MOSFET MN10 and the X port. The n-MOSFET MN10 has a source to which a second power supply voltage (VSS) is applied, a gate connected to the lower current mirror terminal 1140, and a drain connected to both the p-MOSFET MP10 and the X port. The first driver 1210 serves to connect the output to the X port of the input stage to suit the structure of a second-generation current transmitter.

[0322] The second driver 2220 consists of a p-MOSFET MP11 and an n-MOSFET MN11 connected in series with the same structure as the first driver 1210, a p-MOSFET MP12 and a p-MOSFET MP13 connected to the n-MOSFET MN11 and outputting a first normal output current through the first ZP port (IZPP), and an n-MOSFET MN12 and an n-MOSFET MN13 connected to the p-MOSFET MP11 and outputting a second normal output current through the second ZP port (IZPN).

[0323] The p-MOSFET MP11 has a source with applied VDD, a gate connected to the upper current mirror terminal 1130 and the gate of the p-MOSFET MP10, and a drain connected to the source of the n-MOSFET MN12. The n-MOSFET MN11 has a source with applied VSS, a gate connected to the lower current mirror terminal 1140 and the gate of the n-MOSFET MN10, and a drain connected to the drain of the p-MOSFET MP12.

[0324] p-MOSFET MP12 has a source with applied VDD, a gate and a drain that are connected to the source of n-MOSFET MN11. p-MOSFET MP13 has a source with applied VDD, a gate connected to the gate of p-MOSFET MP12, and a drain connected to the first ZP port. p-MOSFET MP12 and p-MOSFET MP13 function as current mirrors for sourcing current.

[0325] n-MOSFET MN12 has a source connected to the drain of p-MOSFET MP11, a gate connected to both the source and the drain of p-MOSFET MP11, and a drain connected to VSS. n-MOSFET MN13 has a source connected to the second ZP port, a gate connected to the gate of n-MOSFET MN12, and a drain connected to VSS. n-MOSFET MN12 and n-MOSFET MN13 function as current mirrors for sinking current.

[0326] Unlike the first driver 1210, which is connected to the X port of the differential input stage of the upper differential input terminal 1110 and the lower differential input terminal 1120, the second driver 2220 is connected to the first ZP port (IZPP) and the second ZP port (IZPN) for output driving.

[0327] On the other hand, Figure 16 The text describes a voltage generation unit 510 that generates an output voltage based on the mirror current of the current transmitter's output, i.e., the ZP port. It is described as being constructed from an RC parallel circuit, but the voltage generation unit 510 can also be constructed from resistive elements alone.

[0328] Figure 24 It is used for explanation Figure 16 The circuit diagram shown is an example of a voltage generation unit.

[0329] Reference Figure 24 The voltage generation unit 510 includes a source follower 512 composed of a first NMOS M1 and a first PMOS M2 whose gates are connected together, and a CMOS inverter 514 composed of a second PMOS M3 and a second NMOS M4 whose gates are connected together.

[0330] The first NMOS M1 includes a drain connected to a power supply voltage, a gate connected to the gate of the first PMOS M2, and a source connected to the drain of the first PMOS M2. The first PMOS M2 includes a drain connected to the source of the first NMOS M1, a gate connected to the gate of the first NMOS M1, and a source connected to ground. The source of the first NMOS M1 and the drain of the first PMOS M2 are connected together and are subject to an input current Iin. The gates of the first NMOS M1 and the first PMOS M2 are connected together and output a voltage Vout.

[0331] The second PMOS M3 includes a drain connected to the power supply voltage, a gate connected to the gate of the second NMOS M4, and a source connected to the drain of the second NMOS M4. The second NMOS M4 includes a drain connected to the source of the second PMOS M3, a gate connected to the gate of the second PMOS M3, and a source connected to ground. The source of the second PMOS M3 and the drain of the second NMOS M4 are connected together to output the output voltage Vout.

[0332] The input current Iin represents the difference between the input currents, and the output voltage Vout is the result of the comparison. It is amplified by subsequent CMOS inverters (M3 and M4) and output as a rail-to-rail signal.

[0333] In this embodiment, the voltage generation unit 510 uses source followers (M1 and M2) as the input stage and CMOS inverters (M3 and M4) as positive feedback. Compared with the voltage generation unit based on the conventional current mirror, the input resistance can be reduced and the response time can be shortened.

[0334] On the other hand, in the dynamic response of a small input current, there is a temporary dead zone where both input transistors (M1 and M2) are turned off, resulting in high input resistance. Therefore, when the input current decreases, the dynamic response time of the voltage generation unit 510 increases sharply.

[0335] Figure 25 It is used for explanation Figure 16 The circuit diagram shows another example of a voltage generation unit.

[0336] Reference Figure 25 The voltage generation unit 510 includes source followers (M1 and M2), diode-operated transistors (MB1 and MB2), four current sources (IB1A, IB1B, IB2A, IB2B) for the bias circuit, and CMOS inverters (M3 and M4).

[0337] exist Figure 25 In the voltage generation unit 510 shown, the bias mode of the input stage is changed from Class B to Class AB operation, and... Figure 18 Compared to the voltage generation unit 510 shown, two additional diode-operated transistors (MB1 and MB2) are added. This reduces the dead time and the response time to small input currents.

[0338] Figure 26 It is used for explanation Figure 11 The circuit diagram shows another example of an RCV block. Specifically, it shows a configuration including... Figure 16 The circuit diagram of the RCV block of the current transmitter is shown.

[0339] Reference Figure 26The RCV block includes a first current transmitter (CC1), a second current transmitter (CC2), a third current transmitter (CC3), a fourth current transmitter (CC4), a first differential current comparator (COP1), a second differential current comparator (COP1), a third differential current comparator (COP3), a fourth differential current comparator (COP4), a fifth differential current comparator (COP5), and a sixth differential current comparator (COP6).

[0340] The first current transmitter (CC1) includes an X port connected to the first pad (PAD[0]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied to the transmission line, a first ZP port (IZP) that mirrors and outputs a first normal output current, and a second ZP port (IZN) that mirrors and outputs a second normal output current. Here, the first ZP port (IZP) and the second ZP port (IZN) of the first current transmitter (CC1) are respectively connected to the first differential current comparator (COP1), the fourth differential current comparator (COP4), and the fifth differential current comparator (COP5) to output the mirrored current.

[0341] The second current transmitter (CC2) includes an X port connected to the second pad (PAD[1]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied to the transmission line, a first ZP port (IZP) that mirrors and outputs the first normal output current, and a second ZP port (IZN) that mirrors and outputs the second normal output current. Here, the first ZP port (IZP) and the second ZP port (IZN) of the second current transmitter (CC2) are respectively connected to the first differential current comparator (COP1), the second differential current comparator (COP2) and the fifth differential current comparator (COP5) to output the mirrored current.

[0342] The third current transmitter (CC3) includes an X port connected to the third pad (PAD[2]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied to the transmission line, a first ZP port (IZP) that mirrors and outputs the first normal output current, and a second ZP port (IZN) that mirrors and outputs the second normal output current. Here, the first ZP port (IZP) and the second ZP port (IZN) of the third current transmitter (CC3) are respectively connected to the second differential current comparator (COP2), the third differential current comparator (COP3), and the fifth differential current comparator (COP5) to output the mirrored current.

[0343] The fourth current transmitter (CC4) includes an X port connected to the fourth pad (PAD[3]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied to the transmission line, a first ZP port (IZP) that mirrors and outputs the first normal output current, and a second ZP port (IZN) that mirrors and outputs the second normal output current. Here, the first ZP port (IZP) and the second ZP port (IZN) of the fourth current transmitter (CC4) are respectively connected to the third differential current comparator (COP3), the fourth differential current comparator (COP4), and the sixth differential current comparator (COP6) to output the mirrored current.

[0344] The first differential current comparator (COP1) responds to the clock signal and outputs a first differential current (OUT[0]) that performs a differential comparison between the first and second normal output currents provided from the first current transmitter (CC1) and the first and second normal output currents provided from the second current transmitter (CC2).

[0345] The second differential current comparator (COP2) responds to the clock signal and outputs a second differential current (OUT[1]) that performs a differential comparison between the first and second normal output currents provided by the second current transmitter (CC2) and the first and second normal output currents provided by the third current transmitter (CC3).

[0346] The third differential current comparator (COP3) responds to the clock signal and outputs a third differential current (OUT[2]) that performs a differential comparison between the first and second normal output currents provided by the third current transmitter (CC3) and the first and second normal output currents provided by the fourth current transmitter (CC4).

[0347] The fourth differential current comparator (COP4) responds to the clock signal and outputs a fourth differential current (OUT[3]) that performs a differential comparison between the first and second normal output currents provided from the first current transmitter (CC1) and the first and second normal output currents provided from the fourth current transmitter (CC4).

[0348] The fifth differential current comparator (COP5) responds to the clock signal and outputs a fifth differential current (OUT[4]) that performs a differential comparison between the first and second normal output currents provided by the first current transmitter (CC1) and the first and second normal output currents provided by the third current transmitter (CC3).

[0349] The sixth differential current comparator (COP6) responds to the clock signal and outputs a sixth differential current (OUT[5]) that performs a differential comparison between the first and second normal output currents provided from the second current transmitter (CC2) and the first and second normal output currents provided from the fourth current transmitter (CC4).

[0350] Figure 27 It is used for explanation Figure 11 The circuit diagram shows another example of an RCV block.

[0351] Reference Figure 27 According to another example, the RCV block 500 includes: a voltage generation unit 540 that converts the current of the PAM4 signal provided through the transmission line into a voltage; and a voltage comparator module 530 that performs differential comparison on the PAM4 signal converted into a voltage by the voltage generation unit 540. Figure 27 The voltage comparator module 530 shown is Figure 17 The voltage comparator module 530 shown is the same, therefore it is given the same reference numerals and detailed descriptions are omitted.

[0352] The voltage generation unit 540 includes multiple variable resistors (Rin) connected at one end to the transmission line, multiple current transmitters (CC) connected at the other end of the variable resistors (Rin), and multiple RC parallel circuits arranged between the current transmitters (CC) and the voltage comparator module 530. Figure 27 The current transmitter (CC) and RC parallel circuit shown are... Figure 17 The current transmitter (CC) and RC parallel circuit shown are the same, therefore they are given the same reference numerals and detailed descriptions are omitted. Figure 27 The RCV block 500 shown is... Figure 17 Compared to the RCV block 500 shown, a variable resistor is further included between the pad and the X port of the current transmitter.

[0353] The purpose of the variable resistor (Rin), namely the reason why the X port needs a variable resistor for impedance matching, is explained as follows.

[0354] To receive the current transmitted from the DRV block, the current transmitter of the RCV block drives a current opposite to the current transmitted to the X port. In this case, if the impedance of the transmission line matches the output impedance of the X port, the received signal can guarantee optimal rise and fall times without overshoot or undershoot, thus improving communication quality.

[0355] Transmission lines are composed of PCBs, TSVs, wires, etc., and their shapes, lengths, and construction conditions are inevitably diverse. Therefore, the impedance values ​​of transmission lines may vary. Thus, it is necessary to match the output impedance of the X port of the RCV block (which acts as the receiving end) with the impedance of the transmission line (or make their impedances identical).

[0356] To achieve this impedance matching, in this invention, a series resistor capable of changing and adjusting the resistance value is inserted between the PAD of the RCV block, which serves as the receiving end, and the X port of the current transmitter.

[0357] Figure 28a , Figure 28b and Figure 28c It shows the basis Figure 27 The graph shows the signal amplitude of the output impedance at the X port of the RCV block. Specifically, Figure 28a It is shown Figure 27 The graph shows the waveform of the RCV block with low output impedance at the X port. Figure 28b It is shown Figure 27 The graph shows the waveform of the RCV X port of the RCV block when the output impedance is high. Figure 28c It is shown Figure 27 The graph shows the waveform of the RCV X port of the RCV block when the output impedance is appropriate.

[0358] Reference Figure 28a When the output impedance of port X is less than the impedance of the transmission line, overshoot and undershoot waveforms that interfere with communication are generated. At this time, by increasing the resistance value of Rin, the output impedance of port X is controlled to match the impedance of the transmission line, thereby generating waveforms such as... Figure 28c The signal waveform shown is used for stable communication.

[0359] Reference Figure 28b When the output impedance of port X is greater than the impedance of the transmission line, there is no overshoot or undershoot, but the rise and fall times are significantly increased. In this case, by reducing the resistance value of Rin, the output impedance of port X can be controlled to match the impedance of the transmission line, thus ensuring... Figure 28c The optimal rise and fall times shown can be used to generate signal waveforms for stable communication.

[0360] Figure 29a and Figure 29b It is used for explanation Figure 16 or Figure 17 The circuit diagram shows another example of a current comparator module.

[0361] Reference Figure 29a and Figure 29bThe RCV block includes a first current transmitter (CC11), a second current transmitter (CC12), a third current transmitter (CC21), a fourth current transmitter (CC22), a fifth current transmitter (CC31), a sixth current transmitter (CC32), a seventh current transmitter (CC41), an eighth current transmitter (CC42), a ninth current transmitter (CC51), a tenth current transmitter (CC52), an eleventh current transmitter (CC61), a twelfth current transmitter (CC62), a first differential current comparator (COP1), a second differential current comparator (COP1), a third differential current comparator (COP3), a fourth differential current comparator (COP4), a fifth differential current comparator (COP5), and a sixth differential current comparator (COP6).

[0362] The first current transmitter (CC11) includes an X port connected to the first pad (IN[0]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied on the transmission line, a first ZP port (IZP) mirroring the first normal output current and outputting it to the first differential current comparator (COP1), and a second ZP port (IZN) mirroring the second normal output current and outputting it to the first differential current comparator (COP1).

[0363] The second current transmitter (CC12) includes an X port connected to the second pad (IN[1]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied on the transmission line, a first ZP port (IZP) that mirrors the first normal output current and outputs it to the first differential current comparator (COP1), and a second ZP port (IZN) that mirrors the second normal output current and outputs it to the first differential current comparator (COP1).

[0364] The third current transmitter (CC21) includes an X port connected to the second pad (IN[1]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied on the transmission line, a first ZP port (IZP) that mirrors the first normal output current and outputs it to the second differential current comparator (COP2), and a second ZP port (IZN) that mirrors the second normal output current and outputs it to the second differential current comparator (COP2).

[0365] The fourth current transmitter (CC22) includes an X port that is connected to the third pad (IN[2]) and a common-mode voltage (VCOM) applied to the transmission line, a first ZP port (IZP) that mirrors the first normal output current and outputs it to the second differential current comparator (COP2), and a second ZP port (IZN) that mirrors the second normal output current and outputs it to the second differential current comparator (COP2).

[0366] The fifth current transmitter (CC31) includes an X port that is connected to the third pad (IN[2]) and a common-mode voltage (VCOM) applied to the transmission line, a first ZP port (IZP) that mirrors the first normal output current and outputs it to the third differential current comparator (COP3), and a second ZP port (IZN) that mirrors the second normal output current and outputs it to the third differential current comparator (COP3).

[0367] The sixth current transmitter (CC32) includes an X port connected to the fourth pad (IN[3]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied on the transmission line, a first ZP port (IZP) mirroring the first normal output current and outputting it to the third differential current comparator (COP3), and a second ZP port (IZN) mirroring the second normal output current and outputting it to the third differential current comparator (COP3).

[0368] The seventh current transmitter (CC41) includes an X port that is connected to the third pad (IN[2]) and a common-mode voltage (VCOM) applied to the transmission line, a first ZP port (IZP) that mirrors the first normal output current and outputs it to the fourth differential current comparator (COP4), and a second ZP port (IZN) that mirrors the second normal output current and outputs it to the fourth differential current comparator (COP4).

[0369] The eighth current transmitter (CC42) includes an X port connected to the first pad (IN[0]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied on the transmission line, a first ZP port (IZP) mirroring the first normal output current and outputting it to the fourth differential current comparator (COP4), and a second ZP port (IZN) mirroring the second normal output current and outputting it to the fourth differential current comparator (COP4).

[0370] The ninth current transmitter (CC51) includes an X port connected to the first pad (IN[0]) where current is applied, a Y port where a common-mode voltage (VCOM) is applied on the transmission line, a first ZP port (IZP) mirroring the first normal output current and outputting it to the fifth differential current comparator (COP5), and a second ZP port (IZN) mirroring the second normal output current and outputting it to the fifth differential current comparator (COP5).

[0371] The tenth current transmitter (CC52) includes an X port that is connected to the third pad (IN[2]) and a common-mode voltage (VCOM) applied to the transmission line, a first ZP port (IZP) that mirrors the first normal output current and outputs it to the fifth differential current comparator (COP5), and a second ZP port (IZN) that mirrors the second normal output current and outputs it to the fifth differential current comparator (COP5).

[0372] The eleventh current transmitter (CC61) includes an X port that is connected to the second pad (IN[1]) and a common-mode voltage (VCOM) applied to the transmission line, a first ZP port (IZP) that mirrors the first normal output current and outputs it to the sixth differential current comparator (COP6), and a second ZP port (IZN) that mirrors the second normal output current and outputs it to the sixth differential current comparator (COP6).

[0373] The twelfth current transmitter (CC62) includes an X port that is connected to the third pad (IN[2]) to apply current, a Y port to which a common-mode voltage (VCOM) is applied on the transmission line, a first ZP port (IZP) that mirrors the first normal output current and outputs it to the sixth differential current comparator (COP6), and a second ZP port (IZN) that mirrors the second normal output current and outputs it to the sixth differential current comparator (COP6).

[0374] The first differential current comparator (COP1) responds to the clock signal and outputs a first differential current (OUT[0]) that performs a differential comparison between the first and second normal output currents provided from the first current transmitter (CC11) and the first and second normal output currents provided from the second current transmitter (CC12).

[0375] The second differential current comparator (COP2) responds to the clock signal and outputs a second differential current (OUT[1]) that performs a differential comparison between the first and second normal output currents provided by the third current transmitter (CC21) and the first and second normal output currents provided by the fourth current transmitter (CC22).

[0376] The third differential current comparator (COP3) responds to the clock signal and outputs a third differential current (OUT[2]) that performs a differential comparison between the first and second normal output currents provided by the fifth current transmitter (CC31) and the first and second normal output currents provided by the sixth current transmitter (CC32).

[0377] The fourth differential current comparator (COP4) responds to the clock signal and outputs a fourth differential current (OUT[3]) that performs a differential comparison between the first and second normal output currents provided from the seventh current transmitter (CC41) and the first and second normal output currents provided from the eighth current transmitter (CC42).

[0378] The fifth differential current comparator (COP5) responds to the clock signal and outputs a fifth differential current (OUT[4]) that performs a differential comparison between the first and second normal output currents provided by the ninth current transmitter (CC51) and the first and second normal output currents provided by the tenth current transmitter (CC52).

[0379] The sixth differential current comparator (COP6) responds to the clock signal and outputs a sixth differential current (OUT[5]) that performs a differential comparison between the first and second normal output currents provided from the eleventh current transmitter (CC61) and the first and second normal output currents provided from the twelfth current transmitter (CC62).

[0380] Figure 30 It is used for explanation Figure 26 Or the circuit diagram of the first differential current comparator of the current comparator module shown in Figure 29.

[0381] Reference Figure 30 The first differential current comparator (COP1) includes a dynamic latch comparator that compares two input currents and generates an output signal based on their difference. Specifically, the first differential current comparator (COP1) compares two input currents input through a first positive input port (IZPP) and a second positive input port (IZPN) and generates an output signal based on their difference. Alternatively, the first differential current comparator (COP1) compares two input currents input through a first negative input port (IZNP) and a second negative input port (IZNN) and generates an output signal based on their difference.

[0382] The dynamic latch comparators include p-MOSFET MP0, p-MOSFET MP1, p-MOSFET MP2, p-MOSFET MP3, n-MOSFET MN0, n-MOSFET MN1, n-MOSFET MN2, n-MOSFET MN3, p-MOSFET MP4, and p-MOSFET MP5.

[0383] p-MOSFET MP0 is connected to the first positive input port (IZPP) via its source, to the clock signal (CLK) via its gate, and to the power supply voltage (VDD) via its drain. p-MOSFET MP1 is connected to the first positive input port (IZPP) via its source, to the source of p-MOSFET MP2 via its gate, and to the power supply voltage (VDD) via its drain. p-MOSFET MP2 is connected to the second positive input port (IZPN) via its source, to the sources of both p-MOSFET MP0 and p-MOSFET MP1 via its gate, and to the power supply voltage (VDD) via its drain. p-MOSFET MP3 is connected to the second positive input port (IZPN) via its source, to the clock signal (CLK) via its gate, and to the power supply voltage (VDD) via its drain.

[0384] n-MOSFET MN0 is connected to ground via its source, to the gate of p-MOSFET MP1 via its gate, and to the first negative input port (IZNP) via its drain. n-MOSFET MN1 is connected to ground via its source, to the gate of p-MOSFET MP2 via its gate, and to the second negative input port (IZNN) via its drain. n-MOSFET MN2 is connected to the first positive input port (IZNP) via its source, to the clock signal (CLK) via its gate, and to the source of p-MOSFET MP1 via its drain. n-MOSFET MN3 is connected to the second positive input port (IZNN) via its source, to the clock signal (CLK) via its gate, and to the source of p-MOSFET MP2 via its drain. p-MOSFET MP4 is connected to the first positive input port (IZNP) via its source, to the gate of p-MOSFET MP5 via its gate, and to the source of p-MOSFET MP1 via its drain.

[0385] p-MOSFET MP5 is connected to the second positive input port (IZNN) through its source, to the gate of p-MOSFET MP4 through its gate, and to the source of p-MOSFET MP2 through its drain.

[0386] The first differential current comparator (COP1) has been described above, but the second differential current comparator (COP2) through the sixth differential current comparator (COP6) are the same, so their detailed descriptions are omitted.

[0387] Figure 31 It is used for explanation Figure 26 Or the circuit diagram of the first differential current comparator of the current comparator module shown in Figure 29.

[0388] Reference Figure 31The first differential current comparator (COP1) includes a dynamic latch comparator and an SR latch, comparing two input currents and generating an output signal based on their difference. Specifically, the first differential current comparator (COP1) compares two input currents input through the first positive input port (IZPP) and the second positive input port (IZPN), and generates an output signal based on their difference. Alternatively, the first differential current comparator (COP1) compares two input currents input through the first negative input port (IZNP) and the second negative input port (IZNN), and generates an output signal based on their difference.

[0389] The dynamic latch comparators include p-MOSFET MP0, p-MOSFET MP1, p-MOSFET MP2, p-MOSFET MP3, n-MOSFET MN0, n-MOSFET MN1, n-MOSFET MN2, n-MOSFET MN3, p-MOSFET MP4, and p-MOSFET MP5, which have been... Figure 30 The explanation is in the text, therefore detailed instructions are omitted.

[0390] The SR latch includes a first inverter (INV1), a second inverter (INV2), a first NAND gate (NAND1), and a second NAND gate (NAND2). Specifically, the first inverter (INV1) is connected to the first negative input port (IZNP) via its input terminal, and the second inverter (INV2) is connected to the second negative input port (IZNN) via its input terminal. The first NAND gate (NAND1) is connected to the output terminal of the first inverter (INV1) via its first input terminal and to the output terminal of the second NAND gate (NAND2) via its second input terminal. The second NAND gate (NAND2) is connected to the output terminal of the first NAND gate (NAND1) via its first input terminal and to the output terminal of the second inverter (INV2) via its second input terminal.

[0391] During operation, when the current at both the first negative input port (IZNP) and the second negative input port (IZNN) is high, it is in data hold state. When the current at both the first negative input port (IZNP) and the second negative input port (IZNN) is low, it is in data vanish state. When the current at both the first negative input port (IZNP) and the second negative input port (IZNN) is high, it is in data set state. When the current at both the first negative input port (IZNP) and the second negative input port (IZNN) is low, it is in data reset state.

[0392] On the other hand, the equalization used in this invention employs the following method: controlling the receiving sensitivity of the RCV block to improve the quality of the received signal, thereby changing the bias current of the comparator or controlling the data comparison timing, thereby reducing inter-symbol interference (ISI) generated in the PAM4 signal and improving the quality of the received signal.

[0393] The following Figure 32 An eye diagram showing the characteristics of a PAM4 signal exhibiting fragility is presented. Figure 33 The eye diagram of the PAM4 signal with improved characteristics through the pre-emphasis circuit (PEC) is shown.

[0394] Figure 32 The diagram shows the eye diagram of the PAM4 signal received by the PAM4 signal-based communication system according to the comparative example.

[0395] Reference Figure 32 As can be seen, in the eye pattern, the area of ​​the eye region (the white part in the center) is small, and it produces jitter due to inconsistent data clock cycles. This increase in the narrow eye pattern area and jitter is attributed to the driving characteristics of the high-speed PHY unit and the signal transmission characteristics of the transmission line.

[0396] The shape of this narrow-eye pattern and the large jitter characteristics increase the probability of errors in the transmission line, which is the cause of increased BER. As a way to improve this, a pre-emphasis function is needed.

[0397] Figure 33 The diagram shows an eye diagram of a PAM4 signal received by a PAM4 signal-based communication system according to the present invention. In particular, it shows the eye pattern of the received PAM4 signal when pre-emphasis is performed on the DRV block side and equalization is performed on the RCV block side.

[0398] Reference Figure 33 It can be seen that in the eye pattern, the eye region (the white part in the center) has a large area, the data clock period is relatively constant, and it is a signal waveform with reduced jitter.

[0399] By understanding the signal transmission characteristics of high-speed transmission lines and performing pre-emphasis, data transmission speed or BER can be improved. Therefore, pre-emphasis and equalization circuits are usually included in high-speed communication systems. Examples of this invention also apply the characteristics of the circuits and transmission lines.

[0400] Hereinafter, embodiments of the present invention will be described, which transmit / receive PAM4 signals through a link unit having four transmission lines and use current transmitters in the DRV and RCV blocks.

[0401] An embodiment of the present invention is a system that transmits, receives, and decodes data as is by encoding 24 status symbols with the data to be transmitted in a 1:1 match.

[0402] The embodiments of the present invention are methods that do not require controlling the DC level of the link unit (transmission line) as in the parallel transmission method of the comparative example, and are used to transmit more status symbols than before.

[0403] Table 5 is a table illustrating the number of bits transmitted per transmission line unit according to the parallel transmission method (NRZ method) of the comparative example and the transmission method of the present invention (PAM4 method).

[0404] [Table 5]

[0405] Referring to Table 5, in data transmission, when represented by 4 transmission lines as the basic unit, the number of state symbols per transmission line using the parallel transmission method of the comparative example (i.e., NRZ method) is 2. 4 Therefore, a total of 16 status symbols can be transmitted at once. This means that 4 bits of data can be transmitted across 4 transmission lines at a time. In contrast, this invention uses status symbols composed of 24 differential PAM4 signals selected from 256 status symbols achievable across 4 transmission lines to send / receive data. This means that each link unit with 4 transmission lines can transmit 24 different status symbols. This means that 4.585 bits of data can be transmitted across 4 transmission lines at a time.

[0406] On the other hand, when using 16 link units (i.e., when the link consists of 64 transmission lines), the number of state symbols that can be transmitted at one time in the comparative example's NRZ method is 1.84467E+19 (2 64 Or 16 16 ) . In contrast, the number of state symbols that can be transmitted at one time in the PAM4 method of this invention is 1.21166E+22 (24 16 Therefore, in the same link, the PAM4 method of the present invention can transmit approximately 656.8 times more state symbols compared to the NRZ method of the comparative example.

[0407] Furthermore, to transmit 64 bits of data at a time, the comparative example's NRZ method requires a communication link with 64 transmission lines. However, the PAM4 method of the present invention can be implemented with a link having 56 transmission lines. Therefore, the PAM4 method of the present invention can reduce the number of transmission lines compared to the comparative example's NRZ method.

[0408] In the comparative example of NRZ mode, the number of state symbols that can be transmitted at one time in a link with 64 (link units × 16) transmission lines, i.e., the number of state symbols in a link with 64 transmission lines, is 16. 16 (2 64 =18,446,744,073,709,551,616.

[0409] In contrast, in the PAM4 method of the present invention, the number of state symbols that can be transmitted at one time in a link with 56 (link unit of the present invention × 14) transmission lines, i.e., the number of state symbols in a link with 56 transmission lines, is 24. 14 =21,035,720,123,168,587,776.

[0410] In summary, according to the PAM4 method of the present invention, the state symbol number of the comparative example NRZ method with 64 transmission lines can be transmitted with the state symbol number of the link with 56 transmission lines.

[0411] Figure 34 It is used for explanation Figure 10 The block diagram shown is of the first encoding / decoding unit.

[0412] Reference Figure 10 and Figure 34 The first encoding / decoding unit 220 includes encoder logic 222 and decoder logic 224.

[0413] During signal transmission, encoder logic 222 receives the data to be transmitted (TX_DATA[n:0]) from the communication entity, such as a processor unit or memory device, and generates a TX signal (TX[7:0]) and a TX enable signal (TX_EN[7:0]) to drive the first PHY unit 210 using a status symbol that matches the data 1:1. The TX signal (TX[7:0]) and the TX enable signal (TX_EN[7:0]) generated by encoder logic 222 are converted into current form by a current transmitter and then output to the link unit through each I / O pad.

[0414] During data reception, the decoder logic 224 receives the 6 PAM4 comparison signals (RX[5:0]) output from the second PHY unit 310, recovers them into 24 status symbols, and converts the recovered status symbols into digital value data (RX_DATA[n:0]).

[0415] Examples of encoding and decoding methods for state symbols are shown in Table 4 above.

[0416] Referring again to Table 4, the 24 state symbols defined by the graphics coloring theory are shown, along with their decimal and base-24 assignments and the transmission line unit signal value (PAM4 value / transmission line unit value) for each state symbol. Furthermore, the comparison values ​​of the six distinct receiver comparators are marked in RX[0]~RX[5], and the results of the six comparators are represented as distinct decimal values ​​RX[0:5] with 6 bits each.

[0417] With each of the four transmission lines driven by a PAM4 signal, there are a total of 256 possible cases. However, as mentioned earlier, using graph coloring theory, the sum of the PAM4 signals is "0", and the results of the six comparators have 24 unique intrinsic values. In this embodiment, only 24 state symbols are used for communication.

[0418] Decimal data from 0 to 23 can be defined as base-24 status symbols as follows.

[0419] [0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,G,H,I,J,K,L,M,N] That is, when representing decimal data as base-24 data, numbers greater than decimal 10 can be assigned base-24 numbers in alphabetical order. This is the assignment used in this invention, but it is only an example; any form of labeling is acceptable as long as it is a symbolic representation capable of distinguishing the 24 values.

[0420] Figure 35 It is used for explanation Figure 10 The diagram shows the state symbol recovery process performed by the first or second communication unit.

[0421] Reference Figure 10 and Figure 35This illustrates the process of mapping the status symbol from the signal received by the second communication unit 300 and decoding the transmitted signal when 24-ary data [0,C,1,4,9,3,D,J,A,L,0] (or decimal data with the same meaning [0,12,1,4,9,3,13,19,10,21,0]) is transmitted from the first communication unit 200 through the link unit 100.

[0422] Data is sent or received at a predetermined clock data (CD) rate.

[0423] exist Figure 35 The text describes the data recovery process performed in the receiver of the second communication unit 300, but the encoding process performed in the transmitter is in reverse order to the recovery process performed in the receiver, so a separate description is omitted.

[0424] When CD=0 is received, the value of RX[0:5] is binary

[00100] . It can be seen that this binary value corresponds to the A0 state symbol in the aforementioned state symbol table 4. The A0 state symbol means decimal 0, and its base-24 value also means 0. This process is defined as decoding, which occurs when a decimal 0 or base-24 0 is received.

[0425] When CD=1 is received, the value of RX[0:5] is binary[111011]. It can be seen that this binary value corresponds to the B0 state symbol in the aforementioned state symbol table 4. The B0 state symbol means decimal 12, and the base-24 value means C.

[0426] If the remaining data from CD=2 to CD=10 is received, it is received and decoded in the same manner as described above, and the transmitted data value is recovered from the difference of the received PAM4 signal.

[0427] The following example illustrates the use of PAM4 signals and a link unit with four transmission lines, and the implementation of a drive circuit (DRV) and a receiver circuit (RCV) via a current transmitter.

[0428] Based on the relationship between the previous and current state symbols, the 24 state symbols are divided into 21 data symbols and 2 control symbols, "IDLE" and "END".

[0429] First communication unit 200 ( Figure 10The link unit (shown) includes a driver circuit (DRV) and a receiver circuit (RCV). It encodes the data to be transmitted into status symbols according to clock data (CD) and transmits the encoded status symbols to one end of the link unit. The link unit outputs the transmitted signal to the second communication unit 300 connected to the other end. Figure 10 (As shown).

[0430] Second communication unit 300 ( Figure 10 The circuit (shown) includes a drive circuit (DRV) and a receiver circuit (RCV), which are connected to the other end of the link unit to decode the received status symbols according to the definition of this invention, thereby recovering the transmitted data.

[0431] However, in a data communication system where separate status symbols or signals related to communication control (i.e., the start and end of data communication, waiting states, etc.) can be used through separate link units, the control symbols (i.e., IDLE and END) can be sent and received by changing their meaning to add two data symbols to the 21 data symbols, thereby increasing the data transmission capacity of the link unit.

[0432] In this specification, encoding refers to the process of calculating and outputting the position of a state symbol according to the definition of this invention, based on the difference between a previous state symbol and a new state symbol to be transmitted. Furthermore, decoding refers to the process of recovering the transmitted value based on the difference between a previously received state symbol and a newly received state symbol.

[0433] Refer again Figure 34 The encoder logic 222 receives the data to be transmitted (TX_DATA[n:0]) from the communication subject (i.e., the processor unit or memory device), encodes it according to the definition of the present invention, and generates signals (TX_EN[7:0], TX[7:0]) for driving the PHY of the first communication unit 200 to transmit status symbol signals.

[0434] Decoder logic 224 receives six PAM4 comparison signals (RX[5:0]) output from the PHY of the second communication unit 300, recovers 24 status symbols, and decodes them into data symbols to recover the data.

[0435] Thus, encoder logic 222 and decoder logic 224 are used identically in the first communication unit 200 and the second communication unit 300, respectively, and the communication direction can be controlled by separate means.

[0436] In conventional communication methods (e.g., systems using existing HBM PHYs and transmitting parallel data in NRZ mode), there is a high probability that the same values ​​('0' or '1') are repeated and sustained in the transmission line. This persistence of DC levels, i.e., the phenomenon of maintaining the same voltage state for a certain period of time, adversely affects the impedance changes and response characteristics of the transmission line, resulting in one of the main reasons for signal quality degradation and transmission speed limitations.

[0437] Therefore, this invention reduces the number of cases where the electrical value of a signal transmitted according to state symbols (e.g., the level value of the PAM4 signal) remains constant by controlling the DC level characteristics of the transmission lines of a link unit with four transmission lines transmitting PAM4 signals. This reduces the frequency of the same electrical state persisting, thus mitigating transmission line impedance variations in the link unit and improving overall response characteristics. Furthermore, it reduces electrical interference between transmission lines, thereby reducing distortion caused by signal interference. Additionally, the bit error rate (BER) is reduced as signal quality improves. Moreover, even under the same link unit and PHY conditions, the clock data (CD) transmission speed can be increased.

[0438] As a result, compared with previous NRZ-based data communication systems, this method effectively alleviates the DC level maintenance problem of the transmission line, thereby improving both signal integrity and transmission efficiency in high-speed data transmission environments. Thus, two of the 24 transmittable status symbols are used as control signals. Although the number of status symbols transmitted per data clock is reduced, the response characteristics of the link unit to signal attenuation are improved by controlling the DC level, enabling faster data transmission and thus increasing overall data transmission efficiency.

[0439] Referring again to Table 4, the 24 state symbols defined by the graphics coloring theory are shown, along with their decimal and base-24 assignments and the definition of the transmission line unit signal value for each state symbol. Furthermore, the comparison values ​​of the six mutually distinguishable comparators are marked in RX[0] to RX[5], and the results of the six comparators are represented as mutually distinguishable decimal values ​​RX[0:5] with 6 bits.

[0440] In this embodiment, when a link unit consisting of four transmission lines is driven by a PAM4 signal, there are 256 possible cases. However, using the aforementioned graph coloring theory, the sum of the PAM4 signals is 0, and the six comparator results have non-repeating intrinsic values, resulting in only 24 cases. Only these 24 state symbols are used for communication.

[0441] Figure 36This is a diagram illustrating a signal transmission state transition diagram with state symbols arranged in a ring shape according to the definition of the present invention. Specifically, it shows a state transition diagram with 24 state symbols divided into groups A and B and arranged in a ring shape.

[0442] Reference Figure 36 The State Transition Diagram includes Group A, corresponding to the inner circle, and Group B, corresponding to the outer circle. The 12 state symbols in Group A form a circle inside the State Transition Diagram and are arranged clockwise. The 12 state symbols in Group B, arranged in the same order and numbering as those in Group A, face each other in a circle outside Group A and are also arranged clockwise. In the State Transition Diagram, the transition symbols X, Y, and Z define the relative distances between the state symbols.

[0443] The transition symbol X represents an exchange between state symbols belonging to group A and group B, and also represents an exchange between state symbols with the same index. The transition symbol Y represents a state symbol belonging to group A or group B moving one step clockwise within the same group. As the number of transition symbols Y increases, the number of steps also increases. The transition symbol Z represents a state symbol moving one step clockwise from group A or group B to group B or group A.

[0444] In this embodiment, the total number of data symbols that can be calculated from the rotation (ROTATE, R) or rotation-swap (ROTATE-SWAP, RS) of the position of the moving state symbols in the same group is at most 22. When the value of the 22nd movement, which is the maximum movement amount obtained through rotation-swap (RS), is used as the end (END) state symbol, the number of data symbols is 21.

[0445] The position value of the initial state symbol indicating the start of signal transmission is set to state symbol A0. In this embodiment, the position of the initial state symbol is defined as state symbol A0 for ease of explanation, but it can also be set to other state symbols in group A such as A1, A2, or other state symbols in group B such as B0, B1, B3.

[0446] Before transmitting data, to notify the other side of a communication line that it is in a waiting state, the values ​​of state symbols A0 and B0 can be swapped (SWAP) at the data clock speed, and this action (IDLE state) can be repeated more than once. This process of exchanging (SWAP) information between state symbols is defined as the waiting state (IDLE state), and the signal used for this swapping is called the waiting signal (IDLE), represented by the transition symbol X in the state transition diagram. If there are an even number of waiting signals, the position of the state symbol at the end of the waiting signal period is the starting group's own number; if there are an odd number of waiting signals, the position of the state symbol is the swapped group's own number.

[0447] In the waiting state, electrical signals corresponding to the state symbols A0 and B0 facing each other are applied to the communication lines A, B, C, and D of the link unit with opposite values. Due to this state, it is already known from the first PHY unit 210 ( Figure 10 The value of the information transmitted in the second PHY unit 310 (shown) and the value of the information transmitted in the second PHY unit 310 (shown) Figure 10 The expected value of the signal received at (shown).

[0448] Therefore, for the first PHY unit 210 ( Figure 10 The driving value of the second PHY unit 310 (as shown) Figure 10 The received values ​​(as shown) can be used for calibration processes considering the load conditions of each transmission line, or for testing the normal state of the PHY and link units. Here, calibration involves a series of actions to improve communication quality. Specifically, the driving circuit (DRV) of the PHY responsible for data signal transmission on one side performs pre-emphasis, while the receiving circuit (RCV) of the PHY on the other side performs equalization, measuring receiver sensitivity and data timing of the received signal, and synchronizing the data clock speed.

[0449] In both the ring structures of Group A and Group B, regardless of the position (state) of the transmitted status symbol, the above objective can be achieved by exchanging (SWAP) the status symbol data with the same sequence number between Group A and Group B. Furthermore, the above objective can also be achieved using a combination of test data transmission status symbols with specific meanings and control transmission status symbols.

[0450] Data transmission must be defined as the position value of the state symbol used to represent a clockwise rotation (R) or rotation-exchange (RS) from the previous position of the state symbol.

[0451] The following is an explanation of the value assignment for the status symbols used for data transmission.

[0452] - In the case where the difference in state symbols is solely determined by rotation, 11 rotatable positions can be assigned within the same state symbol group, rotating clockwise one full circle until it is about to reach its own position. This rotation is represented by the transformation symbol "Y," and the Y value increases by +1 for each clockwise movement (rotation).

[0453] The value of [rotation Y value - 1] is mapped to the data value to be transmitted. In summary, the position movement of the status symbol can be decimal 1~11, and the transmitted data (i.e., the mapped data) that can be transmitted through position movement can be defined as a decimal value (the value of the data symbol) from 0~10.

[0454] It has the relation [Mapping Data(Data symbol) = Y - 1] ([Mapping Data(Data symbol) = Y - 1]).

[0455] - In the case of a difference in state symbols formed by rotation-exchange (RS), it is necessary to assign a position movement value of 12 to 22. Rotation is represented as a Y value that can be assigned decimal 0 to 10 as described above, and exchange is defined as a Z value that can only be performed once, with the Z position movement having a value of decimal + 12.

[0456] The value of [ROTATE + RS - 1] is mapped to the data value to be transmitted. In summary, the position movement of the status symbol can be decimal 12~22, and the transmitted data (i.e., the mapped data) that can be transmitted through position movement can be defined as a value of decimal 11~21.

[0457] It has the relation [Mapping Data (Data symbol) = Y + Z - 1 ([Mapping Data (Data symbol) = Y + Z - 1) (where Z represents 12)].

[0458] At this time, the value of the state symbol when the value of the mapped data is decimal 21 (i.e., the position movement value is 22) can be used as the end (END) control signal (control symbol) to specify the end of data transmission and reassign the position of the initial state symbol to A0.

[0459] In the IDLE state, the first value that marks the start of signal transmission is represented as the value Y, which is rotated clockwise from position A0 or B0, or the difference between a combination of Y and Z.

[0460] For example, the case where Y is 1 is defined as data "0". That is, if the data to be transmitted by the link unit is 0, then the PAM4 value corresponding to the state symbol that is increased by 1 Y in the clockwise direction from the current position is transmitted. By defining the protocol in this way that the value of the state symbol is transformed by +1 and transmitted for the data 0 value, the DC value of the link unit can be prevented from increasing excessively.

[0461] On the other hand, the case where Y is 2 is defined as data "1". That is, if the data to be transmitted by the link unit is 1, then the PAM4 value corresponding to the state symbol that is increased by 2 Y in the clockwise direction from the current position is transmitted. By defining the protocol in this way that the PAM4 value of the state symbol is transformed by +2 and transmitted for data 0, the DC value of the link unit can be prevented from increasing excessively.

[0462] As in the example above, when transmitting consecutive data sequences of 0s or 1s, continuously changing the value of the PAM4 status symbol can reduce the DC level generated on the transmission line. Furthermore, it can reduce bit errors and increase transmission speed.

[0463] Figure 36 In the state transition diagram shown, the state symbols of groups A and B are arranged in a ring. In the state transition diagram, to determine the location of the data or control signal to be transmitted, a definition of the relationship between the previous state symbol value and the current state symbol value is required. These state transition rules and the transition symbols defining these state transitions are described in Table 6 below.

[0464] [Table 6]

[0465] Referring to Table 6, swapping (S) is an operation that changes the position of state symbols by exchanging only the groups while maintaining the same state symbol sequence number. This operation can be performed more than once as required in each data transmission and can be performed on any state symbol. Data transmission can begin through the IDLE state or proceed directly without going through the IDLE state.

[0466] The End (END, E) signal indicates the end of data transmission. After data transmission ends, the position of the state symbol is re-initialized to its initial position, i.e., state symbol A0. The value of (Y×10+Z=22), which represents the maximum possible state change resulting from rotations and rotation-exchanges, is defined as the END state.

[0467] Rotation (R) is an action that increments the index clockwise to the next index (+1) within the same group without changing the group. This operation can rotate from 1 to a maximum of 11 in a single state change.

[0468] Rotation-Exchange (RS) is a composite operation that occurs simultaneously when the group is changed due to a group exchange in the current position, and a rotation to the next index +1 occurs in the changed group. This operation can only involve 0 to 10 rotations and 1 exchange in a single state change.

[0469] Refer again Figure 36 The following is an example of how to determine the value of a status symbol based on a transmitted data signal or a transmitted control signal.

[0470] To transfer the IDLE state from position A0, a swap (SWAP) value is selected at the same position, changing only the group name, i.e., position B0. That is, move X.

[0471] In order to transmit the decimal data "0" from the position of the status symbol A0, the value of rotating (ROTATE) 1 Y in the clockwise direction is selected, which is the status symbol A1.

[0472] In order to transmit the decimal data "1" from the position of status symbol A0, the value of rotating (ROTATE) 2 Y in the clockwise direction is selected, which is the status symbol A2.

[0473] In order to transmit the decimal data "10" from the position of the status symbol A0, the value of rotating (ROTATE) 11 Y in the clockwise direction is selected, which is the status symbol A11.

[0474] To transfer the decimal data "11" from the position of status symbol A0, rotating (ROTATE) 12 Y' clockwise returns to the current position (A0), making it impossible to allocate a new position. Therefore, status symbol B1, which performs a rotation (ROTATE) 1 and a swap (SWAP), is selected. This situation is called Rotate-Swap (RS). In the above, the position movement value of Rotate-Swap (RS) is +12.

[0475] To transmit the decimal data "20" from the position of status symbol A0, 21 position shift values ​​are required. Therefore, subtracting 12 (rotate-swap (RS) position value + 12) from 21, i.e., rotating (ROTATE) 9 times, assigns the position of status symbol A9 as the intermediate value. The position of status symbol B10, which is rotated and swapped (ROTATE-SWAP, + 12 position shift value) from the position of A9, is selected as the final transmitted status symbol.

[0476] To transmit the notification that data transmission has ended (END) from the position of status symbol A0, 22 position shift values ​​are required. Therefore, the position of status symbol A10 is assigned as the intermediate value by subtracting 12 (rotate-swap (RS) position value + 12) from 22, i.e., by rotating (ROTATE) 10 times. The position of status symbol B11, which is rotated and swapped (ROTATE-SWAP, + 12 position shift values) from the position of A10, is selected as the final transmitted status symbol.

[0477] Figure 37 This is a diagram illustrating the process of allocating and receiving decimal transmitted data. In particular, it illustrates the process of allocating and receiving the decimal transmitted data "11, 1, 3, 7, 20, 5, 13" (i.e., base-21 data B, 1, 3, 7, K, 5, D) according to the mapping definition.

[0478] Reference Figure 37 During the transmission and reception process, the six results of the comparator after comparing the PAM4 values ​​of the four transmission lines received according to the clock data (CD) are used to distinguish the control symbols and data symbols by the relationship between the received status symbols (A0~A11, B0~B11) and decode them to calculate the transmitted data value.

[0479] Clock data (CD) defines the timing and clock sequence of an 11-cycle clock from decimal 0 to 10.

[0480] The differential receive comparison value of the link unit refers to the output value of the six comparators (i.e., (RX[0], RX[1], RX[2], RX[3], RX[4], RX[5]) (or RX[0:5]) as shown in Table 4, which is composed of the comparison values ​​of the two endpoints of the line segments that constitute the transmission lines A, B, C, and D of the link unit, implemented by the graphic coloring theory).

[0481] When converting decimal data from 0 to 21 to base 21, they can be represented in ascending order as "0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F, G, H, I, J, K".

[0482] In CD 0, the initial value state symbol used for data transmission is A0.

[0483] In CD 1, B0 is transmitted to transmit a switch signal, which becomes a condition for a control signal (Symbol). The result is the IDLE state, which is also a control signal. The control signal for transitioning from the IDLE state to the data transmission state is not separately defined. When the relative distance representing the movement of the state symbol is between decimal 1 and 21, the state transitions to data transmission, and the value obtained by subtracting 1 from the relative distance becomes the 21-ary data to be transmitted or received.

[0484] In CD 2, in order to transmit base 21 B (i.e., decimal 11), the state symbol A1, which is at a relative distance of decimal 12, is transmitted from the state symbol B0.

[0485] In CD 3, in order to transmit a base-21 1, a state symbol A3 with a relative distance of 2 is transmitted from state symbol A1.

[0486] In the same manner, status symbols corresponding to the relative distance are transmitted from CD 3 to CD 8.

[0487] Next, in CD 9, the control symbol END signal with a relative distance of decimal 22 is transmitted from the status symbol A10, thereby defining the end of the data bundle transmission. In order to prepare for the next sequence of data transmission, the value of the status symbol is initialized to A0, preparing for the next sequence of data transmission.

[0488] A data transfer bundle (or data transfer unit) typically refers to the basic unit of data transfer between communication entities (memory elements such as DRAM, flash memory, and SRAM, and processor units, or between processor units), i.e., the size of a page, or the basic data unit for performing Direct Memory Access (DMA). Depending on the application, it can be set to various sizes such as 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1KB, 2KB to 1024KB, etc. It refers to the basic unit of optimized data transfer volume composed of multiple data sets defined according to the data transfer protocol between the communicating entities.

[0489] exist Figure 36 In this context, the swap signal transmitted between CD0 and CD1 signifies an idle state. The idle state can be repeated more than one desired number of times.

[0490] In the waiting state, the values ​​of the state symbols A0 and B0 facing each other have opposite values, and the expected value of the information transmitted from one PHY and the signal received from the other PHY is already known. Therefore, for the driving value and the receiving value of the PHY, calibration can be performed taking into account the respective load conditions of the transmission lines (the driving circuit (DRV) of the PHY responsible for data signal transmission on one side optimizes the driving characteristics by minimizing signal jitter and maximizing the area of ​​the eye pattern through pre-emphasis, while the receiving circuit (RCV) of the PHY on the other side improves the communication quality by measuring and adjusting the receiving sensitivity and the data timing of the received signal through adaptive equalization processes).

[0491] Figure 38 This is a block diagram illustrating encoder logic 222 according to an embodiment of the present invention. In particular, Figure 38 This is a detailed explanation. Figure 34 The diagram shown is of encoder logic 222.

[0492] Reference Figure 38 According to an embodiment of the present invention, encoder logic 222 includes a transmission initial position setting module 710, a data input module 720, and a transmission status judgment module 730. In this embodiment, it is described that encoder logic 222 is composed of transmission initial position setting module 710, data input module 720, and transmission status judgment module 730, but this is only a logical distinction for the convenience of explanation, and not a hardware distinction.

[0493] The initial position setting module 710 sets a specific position that was set as the initial position to a new position (NP) in the state transition diagram. That is, the initial position setting module 710 sets the position of the initial state symbol that indicates the start of signal transmission to state symbol A0, and sets the set state symbol A0 to the new position (NP). In this embodiment, the position of the initial state symbol is defined as state symbol A0 for the convenience of explanation, but it can also be set to other state symbols such as A1, A2, etc.

[0494] The data input module 720 receives transmitted data from the transmitted data stream.

[0495] The transmission status determination module 730 includes a first transmission condition processing unit 731, a second transmission condition processing unit 732, a third transmission condition processing unit 733, a fourth transmission condition processing unit 734, and a transmission error determination unit 735. It is configured to check whether the transmission data input from the transmission data stream satisfies any one of the first, second, third, and fourth transmission conditions, determine the corresponding status, and set a new position (NP). In this embodiment, the transmission status determination module 730 is described as consisting of the first transmission condition processing unit 731, the second transmission condition processing unit 732, the third transmission condition processing unit 733, the fourth transmission condition processing unit 734, and the transmission error determination unit 735. However, this distinction is only for the sake of explanation and not a hardware distinction.

[0496] When the transmitted data satisfies the first transmission condition of 22, the first transmission condition processing unit 731 determines that the meaning of the transmitted data is an idle (IDLE) state, sets the new position (NP) as the old position (OP), and sets the position in the old position (OP) that is converted to X as the new position (NP).

[0497] When the transmitted data satisfies the second transmission condition of being greater than or equal to 0 and less than or equal to 10, the second transmission condition processing unit 732 determines the meaning of the transmitted data as a rotation (R) state, sets the new position (NP) as the old position (OP), and sets the position of the old position (OP) plus Y×(D+1) as the new position (NP).

[0498] When the transmitted data satisfies the third transmission condition of being greater than or equal to 11 and less than or equal to 20, the third transmission condition processing unit 733 determines the meaning of the transmitted data as a rotation-exchange (RS) state, sets the new position (NP) as the old position (OP), applies rotation-exchange (RS) to the old position (OP), and sets the position that has been moved by Y×(D-11) as the new position (NP).

[0499] When the transmission data satisfies the fourth transmission condition of 21, the fourth transmission condition processing unit 734 determines that the meaning of the transmission data is an end state, sets the new position (NP) as the old position (OP), applies rotation-exchange (RS) to the old position (OP), and sets the position that has been moved by Y×(D-11) as the new position (NP).

[0500] When the transmitted data does not meet the first to fourth transmission conditions, the transmission error judgment unit 735 determines that it is in an error state.

[0501] Figure 39This is a block diagram illustrating decoder logic 224 according to an embodiment of the present invention. In particular, Figure 39 This is a detailed explanation. Figure 34 The diagram shown is of decoder logic 224.

[0502] Reference Figure 39 According to an embodiment of the present invention, the decoder logic 224 includes a receiving initial position setting module 810, a data analysis module 820, and a receiving state judgment module 830. In this embodiment, it is described that the decoder logic 224 is composed of the receiving initial position setting module 810, the data analysis module 820, and the receiving state judgment module 830, but this is only a logical distinction for the convenience of explanation, and not a hardware distinction.

[0503] The initial position setting module 810 is configured to set the new position (NP) as the initial position in the state transition diagram and set the new data of the received data.

[0504] The data analysis module 820 is configured to receive data as a receiving data stream is input, set new data as old data, set the received data as new data, and is configured to calculate the data difference between the old data and the new data, and analyze the number of X, Y, and Z respectively.

[0505] The reception status determination module 830 includes a first reception condition processing unit 831, a second reception condition processing unit 832, a third reception condition processing unit 833, a fourth reception condition processing unit 834, and a reception error determination unit 835. It is configured to check any one of the first, second, third, and fourth reception conditions based on the analyzed number of X, Y, and Z values ​​and the received data, and determine the corresponding status. In this embodiment, the reception status determination module 830 is described as consisting of the first reception condition processing unit 831, the second reception condition processing unit 832, the third reception condition processing unit 833, the fourth reception condition processing unit 834, and the reception error determination unit 835. However, this distinction is only for the sake of explanation and not a hardware distinction.

[0506] When the first receiving condition processing unit 831 analyzes the received data and finds that the first receiving condition is met (X = 1, Y = 0, Z = 0), it determines that the received data is in an idle state and stores the received data.

[0507] When the second receiving condition processing unit 832 analyzes the received data and finds that the second receiving condition is met (the number of X is 0, the number of Y is 1 to 11, and the number of Z is 0), it determines that the received data corresponds to the position Y-1 and stores the received data.

[0508] When the third receiving condition processing unit 833 analyzes the received data and finds that the third receiving condition is met (the number of X is 0, the number of Y is 0 to 9, and the number of Z is 1), it determines that the received data corresponds to the position 11+Y and stores the received data.

[0509] When the fourth receiving condition processing unit 834 analyzes the received data and finds that the fourth receiving condition is met (X = 0, Y = 10, Z = 1), it determines that the received data is in an end state and stores the received data.

[0510] When the first to fourth receiving conditions are not met, the receiving error judgment unit 835 judges the received data as an error state.

[0511] Figure 40 This is a flowchart illustrating an encoding method according to an embodiment of the present invention.

[0512] Reference Figure 40 In the state transition diagram, A0, which is a specific position, is used as the initial position to set a new position (NP) (step S102). Step S102 can be achieved by... Figure 38 The initial position setting module 710 described in the document is executed.

[0513] Next, transmit data (D) is received from the transmit data stream (step S104). The transmit data (D) is the data conventionally transmitted in the transmit circuit, including actual data from 0 to 20 and two control data sets (21 (END), 22 (IDLE)). Step S104 can be performed by... Figure 38 The data input module 720 described herein is executed.

[0514] Next, check whether the transmitted data satisfies the first transmission condition of "22" (step S106). Step S106 can be performed by... Figure 38 The first transmission condition processing unit 731 of the transmission status judgment module 730 described herein is executed.

[0515] In step S106, if the transmitted data is found to meet the first transmission condition, the meaning of the transmitted data is determined to be an idle state, the action is S, and the status symbol is X. The new position (NP) is set to the old position (OP), and the position in the old position (OP) that is converted to X is set to the new position (NP) (i.e., OP←NP, NP=S(OP)) (step S108). Here, the action corresponding to the idle state is swap (S), and the status symbol corresponding to the idle state is X. OP←NP, NP=S(OP) means that the position of OP moved by X is set to NP.

[0516] In this embodiment, the idle time (IDLE) can be transmitted at the beginning of the data column transmission, or it can be arbitrarily inserted to reduce the DC level generated between the transmitted data columns.

[0517] In this embodiment, swap (S) is a function of exchanging positions with the same numbers in group A (0~11) and group B (0~11), defined as X occurring only once in one transmission. End (E) is a signal indicating data transmission, defined as END occurring only once in one transmission of a data column. The data unit of a transmission column represents a data block. Rotate (R) defines a clockwise rotational movement within its own group. Rotation can occur multiple times in one data transmission. Rotate-swap (RS) defines a movement that performs a position swap (SWAP) after a previous position rotation. Defined as Z occurring only once in one transmission. Step S108 can be performed by... Figure 38 The first transmission condition processing unit 731 of the transmission status judgment module 730 described herein is executed.

[0518] Next, the PAM4 value of the data corresponding to the new position is transmitted to the transmission line via the PHY (step S110), and then the process returns to step S104. Specifically, the name of the status symbol corresponding to the new position is found in Table 4, the PAM4 data value [3, 1, -1, -3] is encoded, and the data (i.e., the encoded PAM4 data) is transmitted via the PHY. Step S110 can be performed by... Figure 38 The first transmission condition processing unit 731 of the transmission status judgment module 730 described herein is executed.

[0519] In step S106, if the transmitted data is found not to meet the first transmission condition, then it is checked whether the transmitted data meets the second transmission condition of being greater than or equal to 0 and less than or equal to 10 (step S112). Step S112 can be determined by... Figure 38 The second transmission condition processing unit 732 of the transmission status judgment module 730 described herein is executed.

[0520] In step S112, if the second transmission condition is met, the meaning of the transmitted data is determined to be a rotation (R) state, the action is R, and the state symbol is Y×(D+1). The new position (NP) is set as the old position (OP), and the position of the old position (OP) plus Y×(D+1) is set as the new position (i.e., NP=OP+Y(D+1)) (step S114), then return to step S110. For example, if D is 1, then Y moves 2 units clockwise. The meaning of NP=OP+Y(D+1) is to set the position of OP that has moved D+1 units Y as the new position (NP). Step S114 can be determined by... Figure 38The second transmission condition processing unit 732 of the transmission status judgment module 730 described herein is executed.

[0521] In step S112, if the second transmission condition is not met, then it is checked whether the transmitted data meets the third transmission condition of being greater than or equal to 11 and less than or equal to 20 (step S116). Step S116 can be determined by... Figure 38 The third transmission condition processing unit 733 of the transmission status judgment module 730 described herein is executed.

[0522] In step S116, if the third transmission condition is met, the meaning of the transmitted data is determined to be a rotation-exchange (RS) state, the action is RS, and the state symbol is Z+Y. The new position (NP) is set as the old position (OP). After applying rotation-exchange (RS) to the old position (OP), the position moved by Y×(D-11) is set as the new position (NP) (i.e., NP=Z(OP)+Y×(D-11)) (step S118), and the process returns to step S110. The meaning of NP=Z(OP)+Y×(D-11) is to move OP by Z and set the position by moving D-11 numbers of Y as the new position (NP). Step S118 can be determined by... Figure 38 The third transmission condition processing unit 733 of the transmission status judgment module 730 described herein is executed.

[0523] In step S116, if the third transmission condition is not met, then it is checked whether the transmitted data meets the fourth transmission condition of 21 (step S120). Step S120 can be performed by... Figure 38 The fourth transmission condition processing unit 734 of the transmission status judgment module 730 described herein is executed.

[0524] In step S120, if the transmitted data is found to meet the fourth transmission condition, the meaning of the transmitted data is determined to be the end (END) state of the transmitted data stream, the action is E, and the state symbol is E. The new position (NP) is set as the old position (OP). After applying rotation-swapping (RS) to the old position (OP), the position that has been moved by Y×(D-11) is set as the new position (NP) (i.e., NP=Z(OP)+Y×(D-11)) (step S122). Step S122 can be determined by... Figure 38 The fourth transmission condition processing unit 734 of the transmission status judgment module 730 described herein is executed.

[0525] Next, in step S122, the name of the status symbol corresponding to the new position is found in Table 4. The corresponding PAM4 value is then transmitted to the transmission line via the PHY to transmit the data (i.e., the encoded PAM4 data) (step S124), and the process returns to step S102. Step S124 can be... Figure 38 The fourth transmission condition processing unit 734 of the transmission status judgment module 730 described herein is executed.

[0526] In step S120, if the transmitted data is found to not meet the fourth transmission condition, an error state is determined (step S126), and the process returns to step S102. Step S126 can be determined by... Figure 38 The transmission error judgment unit 735 of the transmission status judgment module 730 described herein is executed.

[0527] Figure 41 This is a flowchart illustrating a decoding method according to an embodiment of the present invention.

[0528] Reference Figure 41 In the state transition diagram, A0, which is a specific position, is set as the initial position to a new position (NP), and 0 is set as the new data (ND) (step S202). Step S202 can be performed by... Figure 39 The initial position setting module 810 described in the document is executed.

[0529] Next, in step S202, receive data (D) from the received data stream, set the new data (ND) as the old data (OD), set the received data (D) as the new data (ND), and analyze the number of X, Y, and Z respectively by the data difference (DD) between the old data (OD) and the new data (ND) (step S204).

[0530] Here, the received data (D) is the data received to the receiving circuit through the transmission line, and is mapped to the values ​​of state symbols A0~A11 and B0~B11 respectively, each providing the position for obtaining information about the received data (D) and control signals. In addition, the data difference (DD) is the value used to calculate the difference between the positions of the state transition diagram of the old data (OD) and the new data (ND) on the receiving side, and each difference can be represented by the number of X, Y, and Z.

[0531] For example, let's illustrate the case where the initial value OP is A0 and the received new position (NP) value is B0 in the initial settings. If the comparator output at the receiving end is [0,0,0,1,0,0], the state symbol is determined to be A0 according to Table 4. Subsequently, if the comparator output at the receiving end is [1,1,1,0,1,1], the state symbol is determined to be B0 according to Table 4. The state transition diagram confirms that there is an X as a data difference (DD) between state symbols A0 and B0. Step S204 can be performed by... Figure 39 The data analysis module 820 described in the document is executed.

[0532] Next, in step S204, in the result of analyzing the received data (D), it is checked whether the first reception condition of X being 1, Y being 0, and Z being 0 is met (step S206). Step S206 can be determined by... Figure 39 The first receiving condition processing unit 831 of the receiving status judgment module 830 described herein is executed.

[0533] In step S206, if the first reception condition is met, the received data (D) is determined to be in an idle state (step S208), the received data (D) is stored (step S210), and the process returns to step S204. In this embodiment, the idle state can be transmitted at the beginning of a data column transmission, or it can be arbitrarily inserted to reduce the DC level generated between transmitted data columns. Steps S208 and S210 can be determined by... Figure 39 The first receiving condition processing unit 831 of the receiving status judgment module 830 described herein is executed.

[0534] In step S206, if the first reception condition is not met, then in the result of analyzing the received data (D), it is checked whether the second reception condition is met (X = 0, Y = 1 to 11, Z = 0) is satisfied (step S212). Step S212 can be determined by... Figure 39 The second receiving condition processing unit 832 of the receiving status judgment module 830 described herein is executed.

[0535] In step S212, if the second reception condition is met, the received data (D) is determined to correspond to the position [Y-1] (step S214), and the process returns to step S210. Step S214 can be determined by... Figure 39 The second receiving condition processing unit 832 of the receiving status judgment module 830 described herein is executed.

[0536] In step S212, if the second reception condition is not met, then in the result of analyzing the received data (D), it is checked whether the third reception condition is met: the number of X is 0, the number of Y is 0 to 9, and the number of Z is 1 (step S216). Step S216 can be determined by... Figure 39 The third receiving condition processing unit 833 of the receiving status judgment module 830 described herein is executed.

[0537] In step S216, if the third reception condition is met, the received data (D) is determined to correspond to the position [11+Y] (step S218), and the process returns to step S210. Step S218 can be determined by... Figure 39 The third receiving condition processing unit 833 of the receiving status judgment module 830 described herein is executed.

[0538] In step S216, if the third reception condition is not met, then in the result of analyzing the received data (D), it is checked whether the fourth reception condition is met: the number of X elements is 0, the number of Y elements is 10, and the number of Z elements is 1 (step S220). Step S220 can be determined by... Figure 39 The fourth receiving condition processing unit 834 of the receiving status judgment module 830 described herein is executed.

[0539] In step S220, if the fourth reception condition is met, the received data (D) is determined to be an end control signal (step S222), the received data (D) is stored (step S224), and the process returns to step S202. Steps S222 and S224 can be determined by... Figure 39 The fourth receiving condition processing unit 834 of the receiving status judgment module 830 described herein is executed.

[0540] In step S220, if the fourth receiving condition is not met, an error is determined (step S226), and the process returns to step S202. Step S226 can be determined by... Figure 39 The reception error judgment unit 835 of the reception status judgment module 830 described herein is executed.

[0541] As described above, according to the present invention, by controlling the DC level characteristics of the four transmission lines transmitting PAM4 signals, the frequency at which a specific symbol level is maintained for a long time can be minimized. This suppresses the persistence of the same electrical state, thereby mitigating transmission line impedance variations in link units, and consequently improving the overall system response characteristics.

[0542] The above description refers to the embodiments, but those skilled in the art will understand that various modifications and alterations can be made to the invention without departing from the spirit and scope of the invention as set forth in the appended claims.

[0543] <Explanation of Figure Markers> 10: Transmission line; 21: First processor unit 22: First encoder / decoder 23: First transmit / receive buffer 31: Second transmit / receive buffer; 32: Second encoder / decoder 33: Second processor unit; 200: First communication unit 210: First PHY unit; 220: First encoding / decoding unit 230: First pre-encoder; 240: First post-decoder 300: Second communication unit; 310: Second PHY unit 320: Second encoding / decoding unit; 330: Second pre-encoder 340: Second post-decoder; 400: DRV block 500: RCV block 710: Send initial position setting module 720: Data Input Module; 730: Transmission Status Judgment Module 731: First transmission condition processing unit; 732: Second transmission condition processing unit 733: Third Transmission Condition Processing Unit; 734: Fourth Transmission Condition Processing Unit 735: Error detection unit; 810: Initial position setting module. 820: Data Analysis Module; 830: Receive Status Judgment Module 831: First receiving condition processing unit; 832: Second receiving condition processing unit 833: Third Receiving Condition Processing Unit; 834: Fourth Receiving Condition Processing Unit 835: Error detection unit.

Claims

1. A data communication system, comprising: The link unit consists of four transmission lines and is driven by PAM4 signals; The first communication unit includes a first PHY unit connected to one side of the link unit and performing the transmission / reception of the PAM4 signal, and a first encoding / decoding unit connected to the first PHY unit; as well as The second communication unit includes a second PHY unit connected to the other side of the link unit and performing the transmission / reception of the PAM4 signal, and a second encoding / decoding unit connected to the second PHY unit. Each of the first encoding / decoding unit and the second encoding / decoding unit includes: The encoder logic assigns signal pairs that satisfy the following conditions to vertices and line segments in the graphics shading theory, defines the signal pair as a state symbol according to a determined relationship, matches the transmitted data to the state symbol, encodes the data using a definition of the relationship between the previous and current state symbols, and transmits it to the link unit: the sum of the PAM4 signals of each transmission line is 0, and the PAM values ​​of the simultaneously driven transmission lines have different signal levels; and The decoder logic uses the definition of the relationship between the previous state symbol and the current state symbol to decode the signal received through the link unit and recover it as data.

2. The data communication system according to claim 1, wherein, The number of data items transmitted using the PAM4 signal used for transmission / reception is 23. Of the 23 data points, 21 are actual communication data, and 2 include control signals for transmission.

3. The data communication system according to claim 1, wherein, The encoder logic includes: The initial position setting module sends a message to the state transition diagram, which has 24 state symbols and the relative distance between each state symbol is defined by the transition symbols X, Y and Z, and sets the specific position set as the initial position as the new position. The data input module receives transmitted data from the transmitted data stream; and The transmission status judgment module is configured to check whether the transmitted data meets any of a plurality of transmission conditions, determine the corresponding status, and set a new position.

4. The data communication system according to claim 3, wherein, The state transition diagram includes: group A, which has 12 state symbols arranged corresponding to the inner circle, and group B, which has 12 state symbols arranged corresponding to the outer circle. In the state transition diagram, the transition symbols X, Y, and Z define the relative distances between the state symbols. The conversion symbol X represents the exchange between state symbols belonging to group A and state symbols belonging to group B, and also represents the exchange between state symbols with the same sequence number. The transition symbol Y indicates that the state symbol belonging to group A or group B moves one step within the same group. The transition symbol Z represents moving one step from the state symbol belonging to group A or group B to the state symbol belonging to group B or group A.

5. The data communication system according to claim 4, wherein, The decoder logic includes: The initial position setting module receives the initial position setting in the state transition diagram, sets the specific position set as the initial position as the new position, and sets 0 as the new data; The data analysis module receives data from the received data stream, sets new data as old data, sets the received data as new data, calculates the data difference between the set old data and the set new data, and analyzes the number of X, Y, and Z values ​​respectively; and The receiving status determination module checks any one of multiple receiving conditions based on the number of X, Y, and Z values ​​analyzed and the received data, and determines the corresponding status.

6. The data communication system according to claim 5, wherein, The state is any of the following: a swap (SWAP, S) in which the state symbols of group A and group B are not sequentially increased but are transferred to the opposite group and only their positions are exchanged; an end of data communication (END, E); a rotation (R) in which the group is not changed in the previous state symbol of group A or group B but is moved only in a circular direction within the same group; and a rotation-swap (RS) in which the group is exchanged to another group in the previous state symbol of group A or group B and rotation occurs in the exchanged group.

7. The data communication system according to claim 1, wherein, The first encoding / decoding unit is used for: During signal transmission, the received data is used to form a status symbol based on the TX signal and the TX enable signal, and the formed status symbol is provided to the first PHY unit. During signal reception, the state symbol is recovered based on the RX signal provided from the first PHY unit.

8. The data communication system according to claim 7, wherein, The first PHY unit includes: one or more DRV blocks that convert TX signals of externally input voltage levels into current and output them to the transmission line through I / O pads; and one or more RCV blocks that receive PAM4 signals transmitted through the link unit and send / receive PAM4 signals.

9. The data communication system according to claim 1, wherein, The second encoding / decoding unit is used for: During signal reception, the state symbol is recovered based on the RX signal provided by the second PHY unit. During signal transmission, the received data is used to form a status symbol based on the TX signal and the TX enable signal, and the formed status symbol is provided to the second PHY unit.

10. The data communication system according to claim 9, wherein, The second PHY unit includes: one or more DRV blocks, which convert TX signals of externally input voltage levels into current and output them to the transmission line through I / O pads; and one or more RCV blocks, which receive PAM4 signals transmitted through the link unit and send / receive PAM4 signals.

11. An encoder logic configured in a data communication system, wherein the data communication system drives link units consisting of four transmission lines each with PAM4 signals, and uses graph coloring theory to use 24 state symbols whose sum of PAM4 signals is 0 and whose results from six comparators are non-repeating for communication; the encoder logic generates signals to drive the PHY unit of the communication unit; the communication unit receives data to be transmitted and encodes it to transmit state symbol signals, wherein... The encoder logic includes: The initial position setting module sends a message to the state transition diagram, which has 24 state symbols and the relative distance between each state symbol is defined by the transition symbols X, Y and Z, and sets the specific position set as the initial position as the new position. The data input module receives transmitted data from the transmitted data stream; and The transmission status judgment module is configured to check whether the transmitted data meets any of a plurality of transmission conditions, determine the corresponding status, and set a new position.

12. The encoder logic according to claim 11, wherein, The sending status determination module includes: The first transmission condition processing unit determines the meaning of the transmission data as an idle state when the transmission data satisfies the first transmission condition of 22, sets the new position as the old position, and sets the position in the old position that is converted to X as the new position. The second transmission condition processing unit determines the meaning of the transmission data as a rotation (ROTATE, R) state when the transmission data satisfies the second transmission condition of being greater than or equal to 0 and less than or equal to 10. It then sets the new position as the old position and sets the position of the old position plus Y(D+1) as the new position. The third transmission condition processing unit, when the transmitted data satisfies the third transmission condition of being greater than or equal to 11 and less than or equal to 20, determines the meaning of the transmitted data to be in a rotation-swap (RS) state, sets the new position as the old position, applies rotation-swap (RS) to the old position, and sets the position that has been moved by Y(D-11) as the new position; and The fourth transmission condition processing unit determines the meaning of the transmission data as an end state when the transmission data satisfies the fourth transmission condition of 21, sets the new position as the old position, applies rotation-exchange (RS) to the old position, and sets the position that has been moved by Y (D-11) as the new position.

13. The encoder logic according to claim 12, wherein, The sending status judgment module further includes a sending error judgment unit, which judges the sending error status when the sending data does not meet the first to the fourth sending conditions.

14. A decoder logic configured in a data communication system, wherein the data communication system drives link units consisting of four transmission lines each with PAM4 signals, and uses graph coloring theory to use 24 state symbols whose sum of PAM4 signals is 0 and whose results from six comparators are non-repeating for communication, wherein the decoder logic receives six PAM4 comparison signals output from the PHY unit of the communication unit and recovers the 24 state symbols, wherein, The decoder logic includes: The initial position setting module receives the initial position setting module, which sets the specific position set as the initial position as the new position in the state transition diagram with 24 state symbols and the relative distance between each state symbol defined by the transition symbols X, Y and Z, and sets 0 as the new data. The data analysis module receives data from the received data stream, sets new data as old data, sets the received data as new data, calculates the data difference between the set old data and the set new data, and analyzes the number of X, Y, and Z values ​​respectively; and The receiving status determination module checks any one of multiple receiving conditions based on the number of X, Y, and Z values ​​analyzed and the received data, and determines the corresponding status.

15. The decoder logic according to claim 14, wherein, The receiving status determination module includes: The first receiving condition processing unit determines the received data to be in an idle state and stores the received data when the result of analyzing the received data satisfies the first receiving condition that the number of X is 1, the number of Y is 0, and the number of Z is 0. The second receiving condition processing unit, when analyzing the received data and finding that the result satisfies the second receiving condition that the number of X is 0, the number of Y is 1 to 11, and the number of Z is 0, determines that the received data corresponds to the position Y-1 and stores the received data. The third receiving condition processing unit, when analyzing the received data and finding that the number of X's is 0, the number of Y's is 0 to 9, and the number of Z's is 1, determines that the received data corresponds to the position 11+Y and stores the received data; and The fourth receiving condition processing unit determines the received data as an end state and stores the received data when the result of analyzing the received data satisfies the fourth receiving condition that the number of X is 0, the number of Y is 10, and the number of Z is 1.

16. The decoder logic according to claim 15, wherein, The receiving status determination module further includes: The receiving error judgment unit determines the received data as an error state when the first to fourth receiving conditions are not met.

17. An encoding method, comprising the following steps: (a) In a state transition diagram with 24 state symbols and the relative distance between each state symbol defined by transition symbols X, Y and Z, a specific position set as the initial position is set as the new position; (b) Receive transmitted data from the transmitted data stream; (c) When the transmitted data satisfies the first transmission condition of 22, the meaning of the transmitted data is determined to be an idle state, the new position is set as the old position, and the position in the old position that is converted to X is set as the new position; (d) After transmitting the PAM4 value of the data corresponding to the new position to the transmission line via PHY, return to step (b); (e) When the transmitted data satisfies the second transmission condition of being greater than or equal to 0 and less than or equal to 10, the meaning of the transmitted data is determined to be a rotation (ROTATE, R) state, the new position is set as the old position, the position of the old position plus Y(D+1) is set as the new position, and then the process returns to step (d). (f) When the transmitted data meets the third transmission condition of being greater than or equal to 11 and less than or equal to 20, the meaning of the transmitted data is determined to be a rotation-swap (RS) state. The new position is set as the old position. After applying rotation-swap (RS) to the old position, the position that has been moved by Y(D-11) is set as the new position, and the process returns to step (d); and (g) When the transmitted data satisfies the fourth transmission condition of 21, the meaning of the transmitted data is determined to be the end state, the new position is set as the old position, after applying rotation-swap (RS) to the old position, the position that has been moved by Y (D-11) is set as the new position, and then the process returns to step (a).

18. The encoding method according to claim 17 further comprises the following steps: (h) When the transmitted data does not meet the first to fourth transmission conditions, it is determined to be an error state and then returns to step (a).

19. A decoding method, comprising the following steps: (a) In a state transition diagram with 24 state symbols and the relative distance between each state symbol defined by transition symbols X, Y and Z, a specific position set as the initial position is set as the new position, and 0 is set as the new data; (b) As receiving data from the received data stream, setting new data as old data, after setting the received data as new data, calculating the data difference between the set old data and the set new data, and analyzing the number of X, Y and Z respectively; (c) When the result of analyzing the received data satisfies the first receiving condition that the number of X is 1, the number of Y is 0, and the number of Z is 0, the received data is determined to be in an idle state, the received data is stored, and then the process returns to step (b). (d) When the result of analyzing the received data satisfies the second receiving condition that the number of X is 0, the number of Y is 1 to 11, and the number of Z is 0, the received data is determined to correspond to the position of Y-1, the received data is stored, and then the process returns to step (b). (e) When the analysis of the received data satisfies the third receiving condition that the number of X is 0, the number of Y is 0 to 9, and the number of Z is 1, the received data is determined to correspond to the position 11+Y, the received data is stored, and the process returns to step (b); and (f) When the result of analyzing the received data satisfies the fourth receiving condition that the number of X is 0, the number of Y is 10, and the number of Z is 1, the received data is judged to be finished, the received data is stored, and the process returns to step (a).

20. The decoding method according to claim 19 further includes the following steps: (g) When the received data does not meet the first to fourth receiving conditions, it is determined to be an error state and then returns to step (a).

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