Circuit board and semiconductor package including the same

Abstract

One embodiment of the present invention discloses a circuit board including a first core layer; a second core layer disposed on the first core layer; a wiring layer disposed between the first core layer and the second core layer; and a via electrode passing through the first core layer, the wiring layer, and the second core layer.

Description

Technical Field

[0001] Embodiments of this disclosure relate to circuit boards and semiconductor packages. Background Technology

[0002] As electrical / electronic products become increasingly high-performance, technologies for mounting a greater number of packages on substrates of limited size are being proposed and researched. However, since typical packages are essentially designed to mount a single semiconductor chip, there are limitations in achieving the desired performance.

[0003] A typical circuit board or packaging substrate has the following configuration: a processor package containing a processor chip is integrated with a memory package containing a memory chip. This type of packaging substrate offers advantages such as reduced chip footprint by manufacturing the processor chip and memory chip as a single integrated package, and the ability to achieve high-speed signal processing through short paths. Due to these advantages, this type of packaging substrate is widely used in many mobile devices and similar applications.

[0004] Meanwhile, recently, due to the improved performance of electronic devices such as mobile devices and the adoption of high-bandwidth memory (HBM), package sizes are increasing. Furthermore, as the required functions of application processors increase, a circuit board is needed that can configure each function as a separate processor chip and mount these processor chips. In this case, even if the application processor is divided into two processor chips according to function, the number of terminals (input / output) set in each processor chip is increasing.

[0005] Furthermore, recently, due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the amount of power and signals has increased, leading to a gradual increase in the number of terminals on processor chips. Consequently, the area and thickness of circuit boards, as well as the density of circuit patterns, are also increasing. When the area or thickness of the circuit board increases, it becomes difficult to achieve product miniaturization and can lead to reliability issues, including circuit board warping, and increased product costs. Therefore, compared to increasing the area and thickness of the circuit board, increasing the density of circuit patterns is more advantageous in terms of product cost, reliability (including warping resistance), and product miniaturization. Therefore, miniaturization of circuit patterns or through electrodes is necessary.

[0006] In particular, as circuit boards become thinner, the warping, twisting, and other deformations that occur during the circuit board manufacturing process increase. To prevent this, a glass core structure in which a glass plate is formed in the core of the circuit board is being proposed. Summary of the Invention

[0007] Technical issues

[0008] Embodiments of this disclosure provide a circuit board and a semiconductor package including the same, in which warpage is suppressed and electrical characteristics are improved even with increased thickness due to the use of glass layers having high stiffness and low coefficient of thermal expansion. In particular, this disclosure can provide various examples of circuit boards and semiconductor packages including the same, in which electrical and structural reliability are improved because multiple glass layers are configured as core layers.

[0009] Furthermore, embodiments can realize a circuit board and a semiconductor package including the circuit board, in which reliability is further improved even with an increase in the thickness of the circuit board by having multiple glass layers.

[0010] Alternatively, embodiments may implement a circuit board and a semiconductor package including the circuit board, which reduces crosstalk due to reduced electrical distance by providing a ground plane between multiple core layers.

[0011] Furthermore, embodiments can realize a circuit board and a semiconductor package including the circuit board, in which voltage concentration effects are suppressed by curved patterned grooves, thereby improving electrical reliability.

[0012] Furthermore, embodiments may implement a circuit board and a semiconductor package including the circuit board in which structural reliability is improved by setting the via electrodes to be staggered from each other.

[0013] The problems to be solved in the embodiments are not limited to these. It should be understood that the problems also include the objectives or effects that can be understood from the technical solutions or embodiments described below.

[0014] Technical solution

[0015] The circuit board according to an embodiment of the present disclosure includes: a first core layer; a second core layer disposed on the first core layer; a wiring layer disposed between the first core layer and the second core layer; and a via electrode passing through the first core layer, the wiring layer and the second core layer.

[0016] The ground plane can be set on the cabling layer.

[0017] The first core layer may include a first upper surface and a first lower surface opposite to the first upper surface, and the second core layer may include a second upper surface and a second lower surface opposite to the second upper surface.

[0018] The ground plane can be set between the first lower surface of the first core layer and the second upper surface of the second core layer.

[0019] The ground plane can be placed at the center of the cabling layer.

[0020] The distance between the ground plane and the first upper surface can be equal to the distance between the ground plane and the second lower surface.

[0021] The ground plane can be set to be adjacent to the first upper surface or the second lower surface.

[0022] The distance between the ground plane and the first upper surface may be different from the distance between the ground plane and the second lower surface.

[0023] The ground plane can contact the first upper surface and be embedded in the first core layer.

[0024] The ground plane may include a first ground plane and a second ground plane spaced apart from the first ground plane.

[0025] The first and second ground planes can be set in the cabling layer.

[0026] The first and second ground surfaces may not overlap at least partially in the stacking direction.

[0027] The distance between the first ground surface and the first upper surface may be different from the distance between the second ground surface and the second lower surface.

[0028] The first ground plane can contact the first upper surface, and the second ground plane can contact the second lower surface.

[0029] The first ground plane can be embedded in the first core layer, and the second ground plane can be located at the center of the wiring layer.

[0030] The circuit board may include: a first insulating layer disposed below a first core layer; and a second insulating layer disposed above a second core layer.

[0031] The thickness of the wiring layer can be greater than the thickness of at least one of the first insulating layer and the second insulating layer.

[0032] The first core layer may include a first via, and the second core layer may include a second via.

[0033] The first via can overlap with the second via in the stacking direction.

[0034] The center axis of the first via in the horizontal direction can be offset from the center axis of the second via in the horizontal direction.

[0035] It may include a through-hole that penetrates a first insulating layer, a first via, a wiring layer, a second via, and a second insulating layer, and the via electrode may be disposed in the through-hole.

[0036] The distance between the center of the via electrode and the inner wall of the first via can vary in a plane perpendicular to the stacking direction.

[0037] The first via may have a structure in which the diameter or width increases from the center of the first core layer toward each of the upper and lower surfaces of the first core layer, and the second via may have a structure in which the diameter or width increases from the center of the second core layer toward each of the upper and lower surfaces of the first core layer.

[0038] The distance between the first via and the through electrode can be smaller than the distance between the second via and the through electrode.

[0039] A circuit board according to an embodiment of the present disclosure includes: a first core layer including glass and a first via; and a second core layer including glass and a second via and disposed below the first core layer, wherein the first via at least partially overlaps with the second via, and a first central axis of the first via is offset from the central axis of the second via.

[0040] The first core layer may include a first lower surface and a first upper surface, and the second core layer may include a second lower surface and a second upper surface.

[0041] The first lower surface can contact the second upper surface.

[0042] The first core layer may include a first groove formed around a first via in a first lower surface, and the second core layer may include a second groove formed around a second via in a second upper surface.

[0043] The first and second slots may at least partially not overlap in the stacking direction.

[0044] The central axis of the first slot can be offset from the central axis of the second slot.

[0045] It may include a first patterned groove embedded in a first lower surface and a second patterned groove embedded in a second upper surface.

[0046] The first pattern slot can be adjacent to the second pattern slot.

[0047] The first pattern groove and the second pattern groove may include a side surface, a bottom surface, and a connecting surface connecting the side surface and the bottom surface.

[0048] The connecting surface can be a curved surface.

[0049] The first pattern slot and the second pattern slot may not overlap at least partially in the stacking direction.

[0050] The minimum length between the edge of the first via and the edge of the second via can correspond to the minimum length between the edge of the first pattern groove and the edge of the second pattern groove.

[0051] It may include a first insulating layer disposed above the first core layer and a second insulating layer disposed below the second core layer.

[0052] It may include a first via electrode disposed in a first via and a second via electrode disposed in a second via.

[0053] Beneficial effects

[0054] Embodiments of this disclosure provide a circuit board and a semiconductor package including the circuit board, wherein warping and electrical properties are suppressed and improved even with increased thickness by means of a glass layer having high stiffness and low coefficient of thermal expansion.

[0055] Furthermore, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein reliability is further improved even with an increase in the thickness of the circuit board by having multiple glass layers.

[0056] Alternatively, embodiments may provide a circuit board and a semiconductor package including the circuit board, which reduces crosstalk due to reduced electrical distance by providing a ground plane between multiple core layers.

[0057] Furthermore, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein structural reliability is improved by setting the via electrodes to be staggered from one another.

[0058] Furthermore, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein voltage concentration effects are suppressed by curved patterned grooves, thereby improving electrical reliability.

[0059] The various and beneficial advantages and effects of this disclosure are not limited to those described above, and will be more readily understood in the process of describing specific embodiments of this disclosure. Attached Figure Description

[0060] Figure 1 This is a plan view of a circuit board according to a first embodiment of the present disclosure; Figure 2 It is along Figure 1 The view captured by line AA' in the middle; Figure 3 yes Figure 2 A magnified view of K1; Figure 4 yes Figure 3 Another example; Figure 5 yes Figure 4 Another example; Figure 6 This is a cross-sectional view of a circuit board according to a second embodiment of the present disclosure; Figure 7 yes Figure 6 Enlarged view of K2; Figure 8 yes Figure 7Another example; Figure 9 yes Figure 7 Another example; Figures 10 to 15 This is a view used to describe a method of manufacturing a circuit board according to an embodiment of the present disclosure; Figure 16 This is a cross-sectional view of a circuit board according to a third embodiment of the present disclosure; Figure 17 yes Figure 16 A magnified view of K3; Figure 18 yes Figure 17 Variations; Figure 19 This is a plan view of a circuit board according to the fourth embodiment of the present disclosure; Figure 20 It is along Figure 1 The view captured by line AA' in the middle; Figure 21 yes Figure 2 A magnified view of K1; Figure 22 yes Figure 1 Enlarged view of K; Figure 23 This is a cross-sectional view of a circuit board according to the fifth embodiment of this disclosure; Figure 24 yes Figure 23 Enlarged view of K2; Figures 25 to 33 This is a view used to describe a method of manufacturing a core layer in a circuit board according to embodiments of the present disclosure; Figure 34 and Figure 35 This is a view showing the bonding of a first core layer and a second core layer in a circuit board according to a fifth embodiment of the present disclosure; and Figures 36 to 38 This is a view showing the bonding of a first core layer and a second core layer in a circuit board according to a fourth embodiment of the present disclosure.

[0061] Figure 39 This is a cross-sectional view of a circuit board according to the sixth embodiment of the present disclosure; Figure 40 yes Figure 39 Enlarged view of K3; and Figure 41 It is a plan view of the circuit board based on the modified example. Detailed Implementation

[0062] This disclosure is capable of various modifications and has various embodiments, specific of which are shown in the accompanying drawings and will be described. However, this is not intended to limit this disclosure to the specific embodiments.

[0063] It should be understood to include all modifications, equivalents, and substitutions that fall within the spirit and scope of this disclosure.

[0064] Although terms such as "first," "second," etc., may be used to describe various components, these components are not limited by these terms. The terms are used to distinguish one component from another. For example, without departing from the scope of the claims disclosed herein, a second component may be referred to as a first component, and similarly, a first component may be referred to as a second component. The term "and / or" includes any combination of the plurality of related listed items or any one of the plurality of related listed items.

[0065] What will be understood is that when a component is described as being "connected" or "joined" to another component, it can be directly connected or joined to that other component, or there may be intermediate components. Conversely, when a component is described as being "directly connected" or "directly joined" to another component, there are no intermediate components.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. It will also be understood in this application that, when used in this specification, the term "comprising," etc., designates the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0067] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined in this application.

[0068] In the following description, embodiments will be described in detail with reference to the accompanying drawings, and regardless of the reference numerals, the same or corresponding parts will be indicated by the same reference numerals, and repeated descriptions thereof will be omitted.

[0069] Before describing the embodiments, a circuit board and semiconductor-packaged electronic device of the application embodiments will be briefly described. The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to the semiconductor package of the embodiments. Various connection members (e.g., semiconductor devices) may be mounted on the semiconductor package.

[0070] The connection component may include active and / or passive devices. Active devices may be semiconductor chips in the form of integrated circuits (ICs), where hundreds to millions or more devices are integrated into a single chip. The connection component may be a logic chip, a memory chip, etc. A logic chip may be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, a logic chip may be an application processor (AP) chip that includes at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller; or it may be an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc.; or it may be a chipset that includes a specific combination of the items listed above.

[0071] The memory chip can be a stacked memory such as HBM. In addition, the memory chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory.

[0072] Meanwhile, the product group of semiconductor packaging in the application embodiment can be any one of chip-scale packaging (CSP), flip chip-to-chip-scale packaging (FC-CSP), flip chip ball grid array (FC-BGA), stacked package (POP), and system-in-package (SIP), but is not limited thereto.

[0073] Furthermore, electronic devices can be smartphones, personal digital assistants, digital camcorders, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video games, smartwatches, automobiles, etc. However, this disclosure is not limited to these; of course, an electronic device can also be any other electronic device that processes data.

[0074] In the following description, in a circuit board according to an embodiment of the present disclosure, the insulating layer may consist of multiple insulating layers. The insulating layer may include a core layer (the glass layer described below) and an insulating layer. Such a circuit board may be divided into an outer stacked region and an inner stacked region, and the inner stacked region may correspond to the core layer.

[0075] Figure 1 This is a plan view of a circuit board according to the first embodiment of the present disclosure. Figure 2 It is along Figure 1 The view intercepted by line AA' in the middle. Figure 3 yes Figure 2 Enlarged view of K1, Figure 4 yes Figure 3 Another example, Figure 5 yes Figure 4 Another example.

[0076] Reference Figure 1 and Figure 2, refer to Figure 1 and Figure 2 The circuit board 100 according to the first embodiment may include a core layer 110, an insulating layer 120, a protective layer 130, and an electrode portion. Furthermore, the circuit board 100 according to the embodiment may include a semiconductor device SD and conductive members CB1 and CB2 located on one side (e.g., the upper part).

[0077] The circuit board 100 according to the first embodiment may include a core layer 110, an insulating layer 120, a protective layer 130, and an electrode portion. Furthermore, the circuit board 100 according to the embodiment may include a semiconductor device SD and conductive members CB1 and CB2 located on one side (e.g., the upper part).

[0078] The core layer 110 can be either a "core layer" or a "substrate layer". The core layer 110 can suppress warping that occurs as the circuit board becomes thinner. In other words, warping can be reduced by providing a glass layer (or glass core) with high rigidity and a low coefficient of thermal expansion (CTE) at the center or core of the circuit board. For example, the core layer 110 can have higher rigidity and a lower coefficient of thermal expansion than an insulating layer or protective layer.

[0079] Furthermore, the core layer 110 can be made of glass materials. For example, the core layer 110 can contain pure silicon dioxide (approximately 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc., and is not limited to silicon-based glass compositions; alternative glass materials can also be used, such as fluoride glass, phosphate glass, chalcogenide glass, etc. In addition, the core layer 110 can also contain other additives to form a glass with specific physical properties. These additives can contain calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda ash), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements and other elements.

[0080] Furthermore, the core layer 110 can be made of insulating material. Therefore, the core layer 110 can be referred to as an "insulating layer", etc.

[0081] Furthermore, the core layer 110 may be disposed at the center of the insulating layer 120. Additionally, as described below, the core layer 110 may include vias 111h and 112h. The vias 111h and 112h may have various shapes with different numbers and structures than those shown in the figures, and may be formed in various locations.

[0082] Multiple core layers 110 may exist. According to an embodiment, the core layer 110 may include a first core layer 111 and a second core layer 112. The second core layer 112 may be located on top of the first core layer 111. The first core layer 111 and the second core layer 112 may be spaced apart in the stacking direction or the vertical direction (Z-axis direction).

[0083] In an embodiment, the first core layer 111 may include a first lower surface BS1 and a first upper surface US1. The first lower surface BS1 and the first upper surface US1 may be outer surfaces of the first core layer 111 that face each other in the stacking direction or vertical direction. Furthermore, the first lower surface BS1 and the first upper surface US1 may be opposite each other in the vertical direction within the first core layer 111. Additionally, in each core layer, the upper and lower surfaces may be outer surfaces that are maximally spaced apart along the stacking direction or vertical direction.

[0084] The second core layer 112 may include a second lower surface BS2 and a second upper surface US2. The second lower surface BS2 and the second upper surface US2 may be the outer surfaces of the second core layer 112 that face each other in the stacking direction or the vertical direction. The second lower surface BS2 and the second upper surface US2 may be opposite each other in the vertical direction in the second core layer 112.

[0085] In this embodiment, based on the stacking direction (Z-axis direction), the first core layer 111 may be located below the second core layer 112. The first core layer 111 and the second core layer 112 are spaced apart, but can be connected to each other via a wiring layer 123. For example, the first core layer 111, the wiring layer 123, and the second core layer 112 may be combined. Furthermore, the first upper surface US1 of the first core layer 111 and the second lower surface BS2 of the second core layer 112 may be spaced apart. The wiring layer 123 may be an "intermediate insulating layer" disposed between the first core layer 111 and the second core layer 112.

[0086] The first core layer 111 and the second core layer 112 can be “glass layers” as described above, and can be made of glass material.

[0087] In this embodiment, core layer 110 may include vias 111h and 112h. First core layer 111 may include first via 111h. Second core layer 112 may include second via 112h.

[0088] The first via 111h and the second via 112h can have the following structure: the diameter or width increases from the center toward the upper and lower surfaces in each of the first core layer 111 and the second core layer 112. For example, the diameter of the first via 111h can increase from the center of the first core layer 111 toward the first upper surface US1 and the first lower surface BS1. Therefore, the inner surface of the first via 111h can be inclined relative to the first upper surface US1 and the first lower surface BS1. This can also be applied to the second core layer 112.

[0089] The first via 111h may overlap with the second via 112h in the stacking direction. In an embodiment, the first via 111h may at least partially overlap with the second via 112h in the stacking direction. Furthermore, as a variation described below, the first via 111h may not partially overlap with the second via 112h in the stacking direction.

[0090] Furthermore, the diameter of the first via 111h can increase from its central portion toward the first lower surface BS1. The diameter of the second via 112h can increase from its central portion toward the second upper surface US2. That is, in the embodiment, the diameters of adjacent vias can increase toward the surfaces that contact each other.

[0091] The insulating layer 120 may surround at least a portion of the core layer 110. For example, the insulating layer 120 may be located outside the core layer 110. Therefore, damage to the core layer 110 can be prevented. Furthermore, the insulating layer 120 may be located on the upper or lower portion of the core layer 110. In embodiments, the insulating layer 120 may contact the outer surface of the core layer 110, or its upper or lower surface.

[0092] In this embodiment, the insulating layer 120 may be composed of multiple insulating layers. These multiple insulating layers may be made of the same insulating material or different insulating materials.

[0093] In an embodiment, the insulating layer 120 may include a first insulating layer 121 and a second insulating layer 122 disposed on the upper or lower part of the core layer 110. Furthermore, the insulating layer 120 may include a wiring layer 123, a first sub-insulating layer 124, and a second sub-insulating layer 125.

[0094] The first insulating layer 121 and the second insulating layer 122 can be located on the lower and upper parts of the core layer 110, respectively. For example, the second insulating layer 122 can be located on the upper part of the core layer 110, and the first insulating layer 121 can be located on the lower part of the core layer 110. For example, the first insulating layer 121 can be in contact with the lower surface of the core layer 110, and the second insulating layer 122 can be in contact with the upper surface of the core layer 110.

[0095] The wiring layer 123 can be located between the first core layer 111 and the second core layer 112.

[0096] Furthermore, the sub-insulating layer can be located within the first via 111h of the first core layer 111 or within the second via 112h of the second core layer 112. The first sub-insulating layer 124 can be located within the first via 111h of the first core layer 111. The second sub-insulating layer 125 can be located within the second via 112h of the second core layer 112.

[0097] As described above, depending on the structure or design of the circuit board 100, the insulating layer 120 may be composed of multiple layers. For example, the first insulating layer 121 and the second insulating layer 122 may be composed of multiple insulating layers.

[0098] Furthermore, multiple circuit patterns, vias, via electrodes, etc., can be located in the insulating layer 120. For example, the vias in the insulating layer 120 can also be connected to the vias in the core layer 110. In other words, the via electrodes disposed in the vias of the insulating layer 120 can be electrically connected to the via electrodes disposed in the vias of the core layer 110.

[0099] The insulating layer 120 may comprise a thermosetting resin such as epoxy resin, or a thermoplastic resin such as polyimide. Furthermore, the insulating layer 120 may also contain reinforcing materials in the resin. Reinforcing materials may be, for example, fabric reinforcement materials, inorganic fillers, etc. The fabric reinforcement material may be glass fiber, and the glass fiber may be impregnated in the resin to form a prepreg (PPG).

[0100] For example, the insulating layer 120 can be any insulating resin such as a thermosetting resin and / or a photocurable resin. As a thermosetting resin, Ajinomoto Composite Film (ABF), a product of Ajinomoto Corporation, can be used, and materials such as prepreg (PPG) including glass fibers can be used. As a photocurable resin, any insulating resin such as photoimaging dielectric (PID) resin can be used. Any of the aforementioned insulating resins can be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and can include inorganic fillers such as silica. When the insulating resin is used as a core, it can include reinforcing materials such as glass fibers, aramid fibers, etc. For example, the insulating layer 120 can use Ajinomoto Composite Film (ABF), a product of Ajinomoto Corporation, and FR-4, BT (bismaleimide triazine), PID (photoimaging dielectric resin), BT, etc. can be used. For example, the insulating layer 120 can include multiple layers composed of ABF.

[0101] The protective layer 130 may be located on the upper or lower part of the insulating layer 120. For example, the protective layer 130 may include a first protective layer 131 located on the upper part of the second insulating layer 122 and a second protective layer 132 located on the lower part of the second insulating layer 122.

[0102] The protective layer 130 serves to protect the pads from external moisture or contaminants, and to prevent short circuits during the bonding process between the semiconductor device and / or the motherboard and the circuit board, the protective layer 130 may be configured as a solder resist, for example. Specifically, the semiconductor device and / or motherboard, etc., have multiple terminals for connection to the circuit board. Furthermore, the multiple terminals can be arranged in a high density. Solder can be used, for example, when the multiple terminals are bonded to the pads of the circuit board. When using solder, solder short circuits can occur between the high-density terminals, and to address this short circuit problem, a solder resist with poor wettability to the solder can be used. Furthermore, the protective layer 130 can be made of a material that has insulating properties for electrical connections. The protective layer 130 may include resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic monomers, etc. Additionally, the third insulating layer (not shown) may include any one of a photosensitive solder resist layer, a cover film, and a polymer material.

[0103] Furthermore, the protective layer 130 located in the outer stacked area of ​​the circuit board may have an opening. Through this opening, it can be electrically connected to another semiconductor device, circuit board, etc.

[0104] For the aforementioned electrical connections, conductive members CB1 and CB2 can be located on the upper or lower part of the circuit board 100. The conductive member CB1 located on the upper part can perform an electrical connection between the semiconductor device SD and the electrode portion. Furthermore, the conductive member CB2 located on the lower part can perform an electrical connection with another substrate, etc.

[0105] In this embodiment, wiring or electrode portions may be provided for electrical connections between a motherboard or similar device and a chip (or semiconductor device SD, bare die). The electrode portions may include circuit patterns (or circuit pattern layers), pads, and via electrodes. Wiring may correspond to "electrode pattern," "pattern," "line," etc.

[0106] In the electrode section (not shown), the circuit pattern can be designed in various forms for signal and / or power transmission with semiconductor devices and is disposed within each stacked insulating layer 120. For example, the electrode section may include a through electrode TE. The through electrode TE may be located within a via TH that penetrates the core layer 110 and the insulating layer 120. The through electrode TE is described interchangeably with "via electrode TE".

[0107] Furthermore, in the electrode section, the via electrode is configured to penetrate a portion of each insulating layer for vertical connection between the circuit patterns disposed in each vertically stacked core layer and insulating layer. That is, the insulating layer may include vias (e.g., 110h) for disposing of the via electrode. And to optimize impedance or heat dissipation, the via electrode may have a wider width than the circuit pattern, but is not limited to this, and can be freely designed.

[0108] In the electrode section, pads can be disposed in each insulating layer. These pads can be electrically connected to circuit patterns. Furthermore, the pads can be electrically connected to semiconductor devices and / or the motherboard or substrate. Additionally, the pads can be electrically connected to via electrodes.

[0109] Specifically, among the pads, the outer pads can be bonded to semiconductor devices, substrates, boards, etc., using solder, leads, conductive adhesives, etc., and to address issues such as ensuring yield, they can be set to have a width greater than the width of the circuit pattern. However, they are not limited to this; depending on the technical limitations of the bonding process, they can have the same width as the circuit pattern.

[0110] Furthermore, the pads located on the inner side serve to connect the via electrode and the circuit pattern. When the via electrode is configured to have a width wider than the circuit pattern, in the via electrode manufacturing process—where the via electrode is positioned on each circuit pattern—pads with a width wider than the circuit pattern are provided for alignment accuracy. Therefore, each via electrode may have an upper surface coplanarly positioned with the lower surface of the upper pad that directly contacts the via electrode, and a lower surface coplanarly positioned with the upper surface of the lower pad that directly contacts the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, but should be understood to include concave or convex surfaces that may appear depending on various processes.

[0111] The semiconductor device SD can be mounted on the upper part of the circuit board 100. The semiconductor device SD can be a logic chip, a memory chip, etc. The logic chip can be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, the logic chip can be an AP including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller, or it can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc., or it can be a chipset including a specific combination of the above. The memory chip can be a stacked memory such as HBM. Furthermore, the memory chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), or flash memory. The semiconductor device SD can be electrically connected to the electrode portion through the aforementioned conductive member CB2.

[0112] Circuit boards can be functionally divided into a packaging substrate and an interposer. The packaging substrate serves to mount semiconductor devices and / or act as an interposer. Due to increasing data density, as the area of ​​the circuit board increases or the number of stacked insulating layers increases, the yield of the circuit board may decrease significantly. Therefore, to improve the yield of circuit boards with a high number of stacked layers, it is possible to improve the yield by separating them into an interposer and a packaging substrate. Furthermore, as the density of semiconductor device terminals increases, it may be difficult to achieve a packaging substrate with pads that correspond to the area of ​​the semiconductor device terminals. Therefore, it can be used as a buffer between the pad size of the packaging substrate and the fine pattern size of the semiconductor device terminals.

[0113] The aforementioned packaging substrate and interposer can be classified into cored substrates and coreless substrates according to the structure of the insulating layer. In an embodiment according to this disclosure, a circuit board having a core layer including glass is described.

[0114] Further reference Figure 3 The circuit board 100 according to an embodiment may include a ground plane GP. The ground plane GP can operate electrically as ground or earth. For example, the ground plane GP can be a "ground layer" or a "grounding layer". Furthermore, the ground plane GP can be made of a conductive material, such as metal. For example, the ground plane GP can be composed of circuit patterns of electrode portions, pads, etc. Therefore, the ground plane GP can be connected to an upper via electrode or circuit pattern, or a lower via electrode or circuit pattern. And in embodiments according to this disclosure, the ground plane can be disposed between multiple core layers.

[0115] A ground plane GP can be disposed between the first core layer 111 and the second core layer 112. For example, the ground plane GP can be disposed between the first lower surface BS1 of the first core layer 111 and the second upper surface US2 of the second core layer 112. Alternatively, the ground plane GP can be disposed between the first upper surface US1 of the first core layer 111 and the second lower surface BS2 of the second core layer 112. Thus, by forming a ground plane between multiple core layers, the thickness of the ground plane can be easily changed, and the electrical connection distance is reduced, thereby enabling easy power supply with relatively reduced or low resistance.

[0116] Furthermore, as described above, the wiring layer 123 can be disposed between the first core layer 111 and the second core layer 112. Therefore, the ground plane GP can at least partially contact the wiring layer 123, or can be disposed within the wiring layer 123.

[0117] In this embodiment, the ground plane GP can be disposed on the wiring layer 123. Therefore, the ground plane GP can be disposed between the first lower surface BS1 of the first core layer 111 and the second upper surface US2 of the second core layer 112. Thus, the warpage of the circuit board can be improved by the ground plane GP. Furthermore, this configuration minimizes the electrical connection distance from the top or bottom of the circuit board to the ground plane. As a result, a circuit board with reduced crosstalk can be provided.

[0118] Furthermore, the ground plane GP can be located at the center of the wiring layer 123. For example, the ground plane GP can be located at the bisection point in the vertical direction of the wiring layer 123.

[0119] Furthermore, the distance d1 between the ground plane GP and the first upper surface US1 and the distance d2 between the ground plane GP and the second lower surface BS2 can be equal. These distances can correspond to the minimum distance in the vertical direction. With this configuration, the ground plane GP is located at the center of the circuit board or core layer 110, thereby further improving the warpage reduction effect. In addition, the length, i.e., the thickness, of the ground plane GP in the stacking direction can be easily changed. As a result, resistance reduction can be achieved more easily.

[0120] Further reference Figure 4 As another example, the ground plane GP can be disposed adjacent to either the first upper surface US1 or the second lower surface BS2. For example, the ground plane GP can be disposed adjacent to the first upper surface US1. Therefore, the lower surface of the ground plane GP can contact the first upper surface US1. The lower surface of the ground plane GP can be coplanar with the first upper surface US1.

[0121] Furthermore, the distance between the ground plane GP and the first upper surface US1 can be different from the distance d3 between the ground plane GP and the second lower surface BS2. For example, the distance between the ground plane GP and the first upper surface US1 can be smaller than the distance d3 between the ground plane GP and the second lower surface BS2. As another example, the ground plane GP can be positioned adjacent to the second lower surface BS2 instead of the first upper surface US1. Therefore, the distance between the ground plane GP and the first upper surface US1 can be greater than the distance d3 between the ground plane GP and the second lower surface BS2. With this configuration, warping caused by differences in the coefficient of thermal expansion can be reduced by adjusting the position of the ground plane GP on the circuit board.

[0122] In addition, further reference Figure 5 In another example, the ground plane GP may contact the first upper surface US1 and be embedded in the first core layer 111. For example, the first core layer 111 may include a first grounding groove 111g. And, the first grounding groove 111g may be disposed on the first upper surface US1.

[0123] Furthermore, the distance d4 between the second lower surface BS2 and the ground plane GP can be equal to the length or thickness d5 of the wiring layer 123 in the stacking direction. Therefore, the lower surface of the wiring layer 123 is flat, thereby providing structural reliability and allowing easy connection to the ground plane GP without the need for additional holes.

[0124] Furthermore, as a variation, the distance d4 between the second lower surface BS2 and the ground plane GP can be less than the length or thickness d5 of the wiring layer 123 in the stacking direction.

[0125] In addition, refer to again Figure 2 In the circuit board according to the embodiment, the thickness T1 of the wiring layer 123 can be greater than the thickness T2 or T3 of at least one of the first insulating layer 121 and the second insulating layer 122. This configuration can further improve the warpage reduction effect.

[0126] Furthermore, the circuit board may include a through-hole TH penetrating the first insulating layer 121, the first core layer 111, the wiring layer 123, the second core layer 112, and the second insulating layer 122, and a through electrode TE disposed in the through-hole TH. The electrode portion may include the through electrode TE.

[0127] The via TH can penetrate the first sub-insulating layer 124 disposed within the first via 111h of the first core layer 111. For example, the first sub-insulating layer 124 can be disposed on the inner side of the first via 111h. Furthermore, the through electrode TE can be disposed inside the first sub-insulating layer 124. Therefore, the first sub-insulating layer 124 and the first core layer 111 (first via) can be disposed sequentially outside the through electrode TE within the via TH.

[0128] Furthermore, the via TH can penetrate the second sub-insulating layer 125 disposed within the second via 112h of the second core layer 112. The second sub-insulating layer 125 can be disposed on the inner side of the second via 112h. And, the through electrode TE can be disposed inside the second sub-insulating layer 125. Therefore, the second sub-insulating layer 125 and the second core layer 112 (second via) can be sequentially disposed outside the through electrode TE within the via TH.

[0129] The width W1 or diameter of the via TH can increase or decrease along the stacking direction. For example, the width W1 of the via TH can increase along the stacking direction. In an embodiment, the width of the via TH within the first via 111h or the first sub-insulating layer 124 of the first core layer 111 can be smaller than its width within the second via 112h or the second sub-insulating layer 125 of the second core layer 112. Alternatively, the diameter of the via TH can be minimum in the first insulating layer 121 and maximum in the second insulating layer 122. This description can also be applied to the through electrode TE. That is, the width or diameter of the through electrode TE can increase or decrease along the stacking direction. In an embodiment, the width or diameter of the through electrode TE can increase along the stacking direction (or from the first core layer toward the second core layer).

[0130] Furthermore, according to the embodiment, the through-hole TH or through electrode TE can be disposed at the central axis of the first via 111h or the second via 112h. Specifically, the central axis of the through-hole TH or through electrode TE can overlap with the central axis of the first via 111h or the second via 112h. Therefore, the through-hole TH or through electrode TE can have the same vertical spacing as the first via 111h (or the second via). This makes it easier to form the through-holes and through electrodes on the circuit board. Furthermore, the symmetrical structure improves the structural reliability of the circuit board.

[0131] Therefore, within the first via 111h of the first core layer 111, the gap 2 between the through electrode TE and the first via 111h can be smaller than the gap 1 between the through electrode TE and the second via 112h of the second core layer 112. For example, the minimum gap between the through electrode TE and the first via 111h can be smaller than the minimum gap between the through electrode TE and the second via 112h.

[0132] The through electrode TE can penetrate through the wiring layer 123. As described above, a ground plane or other wiring in another insulating layer can be provided in the wiring layer 123 adjacent to the through electrode TE. For example, when the through electrode TE contacts the ground plane or wiring, the ground plane or wiring can be exposed by the through-hole of the through electrode TE. Alternatively, the through electrode TE can contact the wiring and can penetrate into a portion of the layer (such as wiring layer 123) where the wiring exists.

[0133] Furthermore, according to the embodiment, the first sub-insulating layer 124 and the second sub-insulating layer 125 may have different areas or region sizes along the stacking direction. For example, the areas may vary along the stacking direction.

[0134] For example, using a plane perpendicular to the vertical direction as a reference, the area or region size of the first sub-insulating layer 124 can be reduced along the stacking direction within the first via 111h. Furthermore, using a plane perpendicular to the vertical direction as a reference, the area or region size of the second sub-insulating layer 125 can be reduced along the stacking direction within the second via 112h. Additionally, using a plane perpendicular to the vertical direction as a reference, the area of ​​the first sub-insulating layer 124 can be larger than the area of ​​the second sub-insulating layer 125.

[0135] Figure 6 This is a cross-sectional view of a circuit board according to a second embodiment of the present disclosure. Figure 7 yes Figure 6 Enlarged view of K2, Figure 8 yes Figure 7 Another example, Figure 9 yes Figure 7 Another example.

[0136] Reference Figure 6 and Figure 7 According to the second embodiment, the circuit board 100A may include a core layer 110, an insulating layer 120, a protective layer 130, and a through electrode TE. Furthermore, the circuit board 100 according to the embodiment may include a semiconductor device SD and conductive members CB1 and CB2 disposed on one side (e.g., the upper part). Additionally, the circuit board 100A may include a via TH penetrating the first insulating layer 121, the first core layer 111, the wiring layer 123, the second core layer 112, and the second insulating layer 122, and a through electrode TE disposed in the via TH. The electrode portion may include the through electrode TE. In the following text, the above description applies in addition to the content otherwise described.

[0137] According to this embodiment, multiple ground planes (GPs) may exist. For example, the ground planes (GPs) may include a first ground plane (GP1) and a second ground plane (GP2) that are spaced apart from each other.

[0138] The first ground plane GP1 and the second ground plane GP2 can be disposed adjacent to the first upper surface US1 and the second lower surface BS2, respectively. The first ground plane GP1 can be disposed adjacent to the first upper surface US1 but not the second lower surface BS2. The second ground plane GP2 can be disposed adjacent to the second lower surface BS2 but not the first upper surface US1. Therefore, one surface of the ground plane GP can be adjacent to either the first upper surface US1 or the second lower surface BS2. For example, the lower surface of the first ground plane GP1 can be adjacent to the first upper surface US1. And the upper surface of the second ground plane GP2 can be adjacent to the second lower surface BS2.

[0139] The first ground plane GP1 and the second ground plane GP2 can be disposed within the wiring layer 123. The distance between the first ground plane GP1 and the second ground plane GP2 can be less than the thickness or length of the wiring layer 123 in the stacking direction.

[0140] The first ground plane GP1 and the second ground plane GP2 may at least partially not overlap in the stacking direction or vertical direction. That is, the first ground plane GP1 and the second ground plane GP2 may be staggered from each other. This configuration prevents stress concentration in one area. Furthermore, even when the first ground plane GP1 and the second ground plane GP2 are electrically connected to the upper or lower electrode (or external device), the physical length of the electrical connection is reduced, thereby reducing crosstalk.

[0141] Further reference Figure 8 In another example, either the first ground plane GP1 or the second ground plane GP2 can be positioned closer to the core layer than the other. Furthermore, either the first ground plane GP1 or the second ground plane GP2 can contact an adjacent core layer. For example, the first ground plane GP1 can contact the first upper surface US1. And the second ground plane GP2 is positioned above the first ground plane GP1 and can be positioned adjacent to the second lower surface BS2 instead of the first upper surface US1. For example, the distance d6 between the second ground plane GP2 and the second lower surface BS2 can be less than the distance d6' between the second ground plane GP2 and the first upper surface US1.

[0142] Furthermore, the distance between the first ground plane GP1 and the first upper surface US1 can be different from the distance d6 between the second ground plane GP2 and the second lower surface BS2. For example, the distance between the first ground plane GP1 and the first upper surface US1 can be smaller than the distance d6 between the second ground plane GP2 and the second lower surface BS2. With this configuration, warping caused by differences in the coefficient of thermal expansion can be reduced by adjusting the position of the ground plane GP in the circuit board.

[0143] As an additional example of use, the first ground plane GP1 can contact the first upper surface US1, and the second ground plane GP2 can contact the second lower surface BS2. As a result, structural reliability can be improved through a symmetrical structure.

[0144] In addition, further reference Figure 9 In a circuit board according to another example, at least one of a first ground plane GP1 and a second ground plane GP2 can be embedded in a core layer. In an embodiment, the first ground plane GP1 can be embedded in a first core layer 111. Furthermore, the second ground plane GP20 can be located at the center of the wiring layer 123. With this configuration, a ground plane is located at the center of the circuit board or core layer 110, thereby further improving the warpage reduction effect.

[0145] For example, the second ground plane GP2 can be located at the center within the wiring layer 123. The distance d7 between the second ground plane GP2 and the second lower surface BS2 can be equal to the distance d8 between the second ground plane GP2 and the first upper surface US1. Furthermore, the length d10 of the wiring layer 123 in the stacking direction can be equal to the distance between the first ground plane GP1 and the second lower surface BS2.

[0146] Figures 10 to 15 This is a view used to describe a method of manufacturing a circuit board according to an embodiment of the present disclosure.

[0147] For the same components described above, the same reference numerals are assigned, repeated descriptions of the same components are omitted, and only the differences are described.

[0148] Furthermore, the circuit board according to the embodiment can correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board can be formed from unit circuit boards. The mother circuit board can be separated into multiple unit circuit boards along a cutting line.

[0149] To form such a master circuit board, a glass layer can be first laid. The fabrication of the unit circuit board will be described below.

[0150] Reference Figure 10 and Figure 11 In the circuit board manufacturing method according to the embodiment, a core layer made of glass can be prepared (S510). The core layer may correspond to the first core layer or the second core layer described above. Hereinafter, it will be described based on the first core layer 111.

[0151] Furthermore, vias can be formed in the core layer. In an embodiment, a first via 111h can be formed in the first core layer 111 (S515). The first via 111h can be formed by etching the two surfaces of the first core layer 111. For example, the first via 111h can be formed by photolithography using a photomask, laser methods, etc.

[0152] Reference Figure 12 An insulating layer can be applied to the first core layer 111 (S520). For example, a first insulating layer 121 can be disposed on the lower part of the first core layer 111, a first sub-insulating layer 124 can be disposed within the first via 111h, and a portion of the wiring layer 123 can be disposed on the upper part of the first core layer 111.

[0153] Reference Figure 13The first core layer 111 coated with an insulating layer can be bonded to the second core layer 112 (S525). Furthermore, before bonding, a ground plane can be formed in the insulating layers of the first core layer 111 and the second core layer 112. The ground plane is a ground electrode and can be formed in a patterned groove or via by etching. The ground plane can be formed, like an electrode portion, by plating or the like. Furthermore, the ground plane can be formed in a portion of a wiring layer disposed on the first core layer 111 side or in a portion of a wiring layer disposed on the second core layer 112 side.

[0154] The second core layer 112 can be disposed on the upper part of the first core layer 111. Therefore, the first insulating layer 121, the first core layer 111 (first sub-insulating layer), the wiring layer 123, the second core layer 112 (second sub-insulating layer), and the second insulating layer 122 can be disposed sequentially in the stacking direction.

[0155] Further reference Figure 14 Through-hole TH (S530) can be formed in the core layer and the insulating layer. Through-hole TH can penetrate the first insulating layer 121, the first sub-insulating layer 124 (first core layer), the wiring layer 123, the second sub-insulating layer 125 (second core layer) and the second insulating layer 122.

[0156] A via (TH) can be formed by etching a core layer and an insulating layer. For example, a via (TH) can be formed by applying a photoresist (PR) (or resist layer) as a mask on a surface (e.g., the upper surface) and performing exposure by irradiation with light (e.g., ultraviolet (UV) light) (S525). Alternatively, etching can be selectively performed using photoresist, a chromium mask, an etch-resistant film, etc. Furthermore, etching can be performed to remove the mask, etc. The mask can be removed by etching.

[0157] Reference Figure 15 A through electrode TE can be formed in the via TH (S535). For example, a seed layer can be formed in the via TH. Furthermore, plating can be performed to form the through electrode TE. The through electrode TE can be disposed within the via TH. That is, the through electrode TE also penetrates the first insulating layer 121, the first sub-insulating layer 124 (first core layer), the wiring layer 123, the second sub-insulating layer 125 (second core layer), and the second insulating layer 122.

[0158] Using the method described above, the core layer of the circuit board according to the embodiment can be manufactured. Thereafter, an insulating layer can be applied to the upper or lower portion of the core layer, and electrode portions can be formed through patterned grooves or vias. In the electrode portions, circuit patterns can be formed using printed circuit board manufacturing processes such as additive, subtractive, modified semi-additive (MSAP), and semi-additive (SAP) processes.

[0159] In addition, a protective layer can be formed on the upper or lower part of the insulating layer. Furthermore, an opening region for conductive components can be formed in the protective layer.

[0160] Figure 16 This is a cross-sectional view of a circuit board according to a third embodiment of the present disclosure. Figure 17 yes Figure 16 A magnified view of K3 in the image, and Figure 18 yes Figure 17 A variation of the above.

[0161] Reference Figure 16 and Figure 17 According to the third embodiment, the circuit board 100B may include a core layer 110, an insulating layer 120, a protective layer 130, and a through electrode TE. Furthermore, the circuit board 100 according to the embodiment may include a semiconductor device SD and conductive members CB1 and CB2 disposed on one side (e.g., the upper part). Additionally, the circuit board 100A may include a via TH penetrating the first insulating layer 121, the first core layer 111, the wiring layer 123, the second core layer 112, and the second insulating layer 122, and a through electrode TE disposed in the via TH. The electrode portion may include the through electrode TE. In the following text, the above description applies in addition to the content described below. Furthermore, regarding the ground plane, all content described in the various embodiments may be applied.

[0162] In an embodiment, the first central axis AX1 of the first via 111h may extend parallel to the stacking direction. Furthermore, the first central axis AX1 may be an axis that bisects the first via 111h in the horizontal direction. For example, the first vias 111h may have the same diameter based on the first central axis AX1. In this case, the diameter may increase or decrease along the stacking direction. Additionally, the first vias 111h may form a symmetrical structure based on the first central axis AX1.

[0163] Furthermore, in this embodiment, the second central axis AX2 of the second via 112h can be positioned offset from the first central axis AX1 of the first via 111h. The second central axis AX2 of the second via 112h can be parallel to the stacking direction. Additionally, the second central axis AX2 can be an axis that bisects the second via 112h in the horizontal direction. For example, the second via 112h can have the same diameter as the second central axis AX2. In this case, the diameter can increase or decrease along the stacking direction. Furthermore, the second via 112h can form a symmetrical structure based on the second central axis AX2.

[0164] Furthermore, in this embodiment, the first central axis AX1 and the second central axis AX2 may overlap. Therefore, the first via 111h and the second via 112h may overlap in the vertical direction or in the stacking direction.

[0165] In an embodiment, the third central axis AX3 of the via TH and the through electrode TE may not overlap with the first central axis AX1 and the second central axis AX2. That is, the third central axis AX3 may be set to be offset from the first central axis AX1 and the second central axis AX2. In an embodiment, the third central axis AX3 may be an axis that bisects the via TH and the through electrode TE in the horizontal direction. For example, the via TH and the through electrode TE may have the same width or diameter based on the third central axis AX3. Furthermore, the via TH and the through electrode TE may form a symmetrical structure based on the third central axis AX3. In addition, in an embodiment, the width or diameter of the via TH and the through electrode TE may increase along the stacking direction.

[0166] Therefore, within the first via 111h and the second via 112h, the through hole TH and the through electrode TE can be set to be offset in the horizontal direction. Thus, in a plane perpendicular to the vertical direction, the width between the through hole TH (or through electrode) and the first via 111h can be different. In other words, in a plane perpendicular to the stacking direction, the distances gap5 and gap6 between the third central axis AX3 of the through hole TH (or through electrode) and the inner wall of the first via 111h can vary.

[0167] For example, the gap 5 between the through hole TH (or through electrode) and the first through hole 111h in the horizontal direction can be different from the gap 6 between the through hole TH (or through electrode) and the first through hole 111h in the opposite direction to the horizontal direction.

[0168] Furthermore, within the second via 111h and the second via 112h, the through-hole TH and the through electrode TE can be configured to be offset in the horizontal direction. Therefore, the width between the through-hole TH (or through electrode) and the second via 111h can be different in a plane perpendicular to the vertical direction. In other words, the distances gap3 and gap4 between the third central axis AX3 of the through-hole TH (or through electrode) and the inner wall of the second via 112h can vary in a plane perpendicular to the stacking direction. For example, the gap3 between the through-hole TH (or through electrode) and the second via 111h in the horizontal direction can be different from the gap4 between the through-hole TH (or through electrode) and the second via 111h in the direction opposite to the horizontal direction.

[0169] Furthermore, since the diameter of the through-hole TH (or through electrode) increases along the stacking direction, the widths of the first through-hole 111h and the second through-hole 112h can be different from each other.

[0170] Further reference Figure 18As a variation, the first core layer 111 and the second core layer 112 can be joined so that they are staggered from each other in the horizontal direction. For example, the first via 111h and the second via 112h can be partially non-overlapping in the stacking direction. That is, the first via 111h and the second via 112h can be set to be staggered in the stacking direction. Therefore, the first central axis AX1 and the second central axis AX2 can be non-overlapping in the vertical direction.

[0171] Therefore, the length from the first central axis AX1 to the edge of the first via 111h can be different. For example, the distance from the first central axis AX1 to the edge of the first via 111h adjacent to the second central axis AX2 can be the largest.

[0172] Furthermore, the length from the second central axis AX2 to the edge of the first via 111h can be different. For example, the distance from the second central axis AX2 to the edge of the first via 111h adjacent to the first central axis AX1 can be the largest.

[0173] Furthermore, the first core layer 111 and the second core layer 112 may have warping due to their bonding. For example, the first core layer 111 and the second core layer 112 may have concave or convex shapes in the stacking direction. Therefore, the misalignment will be biased at the center and the outer part of the circuit board or core layer. The center of the core layer 110 is the bisection point in a direction perpendicular to the vertical direction, and may correspond to the center of gravity, etc. The outer part of the core layer 110 is an edge region spaced apart from the center, and may correspond to the outermost corner region in a plane perpendicular to the vertical direction.

[0174] In this embodiment, the offset between the first central axis AX1 and the second central axis AX2 may differ at the central portion and the outer portion. For example, the first spacing distance at the central portion of the core layer 110 may differ from the second spacing distance at the outer portion.

[0175] Furthermore, the overlapping region (or area) in the stacking direction between the first via 111h and the first via 111h at the central portion of the core layer 110 may differ from the overlapping region (or area) in the stacking direction between the first via 111h and the first via 111h at the external portion. The overlapping region (or area) in the stacking direction between the first via 111h and the first via 111h at the central portion of the core layer 110 may be larger than the overlapping region (or area) in the stacking direction between the first via 111h and the first via 111h at the external portion.

[0176] Furthermore, the through electrode TE according to the embodiment may include a first electrode portion TE1 passing through the wiring layer 123, a second electrode portion TE3 passing through the first via 111h (or the first sub-insulating layer), and a second electrode portion TE2 passing through the second via 112h (or the second sub-insulating layer).

[0177] The first electrode section TE1, the second electrode section TE2, and the third electrode section TE3 can be connected to each other. That is, the first electrode section TE1, the second electrode section TE2, and the third electrode section TE3 can be in contact with each other. Furthermore, the first electrode section TE1, the second electrode section TE2, and the third electrode section TE3 can overlap in the stacking direction.

[0178] Furthermore, since the first via 111h and the second via 112h are offset in the stacking direction, and since the core layer 110 is warped, at least two of the first electrode portion TE1, the second electrode portion TE2 and the third electrode portion TE3 can be set to be offset in the stacking direction.

[0179] Figure 19 This is a plan view of a circuit board according to the fourth embodiment of the present disclosure. Figure 20 It is along Figure 19 The view intercepted by line AA' in the middle. Figure 21 yes Figure 20 A magnified view of K1 in the image, and Figure 22 yes Figure 19 A magnified view of K in the image.

[0180] Reference Figure 19 and Figure 20 The circuit board 100C according to the fourth embodiment may include a core layer 110, an insulating layer 120, a protective layer 130, and an electrode portion 140. Furthermore, the circuit board 100C according to the embodiment may include a semiconductor device SD and conductive members CB1 and CB2 disposed on one side portion (e.g., the upper portion). In addition to the descriptions below, the above descriptions are applicable to various embodiments.

[0181] The core layer 110 can be referred to as a "core layer" or a "substrate layer." Furthermore, the core layer 110 can be made of glass. The foregoing description applies to this.

[0182] The first insulating layer 121 and the second insulating layer 122 may be located on the upper and lower parts of the core layer 110, respectively. For example, the first insulating layer 121 may be located on the upper part of the core layer 110, and the second insulating layer 122 may be located on the lower part of the core layer 110. For example, the first insulating layer 121 may be in contact with the upper surface of the core layer 110, and the second insulating layer 122 may be in contact with the lower surface of the core layer 110.

[0183] As described above, the insulating layer 120 can be composed of multiple layers depending on the structure or design of the circuit board 100C. For example, the first insulating layer 121 can be composed of multiple insulating layers. And the second insulating layer 122 can be composed of multiple insulating layers.

[0184] Furthermore, multiple circuit patterns, vias, etc., can be located in the insulating layer 120. For example, the vias in the insulating layer 120 can also be connected to the vias in the core layer 110. In other words, the via electrodes disposed in the vias of the insulating layer 120 can be electrically connected to the via electrodes disposed in the vias of the core layer 110.

[0185] The protective layer 130 may be located on the upper or lower part of the insulating layer 120. The above description also applies to this. Furthermore, the above description also applies to the electrode portion 140.

[0186] The semiconductor device SD can be mounted on the upper part of the circuit board 100C.

[0187] Furthermore, the aforementioned packaging substrate and interposer can be classified into cored substrates and coreless substrates according to the structure of the insulating layer. In an embodiment according to this disclosure, a circuit board having a core layer including glass is described.

[0188] Further reference Figure 21 and Figure 22 According to the embodiment, the core layer 110 may include a first core layer 111 and a second core layer 112. The first core layer 111 may be located on the second core layer 112.

[0189] In an embodiment, the first core layer 111 may include a first lower surface BS1 and a first upper surface US1. The first lower surface BS1 and the first upper surface US1 may be the outer surfaces of the first core layer 111 that face each other in the stacking direction or the vertical direction.

[0190] The second core layer 112 may include a second lower surface BS2 and a second upper surface US2. The second lower surface BS2 and the second upper surface US2 may be the outer surfaces of the second core layer 112 that face each other in the stacking direction or vertical direction. In an embodiment, based on the stacking direction (Z-axis direction), the first core layer 111 may be located on top of the second core layer 112. Furthermore, the first core layer 111 may be in contact with the second core layer 112. That is, the first lower surface BS1 may be in contact with the second upper surface US2. For example, the first lower surface BS1 and the second upper surface US2 may be coplanar.

[0191] As described above, the first core layer 111 and the second core layer 112 can be "glass layers" and can be made of glass material.

[0192] In this embodiment, core layer 110 may include vias 111h and 112h. First core layer 111 may include first via 111h. Second core layer 112 may include second via 112h.

[0193] The first via 111h and the second via 112h can have the following structure: in each of the first core layer 111 and the second core layer 112, the diameter or width increases from the center toward the upper and lower surfaces. For example, the diameter of the first via 111h can increase within the first core layer 111 from the center toward the first upper surface US1 and the first lower surface BS1. Therefore, the inner surface of the first via 111h can be inclined relative to the first upper surface US1 and the first lower surface BS1. This can also be applied to the second core layer 112.

[0194] The first via 111h and the second via 112h may overlap in the stacking direction. In an embodiment, the first via 111h and the second via 112h may at least partially overlap in the stacking direction. Furthermore, the first via 111h and the second via 112h may partially not overlap in the stacking direction.

[0195] According to an embodiment, the first central axis AX1 of the first via 111h can be positioned offset from the second central axis AX2 of the second via 112h. As shown, the first central axis AX1 and the second central axis AX2 can be spaced apart from each other in the horizontal direction (X-axis direction). However, the direction in which the first central axis AX1 and the second central axis AX2 are spaced apart from each other is not limited to the horizontal direction, as long as it is a direction perpendicular to the stacking direction (including the X-axis direction).

[0196] The diameter of the first via 111h can increase from the central portion toward the first lower surface BS1. The diameter of the second via 112h can increase from the central portion toward the second upper surface US2. That is, in this embodiment, the diameters of adjacent vias can increase toward the surfaces that contact each other.

[0197] The first central axis AX1 of the first via 111h can be parallel to the stacking direction. Furthermore, the first central axis AX1 can be an axis that bisects the first via 111h in the horizontal direction. For example, the first vias 111h can have the same diameter based on the first central axis AX1. In this case, the diameter can increase or decrease along the stacking direction. Additionally, the first vias 111h can form a symmetrical structure based on the first central axis AX1.

[0198] Furthermore, the second central axis AX2 of the second via 112h can be parallel to the stacking direction. Additionally, the second central axis AX2 can be an axis that bisects the second via 112h in the horizontal direction. For example, the second via 112h can have the same diameter as the second central axis AX2. In this case, the diameter can increase or decrease along the stacking direction. Furthermore, the second via 112h can form a symmetrical structure based on the second central axis AX2.

[0199] Furthermore, in an embodiment, the second central axis AX2 of the second via 112h can be configured to be spaced apart from the first central axis AX1 of the first via 111h in the horizontal direction and positioned parallel to the stacking direction.

[0200] Furthermore, the length from the first central axis AX1 to the edge of the second via 112h can be different. For example, the distance from the first central axis AX1 to the edge of the second via 112h adjacent to the second central axis AX2 can be the largest.

[0201] Furthermore, the length from the second central axis AX2 to the edge of the first via 111h can be different. For example, the distance from the second central axis AX2 to the edge of the first via 111h adjacent to the first central axis AX1 can be the largest.

[0202] Therefore, the first central axis AX1 and the second central axis AX2 can be non-overlapping in the vertical direction. The first central axis AX1 and the second central axis AX2 can have a first spacing gap1 in the horizontal direction. This configuration can alleviate stress concentration on the via electrodes (e.g., 145, 146) of the insulating layer 120 disposed on the upper or lower part of each of the first core layer 111 and the second core layer 112. In other words, stress balancing becomes possible, thereby providing a circuit board with improved structural reliability.

[0203] Furthermore, the width or diameter of the first via 111h can be greater than the first horizontal spacing gap1 between the central axis AX1 and the second central axis AX2. For example, the minimum width (or diameter) r1 of the first via 111h can be greater than the first horizontal spacing gap1 between the central axis AX1 and the second central axis AX2.

[0204] In addition, the outer surfaces of the first core layer 111 and the second core layer 112 can also be positioned offset from each other.

[0205] As another example, as described below, a portion of the circuit board will overlap as it warps. Furthermore, the first core layer 111 and the second core layer 112 will warp due to their bonding. For example, the first core layer 111 and the second core layer 112 may have concave or convex shapes in the stacking direction. Therefore, the misalignment will be biased at the center and outer edges of the circuit board or core layer 110. The center of core layer 110 is the bisection point in a direction perpendicular to the vertical direction and may correspond to the center of gravity, etc. The outer edge of core layer 110 is an edge region spaced apart from the center and may correspond to the outermost corner region in a plane perpendicular to the vertical direction.

[0206] In this embodiment, the offset between the first central axis AX1 and the second central axis AX2 may differ at the central portion and the outer portion. For example, the first spacing distance at the central portion of the core layer 110 may differ from the second spacing distance at the outer portion.

[0207] Furthermore, the overlap region (or area) in the stacking direction between the first via 111h and the second via 112h at the central portion of the core layer 110 may differ from the overlap region (or area) in the stacking direction between the first via 111h and the second via 112h at the external portion. The overlap region (or area) in the stacking direction between the first via 111h and the second via 112h at the central portion of the core layer 110 may be larger than the overlap region (or area) in the stacking direction between the first via 111h and the second via 112h at the external portion.

[0208] In addition, the electrode section 140 may include a first via electrode 141, a second via electrode 142, upper pads 143 and 147, lower pads 144 and 148, a third via electrode 145, and a fourth via electrode 146.

[0209] A first via electrode 141 can be disposed in a first via 111h. A second via electrode 142 can be disposed in a second via 112h. The first via electrode 141 and the second via electrode 142 can be in contact with each other. Therefore, the first via electrode 141 and the second via electrode 142 can be connected to each other.

[0210] Upper pads 143 and 147 can be located on the first core layer 111 or the first insulating layer 121. Lower pads 144 and 148 can be located on the lower part of the second core layer 112 or the lower part of the second insulating layer 122. For example, upper pad 143 can be located on the first upper surface US1 of the first core layer 111. Furthermore, upper pad 143 can contact and connect to the first via electrode 141. Additionally, upper pad 143 can contact and connect to the third via electrode 145. Furthermore, upper pad 9147 can contact and connect to the third via electrode 145. Furthermore, lower pad 144 can be located on the lower part of the second lower surface BS2 of the second core layer 112. Furthermore, lower pad 144 can contact and connect to the second via electrode 142. Furthermore, lower pad 144 can contact and connect to the fourth via electrode 146.

[0211] A third via electrode 145 may be disposed in a third via 121h of the first insulating layer 121. The third via 121h may be positioned parallel to the first via 111h. The first via 111h and the third via 121h may at least partially overlap in the stacking direction. Furthermore, the third via 121h may have a central axis corresponding to the first central axis AX1 of the first via 111h. For example, the third via 121h may have a central axis overlapping the first central axis AX1 of the first via 111h.

[0212] A fourth via electrode 146 may be disposed in a fourth via 122h of the second insulating layer 122. The fourth via 122h may be positioned parallel to the second via 112h. For example, the fourth via 122h and the second via 112h may at least partially overlap in the stacking direction. Furthermore, the central axis of the fourth via 122h may correspond to the second central axis AX2 of the second via 112h. For example, the fourth via 122h may have a central axis that overlaps with the second central axis AX2 of the second via 112h.

[0213] Figure 23 This is a cross-sectional view of a circuit board according to a fifth embodiment of the present disclosure, and Figure 24 yes Figure 23 A magnified view of K2 in the image.

[0214] Reference Figure 23 and Figure 24 According to the fifth embodiment, the circuit board 100D may include a core layer 110, an insulating layer 120, a protective layer 130, and an electrode portion 140. Furthermore, the circuit board 100D according to the embodiment may include a semiconductor device SD and conductive members CB1 and CB2 disposed on one side portion (e.g., the upper portion). In addition to the descriptions below, the above descriptions are equally applicable.

[0215] According to an embodiment, patterned grooves can be formed on the surfaces where the first core layer 111 and the second core layer 112 contact. In an embodiment, the first patterned groove 111g can be disposed on the first lower surface BS1 of the first core layer 111. And the second patterned groove 112g can be disposed on the second upper surface US2 of the second core layer 112.

[0216] The first patterned groove 111g can be embedded in the first core layer 111. That is, the first patterned groove 111g can be embedded in the first lower surface BS1 of the first core layer 111. And, the second patterned groove 112g can be embedded in the second core layer 112. That is, the second patterned groove 112g can be embedded in the second upper surface US2 of the second core layer 112.

[0217] The first pattern groove 111g and the second pattern groove 112g can be arranged adjacent to each other. In an embodiment, the first pattern groove 111g and the second pattern groove 112g can be arranged facing each other. Furthermore, the first pattern groove 111g and the second pattern groove 112g can overlap each other in the optical axis direction. The first pattern groove 111g and the second pattern groove 112g can at least partially overlap in the optical axis direction.

[0218] The first pattern electrode 141a can be disposed in the first pattern groove 111g. And the second pattern electrode 142a can be disposed in the second pattern groove 112g.

[0219] Furthermore, the first pattern groove 111g and the second pattern groove 112g can be configured to be partially offset in the optical axis direction. In other words, the first pattern groove 111g and the second pattern groove 112g can be partially non-overlapping in the optical axis direction or the vertical direction.

[0220] The third central axis AX3 of the first pattern groove 111g can be set to be offset from the fourth central axis AX4 of the second pattern groove 112g. The third central axis AX3 can be an axis that bisects the first pattern groove 111g in the horizontal direction. For example, the first pattern groove 111g can be symmetrical about the third central axis AX3. Furthermore, the fourth central axis AX4 can be an axis that bisects the second pattern groove 112g in the horizontal direction. The second pattern groove 112g can be symmetrical about the fourth central axis AX4.

[0221] Furthermore, the first patterned groove 111g can be configured to be offset from the second patterned groove 112g in one direction. That is, the spacing direction and the second spacing distance gap2 between the third central axis AX3 of the first patterned groove 111g and the fourth central axis AX4 of the second patterned groove 112g can correspond to the spacing direction and spacing distance between the first central axis AX1 of the first via 111h and the second central axis AX2 of the second via 112h. For example, the spacing direction and spacing distance between the third central axis AX3 of the first patterned groove 111g and the fourth central axis AX4 of the second patterned groove 112g can be equal to the spacing direction and spacing distance between the first central axis AX1 of the first via 111h and the second central axis AX2 of the second via 112h.

[0222] The second horizontal spacing gap2 between the third central axis AX3 and the fourth central axis AX4 can be less than the diameter of the first via and the second via or the width of the first pattern electrode 141a (or the second pattern electrode 141b).

[0223] Furthermore, the minimum length dw1 between the edge of the first via 111h and the edge of the second via 112h can correspond to the minimum length dw2 between the edge of the first pattern groove 111g and the edge of the second pattern groove 112g. For example, the minimum length dw1 between the edge of the first via 111h and the edge of the second via 112h can be equal to the minimum length dw2 between the edge of the first pattern groove 111g and the edge of the second pattern groove 112g.

[0224] Furthermore, the patterned groove according to the embodiment (e.g., a first patterned groove and a second patterned groove) may include a side surface SS, a lower surface LS, and a connecting surface CS. The connecting surface CS may be disposed between the side surface SS and the lower surface LS to connect the side surface SS and the lower surface LS. This can also be applied to the first patterned groove 111g and the second patterned groove 112g. Hereinafter, the description will be based on the second patterned groove 112g.

[0225] The second patterned groove 112g may include a side surface SS, a lower surface LS, and a connecting surface CS. The connecting surface CS may contact the side surface SS at one corner. Furthermore, the connecting surface CS may contact the lower surface LS at another corner.

[0226] In this case, the connecting surface CS can have curvature. That is, the side surface SS and the bottom surface LS do not need to be in perpendicular contact with each other. Thus, because the connecting surface CS has curvature, voltage concentration effects can be suppressed. Therefore, the electrical reliability of the circuit board can be improved.

[0227] Figures 25 to 33 This is a view used to illustrate a method for manufacturing a core layer in a circuit board according to embodiments of the present disclosure. Figure 34 and Figure 35 This is a view showing the bonding of the first core layer and the second core layer in a circuit board according to a fifth embodiment of the present disclosure, and Figure 36 , Figure 37 and Figure 38 This is a view showing the bonding of a first core layer and a second core layer in a circuit board according to a fourth embodiment of the present disclosure.

[0228] For the same constituent elements mentioned above, the same reference numerals are assigned, repeated descriptions of the same constituent elements are omitted, and only the differences are described.

[0229] Furthermore, the circuit board according to the embodiment can correspond to a unit circuit board. That is, during the manufacturing process, the mother circuit board can be composed of unit circuit boards. The mother circuit board can be separated into multiple unit circuit boards along a cutting line.

[0230] To form such a master circuit board, a glass layer can be first laid. The following will explain the manufacturing process based on the unit circuit board.

[0231] Reference Figure 25 and Figure 26 In the method for manufacturing a core layer (or core substrate) in a circuit board according to the embodiment, firstly, a core layer 110 made of glass can be prepared (S510). The core layer 110 may correspond to the first core layer or the second core layer described above.

[0232] Furthermore, vias 110h can be formed in the core layer 110 (S515). The via 110h can correspond to the first and second vias described above. The via 110h can be formed by etching both surfaces of the core layer 110. For example, a via electrode can be formed in a via or through-hole in the glass layer. For example, the via 110h can be formed using photolithography with a photomask, laser methods, etc.

[0233] Reference Figure 27 A protective layer PF can be provided on one surface (e.g., the lower surface) of the core layer 110 (S515). For example, the protective layer PF can be applied to the lower surface of the core layer 110.

[0234] Reference Figure 28 Photoresist PR (or resist layer) can be applied to another surface (e.g., the upper surface) of the core layer 110 (S520). For example, photoresist PR can be applied to the upper surface of the core layer 110.

[0235] Reference Figure 29 After aligning the blocking portion or mask M on the core layer 110, exposure can be performed by irradiating with light (e.g., ultraviolet light (UV)) (S525). For example, the mask can be a photomask. The mask can be disposed on the upper surface of the core layer 110 for forming a pattern. Furthermore, the mask can be disposed on a via to overlap with the via in the stacking direction. Therefore, by exposure, exposure can be performed on areas other than those with vias. That is, areas with masks become non-exposed areas, while areas without masks can be exposed areas. For example, the patterned groove 110g described below is formed by selectively etching using photoresist, a chromium mask, an etch-resistant film, etc.

[0236] Reference Figure 30 Patterned grooves 110g can be formed by exposure (S530). Patterned grooves 110g can correspond to the first and second patterned grooves described above. Patterned grooves 110g can be formed on the upper surface of the core layer 110. Furthermore, patterned grooves 110g can be formed by exposure to embed them into the core layer 110.

[0237] Furthermore, etching can be performed to remove the mask (S535). The mask can be removed by etching.

[0238] Reference Figure 31The protective layer PF (S540) disposed on the core layer 110 can be removed.

[0239] Reference Figure 32 Electrode portions can be formed on the core layer 110 by plating (S545). For example, seed layers can be formed on the vias 110h, patterned grooves 110g, upper surface, and lower surface of the core layer 110. Furthermore, plating can be performed to form via electrodes, patterned electrodes, etc., on the core layer 110.

[0240] Reference Figure 33 The electrodes can be removed to expose both surfaces of the core layer (S550). For example, polishing can be performed to partially remove the electrode portion.

[0241] Through such polishing, an electrode portion 140 is formed on the core layer 110, and the electrode portion 140 may be, for example, a patterned electrode 141a.

[0242] Reference Figure 34 and Figure 35 It is possible to prepare for passage. Figures 25 to 33 Two core layers 110 are formed (S550). For example, a first core layer 111 and a second core layer 112 can be prepared. The two core layers 110 can be joined together. The first core layer 111 and the second core layer 112 can be joined together such that the first lower surface of the first core layer 111 and the second upper surface of the second core layer 112 are in contact with each other. For example, the first core layer 111 and the second core layer 112 can be joined together by a hot-pressing method or the like.

[0243] Using this method, the core layer in the circuit board according to the fifth embodiment described above can be manufactured. The core layer in the circuit board according to the fourth embodiment can be manufactured by performing... Figures 25 to 35 Excluding the above Figures 28 to 30 It is manufactured using subsequent processes.

[0244] Reference Figures 36 to 38 It is possible to prepare through Figures 25 to 35 Excluding the above Figures 28 to 30 The two core layers 110 are thus formed. Similarly, a first core layer 111 and a second core layer 112 can be prepared. Furthermore, the two core layers 110 can be bonded to each other. That is, the first core layer 111 and the second core layer 112 can be bonded to each other. Specifically, the first core layer 111 and the second core layer 112 can be bonded to each other such that the first lower surface of the first core layer 111 and the second upper surface of the second core layer 112 are in contact with each other. At this time, the first core layer 111 and the second core layer 112 can be bonded to each other by a hot-pressing method or the like. Therefore, the core layers in the circuit board according to the fourth embodiment can be manufactured.

[0245] Using the method described above, the core layer of the circuit board according to the embodiment can be manufactured. Thereafter, an insulating layer can be applied to the upper or lower portion of the core layer, and electrode portions can be formed through patterned grooves or vias. In the electrode portions, circuit patterns can be formed using printed circuit board manufacturing processes such as additive, subtractive, modified semi-additive (MSAP), and semi-additive (SAP).

[0246] In addition, a protective layer can be formed on the upper or lower part of the insulating layer. Furthermore, an opening region for conductive components can be formed in the protective layer.

[0247] Figure 39 This is a cross-sectional view of a circuit board according to the sixth embodiment of this disclosure, and Figure 40 yes Figure 39 A magnified view of K3.

[0248] Reference Figure 39 and Figure 40 According to the sixth embodiment, the circuit board 100E may include a core layer 110, an insulating layer 120, a protective layer 130, and an electrode portion 140. Furthermore, the circuit board 100E according to the embodiment may include a semiconductor device SD and conductive members CB1 and CB2 disposed on one side portion (e.g., the upper portion). In addition, the above description is equally applicable except as otherwise provided below.

[0249] The first core layer 111 may include a first groove 111b formed around the first via 111h in the first lower surface BS1. The second core layer 1112 may include a second groove 112b formed around the second via 112h in the second upper surface US2. The first groove 111b may be embedded in the first lower surface BS1. Furthermore, the second groove 112b may be embedded in the second upper surface US2.

[0250] Furthermore, the first groove 111b and the second groove 112b can be positioned facing each other. Additionally, the first groove 111b and the second groove 112b can at least partially overlap in the stacking direction. Similarly, the first groove 111b and the second groove 112b can be offset in the stacking direction. Therefore, the first groove 111b and the second groove 112b can partially not overlap in the stacking direction. Consequently, the central axis of the first groove 111b and the central axis of the second groove 112b can also be offset from each other.

[0251] Furthermore, the electrode portion 140 may include a first pad electrode 141b formed or disposed in the first trench 111b. Additionally, the electrode portion 140 may include a second pad electrode 142b formed or disposed in the second trench 112b. The first pad electrode 141b may contact the first via electrode 141. The second pad electrode 142b may contact the second via electrode 142. Furthermore, the first pad electrode 141b may overlap the first via electrode 141 in the stacking direction on the lower portion of the first via electrode 141. The second pad electrode 142b may overlap the second via electrode 142 in the stacking direction on the upper portion of the second via electrode 142.

[0252] Furthermore, with the first central axis AX1 as a reference, the length L1 to one side of the edge of the first pad electrode 141b and the length L2 to the other side in the horizontal direction can be different from each other. Similarly, with the second central axis AX2 as a reference, the length to one side of the edge of the first pad electrode 141b and the length to the other side can be different from each other.

[0253] Figure 41 It is a plan view of the circuit board based on the modified example.

[0254] Reference Figure 41 In the circuit board according to the modified example, as described above, the circuit board may include a first via 111h and a second via 112h.

[0255] At this time, at least one of the first via 111h and the second via 112h can be located at the center CE of the core layer in the circuit board. For example, among the plurality of vias 110, the first via 111h can be located adjacent to the center CE of the circuit board compared to the second via 112h. For example, based on a plane perpendicular to the stacking direction, the center CE of the circuit board can correspond to the intersection of the bisecting lines of the width La and the length Lb, or the center of gravity, etc. For example, the center CE of the circuit board can correspond to the intersection of the bisecting lines in the horizontal direction (X-axis direction) and the length direction (Y-axis direction).

[0256] In such a circuit board, among multiple vias, one via can be offset relative to another. That is, the central axis of the multiple first vias 111h can be misaligned or not aligned with the central axis of each individual via.

[0257] First, compared to the adjacent second via 112h, the first via 111h can be closest to the center CE of the circuit board or core layer. The first via 111h and the second via 112h that are adjacent to each other can have staggered central axes.

[0258] For example, the second center axis of the second via 112h may not overlap with the first center axis of the first via 111h in the vertical direction. That is, the second center axis of the second via 112h may be offset from the first center axis of the first via 111h in the vertical direction. Furthermore, compared to the second center axis of the second via 112h, the first center axis of the first via 111h may be located adjacent to the center CE of the circuit board or core layer.

[0259] Conversely, compared to the first central axis of the first via 111h, the second central axis of the second via 112h can be set adjacent to the center CE of the core layer.

[0260] In various semiconductor packages, the circuit board according to the above embodiments can be disposed in a portion of the area, or can correspond to a substrate.

[0261] Furthermore, when the circuit board with the features of this invention described above is used in IT devices such as smartphones, server computers, or TVs, or in home appliances, it can stably perform functions such as signal transmission or power supply. For example, when the circuit board with the features of this invention performs semiconductor packaging functions, it can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, or electrical open circuits at the terminals supplying power to the semiconductor chip. In addition, when it performs signal transmission functions, it can solve noise problems. Thus, the circuit board with the features of this invention described above enables IT devices or home appliances to maintain stable functionality, thereby enabling functional integration or technical interconnection between the entire product and the circuit board using this invention.

[0262] When a circuit board having the features of the present invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, or can safely protect the semiconductor chip controlling the transportation device from external influences, and solve problems such as leakage current, electrical short circuits between terminals, or electrical open circuits at terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the circuit board using the present invention can achieve functional integration or technical interconnection.

[0263] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment, but are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc., shown in the embodiments can be combined or modified by those skilled in the art for other embodiments. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0264] Although the above description focuses on embodiments, it is merely illustrative and not limiting, and those skilled in the art will recognize that various modifications and applications, not shown above, can be made without departing from the essential characteristics of these embodiments. For example, the constituent elements specifically shown in the embodiments can be modified and implemented. Furthermore, differences associated with such modifications and applications should be interpreted as including within the scope of the embodiments set forth in the appended claims.

Claims

1. A circuit board, comprising: First core layer; A second core layer disposed on the first core layer; A wiring layer disposed between the first core layer and the second core layer; as well as Via electrodes passing through the first core layer, the wiring layer, and the second core layer.

2. The circuit board according to claim 1, wherein, The wiring layer includes a ground plane disposed therein or in contact with it.

3. The circuit board according to claim 2, wherein, The first core layer includes a first upper surface and a first lower surface opposite to the first upper surface, and The second core layer includes a second upper surface and a second lower surface opposite to the second upper surface.

4. The circuit board according to claim 3, wherein, The ground plane is disposed between the first lower surface of the first core layer and the second upper surface of the second core layer.

5. The circuit board according to claim 3, wherein, The ground plane is located at the center of the wiring layer.

6. The circuit board according to claim 3, wherein, The distance between the ground plane and the first upper surface is equal to the distance between the ground plane and the second lower surface.

7. The circuit board according to claim 3, wherein, The ground plane is disposed adjacent to the first upper surface or the second lower surface.

8. The circuit board according to claim 3, wherein, The distance between the ground plane and the first upper surface is different from the distance between the ground plane and the second lower surface.

9. The circuit board according to claim 3, wherein, The ground plane contacts the first upper surface and is embedded in the first core layer.

10. The circuit board according to claim 3, wherein, The ground plane includes a first ground plane and a second ground plane spaced apart from the first ground plane.

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