Semiconductor device

Abstract

A semiconductor device that is easy to manufacture is provided. The semiconductor device includes a substrate, a transistor and a device separation layer formed on the substrate, first to fifth conductive layers, a first insulating layer, and first to fifth connectors. The transistor has a first low-resistance region, a second low-resistance region, and a portion of the first conductive layer. The third and fourth conductive layers are columnar structures perpendicular to the substrate. The first low-resistance region and the second conductive layer are connected via the first connector. The second low-resistance region and the third conductive layer are connected via the second connector. The fourth connector, the fifth connector, and the fourth conductive layer are connected to each other at locations overlapping the device separation layer. The first insulating layer has regions that contact the side surfaces and top surfaces of the third and fourth conductive layers. When viewed in plan view, the fifth conductive layer extends in a direction substantially parallel to the first conductive layer and has regions that contact the side surfaces and top surfaces of the first insulating layer.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the aforementioned technical fields. The technical field of the invention disclosed in this specification relates to an object, a method of operation, or a method of manufacturing. Furthermore, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices (including liquid crystal display devices), light-emitting devices, energy storage devices, imaging devices, storage devices, processing devices, signal processing devices, sensors, arithmetic devices (including processors), electronic devices, systems, methods of driving them, methods of manufacturing them, or methods of inspecting them. Background Technology

[0003] As shown in Non-Patent Document 1, research and development of memories utilizing ferroelectric materials is active. Furthermore, research on ferroelectric HfO2-type materials as next-generation ferroelectric memories (Non-Patent Document 2), and research on Hf... 0.5 Zr 0.5 Studies on the ferroelectricity of O2 thin films (Non-Patent Literature 3), studies on the ferroelectricity of HfO2 thin films (Non-Patent Literature 4), and the use of ferroelectric Hf 0.5 Zr 0.5 Research on hafnium oxide is also active, such as empirical evidence of the integration of O2 FeRAM (Ferroelectric Random Access Memory) and CMOS (Non-Patent Document 5).

[0004] Ferroelectric capacitors are an example of memory or circuit elements that utilize ferroelectric materials. A ferroelectric capacitor is a capacitor in which a ferroelectric insulating material is sandwiched between a pair of electrodes. Data can be retained by utilizing the hysteresis characteristics of the residual polarization of the ferroelectric insulating material. Therefore, data can be retained even without an applied voltage, potentially enabling the development of non-volatile RAM (FeRAM) using ferroelectric capacitors.

[0005] In particular, Patent Documents 1 and 2 disclose a circuit structure in which data can be retained on the ferroelectric capacitor even when the power supply voltage to the trigger circuit is cut off. Using this circuit structure, the data held by the trigger circuit can be backed up to the ferroelectric capacitor side, thereby stopping the trigger circuit.

[0006] [Preliminary Technology Documents] [Patent Literature] [Patent Document 1] Japanese Republishing of PCT Patent Application Publication No. 03-044953 [Patent Document 2] Japanese Patent Application Publication No. 2013-124290 [Non-patent literature] [Non-Patent Literature 1] T.S. Boescke, et al., “Ferroelectricity in hafnium oxide-thin films”, APL99, 2011 [Non-patent document 2] Zhen Fan, et al., "Ferroelectric HfO2-based materials for next-generation ferroelectric memories", JOURNAL OF ADVANCED DIELECTRICS, Vol.6, No.2, 2016 [Non-Patent Literature 3] Jun Okuno, et al., "SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf 0.5 Zr 0.5 O2”, VLSI 2020 [Non-Patent Literature 4] Akira Toriumi, "Ferroelectricity of HfO2 Thin Films", Japan Society of Applied Physics, Vol. 88, No. 9, 2019 [Non-Patent Literature 5] T. Francois, et al., “Demonstration of BEOL-compatible ferroelectric Hf 0.5 Zr 0.5 O2scaled FeRAM co-integrated with 130nm CMOS forembedded NVM applications”, IEDM 2019. Summary of the Invention

[0007] The technical problem that the invention aims to solve With advancements in miniaturization and integration, the miniaturization of the memory cells included in FeRAM has also progressed. Specifically, the miniaturization of ferroelectric capacitors has also been promoted. In this case, the area of ​​dielectric polarization occurring in the ferroelectric insulating layer sandwiched by a pair of electrodes of the ferroelectric capacitor is reduced, thus sometimes decreasing the amount of dielectric polarization. When the amount of dielectric polarization decreases, the threshold voltage distribution of data in the FeRAM also narrows, which may lead to the reading of erroneous data when performing read operations from the FeRAM. Conversely, in order to correctly read data from the FeRAM, it is necessary to ensure that the area of ​​the ferroelectric insulating layer sandwiched by a pair of electrodes of the ferroelectric capacitor is a certain amount.

[0008] Furthermore, unlike DRAM (Dynamic Random Access Memory), FeRAM requires board lines for writing to and reading from ferroelectric capacitors. These board lines are wirings connecting to the electrodes of the ferroelectric capacitors, and preferably extend in the same direction as the word lines. However, depending on the shape of the ferroelectric capacitor, the board lines may sometimes be longer because they extend in the same direction as the word lines. This can sometimes increase wiring resistance, thereby increasing the power consumption of the FeRAM.

[0009] One objective of this invention is to provide a semiconductor device with a reduced footprint. Another objective of this invention is to provide a semiconductor device capable of accurately reading data. Another objective of this invention is to provide a semiconductor device that is easy to manufacture. Another objective of this invention is to provide an electronic device including the aforementioned storage element. Another objective of this invention is to provide a novel storage element or a novel electronic device.

[0010] Note that the purpose of one aspect of the present invention is not limited to the objectives described above. The above objectives do not preclude the existence of other objectives. Furthermore, other objectives are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract objectives not mentioned above from the description, drawings, etc. Moreover, one aspect of the present invention achieves at least one of the above and other objectives. Therefore, one aspect of the present invention does not need to achieve all of the above and other objectives.

[0011] means of solving technical problems In view of the above-mentioned technical problems, one aspect of the present invention is a semiconductor device including a ferroelectric capacitor, the ferroelectric capacitor comprising: a lower conductive layer having a columnar shape along a direction perpendicular to or substantially perpendicular to a substrate; an insulating layer formed on the side and top surfaces of the conductive layer, which may be ferroelectric; and an upper conductive layer having a region opposite the lower conductive layer separated by the insulating layer. Furthermore, a plurality of lower conductive layers are disposed in a manner overlapping word lines along a direction parallel to or substantially parallel to the substrate. Additionally, by forming the upper conductive layer as a plate line along the direction in which the word lines extend, a plurality of ferroelectric capacitors can be arranged in the direction in which the word lines extend.

[0012] In addition, when the distance between adjacent ferroelectric capacitors is long, it is preferable to provide one or more ferroelectric capacitors with pseudo-patterns between the adjacent ferroelectric capacitors.

[0013] The following describes a typical structural example of one aspect of the present invention. (1) One aspect of the present invention is a semiconductor device comprising a substrate, a component separation layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a first insulating layer, a first plug, a second plug, a third plug, a fourth plug, and a fifth plug.

[0015] The substrate has a first low-resistance region serving as one of the source and drain of the transistor, a second low-resistance region serving as the other of the source and drain of the transistor, and a semiconductor region forming the channel of the transistor. Additionally, the transistor includes a portion of a first conductive layer serving as a gate. Furthermore, the first insulating layer comprises a material that may be ferroelectric. Additionally, in cross-section, the height of the third conductive layer is greater than the width of the third conductive layer, and the height of the fourth conductive layer is greater than the width of the fourth conductive layer.

[0016] The first plug has a region that contacts a first low-resistance region, and the second conductive layer has a region that contacts the first plug. Additionally, the second plug has a region that contacts a second low-resistance region, and the third plug has a region that contacts the second plug. Furthermore, in plan view, the third conductive layer is located in a region that contacts the top surface of the third plug and overlaps with the first conductive layer. The fourth plug has a region that contacts a component separation layer, and the fifth plug has a region that contacts the fourth plug. Furthermore, in plan view, the fourth conductive layer is located in a region that contacts the top surface of the fifth plug and overlaps with the component separation layer. The first insulating layer has regions that contact the sides and top surfaces of the third and fourth conductive layers, and in plan view, the fifth conductive layer has a region that overlaps with the first conductive layer and contacts the sides and top surface of the first insulating layer.

[0017] Furthermore, the first conductive layer and the fifth conductive layer are each disposed in a manner extending in a first direction, and the second conductive layer is disposed in a manner extending in a second direction. Additionally, the first direction and the second direction are substantially perpendicular. (2) In addition, in (1) above, one aspect of the present invention may employ a ferroelectric material comprising an oxide containing one or both of hafnium and zirconium. (3) Additionally, in (1) or (2) above, one embodiment of the present invention may also employ a structure including a second insulating layer. Furthermore, the transistor may also include a groove.

[0020] Preferably, when viewed from a planar perspective, the groove is located between the first low-resistance region and the second low-resistance region. Additionally, preferably, the second insulating layer is located in the region that contacts the side and bottom surfaces of the groove, and the semiconductor region is located in the region opposite the first conductive layer, separated by the second insulating layer. (4) In addition, one aspect of the present invention is an electronic device comprising any one of the semiconductor devices described in (1) to (3) above, and a housing.

[0022] Invention Effects By adopting the structure described in (1), the first conductive layer used as word lines and the fifth conductive layer used as board lines can overlap when viewed from a plane. That is, the word lines and board lines can extend in the same direction. In addition, since the board lines can be shortened, the wiring resistance can be reduced, thereby reducing the power consumption of the semiconductor device.

[0023] Furthermore, by providing a third and fourth conductive layer as a columnar lower electrode along the extension direction of the word line, ferroelectric capacitors can be arranged in a symmetrical configuration along the extension direction of the word line. Additionally, since the lower electrode is columnar, the area of ​​the ferroelectric insulating layer sandwiched by a pair of electrodes of the ferroelectric capacitor can be increased. This increases the threshold voltage distribution of data in the FeRAM, thereby enabling the accurate reading of logic "0" and "1".

[0024] Note that in the structure described in (1) above, the ferroelectric capacitor including the fourth conductive layer is formed as a pseudo-pattern.

[0025] Furthermore, in the structure described in (2) above, even a thin film of a few nm can exhibit ferroelectricity. Therefore, the manufacturing process of ferroelectric capacitors can be shortened.

[0026] According to one aspect of the present invention, a storage device with a reduced footprint can be provided. Additionally, according to one aspect of the present invention, a semiconductor device capable of accurately reading data can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device that is easy to manufacture can be provided. Moreover, according to one aspect of the present invention, an electronic device including the aforementioned storage element can be provided. Additionally, according to one aspect of the present invention, a novel storage element or a novel electronic device can be provided.

[0027] Note that the effects of one aspect of the present invention are not limited to those described above. The effects listed above do not preclude the existence of other effects. Furthermore, other effects are those not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description in the specification or drawings, etc. Moreover, one aspect of the present invention has at least one of the above-described effects and other effects. Therefore, one aspect of the present invention may sometimes not have the effects listed above.

[0028] Brief description of the attached figures Figure 1 This is a three-dimensional schematic diagram showing an example of the structure of a semiconductor device.

[0029] Figure 2A and Figure 2B This is a planar schematic diagram illustrating an example of the structure of a semiconductor device.

[0030] Figure 3 This is a planar schematic diagram illustrating an example of the structure of a semiconductor device.

[0031] Figure 4 This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0032] Figure 5 This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0033] Figure 6 This is a cross-sectional schematic diagram showing an example of the structure of a semiconductor device.

[0034] Figure 7 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0035] Figure 8 This is a diagram illustrating an example of the circuit structure of a memory cell array and a memory cell.

[0036] Figure 9A This is a graph illustrating an example of hysteresis characteristics. Figure 9B This is a timing diagram illustrating an example of a driving method for a memory cell.

[0037] Figure 10This is a schematic diagram illustrating the hierarchy of storage devices.

[0038] Figure 11A This is a block diagram illustrating an example of the structure of a semiconductor device. Figure 11B This is a three-dimensional schematic diagram showing an example of the structure of a semiconductor device.

[0039] Figures 12A to 12E This is a diagram illustrating an example of a storage device.

[0040] Figures 13A to 13D This is a diagram showing an example of an electronic component.

[0041] Figure 14A and Figure 14B This is a diagram illustrating an example of an electronic device. Figures 14C to 14E This is a diagram illustrating an example of a large computer.

[0042] Figure 15A This is a diagram illustrating an example of a space device. Figure 15B This is a diagram illustrating an example of a storage system that can be used in a data center.

[0043] Figures 16A1 to 16A7 and Figures 16B1 to 16B6 It is a circuit diagram used to illustrate electrical connections.

[0044] Methods of implementing the invention (Additional notes regarding this instruction manual) In this specification, a semiconductor device refers to a device that utilizes the properties of semiconductors, as well as a circuit that includes semiconductor elements (e.g., transistors, diodes, and photodiodes) and a device that includes such circuits. Furthermore, a semiconductor device refers to all devices capable of functioning by utilizing the properties of semiconductors. An integrated circuit can be cited as an example of a semiconductor device. Furthermore, a chip incorporating an integrated circuit can also be cited as an example of a semiconductor device. Furthermore, electronic components that house a chip in a package can also be cited as an example of a semiconductor device. In addition, for example, storage devices, display devices, light-emitting devices, arithmetic devices, lighting devices, and electronic devices are sometimes semiconductor devices themselves, or sometimes include semiconductor devices.

[0045] In this specification, “connection” includes, for example, “electrical connection”.

[0046] When describing the connection relationship of circuit elements as an object using the term "electrical connection," "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B directly connected" means, for example, that A and B are connected without any circuit element (such as a transistor or switch; note that wiring is not a circuit element). On the other hand, "A and B indirectly connected" means, for example, that A and B are connected through one or more circuit elements. Note that A, B, and C (described later) represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0047] Here, the term "indirectly connected between A and B" refers to a connection relationship in the following ways: That is, when it is assumed that the circuit is operating, and there is a sequence of events such as the exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, such a circuit can be defined as an object "indirectly connected between A and B." Furthermore, even if there is no sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B, but there is still a sequence of events where there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation, it can still be defined as "indirectly connected between A and B." Note that the expression "indirectly connected between A and B" defines the connection relationship of circuit elements as an object. Therefore, for example, even if the circuit is not operating because it is not supplied with a power supply voltage, the circuit can still be defined as an object "indirectly connected between A and B" (however, this is limited, for example, to the case where, when the circuit is operating because it is supplied with a power supply voltage, there is an exchange of electrical signals or the interaction of potentials between A and B during the circuit's operation).

[0048] The following are specific examples of "indirect connection". First, as an example of "A and B are indirectly connected", such as... Figure 16A1 and Figure 16A2As shown, there are cases where A and B are connected through the source and drain of more than one transistor. Other examples of "A and B indirect connection" include cases where A and B are connected through more than one switch. In the case of "A and B indirect connection," the timing sequence ensures that, assuming the circuit is operating, at least one transistor between A and B is in an on-state, a conducting state, or a state where current can flow at least once. Furthermore, the "A and B indirect connection" case includes timing sequences where one transistor between A and B is in a off-state or a non-conducting state. In the case of "A and B indirect connection," if multiple transistors are connected between A and B, the timing sequence ensures that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on-state, a conducting state, or a state where current can flow at least once. That is, in the case of "A and B indirect connection," multiple transistors do not necessarily need to all be in an on-state, a conducting state, or a state where current can flow simultaneously. Therefore, in the case of "A and B being indirectly connected," this includes situations where multiple transistors between A and B are simultaneously or at different times in a closed or non-conducting state. Other examples include... Figure 16A3 As shown, when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". Note that, as described below, when a fixed potential V is supplied to C from the power supply or GND, etc., although it can be said that "A and C are indirectly connected" or "B and C are indirectly connected", it is not possible to say that "A and B are indirectly connected".

[0049] The above examples illustrate situations where "indirect connection" can or cannot be described. However, the following examples show situations where "indirect connection" cannot be described. Even when electrical signals are exchanged or potentials interact between A and B during circuit operation, there are exceptions where "A and B are indirectly connected" cannot be described. An example of this exception is when A and B are connected through an insulator. That is, when A and B are connected through an insulator, "A and B are indirectly connected" cannot be described. Specific examples of A and B being connected through an insulator include... Figure 16A4 The case shown illustrates a capacitor connected between A and B. Other examples of A and B being connected via an insulator include... Figure 16A5 This refers to a situation where a gate insulating film of a transistor is sandwiched between A and B, as shown. In this case, it is not permissible to say that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected".

[0050] As another example where it's inappropriate to say "A and B are indirectly connected," cases where there is no exchange of electrical signals or interaction of electrical potentials between A and B can be cited. For example, the following situations exist: Figure 16A6 and Figure 16A7 As shown, along the path from A to B, multiple transistors are connected through their source and drain terminals, and a fixed potential V is supplied from the power supply or GND at the nodes between the transistors. In this case, although it cannot be said that "A and B are indirectly connected," it is possible to say that "A is indirectly connected to V" or "B is indirectly connected to V." Figure 16A3 In the case where A and C are connected through the source and drain of transistor TrP, and B and C are connected through the source and drain of transistor TrQ, and a fixed potential V is supplied to C from the power supply or GND, etc., it has the same characteristics as... Figure 16A6 and Figure 16A7 Since they are the same relationship, we cannot say "A is indirectly connected to B" but we can say "A is indirectly connected to C" or "B is indirectly connected to C".

[0051] Although the above examples of "indirect connection" are shown, the provisions of "indirect connection" are included in the provisions of "electrical connection", so in the case of "A and B are indirectly connected", it can be said that "A and B are electrically connected".

[0052] The following shows specific examples of the "direct connection" case. For example, in the case of "A and B are directly connected,"... Figure 16B1 , Figure 16B2 and Figure 16B3 As shown, there are cases where A and B are not connected through circuit components. Furthermore, as... Figure 16B4 and Figure 16B5 As shown, when A and B are not connected to a power supply with a fixed potential V or GND via circuit components, it can be said that "A and B are directly connected", "A is directly connected to V", or "B is directly connected to V". Furthermore, as... Figure 16B6 As shown, even when A (or B) is connected to a fixed potential V through the source and drain of a transistor, it can be said that "A and B are directly connected". However, since A and V, or B and V, are connected through the source and drain of a transistor, it cannot be said that they are directly connected; instead, it can be said that "A and V are indirectly connected" or "B and V are indirectly connected".

[0053] Although the above examples show "direct connection", the definition of "direct connection" is included in the definition of "electrical connection", so in the case of "A and B are directly connected", it can be said that "A and B are electrically connected".

[0054] Furthermore, even when independent components are connected to each other in a circuit diagram, sometimes one component performs the function of multiple components. For example, when a portion of a wiring is used as an electrode, a conductive film serves as both a wiring and an electrode. Therefore, the scope of "connection" in this specification also includes such cases where a conductive film performs the function of multiple components.

[0055] In this specification, a "resistive element" can be, for example, a circuit element having a resistance value greater than 0 Ω or a wiring having a resistance value greater than 0 Ω. Therefore, in this specification, a "resistor" includes wiring with a resistance value, a transistor, a diode, or a coil through which current flows between the source and drain. Additionally, a "resistive element" may sometimes be referred to as a "resistor," a "load," or a "region having a resistance value." Correspondingly, "resistor," "load," or "region having a resistance value" may sometimes be replaced with "resistive element." As for the resistance value, it is preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, it may also be 1 Ω or more and 1 × 10⁻¹⁰. 9 Below Ω.

[0056] Additionally, in this specification, "capacitive element" can refer to, for example, a circuit element having an electrostatic capacitance value greater than 0F, a wiring region having an electrostatic capacitance value greater than 0F, or the gate capacitance of a transistor. Furthermore, "capacitor" or "gate capacitance" can sometimes be replaced with "capacitor". Correspondingly, "capacitor" can sometimes be replaced with "capacitive element" or "gate capacitance". Furthermore, a "capacitive element" (including a "capacitive element" with three or more terminals) comprises an insulator and a pair of conductors holding the insulator. Thus, the "pair of conductors" of a "capacitor" can be replaced with "pair of electrodes", "pair of conductive regions", "pair of regions", or "pair of terminals". Furthermore, "one of the pair of terminals" and "the other of the pair of terminals" are sometimes referred to as the first terminal and the second terminal, respectively. The electrostatic capacitance value can, for example, be 0.05fF or more and 10pF or less. Furthermore, for example, it can also be 1pF or more and 10μF or less.

[0057] In this specification, a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the transistor's conductivity type (n-channel or p-channel) and the potential applied to the three terminals, one of the two input / output terminals is used as the source and the other as the drain. Therefore, in this specification, the source and drain may sometimes be interchanged. Furthermore, in this specification, when describing the connection relationship of the transistor, the terms "one of the source and drain" and "the other of the source and drain" are used. Sometimes, "one of the source and drain" is referred to as "first terminal" or "first electrode," and "the other of the source and drain" is referred to as "second terminal" or "second electrode." Additionally, depending on the transistor's structure, sometimes a back gate is included in addition to the three terminals mentioned above. In this case, in this specification, sometimes one of the transistor's gate and back gate is referred to as the first gate, and the other of the transistor's gate and back gate is referred to as the second gate. Furthermore, in the same transistor, the "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, in this specification, each gate is sometimes referred to as the first gate, the second gate, the third gate, etc.

[0058] For example, in this specification, a multi-gate transistor with two or more gate electrodes can be used as an example of a transistor. When a multi-gate structure is used, since the channel forming regions are connected in series, it becomes a structure in which multiple transistors are connected in series. Therefore, by using a multi-gate structure, the off-state current can be reduced, and the transistor's voltage withstand capability (reliability) can be improved. Alternatively, by utilizing a multi-gate structure, when the transistor is operating in the saturation region, even if the voltage between the drain and source changes, the change in the drain-source current is not significant, thus obtaining a voltage-current characteristic with a flat tilt angle. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with extremely high resistance can be realized. As a result, differential circuits or current mirror circuits with good characteristics can be realized.

[0059] Furthermore, a circuit diagram showing a single circuit element sometimes includes cases where that circuit element comprises multiple circuit elements. For example, a circuit diagram showing a single resistor may include cases where two or more resistors are connected in series. Similarly, a circuit diagram showing a single capacitor may include cases where two or more capacitors are connected in parallel. Likewise, a circuit diagram showing a single transistor may include cases where two or more transistors are connected in series and their gates are connected to each other. Likewise, a circuit diagram showing a switch may include cases where the switch comprises two or more transistors connected in series or in parallel and their gates are connected to each other.

[0060] In addition, in this specification, a node may also be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region, depending on the circuit structure and device structure. Furthermore, terminals, wiring, etc., may also be referred to as nodes.

[0061] Additionally, in this specification, a selector sometimes refers to a circuit that includes multiple input terminals and one output terminal, and selects one from the multiple input terminals and establishes a conduction state between the selected input terminal and the output terminal. In other words, a selector sometimes refers to a circuit that selects one from each of the multiple input terminals and outputs the selected input signal to the output terminal. Alternatively, a selector sometimes refers to a circuit that includes multiple output terminals and one input terminal, and selects one from the multiple output terminals and establishes a conduction state between the selected output terminal and the input terminal. In other words, a selector sometimes refers to a circuit that selects one from multiple output terminals and outputs the input signal from the input terminal to the selected output terminal. That is, a selector sometimes refers to a multiplexer or a multiplexer. In particular, in the case of inputting or outputting analog potentials or analog currents, a selector sometimes refers to an analog multiplexer or an analog multiplexer.

[0062] Additionally, the terms "voltage" and "potential" may be interchanged appropriately in this specification. "Voltage" refers to the potential difference between the reference potential and a ground potential. For example, when the reference potential is ground potential (grounding potential), "voltage" may also be referred to as "potential." Ground potential does not necessarily mean 0V. Furthermore, potential is relative; the potential supplied to wiring, the potential applied to circuits, and the potential output from circuits also change according to changes in the reference potential.

[0063] Furthermore, in this specification, "high-level potential" and "low-level potential" do not imply specific potentials. For example, if two wirings are both labeled "wirings used to supply high-level potentials," the high-level potentials supplied by the two wirings may be different. Similarly, if two wirings are both labeled "wirings used to supply low-level potentials," the low-level potentials supplied by the two wirings may be different.

[0064] Additionally, the terms "high potential" and "high level potential" can be interchanged appropriately in this instruction manual. Furthermore, the terms "low potential" and "low level potential" can be interchanged appropriately in this instruction manual.

[0065] Furthermore, "current" refers to the phenomenon of charge migration (conductivity). For example, the description "conductivity occurs in a positively charged body" can be replaced with the description "conductivity occurs in a negatively charged body in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge migration (conductivity) during charge carrier migration. Here, examples of charge carriers include electrons, holes, anions, cations, and complex ions, depending on the system through which the current flows (e.g., semiconductors, metals, electrolytes, and vacuum). Furthermore, the "direction of current" in wiring, etc., refers to the direction of migration of positively charged charge carriers and is described as a positive current quantity. In other words, the direction of migration of negatively charged charge carriers is opposite to the direction of current and is described as a negative current quantity. Therefore, in this specification, unless otherwise specified, regarding the positive or negative (or direction) of the current, the description "current flows from element A to element B" can be replaced with the description "current flows from element B to element A." Furthermore, the description "current input to element A" can be replaced with the description "current output from element A."

[0066] Furthermore, in this specification, ordinal numbers such as "first," "second," and "third" are added to avoid confusion regarding the constituent elements. Therefore, these ordinal numbers do not limit the number of constituent elements. Moreover, these ordinal numbers do not limit the order of the constituent elements. For example, a "first" constituent element in one embodiment of this specification may be referred to as a "second" constituent element in other embodiments or claims. Furthermore, for example, a constituent element referred to by "first" in one embodiment of this specification may be omitted in other embodiments or claims.

[0067] Furthermore, for convenience, terms such as "upper" and "lower" are sometimes used in this specification to indicate the arrangement of components in conjunction with the accompanying drawings. Moreover, the positional relationships of the components may vary appropriately depending on the orientation of each structure being described. Therefore, the terminology used is not limited to that described in the specification; alternative terms may be used as appropriate. For example, by rotating the orientation of the illustrated drawings by 180 degrees, the phrase "insulator located on the top surface of the conductor" may be replaced with "insulator located on the bottom surface of the conductor."

[0068] Furthermore, terms like "above" or "below" are not limited to situations where the constituent elements are directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed directly in contact with insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B. Similarly, the expression "electrode B above insulating layer A" does not necessarily mean that electrode B is formed directly in contact with insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B. Likewise, the expression "electrode B below insulating layer A" does not necessarily mean that electrode B is formed directly in contact below insulating layer A; it can also include situations where other constituent elements are included between insulating layer A and electrode B.

[0069] Furthermore, in this specification, terms such as "row" and "column" are sometimes used to describe the matrix-like configuration of the constituent elements and their positional relationships. Moreover, the positional relationships of the constituent elements may vary appropriately depending on the orientation in which each structure is described. Therefore, the terminology used is not limited to that described in the specification, etc., and may be appropriately changed as needed. For example, by rotating the orientation of the accompanying drawings by 90 degrees, the expression "row direction" may sometimes be replaced with "column direction."

[0070] Furthermore, in this specification, the terms "film" and "layer" may be interchanged depending on the context. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer." Additionally, depending on the situation, other terms may be used instead of "film" and "layer." For example, "conductive layer" or "conductive film" may sometimes be replaced with "conductor." Furthermore, "insulating layer" or "insulating film" may sometimes be replaced with "insulator."

[0071] Furthermore, in this specification, the terms "electrode," "wiring," and "terminal" do not functionally limit their constituent elements. For example, sometimes "electrode" is used as part of "wiring," and vice versa. Moreover, the terms "electrode" or "wiring" also include cases where multiple "electrodes" or "wiring" are formed as one unit. Additionally, for example, sometimes "terminal" is used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where one or more of "electrode," "wiring," and "terminal" are formed as one unit. Thus, for example, an "electrode" can be part of "wiring" or "terminal," and, for example, a "terminal" can be part of "wiring" or "electrode." Furthermore, the terms "electrode," "wiring," or "terminal," etc., are sometimes replaced with terms such as "area," depending on the situation.

[0072] In this manual, the terms "wiring," "signal line," or "power line" may be interchanged depending on the situation or circumstances. For example, sometimes "wiring" may be replaced with "signal line." Similarly, sometimes "wiring" may be changed to "power line," and vice versa. Furthermore, depending on the situation or circumstances, sometimes the "potential" applied to the wiring may be changed to "signal." Conversely, sometimes "signal" may be changed to "potential."

[0073] Furthermore, in this specification, timing diagrams are sometimes used to illustrate the operation of semiconductor devices. The timing diagrams used in this specification show ideal operating examples and, unless otherwise specified, are not limited to the periods, signal (e.g., potential or current) magnitudes, and timing shown in the timing diagram. In the timing diagrams described in this specification, the magnitudes and timing of signals (e.g., potential or current) input to each wiring (including nodes) in the timing diagram can be varied depending on the circumstances. For example, even if two periods are shown at equal intervals in the timing diagram, the lengths of the two periods may sometimes be different. Furthermore, for example, even if one period is shown to be longer than the other, the lengths of the two periods may sometimes be the same, or sometimes one period may be shorter than the other. Additionally, to clearly illustrate the timing diagram, overlapping signals are sometimes intentionally staggered, for example.

[0074] Furthermore, in this specification, impurities in a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, elements with a concentration of less than 0.1 atomic% are considered impurities. When impurities are present, for example, one or more of the following may occur: increased defect state density, decreased carrier mobility, and decreased crystallinity in the semiconductor.

[0075] In this specification, a switch refers to a component that controls whether current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to a component that selects and switches current paths. Therefore, a switch sometimes includes two or more terminals for current flow in addition to control terminals. As an example of a switch, an electrical switch or a mechanical switch can be used. In other words, a switch is not limited to a specific component as long as it has the function of controlling current.

[0076] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits combining these components. When a transistor is used as a switch, its "conduction state" refers, for example, to a state where the source and drain electrodes of the transistor are electrically short-circuited or where current can flow between the source and drain electrodes. Conversely, its "disconduction state" refers to a state where the source and drain electrodes of the transistor are electrically disconnected. Note that when a transistor is used solely as a switch, there are no particular restrictions on its polarity (conduction type).

[0077] As an example of a mechanical switch, there is a switch that utilizes MEMS (microelectromechanical systems) technology. This switch has mechanically movable electrodes, and operates by controlling the on and off states of conduction by moving these electrodes.

[0078] In this specification, "parallel" means that the angle formed by two straight lines is greater than or equal to -10 degrees and less than 10 degrees. Therefore, it also includes angles greater than or equal to -5 degrees and less than 5 degrees. "Approximately parallel" means that the angle formed by two straight lines is greater than or equal to -30 degrees and less than 30 degrees. Furthermore, "perpendicular" means that the angle formed by two straight lines is greater than or equal to 80 degrees and less than 100 degrees. Therefore, it also includes angles greater than or equal to 85 degrees and less than 95 degrees. Additionally, "approximately perpendicular" means that the angle formed by two straight lines is greater than or equal to 60 degrees and less than 120 degrees.

[0079] Furthermore, the structures shown in each embodiment in this specification can be appropriately combined with the structures shown in other embodiments to constitute a mode of the present invention. Additionally, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0080] Furthermore, the content described in one embodiment (part or all of it) may be applied / combined / replaced with at least one of the other content described in that embodiment (part or all of it) and the content described in one or more other embodiments (part or all of it).

[0081] Note that the content described in the embodiments refers to the content illustrated using various accompanying drawings or the content described using the text in the specification.

[0082] Furthermore, more figures can be formed by combining the figures shown in one embodiment (part or all of them) with other parts of the figures, other figures shown in that embodiment (part or all of them), and at least one figure shown in one or more other embodiments (part or all of them).

[0083] The embodiments described in this specification are illustrated with reference to the accompanying drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different forms, and their manner and details can be varied in various ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to denote the same part or parts having the same function, and sometimes repeated descriptions are omitted. In perspective views, etc., illustrations of some constituent elements are sometimes omitted for clarity.

[0084] In this specification, when multiple elements use the same symbol and it is necessary to distinguish them, symbols such as "_1", "[n]", and "[m,n]" are sometimes added to the symbol for identification. Furthermore, in figures and the like, when symbols such as "_1", "[n]", and "[m,n]" are added to the symbol for identification, if it is not necessary to distinguish them in this specification, sometimes these symbols are not added.

[0085] In the accompanying drawings of this specification, sizes, layer thicknesses, or areas are sometimes exaggerated for clarity. Therefore, the invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate ideal examples and are not limited to the shapes or values ​​shown. For example, non-uniformity in signals, voltages, or currents caused by noise or timing deviations may be included.

[0086] (Implementation Method 1) In this embodiment, a storage device of a semiconductor device according to one aspect of the present invention is described.

[0087] <Example of storage device structure> Figures 1 to 6 An example of the structure of this storage device is shown. Figure 1 This is a 3D schematic diagram of the SCD storage device. Figure 2A and Figure 2B This is a plan view of the SCD storage device. Additionally, Figure 3 It is Figure 2A A partially enlarged planar schematic diagram. Additionally, Figure 4 It corresponds to Figure 2A and Figure 2B A cross-sectional diagram of the section marked with dashed lines A1-A2. Additionally, Figure 5 It corresponds to Figure 2A and Figure 2B A cross-sectional diagram of the section marked with dashed lines A3-A4. Additionally, Figure 6 It corresponds to Figure 2A and Figure 2B A cross-sectional diagram of the section marked with dashed lines A5-A6.

[0088] Note that in Figure 2A , Figure 2B , Figure 4 and Figure 5 In each of them, the dotted lines A7-A8 are shown to clarify the positional relationship.

[0089] In addition, Figure 1 In this document, the extension direction of conductive layer ME1 (wiring WL) and conductive layer ME6 (wiring PL), described later, is defined as the X direction. Therefore, the directions of dotted lines A5-A6 and A7-A8 can both be referred to as the X direction. Furthermore, the extension direction of conductive layer ME3 (wiring BL), described later, is defined as the Y direction. Additionally, the direction perpendicular or approximately perpendicular to the X and Y directions is defined as the Z direction. Alternatively, the X and Y directions can be defined as perpendicular or approximately perpendicular to each other. The definitions of the X, Y, and Z directions are provided in [the document / section]. Figure 2A , Figure 2B , Figure 3 and Figure 6 They are sometimes the same and sometimes different. Furthermore, in Figures 2A to 3 In the explanation of the planar schematic diagram, sometimes the right side is designated as the +X direction, the left side as the -X direction, the top side as the +Y direction, and the bottom side as the -Y direction. Additionally, in... Figure 4 In the explanation of cross-sectional diagrams, the right side is sometimes designated as the +X direction, the left side as the -X direction, the top side as the +Z direction, and the bottom side as the -Z direction. Additionally, in... Figure 6 In the description of the cross-sectional diagram, the right side is sometimes designated as the +X direction, the left side as the -X direction, the top side as the +Z direction, and the bottom side as the -Z direction.

[0090] Note that, in order to clearly illustrate the structure of the SCD storage device, Figure 1 Selecting from the three-dimensional schematic diagrams shown in Figures 2 to 3, we can see the results. Figure 6 The diagram shows a portion of the conductive layer, insulating layer, and semiconductor layer.

[0091] exist Figures 1 to 6 In the memory device SCD, there is a substrate BS, a transistor Tr formed on the substrate BS, a capacitor CFE located above the transistor Tr, and a capacitor DCF. Specifically, as shown in the figure... Figure 4 As shown, the storage device SCD includes a storage cell MC, which includes a transistor Tr and a capacitor CFE.

[0092] A memory cell (MC) is a storage circuit that includes a transistor and a capacitor, and it employs a DRAM (Dynamic Random Access Memory) structure. Furthermore, by using a ferroelectric material as the dielectric of the capacitor, the capacitor can be a ferroelectric capacitor, and the memory cell (MC) can employ a FeRAM (Ferroelectric Random Access Memory) structure.

[0093] Additionally, the storage device SCD includes conductive layers ME1, ME2, ME3, ME4, ME5, and ME6, insulating layers GI1, UI1, UI2, UI3, IS1, IS2, IS3, IS4, BI1, BI2, and FDI. Note that some of the components listed above are sometimes also included in transistor Tr, capacitor CFE, or capacitor DCF.

[0094] As the substrate BS, a semiconductor substrate (a single crystal made of silicon, germanium, etc.) can be used, for example. In this specification, a single crystal substrate made of silicon will be used as the substrate BS.

[0095] Reference Figures 1 to 4 Explain the transistor Tr. The transistor Tr is formed on a substrate BS. A transistor region TA is formed by creating a device separation layer ST in the substrate BS. Additionally, two trenches MZ are formed within a transistor region TA, dividing the low-resistance region TA on the substrate BS into three parts. Note that in... Figure 4In this context, these regions are designated as low-resistance regions LRa, LRb, and LRc, respectively. Additionally, semiconductor regions SAb and SAc are formed on the substrate BS, which corresponds to the sides and bottom of the two trench sections MZ. Note that sometimes both semiconductor regions SAb and SAc are referred to as channel formation regions.

[0096] In other words, the transistor Tr has a U-shaped semiconductor region SAb (or semiconductor region SAc) when viewed in cross-section, and low-resistance regions LRa and LRb (or low-resistance regions LRc) opposite each other across the trench MZ when viewed in planar or cross-section. Thus, two transistors Tr can be formed in the transistor region TA.

[0097] The insulating layer GI1 is located on the side and bottom surfaces of the trench MZ formed in the substrate BS. Additionally, within the trench MZ, the conductive layer ME1 is located in the region opposite the semiconductor region SAb (or semiconductor region SAc) across the insulating layer GI1. Furthermore, as... Figures 1 to 3 As shown, the conductive layer ME1 is provided in a manner that extends in the X direction. In addition, the insulating layer UI1 is provided in a manner that fills the remaining portion of the groove MZ and contacts both the conductive layer ME1 and the insulating layer GI1.

[0098] The insulating layer GI1 is used as the gate insulating film of the transistor Tr. In addition, the insulating layer GI1 is also used as an insulating layer to prevent the low-resistance region LRa from directly contacting the low-resistance region LRb (or the low-resistance region LRc).

[0099] As the insulating layer GI1, silicon oxide, silicon nitride, or silicon oxynitride can be used, for example.

[0100] Note that in this specification, etc., "oxynitride" refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while "nitrogen oxide" refers to a material in which the nitrogen content is greater than the oxygen content in its composition. For example, when described as "silicon oxynitride," it refers to a material in which the oxygen content is greater than the nitrogen content in its composition, while when described as "silicon oxynitride," it refers to a material in which the nitrogen content is greater than the oxygen content in its composition.

[0101] The conductive layer ME1 has a region that serves as the gate of the transistor Tr.

[0102] Additionally, the conductive layer ME1 has areas used for wiring. For example, the conductive layer ME1 has areas used for wiring WL, which will be described in Embodiment 2 later. Figures 1 to 6 In the diagram, the conductive layer ME1 is also marked with the symbol WL[x] in parentheses. Note that [x] indicates its wiring sequence number. For example, in... Figure 4In the diagram, the conductive layer ME1, which has the region serving as the gate of the four transistors Tr, is referred to in parentheses as wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]. Note that in this specification, [x] may not always correspond to the row or column number of the matrix.

[0103] In particular, in a storage device SCD, the conductive layer ME1 (wiring WL) is used as a word line to send selection signals when writing or reading from a memory cell MC. Additionally, when the memory cell MC is not being written to or read from, the conductive layer ME1 (wiring WL) is used as a word line to send non-selection signals.

[0104] Note that in the conductive layer ME1, the area used as the gate of the transistor Tr and the area used as wiring are difficult to clearly separate and sometimes share the same area.

[0105] As the conductor ME1, it is preferable to use, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, palladium, iridium, strontium, and lanthanum, or an alloy composed of two or more of the aforementioned metal elements, or a combination of alloys composed of two or more of the aforementioned metal elements. Furthermore, as the conductive layer ME1, it is preferable to use, for example, conductive compounds such as tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even after absorbing oxygen, and are therefore preferred. In addition, as the conductive layer ME1, a semiconductor with high conductivity, such as polycrystalline silicon containing impurity elements (e.g., phosphorus), or a silicide (e.g., nickel silicide) can also be used.

[0106] By using materials with high conductivity (low resistance), the power consumption of the storage device SCD can be reduced. Furthermore, by using materials with high conductivity (low resistance), the generated electrical heat can be reduced, thus minimizing the impact of heat on the transistor Tr.

[0107] Alternatively, the conductive layer ME1 can also be a structure consisting of multiple conductive layers formed using the aforementioned materials stacked together. For example, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing oxygen can also be used. Furthermore, a stacked structure combining materials containing the aforementioned metallic elements and conductive materials containing nitrogen can also be used. Additionally, a stacked structure combining materials containing the aforementioned metallic elements, conductive materials containing oxygen, and conductive materials containing nitrogen can also be used.

[0108] Note that the materials listed above are merely examples, and it is preferable to select them appropriately based on the type of substrate used for the substrate BS. For example, if the substrate BS is a single-crystal substrate containing silicon as a material, the conductive layer ME1 is preferably selected from materials that do not contain metallic elements that diffuse into the single-crystal substrate and cause deterioration of the electrical characteristics of the transistors formed in the substrate BS.

[0109] The insulating layer UI1 is used as a planarization film to fill the groove MZ and cover the uneven shape of the substrate BS. In addition, like the insulating layer GI1, the insulating layer UI1 is also used as an insulating layer to prevent the low-resistance region LRa from directly contacting the low-resistance region LRb (or the low-resistance region LRc).

[0110] The insulating layer UI1 can be, for example, silicon oxide, silicon oxynitride, silicon oxynitride, or silicon nitride. Alternatively, the insulating layer UI1 can be, for example, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. Furthermore, the above-mentioned insulating materials can be appropriately combined as materials for the insulating layer UI1. In addition, the insulating layer UI1 can, for example, be a single-layer structure selected from the above materials or a multilayer structure combining the above materials.

[0111] The low-resistance regions LRa and LRb (or LRc) in transistor region TA are used as the source or drain regions in transistor Tr. For example, one of the two transistors Tr included in transistor region TA can be a transistor that uses low-resistance region LRa as one of the source and drain regions and low-resistance region LRb as the other of the source and drain regions. Furthermore, for example, the other of the two transistors Tr included in transistor region TA can be a transistor that uses low-resistance region LRa as one of the source and drain regions and low-resistance region LRc as the other of the source and drain regions.

[0112] Next, refer to Figure 4 Explain the component separation layer ST.

[0113] Component separation layers (ST) are used, for example, as insulating layers to electrically separate adjacent transistor regions (TA). Additionally, component separation layers (ST) are sometimes referred to as STI (Shallow Trench Isolation) regions, STI sections, etc.

[0114] The component separation layer ST includes, for example, an insulating layer UI2, an insulating layer UI3, and a conductive layer ME1.

[0115] The insulating layer UI2 is used as an insulating layer to electrically isolate adjacent transistor regions TA. Additionally, the insulating layer UI2 also serves as an insulating layer to fill a portion of the trench created when multiple transistor regions TA are formed in the substrate BS. Therefore, the insulating layer UI2 is located on the substrate BS corresponding to the side of this trench.

[0116] The insulating layer UI2 can use the materials that were used in the insulating layer UI1 mentioned above.

[0117] Additionally, a conductive layer ME1 is provided in the groove in such a way that it contacts a portion of the insulating layer UI2. As an example, a conductive layer ME1 is provided in... Figure 4 The conductive layer ME1 within the component separation layer ST has areas used for wiring. Therefore, it is indicated by parentheses... Figure 4 The conductive layer ME1 in the two component separation layers ST shown is respectively recorded as wiring WL[2] and wiring WL[5]. In addition, from the Figure 4 Viewed from different cross sections, conductive layer ME1 (wiring WL[2]) and conductive layer ME1 (wiring WL[5]) each have a region that serves as the gate of transistor Tr. In particular, referring to Figures 2A to 3 As can be seen from the planar schematic diagram, the conductive layer ME1 (wiring WL[2]) located at a position different from the dotted lines A1-A2 has a region that serves as the gate for other transistors Tr.

[0118] In addition, Figure 4 In the process described above, the conductive layer ME1 included in the component separation layer ST can be formed using the same process as the conductive layer ME1 having a region serving as the gate of the transistor Tr. Therefore, the conductive layer ME1 included in the component separation layer ST and the conductive layer ME1 having a region serving as the gate of the transistor Tr can both be made of the same material.

[0119] In addition, Figure 4 In this embodiment, the depth length of the conductive layer ME1 disposed in the component separation layer ST can be the same as or different from the depth length of the conductive layer ME1 disposed in the trench portion MZ of the transistor region TA. For example, the depth length of the conductive layer ME1 disposed in the component separation layer ST can be longer or shorter than the depth length of the conductive layer ME1 disposed in the trench portion MZ of the transistor region TA. Furthermore, the depth length of the conductive layer ME1 disposed in the component separation layer ST is determined based on the depth of the component separation layer ST formed in the substrate BS, the thickness of the insulating layer UI2, etc.

[0120] The insulating layer UI3 is used as a planarization film to fill the grooves of the component separation layer ST and cover the uneven shape of the substrate BS. Additionally, like the insulating layer UI2, the insulating layer UI3 also functions as an insulating layer to prevent adjacent transistor regions TA from directly contacting each other.

[0121] Therefore, insulating layer UI3 can use the materials described above that can be used for insulating layer UI1 or insulating layer UI2.

[0122] An insulating layer IS1 and an insulating layer BI1 are sequentially formed on the top surface of the transistor region TA and the component separation layer ST of the substrate BS.

[0123] The insulating layer IS1 is used as an interlayer film for configuring wiring, capacitors, etc., above the transistor Tr. Note that the insulating layer IS1 can also be formed simultaneously with the insulating layer UI3. That is, the insulating layer IS1 can also be used as a planarization film covering the uneven shape of the substrate BS.

[0124] The insulating layer IS1 can be made of the same material as the insulating layer UI1. In addition, the insulating layer IS1 can also be made of resin in addition to the materials mentioned above.

[0125] Furthermore, insulating layer IS1 is preferably made of a material with a low dielectric constant. By using a material with a low dielectric constant for insulating layer IS1, parasitic capacitance generated between wiring layers (conductive layers) can be reduced. Therefore, insulating layer IS1 is preferably made of one or more of the following materials with relatively low dielectric constants: silicon oxide, silicon oxynitride, fluorinated silicon oxide, carbon-containing silicon oxide, carbon and nitrogen-containing silicon oxide, and porous silicon oxide.

[0126] In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. They are also preferred because materials such as silicon oxide, silicon oxynitride, and porous silicon oxide readily form regions containing oxygen released during heating.

[0127] The insulating layer BI1 serves as an insulating film that separates the transistor Tr from the conductive layer and other insulating layers located above it. Specifically, the insulating layer BI1 acts as a barrier insulating film to prevent impurities from diffusing from above it onto the transistor Tr. Examples of such impurities include materials that degrade the electrical characteristics of the transistor Tr. Furthermore, the insulating layer BI1 can also be used as a barrier insulating film to suppress oxygen diffusion in order to prevent the wiring from oxidizing and increasing its resistance.

[0128] As a barrier insulating film with the function of inhibiting oxygen permeation, an insulator comprising one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used, either as a single layer or in layers. Specifically, examples of insulators with the function of inhibiting oxygen permeation include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Additionally, examples of insulators with the function of inhibiting oxygen permeation include oxides containing aluminum and hafnium (hafnium aluminate). Furthermore, examples of insulators with the function of inhibiting oxygen permeation include nitrides such as aluminum nitride, titanium aluminum nitride, silicon oxynitride, and silicon nitride.

[0129] The insulating layers IS1 and BI1 have multiple openings that extend to each of the low-resistance regions LRa to LRc in the transistor region TA of the substrate BS. Furthermore, a conductive layer ME2, serving as a contact plug (sometimes simply referred to as a plug), is embedded in these openings.

[0130] In particular, in this specification, the conductive layer ME2 that contacts the low-resistance region LRa is sometimes referred to as the first plug, and the conductive layer ME2 that contacts the low-resistance region LRb or the low-resistance region LRc is sometimes referred to as the second plug. Furthermore, a conductive layer ME3 is formed on the top surface of the conductive layer ME2 that serves as the first plug, and a conductive layer ME4 is formed on the top surface of the conductive layer ME2 that serves as the second plug; these will be explained in detail later.

[0131] The conductive layer ME2 used as the plug can be a single layer or a stack of conductive materials selected from one or more of the following: metallic materials, alloy materials, metal nitride materials, and metal oxide materials. High-melting-point materials such as tungsten or molybdenum, which combine heat resistance and conductivity, are preferred, with tungsten being the most preferred. Alternatively, low-resistance conductive materials such as aluminum or copper are preferred. Using low-resistance conductive materials reduces wiring resistance.

[0132] In addition, conductive layer ME2 can use materials that are also available for conductive layer ME1.

[0133] A conductive layer ME3 is formed on the top surface of both the insulating layer BI1 and the conductive layer ME2, which serves as the first plug. Additionally, as... Figures 1 to 3 As shown, the conductive layer ME3 is set in a manner that extends in the Y direction.

[0134] The conductive layer ME3 has areas used for wiring. For example, the conductive layer ME3 has areas used for wiring BL, which will be described in Embodiment 2 later. Additionally, in Figures 1 to 6In the diagram, the conductive layer ME3 is further annotated with the symbol BL[x] using parentheses. Note that, similar to conductive layer ME1, [x] indicates its wiring sequence number. For example, in... Figure 4 In the text, conductive layer ME3 is referred to as wiring BL[2] and wiring BL[3] by using parentheses. Note that, in this specification, as with conductive layer ME1, [x] may not always correspond to the row or column number of the matrix.

[0135] In particular, in the storage device SCD, the conductive layer ME3 (wiring BL) is used as the bit line for sending data signals to the storage cell MC.

[0136] Similar to the wiring layer WL, the conductive layer ME3 is preferably made of a low-resistance material. As an example, the conductive layer ME3 can use a material that can be used for either the conductive layer ME1 or the conductive layer ME2.

[0137] In addition, an insulating layer IS2 is formed on the top surface of both the insulating layer BI1 and the conductive layer ME3.

[0138] Similar to insulating layer IS1, insulating layer IS2 is used as an interlayer film. Therefore, insulating layer IS2 can, for example, use materials that are also suitable for insulating layer IS1.

[0139] In addition, the insulating layer IS2 has multiple openings leading to the insulating layer BI1 and the conductive layer ME2, which serves as the second plug. Furthermore, the conductive layer ME4, which serves as the plug, is embedded in these openings.

[0140] In particular, in this specification, the conductive layer ME4, which is in contact with the conductive layer ME2 used as the second plug, is sometimes referred to as the third plug.

[0141] The conductive layer ME4 has a region that contacts the subsequently formed conductive layer ME5, which will be described in detail later. Furthermore, the conductive layer ME5 is preferably located in the region overlapping with the conductive layer ME1. Thus, the conductive layer ME4 serves as a lead for conducting between the conductive layers ME2 and ME5. To enable conduction between the conductive layers ME2 and ME5, a wiring layer is preferably provided between them. That is, by forming an opening in the insulating layer ME2 for filling the lead, and filling the opening with the conductive layer ME4 serving as the lead, the conductive layer ME5 can be formed in the region overlapping with the conductive layer ME1.

[0142] Similar to the conductive layer ME2 used as the plug, the conductive layer ME4 is preferably made of a low-resistance material. As an example, the conductive layer ME4 can use a material that can be used for conductive layers ME1 to ME3.

[0143] Insulating layer BI2 and insulating layer IS3 are sequentially formed on the top surface of insulating layer IS2 and conductive layer ME4, respectively.

[0144] Similar to insulating layer BI1, insulating layer BI2 is used as a barrier insulating film to suppress the degradation of the electrical characteristics of transistor Tr, oxidation of the conductive layer, etc. Therefore, insulating layer BI2 can use materials that are also suitable for insulating layer BI1.

[0145] Similar to insulating layers IS1 and IS2, insulating layer IS3 is used as an interlayer film. Therefore, insulating layer IS3 can, for example, use materials that are also available for insulating layers IS1 and IS2.

[0146] Multiple openings are provided in insulating layers BI2 and IS3 to reach the conductive layer ME4, which serves as the third plug. Additionally, the bottom of these openings may also contain a portion of insulating layer IS2.

[0147] Furthermore, a conductive layer ME5 in the shape of a column is formed, including the opening and along the +Z direction. Note that the base of the column can be elliptical, curved (e.g., ellipse, cloud shape, triangle with rounded corners, quadrilateral, pentagon, etc.), angular (e.g., triangle, quadrilateral, pentagon, etc.), or a combination of these shapes.

[0148] In this specification, a columnar body refers to a structural body with a high aspect ratio when viewed in cross-section. For example, in Figure 4 In this context, the aspect ratio of the conductive layer ME5 refers to the ratio of its length H (also known as the height of the conductive layer ME5) to its width L (also known as the width L of the conductive layer ME5) when viewed from a cross-section. The length H is the length perpendicular to or approximately perpendicular to the surface being formed, and the length L is the length of the conductive layer ME5 along the dotted line A1-A2 direction. The aspect ratio of the conductive layer ME5 is preferably as large as possible without the conductive layer ME5 collapsing during the manufacturing process of the capacitor CFE or capacitor DCF. That is, the height H of the conductive layer ME5 is preferably greater than the width L of the conductive layer ME5 without the conductive layer ME5 collapsing. Note that the above is provided as an example. Figure 4 The situation viewed from the cross-section was explained, but in relation to... Figure 4 In different cross-sectional views, it is also preferable that the height H of the conductive layer ME5 is greater than the width L of the conductive layer ME5 within the range where the conductive layer ME5 does not collapse.

[0149] Furthermore, in this specification, a column is sometimes referred to as a pillar or column. Additionally, a column or column may also have a conical shape. Also, in this specification, a column or column with a conical shape is sometimes referred to as a frustum.

[0150] In this specification, a conical shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface. Alternatively, it refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the film surface used as the substrate of the constituent element. Furthermore, the angle formed between the inclined side surface and the substrate surface or the film surface is called the cone angle. Additionally, in this specification, a conical shape having a cone angle greater than 0 degrees and less than 90 degrees is called a positive cone, and a conical shape having a cone angle greater than 90 degrees and less than 180 degrees is called a negative cone.

[0151] Note that the aforementioned conductive layer ME5 is used, for example, as one of a pair of electrodes in a capacitor CFE.

[0152] The conductive layer ME5 is preferably made of a low-resistance material, similar to that used in plugs and wiring. As an example, the conductive layer ME5 can use the same material that can be used for conductive layers ME1 to ME4.

[0153] Alternatively, for example, a sacrificial layer of desired thickness can be formed on the top surface of the insulating layer IS3, and multiple openings leading to the conductive layer ME4 can be provided in the sacrificial layer, the insulating layer IS3 and the insulating layer BI2, and the conductive layer ME5 can be embedded in the multiple openings. Then the sacrificial layer is removed, thereby forming the conductive layer ME5.

[0154] An insulating layer FDI is formed on the top surface of both the insulating layer IS3 and the conductive layer ME5. In particular, the insulating layer FDI has a region that also contacts the side and top surfaces of the conductive layer ME5, which is a columnar structure. Furthermore, a conductive layer ME6 is formed on the top surface of the insulating layer FDI. In particular, the conductive layer ME6 is formed such that it has a region that faces the conductive layer ME5 across the insulating layer FDI.

[0155] The insulating layer FDI, for example, has a region that serves as the dielectric material for a capacitor CFE.

[0156] As an example, the insulating layer FDI can use a material that serves as the dielectric. For example, a high-k dielectric material is preferred. Specifically, as an example, the insulating layer FDI can use high-k dielectric materials such as alumina, hafnium oxide, tantalum oxide, zirconium oxide, and hafnium zirconium oxide. Alternatively, as another example, an oxide containing one or both of aluminum and hafnium is preferred, more preferably an oxide having an amorphous structure and containing one or both of aluminum and hafnium, and even more preferably hafnium oxide having an amorphous structure. Additionally, as another example, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used. By using a high-k dielectric material as the dielectric of the capacitor CFE, its electrostatic capacitance value can be increased, thereby maintaining the voltage written to the capacitor CFE for a long period.

[0157] Furthermore, the insulating layer FDI can be made of a material that is ferroelectric. Additionally, when a ferroelectric material is used in the insulating layer FDI, the capacitor CFE can be a ferroelectric capacitor.

[0158] Alternatively, hafnium oxide, zirconium oxide, and zirconium hafnium oxide (sometimes denoted as HfZrO) can be cited as materials that can exhibit ferroelectric properties. X Materials containing (where X is a real number greater than 0), materials made by adding element J1 to hafnium oxide (where element J1 is selected from one or more of zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr), etc.), and materials made by adding element J2 to zirconium oxide (where element J2 is selected from one or more of hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), and strontium (Sr), etc.), etc. Furthermore, lead titanate (sometimes referred to as PbTiO) can also be used as a material that can exhibit ferroelectric properties. X Piezoelectric ceramics with perovskite structures include barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate. Furthermore, as materials capable of ferroelectricity, mixtures or compounds composed of multiple materials selected from the above can be used. Additionally, the crystal structure (characteristics) of hafnium oxide, zirconium oxide, zirconium hafnium oxide, and materials formed by adding element J1 to hafnium oxide can vary depending on various processes, in addition to deposition conditions. Therefore, in this specification, materials exhibiting ferroelectricity are referred not only to ferroelectric materials but also to materials capable of ferroelectricity.

[0159] In particular, materials containing hafnium oxide or materials containing both hafnium oxide and zirconium oxide, even in thin films of just a few nanometers, are preferred as they can exhibit ferroelectricity. Therefore, the manufacturing process of ferroelectric capacitors can be shortened. In this specification, the ferroelectric material formed in a layered manner is sometimes referred to as a ferroelectric layer or a metal oxide film.

[0160] When forming an insulating layer FDI using a material containing hafnium oxide and zirconium oxide via atomic layer deposition (ALD), precursors containing hafnium, such as tetra(ethylmethylamino)hafnium (TEMAHf) or hafnium tetrachloride, can be used. Similarly, precursors containing zirconium, such as tetra(ethylmethylamino)zirconium (TEMAZr) or zirconium tetrachloride, can be used. Furthermore, one or both of H2O and O3 can be used as the oxidizing agent. However, the oxidizing agent is not limited to these. For example, the oxidizing agent can contain any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0161] Furthermore, the insulating layer FDI can have a single-layer structure or a multilayer structure. In particular, when the insulating layer FDI has a multilayer structure, each insulating layer included in the insulating layer FDI can, for example, be one or both of the high-k material and the ferroelectric material described above.

[0162] In addition, the thickness of the insulating layer FDI is preferably 1 nm or more and 30 nm or less, more preferably 2 nm or more and 20 nm or less, and even more preferably 3 nm or more and 15 nm or less.

[0163] Furthermore, unlike paraelectric materials, ferroelectric materials maintain their internal dielectric polarization (sometimes referred to as residual polarization) even after the applied voltage is removed. Because the dielectric polarization is continuously maintained, data degradation held by the memory cell MC can be suppressed when the capacitor CFE is a ferroelectric capacitor. Therefore, the refresh operation of the memory cell MC can be reduced, thereby reducing the power consumption of the storage device SCD.

[0164] The conductive layer ME6, for example, has a region that serves as another of a pair of electrodes for the capacitor CFE.

[0165] Therefore, in Figure 4 In this configuration, a capacitor CFE can be formed, where a portion of the conductive layer ME5 is used as one of a pair of electrodes, a portion of the insulating layer FDI is used as the dielectric, and a portion of the conductive layer ME6 is used as the other of the pair of electrodes. Furthermore, when the conductive layer ME5 is columnar, the area of ​​the insulating layer FDI sandwiched between the pair of electrodes can be increased. This increases the threshold voltage distribution of data in the FeRAM, allowing for the accurate reading of the logic "0" and "1".

[0166] In addition, such as Figures 1 to 3 As shown, the conductive layer ME6 is provided in a manner that extends in the X direction. Furthermore, in order to provide the conductive layer ME6 in a manner that extends in the X direction, as follows... Figure 3 As shown, in the storage device SCD, in addition to the capacitor CFE, a capacitor DCF (described later) is arranged in a manner along the X direction. Figure 4 (Not shown in the image). Additionally, in Figures 2A to 3 In the planar diagram, the conductive layer ME6 is shaped as adjacent circles overlapping each other, with multiple circles arranged along the X direction. Therefore, the conductive layer ME6 is sometimes referred to as beaded wiring.

[0167] Additionally, the conductive layer ME6 has areas used for wiring. For example, the conductive layer ME6 has areas used for wiring PL, which will be described in Embodiment 2 later. Figures 1 to 6In the diagram, conductive layer ME6 is further annotated with the symbol PL[x] using parentheses. Note that, similar to conductive layers ME1 and ME3, [x] indicates its wiring sequence number. For example, in... Figure 4 In this document, conductive layer ME6 is referred to by brackets as wiring PL[1], wiring PL[2], wiring PL[3], wiring PL[4], wiring PL[5], and wiring BL[6]. Note that, as with conductive layers ME1 and ME3, [x] may not always correspond to the row or column number in the matrix.

[0168] In particular, when the capacitor CFE of the storage device SCD is a ferroelectric capacitor, the conductive layer ME6 (wiring PL) is used as a board wire to send a specified signal when writing or reading data to the storage cell MC.

[0169] Note that in the case where the storage device SCD is DRAM instead of FeRAM, the conductive layer ME6 (wiring PL) is preferably used as wiring to supply a fixed potential.

[0170] Furthermore, since the conductive layer ME6 is used for each of the wirings PL[1] to PL[6], it is necessary to electrically isolate adjacent wirings from each other. As a specific process, after the film that will become the conductive layer ME6 is formed on the insulating layer FDI, the area between the wirings in the film that will become the conductive layer ME6 is removed by etching or the like in the manner of forming each of the wirings PL[1] to PL[6].

[0171] Similar to conductive layers ME1 and ME3 used for wiring, conductive layer ME6 is preferably made of a low-resistance material. As an example, conductive layer ME6 can use materials that are also suitable for conductive layers ME1 to ME5.

[0172] An insulating layer IS4 is formed on the top surface of both the insulating layer FDI and the conductive layer ME6.

[0173] Insulating layer IS4 is used as an interlayer film in the same way as insulating layers IS1 to IS3. Therefore, insulating layer IS4 can be made of materials that are also used in insulating layers IS1 to IS3.

[0174] Alternatively, after forming the insulating layer IS4, the top surface of the insulating layer IS4 can be planarized using chemical mechanical polishing (CMP). This allows wiring, circuit elements, etc., to be formed above the insulating layer IS4. In this case, the storage device SCD can be used as part of a monolithic stacked structure. For example, by placing processing circuits, arithmetic circuits, etc., above the storage device SCD, a novel semiconductor layer can be created to temporarily store the processing results from the processing circuits, arithmetic circuits, etc., within the storage device SCD.

[0175] Next, refer to Figure 4 , Figure 5 , Figure 6 The capacitor DCF is described as a pseudo-pattern set up to set the conductive layer ME6 in a manner that extends in the X direction.

[0176] Multiple openings are provided in insulating layers IS1 and BI1 to reach the device separation layer ST of the substrate BS. In particular, in Figure 5 In this structure, the opening is formed in the region overlapping with wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4] and wiring WL[6]). In addition, a conductive layer ME2, which serves as a plug, is embedded in the opening.

[0177] Alternatively, depending on the circumstances, the opening may also be formed in an area that does not overlap with wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4] and wiring WL[6]).

[0178] In particular, in this specification, the conductive layer ME2 that contacts the component separation layer ST is sometimes referred to as the fourth plug.

[0179] Furthermore, the insulating layer IS2 has multiple openings leading to the conductive layer ME2, which serves as the fourth plug. Additionally, the conductive layer ME4, which functions as the plug, is embedded within these openings. These openings may also have a region leading to the insulating layer BI1.

[0180] In particular, in this specification, the conductive layer ME4, which is in contact with the conductive layer ME2 used as the fourth plug, is sometimes referred to as the fifth plug.

[0181] The insulating layers BI2 and IS3 have multiple openings leading to the conductive layer ME4, which serves as the fourth plug. Additionally, the bottom of each opening may also contain a portion of the insulating layer IS2.

[0182] Furthermore, a columnar conductive layer ME5 is formed, including the opening and along a direction substantially parallel to the +Z direction. In particular, in Figure 5In this configuration, the conductive layer ME5 is preferably formed in a region overlapping with the wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]). That is, the openings provided in the insulating layers BI2 and IS3 are preferably formed in a region overlapping with the wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4], and wiring WL[6]). The conductive layer ME5 filling these openings is used as one of a pair of electrodes in the capacitor DCF.

[0183] Similar to capacitor CFE, in capacitor DCF, a portion of conductive layer ME5 is used as one of a pair of electrodes, a portion of insulating layer FDI is used as the dielectric, and a portion of conductive layer ME6 is used as the other of the pair of electrodes. As mentioned above, conductive layer ME2, acting as the fourth connector, is located on the top surface of component separation layer ST, and conductive layer ME4, acting as the fifth connector, does not contact conductive layers other than conductive layers ME2 and ME5. Therefore, conductive layers ME2 (fourth connector), ME4 (fifth connector), and ME5 are all in a floating state. In other words, because one of the pairs of electrodes in capacitor DCF is in a floating state, unlike capacitor CFE, capacitor DCF does not retain data.

[0184] By forming a conductive layer ME5, which serves as one of a pair of electrodes for a capacitor DCF, in the region overlapping with wiring ME1 (wiring WL[1], wiring WL[3], wiring WL[4] and wiring WL[6]), such as Figures 2A to 3 and Figure 6 As shown, conductive layer ME5, serving as one of the pairs of electrodes for capacitor DCF, and conductive layer ME5, serving as one of the pairs of electrodes for capacitor CFE, can be configured to extend along the X direction. Furthermore, by forming conductive layer ME6 opposite to these conductive layers ME5 with an insulating layer FDI in between, capacitor CFE and capacitor DCF as a dummy pattern can be configured to extend along the X direction. Thus, conductive layer ME6, serving as wiring PL, can be configured to extend along the X direction. Therefore, capacitor CFE and wiring PL can be formed simultaneously, making it easy to manufacture memory device SCD. Additionally, it is not necessary to extend the wiring PL for a long time, thus reducing the power consumption of memory device SCD.

[0185] Additionally, when the storage device SCD is FeRAM, such as Figures 1 to 6As shown, the wiring used as word lines and the wiring PL used as board lines are preferably arranged in a manner that extends in the same direction, parallel to each other, or substantially parallel to each other. In FeRAM, the memory cell MC that is supplied with a selection signal from the wiring WL becomes the object of writing or reading, and the memory cell MC that becomes the object is supplied with a specified potential from the wiring PL. Therefore, it is preferable to arrange the wiring WL and the wiring PL in a manner that extends in the same direction, parallel to each other, or substantially parallel to each other.

[0186] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0187] (Implementation Method 2) In this embodiment, refer to Figures 7 to 9B An example of the structure of a storage device and its peripheral circuitry, which is a semiconductor device according to one aspect of the present invention, will be described.

[0188] <Example of storage device structure> Figure 7 An example of the structure of a storage device is shown. Storage device 1400 includes peripheral circuitry 1411 and a storage cell array 1470. Peripheral circuitry 1411 includes row circuitry 1420, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460.

[0189] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is the wiring connected to the memory cells included in the memory cell array 1470. The amplified data signal, as the data signal RDATA, is output to the outside of the memory device 1400 via the output circuit 1440. Additionally, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and a board line driver circuit, and can select the row to be accessed.

[0190] The storage device 1400 is supplied with a low power supply voltage (VSS), the peripheral circuit 1411 is supplied with a high power supply voltage (VDD), and the memory cell array 1470 is supplied with a high power supply voltage (VIL). In addition, the storage device 1400 receives external control signals (CE, WEN, RES), address signals ADDR, and data signals WDATA. The address signal ADDR is input to the row decoder and column decoder, and the data signal WDATA is input to the write circuit.

[0191] The control logic circuit 1460 processes externally input control signals (CE, WEN, RES) to generate control signals for the row decoder and column decoder. Control signal CE is the chip enable signal, control signal WEN is the write enable signal, and control signal RES is the read enable signal. The signals processed by the control logic circuit 1460 are not limited to these; other control signals can be input as needed.

[0192] The memory cell array 1470 includes a plurality of memory cells MCs configured in a row and column arrangement and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a column, etc. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cell MCs included in a row, etc.

[0193] Note that the structure of the peripheral circuit 1411 and the storage cell array 1470 shown in this embodiment is not limited to the structure described above. Furthermore, the configuration or function of these circuits and the wiring and circuit elements connected to them can be changed, removed, or added as needed. One embodiment of the present invention provides a storage device with high operating speed and the ability to retain data for extended periods.

[0194] Figure 8 The above-mentioned storage cell array 1470 and storage cell MC are shown as structural examples.

[0195] Figure 8 The shown memory cell array 1470 comprises m / 2 rows and n columns (m is an even number greater than 1, and n is an integer greater than 1) of memory cells arranged in a matrix. Additionally, Figure 8 The storage cell 1480 shown is a storage circuit that can be used in the aforementioned storage cell MC, and is an example of a circuit structure for a storage cell employing a ferroelectric capacitor. Furthermore, Figure 8 Row circuit 1420 and column circuit 1430 are also shown.

[0196] Figure 8In this embodiment, storage cell 1480 includes transistor M9 and capacitor Cfe. Here, in storage cell 1480, transistor M9 may correspond to transistor Tr described in Embodiment 1, and capacitor Cfe may correspond to capacitor CFE described in Embodiment 1.

[0197] in addition, Figure 8 In the memory cell array 1470, a wiring BL connects m memory cells 1480. Furthermore, in the memory cells 1480 connected to the same wiring BL, the transistors Tr included in two memory cells arranged in the same row can be, for example, [missing information]. Figure 4 The two transistors in the transistor region TA shown.

[0198] Note that the following focuses on Figure 8 Any one of the multiple storage units 1480 shown will be described.

[0199] One of the source and drain of transistor M9 is connected to wiring BL (e.g., any one of wiring BL[1] to wiring BL[n]). The other of the source and drain of transistor M9 is connected to one of the pairs of electrodes of capacitor Cfe. The gate of transistor M9 is connected to wiring WL (e.g., any one of wiring WL[1] to wiring WL[m]). The other of the pairs of electrodes of capacitor Cfe is connected to wiring PL (e.g., any one of wiring PL[1] to wiring PL[m]).

[0200] Wiring WL serves as a word line, and the switching between the on and off states of transistor M9 can be controlled by providing a potential to wiring WL as a select signal or a non-select signal. For example, by providing a high potential (H) to the select signal provided to wiring WL, transistor M9 can be turned on, and by providing a low potential (L) to the non-select signal provided to wiring WL, transistor M9 can be turned off. Wiring WL is connected to the word line driving circuit in row circuit 1420, and the word line driving circuit can provide select or non-select signals to wiring WL.

[0201] Wiring BL serves as a bit line. When transistor M9 is in the ON state, a potential corresponding to the data signal supplied to wiring BL is supplied to one of the pairs of electrodes of capacitor Cfe. Wiring BL is connected to a bit line driving circuit included in column circuit 1430. The bit line driving circuit has the function of generating a data signal to be written to memory cell MC. In addition, the bit line driving circuit has the function of reading data output from memory cell MC. Specifically, a sense amplifier is provided in the bit line driving circuit, which can be used to read the data output from memory cell MC.

[0202] The wiring PL serves as a board line. The other electrode of the capacitor Cfe is supplied with a specified potential to the wiring PL. The wiring PL is connected to a board line drive circuit in the row circuitry 1420, which is, for example, a circuit capable of providing this potential to the wiring PL during write or read operations.

[0203] A capacitor Cfe contains a ferroelectric material as a dielectric layer between its two electrodes. By employing a thin-film ferroelectric layer as the dielectric layer of the capacitor and combining it with miniaturized transistors, highly integrated memory devices can be realized. The dielectric layer included in the capacitor Cfe will be referred to below as the ferroelectric layer.

[0204] The ferroelectric layer contained in the capacitor Cfe exhibits hysteresis characteristics. Figure 9A This is a graph illustrating an example of this hysteresis characteristic. Figure 9A In the diagram, the horizontal axis represents the voltage applied to the ferroelectric layer. This voltage can be, for example, the difference between the potential of one of the electrodes of a capacitor Cfe and the potential of the other electrode of the capacitor Cfe.

[0205] in addition, Figure 9A The vertical axis shows the polarization of the ferroelectric layer. When it is positive, it means that positive charges are biased to one side of one electrode of the pair of electrodes of capacitor Cfe, while negative charges are biased to the other side of the pair of electrodes of capacitor Cfe. When the polarization is negative, it means that positive charges are biased to the other side of the pair of electrodes of capacitor Cfe, while negative charges are biased to one side of one electrode of the pair of electrodes of capacitor Cfe.

[0206] in addition, Figure 9A The voltage shown on the horizontal axis of the graph can also be the difference between the potential of the other electrode in a pair of electrodes of capacitor Cfe and the potential of one electrode in a pair of electrodes of capacitor Cfe. Additionally, Figure 9A The polarization shown on the vertical axis of the graph can also be positive when the positive charge is biased to one side of the other electrode of the pair of electrodes of capacitor Cfe and the negative charge is biased to one side of the pair of electrodes of capacitor Cfe, and negative when the positive charge is biased to one side of the pair of electrodes of capacitor Cfe and the negative charge is biased to the other side of the pair of electrodes of capacitor Cfe.

[0207] like Figure 9A As shown, the hysteresis characteristics of the ferroelectric layer can be represented by curves 61 and 62. The voltage at the intersection of curves 61 and 62 is taken as VSP and -VSP. It can be said that VSP and -VSP have different polarities.

[0208] When the voltage applied to the ferroelectric layer is increased after applying a voltage below -VSP, the polarization of the ferroelectric layer increases according to curve 61. Conversely, when the voltage applied to the ferroelectric layer is decreased after applying a voltage above VSP, the polarization of the ferroelectric layer decreases according to curve 62. Therefore, VSP and -VSP can be considered saturation polarization voltages. Note that sometimes, for example, VSP is referred to as the first saturation polarization voltage and -VSP as the second saturation polarization voltage. Furthermore, in Figure 9A In this case, the absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage are equal, but they can also be different.

[0209] Here, the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer is "0" according to curve 61 is denoted as Vc. Similarly, the voltage applied to the ferroelectric layer when the polarization of the ferroelectric layer is "0" according to curve 62 is denoted as -Vc. Both -Vc and Vc can be considered coercive voltages. The values ​​of Vc and Vc can be considered values ​​between -VSP and VSP. Note that sometimes, for example, Vc is referred to as the first coercive voltage and -Vc as the second coercive voltage. Furthermore, in... Figure 9A The absolute values ​​of the first and second coercive voltages are equal, but they may not be equal.

[0210] Furthermore, the maximum value of polarization when no voltage is applied to the ferroelectric layer is called "residual polarization Pr", and the minimum value is called "residual polarization -Pr". In addition, the difference between residual polarization Pr and residual polarization -Pr is called "residual polarization 2Pr".

[0211] As described above, the voltage applied to the ferroelectric layer comprising the capacitor Cfe can be represented as the difference between the potential of one of the pair of electrodes of the capacitor Cfe and the potential of the other of the pair of electrodes of the capacitor Cfe. Furthermore, as described above, the other of the pair of electrodes of the capacitor Cfe is connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer comprising the capacitor Cfe can be controlled.

[0212] right Figure 8 An example of the driving method for the shown memory cell 1480 will be described. In the following description, the voltage applied to the ferroelectric layer of capacitor Cfe represents the potential difference (potential difference) between the potential of one of the pair of electrodes of capacitor Cfe and the potential of the other (wiring PL) of the pair of electrodes of capacitor Cfe. Transistor M9 is an n-channel transistor.

[0213] Figure 9B This is a timing diagram illustrating an example of the driving method for memory cell 1480. Figure 9BAn example is shown where two-valued digital data is written to and read from memory cell 1480. Specifically, Figure 9B The following example illustrates the following: data "1" is written to storage unit 1480 from time T01 to time T02; data is read and rewritten from time T03 to time T05; data "0" is read and written to storage unit 1480 from time T11 to time T13; data is read and rewritten from time T14 to time T16; and data "1" is read and written to storage unit 1480 from time T17 to time T19.

[0214] The sense amplifier, electrically connected to the wiring BL, is supplied with Vref as a reference potential. Figure 9B In the readout operation shown, data "1" is read out through the bit line drive circuit when the potential of the wiring BL is higher than Vref. On the other hand, data "0" is read out through the bit line drive circuit when the potential of the wiring BL is lower than Vref.

[0215] From time T01 to time T02, a high potential is provided to wiring WL as a selection signal via the word line drive circuit. This turns transistor M9 on. Additionally, the potential of wiring BL becomes Vw. Since transistor M9 is on, the potential of one of the electrodes of capacitor Cfe becomes Vw. Furthermore, GND is provided to wiring PL using the board line drive circuit. Therefore, the voltage applied to the ferroelectric layer of capacitor Cfe becomes "Vw-GND". Thus, data "1" can be written to memory cell 1480. Therefore, time T01 to time T02 can be considered the period of write operation.

[0216] Here, Vw is preferably VSP or higher, for example, preferably equal to VSP. Note that GND is a ground potential in this specification, but GND does not necessarily need to be a ground potential as long as the memory cell 1480 can be driven in a manner that achieves the purpose of one aspect of the present invention. For example, GND can be a potential other than ground when the absolute values ​​of the first saturation polarization voltage and the second saturation polarization voltage are different and the absolute values ​​of the first coercive voltage and the second coercive voltage are different.

[0217] From time T02 to time T03, the bit line drive circuit provides GND to the wiring BL and the board line drive circuit provides GND to the wiring PL. Therefore, the voltage applied to the ferroelectric layer of capacitor Cfe becomes 0V. From time T01 to time T02, the voltage "Vw-GND" applied to the ferroelectric layer of capacitor Cfe can be greater than VSP, thus, from time T02 to time T03, the polarization of the ferroelectric layer of capacitor Cfe is determined according to... Figure 9AThe curve 62 shown changes. Therefore, from time T02 to time T03, no polarization reversal occurs in the ferroelectric layer of capacitor Cfe.

[0218] After providing GND to both wiring BL and PL, a low potential is provided to wiring WL using the word line drive circuit as a non-selection signal. Therefore, transistor M9 becomes off. Thus, the write operation ends, and the data "1" is retained in memory cell 1480. Note that if polarization reversal does not occur in the ferroelectric layer of capacitor Cfe, i.e., the voltage applied to the ferroelectric layer of capacitor Cfe is above -Vc of the second coercive voltage, the potentials of wiring BL and PL can be arbitrary.

[0219] From time T03 to time T04, a high potential is provided to wiring WL using the word line drive circuit as a selection signal. This turns transistor M9 on. Additionally, Vw is provided to wiring PL using the board line drive circuit. This makes the potential of wiring PL Vw, and thus the voltage applied to the ferroelectric layer of capacitor Cfe becomes "GND-Vw". As described above, from time T01 to time T02, the voltage applied to the ferroelectric layer of capacitor Cfe is "Vw-GND". Therefore, polarization reversal occurs in the ferroelectric layer of capacitor Cfe. During polarization reversal, current flows through wiring BL, and the potential of wiring BL is higher than Vref. Therefore, the bit line drive circuit can read the data "1" held by memory cell 1480. Therefore, time T03 to time T04 can be considered the period for readout operation. Note that although it is assumed that Vref is higher than GND and lower than Vw, it can also be higher than Vw, for example.

[0220] Because the aforementioned readout is a destructive readout, the data "1" held by memory cell 1480 disappears. Therefore, from time T04 to time T05, Vw is provided to wiring BL through the bit line drive circuit and GND is provided to wiring PL through the board line drive circuit. Thus, the data "1" in memory cell 1480 can be rewritten. Therefore, time T04 to time T05 can be considered the period during which the rewriting operation takes place.

[0221] Between time T05 and time T11, GND is provided to wiring BL via the bit line drive circuit and to wiring PL via the board line drive circuit. Then, a low potential is provided to wiring WL via the word line drive circuit as a non-selection signal. Thus, the rewrite operation ends, and the data "1" is held in memory cell 1480.

[0222] From time T11 to time T12, a high potential is provided to wiring WL as a selection signal via the word line drive circuit. Additionally, a potential Vw is provided to wiring PL via the board line drive circuit. Because memory cell 1480 holds the data "1", the potential of wiring BL is higher than Vref, and the data "1" held by memory cell 1480 is read out. Therefore, time T11 to time T12 can be considered the period during which the readout operation is performed.

[0223] Between time T12 and time T13, GND is provided to wiring BL via the bit line drive circuit. Since transistor M9 is in the ON state, the potential of one of the electrodes of capacitor Cfe becomes GND. Additionally, a potential Vw is provided to wiring PL via the board line drive circuit. Therefore, the voltage applied to the ferroelectric layer of capacitor Cfe becomes "GND-Vw". Thus, data "0" can be written to memory cell 1480. Therefore, time T12 to time T13 can be considered the period during which the write operation is performed.

[0224] From time T13 to time T14, GND is provided to wiring BL via the bit line drive circuit and to wiring PL via the board line drive circuit. Therefore, the voltage applied to the ferroelectric layer of capacitor Cfe becomes 0V. From time T12 to time T13, the voltage "GND-Vw" applied to the ferroelectric layer of capacitor Cfe can be below -VSP, thus, from time T13 to time T14, the polarization of the ferroelectric layer of capacitor Cfe depends on... Figure 9A The curve 61 shown changes. Therefore, from time T13 to time T14, no polarization reversal occurs in the ferroelectric layer of capacitor Cfe.

[0225] After providing GND to both wiring BL and PL, a low potential is provided to wiring WL using the word line drive circuit as a non-selection signal. Therefore, transistor M9 becomes off. Thus, the write operation ends, and the data "0" is retained in memory cell 1480. Note that if polarization reversal does not occur in the ferroelectric layer of capacitor Cfe, i.e., the voltage applied to the ferroelectric layer of capacitor Cfe is below the first coercive voltage Vc, the potentials of wiring BL and PL can be arbitrary.

[0226] From time T14 to time T15, a high potential is provided to wiring WL as a selection signal via the word line drive circuit. This turns transistor M9 on. Additionally, a potential Vw is provided to wiring PL via the board line drive circuit. By setting the potential of wiring PL to Vw, the voltage applied to the ferroelectric layer of capacitor Cfe becomes "GND-Vw". As described above, the voltage applied to the ferroelectric layer of capacitor Cfe from time T12 to time T13 is "GND-Vw". Therefore, polarization reversal does not occur in the ferroelectric layer of capacitor Cfe. Consequently, the current flowing through wiring BL is smaller than if polarization reversal occurred in the ferroelectric layer of capacitor Cfe. Therefore, the potential rise of wiring BL is smaller than if polarization reversal occurred in the ferroelectric layer of capacitor Cfe; specifically, the potential of wiring BL becomes below Vref. Thus, the bit line drive circuit can read the data "0" held by memory cell 1480. Therefore, time T14 to time T15 can be considered the period for readout operation.

[0227] Between time T15 and time T16, GND is provided to wiring BL through the bit line drive circuit and Vw is provided to wiring PL through the board line drive circuit. This allows the data "0" to be rewritten to memory cell 1480. Therefore, time T15 to time T16 can be considered the period during which the rewriting operation is performed.

[0228] Between time T16 and time T17, GND is provided to wiring BL via the bit line drive circuit and to wiring PL via the board line drive circuit. Then, a low potential is provided to wiring WL via the word line drive circuit as a non-selection signal. Thus, the rewrite operation ends, and the data "0" is held in memory cell 1480.

[0229] From time T17 to time T18, a high potential is provided to wiring WL as a selection signal via the word line drive circuit. Additionally, a potential Vw is provided to wiring PL via the board line drive circuit. Because memory cell 1480 holds data "0", the potential of wiring BL is lower than Vref, and the data "0" held by memory cell 1480 is read out. Therefore, time T17 to time T18 can be considered the period during which the readout operation is performed.

[0230] From time T18 to time T19, a potential Vw is provided to wiring BL via the bit line drive circuit. Since transistor M9 is in the on state, the potential of one electrode of capacitor Cfe becomes Vw. Additionally, a potential GND is provided to wiring PL via the board line drive circuit. Therefore, the voltage applied to the ferroelectric layer of capacitor Cfe becomes "Vw-GND". Thus, data "1" can be written to memory cell 1480. Therefore, time T18 to time T19 can be considered the period of the write operation.

[0231] At time T19, GND is provided to wiring BL via the bit line drive circuit and to wiring PL via the board line drive circuit. Then, a low potential is provided to wiring WL via the word line drive circuit as a non-selection signal. Thus, the write operation ends, and the data "1" is held in memory cell 1480.

[0232] Semiconductor devices that use ferroelectric layers in capacitors (Cfe) are used as non-volatile storage elements that can retain written information even when power is interrupted.

[0233] Furthermore, DRAM requires periodic refresh operations, which increases power consumption. Semiconductor devices that use ferroelectric layers in capacitors (Cfe) do not require refresh operations, thereby reducing power consumption.

[0234] In this specification and other materials, a memory element or memory circuit including a ferroelectric layer is sometimes referred to as a "ferroelectric memory" or "FE memory". Therefore, a semiconductor device according to one aspect of the present invention is a ferroelectric memory, and also an FE memory. FE memories can be expected to achieve 1×102 10 The preferred value is 1×10. 12 The above is preferred to be 1×10 15 The above are the number of rewrites. Furthermore, the FE memory is expected to operate at frequencies of 10MHz or higher, preferably 1GHz or higher.

[0235] Furthermore, in FE memory, the residual polarization 2Pr is related to data retention capability; if the residual polarization 2Pr decreases, the data retention capability decreases. In this specification, the period until the residual polarization 2Pr decreases by 5% (data retention capability decreases by 5%) is referred to as the "retention period". FE memory can be expected to achieve a retention period of more than 1 day, preferably more than 10 days, more preferably more than 1 year, and more preferably more than 10 years at a temperature of 150°C or 200°C.

[0236] Furthermore, FE memory can also be used as cache memory and registers in CPUs (Central Processing Units), GPUs (Graphics Processing Units), etc. By combining FE memory with CPU cache memory and registers, a normally disabled CPU (NoffCPU, registered trademark) can be achieved. Similarly, by combining FE memory with GPU cache memory and registers, a normally disabled GPU (NoffGPU, registered trademark) can be achieved.

[0237] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0238] (Implementation Method 3) In this embodiment, refer to Figure 10 This illustrates one example of the range of semiconductor devices that can be used in one manner as described in this invention.

[0239] Computers and other semiconductor devices use various storage devices depending on their application. Figure 10 This is a conceptual diagram illustrating the hierarchy of a memory device used in semiconductor devices. Figure 10 In the diagram, a triangle is used to illustrate the hierarchy of storage devices. The higher up the triangle, the faster the operating speed of the storage device is required, while the lower down the triangle, the larger the storage capacity and the higher the recording density are required.

[0240] exist Figure 10 In the diagram, starting from the top layer of the triangle, we see memory stored as registers in computing devices such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), and NPUs (Neural Processing Units); cache memory (sometimes simply called cache; typically L1, L2, and L3 caches); main memory represented by DRAM (Dynamic Random Access Memory); and storage devices represented by 3D NAND and hard disk drives (HDDs).

[0241] Because the memory installed along with registers in computing devices such as CPUs, GPUs, and NPUs is used for temporary storage of computation results, it is accessed frequently by these devices. Therefore, a faster operating speed is required compared to a larger storage capacity. Furthermore, registers also have the function of holding settings information for the computing device.

[0242] Cache memory has the function of copying and maintaining a portion of the data held in DRAM. By copying and maintaining frequently used data in cache memory, the speed of data access can be improved. Cache memory requires less storage capacity than DRAM, but requires a faster operating speed. Furthermore, data that is overwritten in cache memory is copied and fed into DRAM. Note that although... Figure 10 The cache memory shown in the diagram only illustrates L1 to L3 caches, but is not limited to this. For example, in the cache, the storage device using oxide semiconductors, as described in one aspect of the present invention, can also be applied to the lowest level LLC (Last Level cache) or FLC (Final Level cache).

[0243] DRAM has the function of storing programs, data, etc. read from 3D NAND.

[0244] 3D NAND has the ability to retain data that needs to be stored for a long time and various programs used by computing devices (such as models of artificial neural networks). Therefore, 3D NAND is required to have larger storage capacity and higher recording density compared to faster operating speeds.

[0245] Hard drives offer large capacity and are non-volatile. Alternatively, SSDs (Solid State Drives) can be used as replacements for hard drives.

[0246] One aspect of the present invention includes a storage device comprising a capacitor containing a ferroelectric material that can retain data for a long period of time. Therefore, it can be applied to... Figure 10 The area shown in the middle is designated as target 1. Note that, as... Figure 10 As indicated by the shading with diagonal lines, target 1 includes a portion of the cache (L1, L2, L3) and a portion of the 3D NAND. In other words, target 1 has boundary regions between DRAM and 3D NAND, and boundary regions between DRAM and the cache (L1, L2, L3). Furthermore, one aspect of the invention, including a memory device containing a ferroelectric capacitor, operates at high speed, thus enabling good write and read operations. Therefore, it can be applied to... Figure 10 The area shown in the middle is designated as target 2.

[0247] For example, preferred to Figure 10The DRAM shown is replaced by a memory device comprising a capacitor containing ferroelectric elements, as described in one aspect of the present invention. Here, because the DRAM requires refresh operations, its power consumption is higher compared to other memory devices. Therefore, by replacing the DRAM with a memory device comprising a capacitor containing ferroelectric elements, power consumption can be reduced. By adopting this structure, compared to a structure using DRAM, power consumption can be reduced to less than one-half, preferably less than one-tenth, more preferably less than one-hundredth, and even more preferably less than one-thousandth.

[0248] Furthermore, as another method to reduce power consumption, a structure can be cited where a computing processing device such as a CPU, GPU, or NPU has a storage device such as DRAM or FeRAM (including a semiconductor device according to one aspect of the present invention) stacked on top of it. Moreover, the structure formed by stacking computing processing devices and storage devices is called a monolithic stack. By having a monolithic stack structure for the computing processing device and storage device, the power consumption required for data access between the computing processing device and the storage device can be significantly reduced, for example. Therefore, by promoting information processing devices including supercomputers (also known as HPCs, high-performance computers), computers, servers, etc., with this structure globally, global warming can be mitigated.

[0249] Thus, according to one aspect of the present invention, the memory device using oxide semiconductors can be used in a wide range of memories, such as memories installed as registers in computing devices such as CPUs, GPUs, and NPUs, to memories in the boundary region between DRAM and 3D NAND.

[0250] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0251] (Implementation Method 4) In this embodiment, refer to Figure 11A and Figure 11B An example of a chip 1200 in which the semiconductor device of the present invention is mounted is described. Multiple circuits (systems) are mounted on the chip 1200. Thus, the technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a System on Chip (SoC).

[0252] like Figure 11AAs shown, chip 1200 includes CPU 1211, GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, and one or more network circuits 1216.

[0253] The chip 1200 has a bump (not shown), which is as follows: Figure 11B It is connected to the first side of the packaging substrate 1201 as shown. In addition, a plurality of bumps 1202 are provided on the back side opposite to the first side of the packaging substrate 1201, and the plurality of bumps 1202 are connected to the mother plate 1203.

[0254] Alternatively, a storage device such as a DRAM 1221 or a flash memory 1222 may be provided on the motherboard 1203. For example, the DRAM 1221 and the flash memory 1222 may be replaced by the storage device SCD described in the previous embodiment 1.

[0255] CPU 1211 preferably has multiple CPU cores. Furthermore, GPU 1212 preferably has multiple GPU cores. Additionally, CPU 1211 and GPU 1212 may each have their own temporary data storage memory. Alternatively, a shared memory for both CPU 1211 and GPU 1212 may be provided on chip 1200. This memory can be the aforementioned storage device SCD. Furthermore, GPU 1212 is suitable for parallel computation of multiple data sets, and can be used for image processing or product operations.

[0256] Furthermore, since the CPU1211 and GPU1212 are located on the same chip, the wiring between the CPU1211 and GPU1212 can be shortened, and high-speed data transfer from the CPU1211 to the GPU1212, data transfer between the memory of the CPU1211 and GPU1212, and transfer of the operation result from the GPU1212 to the CPU1211 after the operation in the GPU1212 is completed can be performed.

[0257] The analog arithmetic unit 1213 includes one or both of an AD (analog-to-digital) conversion circuit and a DA (digital-to-analog) conversion circuit. Alternatively, the aforementioned product summation circuit may also be provided in the analog arithmetic unit 1213.

[0258] The memory controller 1214 has circuitry that serves as a controller for the DRAM 1221 and circuitry that serves as an interface for the flash memory 1222.

[0259] Interface 1215 has interface circuitry for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game console controllers. As the aforementioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc., can be used.

[0260] Network circuit 1216 includes network connection circuits such as LAN (Local Area Network). Additionally, it may include network security circuits.

[0261] The aforementioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, no additional manufacturing steps are needed, and chip 1200 can be manufactured at low cost.

[0262] The motherboard 1203, which includes a package substrate 1201 containing a chip 1200 with a GPU 1212, a DRAM 1221, and a flash memory 1222, can be referred to as a GPU module 1204.

[0263] The GPU module 1204 can be smaller in size because it incorporates the chip 1200 using SoC technology. Furthermore, the GPU module 1204, due to its high image processing capabilities, is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Additionally, the product-sum operation circuitry in the GPU 1212 can be used for computations such as deep neural networks (DNNs) for AI models. Representative examples of AI models include convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0264] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0265] (Implementation Method 5) In this embodiment, an application example of a semiconductor device using a storage device according to one aspect of the present invention will be described. The storage device SCD shown in the above embodiment can be used in various removable storage devices such as cache memory, memory cards (e.g., SD cards) as main memory, USB memory, and SSD (solid-state drive). Figures 12A to 12E Several structural examples of removable storage devices are illustrated schematically. For example, a semiconductor device according to one aspect of the present invention is fabricated as a packaged memory chip and used in various auxiliary storage devices or removable memories.

[0266] Figure 12A This is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed within the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on the substrate 1104. A semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1105, etc.

[0267] Figure 12B This is a schematic diagram of the SD card's appearance. Figure 12C This is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a frame 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed within the frame 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also providing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on the substrate 1113. Thus, through wireless communication between the host device and the SD card 1110, data can be read from and written to the memory chip 1114. A semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1114, etc.

[0268] Figure 12D This is a schematic diagram of the SSD's appearance. Figure 12E This is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The substrate 1153 is housed within the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are mounted on the substrate 1153. The memory chip 1155 serves as the working memory for the controller chip 1156; for example, a DOSRAM chip can be used. By also providing the memory chip 1154 on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device according to one aspect of the present invention can be assembled onto the memory chip 1154, etc.

[0269] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0270] (Implementation Method 6) In this embodiment, electronic components, electronic devices, mainframe computers, space devices, and data centers (also known as DCs) of the semiconductor devices described in the above embodiments are explained. Electronic components, electronic devices, mainframe computers, space devices, and data centers using one aspect of the present invention are highly effective for achieving high performance, such as low power consumption.

[0271] [Electronic Components] Figure 13A A three-dimensional view of electronic component 700 is shown. Figure 13A The illustrated electronic component 700 includes a substrate 701, a semiconductor device 710 on the substrate 701, and a mold 711. Specifically, the semiconductor device 710 is sealed by the mold 711. Note that in... Figure 13A In the text, a portion of the description of electronic component 700 is omitted to indicate its internal structure.

[0272] As the substrate 701, for example, a ceramic substrate, a plastic substrate, or a glass epoxy board can be used.

[0273] Electronic component 700 is provided with, for example, a lead frame 712. A portion of the lead frame 712 located on substrate 701 is covered by mold 711, and another portion of the lead frame 712 is exposed outside of mold 711. In particular, the lead frame 712 exposed outside of mold 711 is used, for example, as a terminal for mounting electronic component 700 to a printed circuit board.

[0274] Within the mold 711, electrode pads 713 are provided on the lead frame 712, and the electrode pads 713 are connected to the semiconductor device 710 via leads 714. Electronic components 700 are mounted on the printed circuit board, for example, by bringing the lead frame 712 into contact with wiring on one side of the printed circuit board. Thus, a circuit board is manufactured by assembling multiple electronic components and connecting them individually on the printed circuit board.

[0275] Next, the semiconductor device 710 will be described. For example, such as Figure 13BAs shown, the semiconductor device 710 includes, for example, a driver circuit layer 715 and a memory layer 716. The memory layer 716 may have a structure with multiple memory cell arrays stacked on top of each other. The stacked structure of the driver circuit layer 715 and the memory layer 716 can be a monolithic stacked structure. As a structure other than a monolithic stack, examples include structures that stack multiple memory layers 716 using through-electrode technology (e.g., TSV (Through Silicon Via)) and Cu-Cu direct bonding technology. By stacking the driver circuit layer 715 and the memory layer 716, for example, a so-called on-chip memory structure in which memory is directly formed on the processor can be realized. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0276] Furthermore, by arranging the semiconductor device 710 in a multi-cell array stacked structure, either or both of the memory bandwidth and memory access latency can be improved. Bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time between accessing and starting data exchange.

[0277] Furthermore, the semiconductor device 710 may be referred to as a bare die. In this specification, a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) and cutting it into rectangular pieces during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for bare dies include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon wafer.

[0278] then, Figure 13C A variation example of electronic component 700 is shown. Figure 13C The electronic component 700A shown differs from electronic component 700 in that it does not use a lead frame 712, and an electrode 733 is provided on the bottom of the substrate 701. The electrode 733 is used as a connection terminal for mounting electronic component 700A onto a printed circuit board.

[0279] Figure 13C An example of forming electrode 733 using solder balls is shown. BGA (Ball Grid Array) mounting can be achieved by arranging solder balls in a matrix pattern at the bottom of substrate 701. Therefore, substrate 701 is provided with through-holes, on which conductive layers 732 for wiring are disposed. Electrode pads 713 are disposed on substrate 701 above the conductive layer 732 in contact with ground, and electrodes 733 are disposed on substrate 701 below the conductive layer 732 in contact with ground.

[0280] Furthermore, electrode 733 can also be formed using conductive pins instead of solder balls. By arranging conductive pins in a matrix at the bottom of substrate 701, PGA (Pin Grid Array) mounting can be achieved.

[0281] Furthermore, the 700A electronic component can be mounted on other substrates using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0282] Alternatively, the electronic component of one embodiment of the present invention can also be in the form of SiP (System in Package) or MCM (Multi-Chip Module). For example, in Figure 13D In the electronic component 700C shown, an interposer 731 is provided on the packaging substrate 734 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0283] Figure 13D The electronic component 700C illustrates an example of using the semiconductor device 710 as a high-bandwidth memory (HBM). For example, the semiconductor device 735 can be used as a computing circuit in integrated circuits such as CPUs, GPUs, or FPGAs (Field Programmable Gate Arrays).

[0284] Similar to substrate 701, packaging substrate 734 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. Through-hole plate 731 can be, for example, a silicon through-hole plate or a resin through-hole plate.

[0285] The through-hole board 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal spacings. The multiple wirings are composed of a single layer or multiple layers. Furthermore, the through-hole board 731 functions to connect the integrated circuits disposed on the through-hole board 731 to electrodes disposed on the package substrate 734. Therefore, the through-hole board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". Additionally, sometimes a through electrode is provided in the through-hole board 731, through which the integrated circuit is connected to the package substrate 734. Furthermore, in the case of using a silicon through-hole board, a TSV can also be used as the through electrode.

[0286] In HBM, numerous wirings are required to achieve wide memory bandwidth. Therefore, the mounting board for HBM must be capable of forming fine wirings at high density. Consequently, silicon mounting boards are preferred as mounting boards for HBM.

[0287] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in the coefficients of thermal expansion between the integrated circuits and the interposer is less likely to occur. Additionally, due to the high surface flatness of the silicon interposer, poor connection between the integrated circuits mounted on the interposer and the interposer is less likely to occur. Silicon interposers are particularly preferred for 2.5D packaging (2.5D mounting), where multiple integrated circuits are arranged horizontally and disposed on the interposer.

[0288] Furthermore, when the temperature of the electronic component 700C rises due to current heat or other reasons, the characteristics of the circuit elements (e.g., transistors) included in the electronic component 700C may degrade. Therefore, it is preferable to provide a heat sink (heat plate) overlapping the electronic component 700C. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the insert 731 consistent. For example, in the electronic component 700C shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0289] [Electronic Devices] then, Figure 14A A 3D view of electronic device 6500 is shown. Figure 14A The illustrated electronic device 6500 is a portable information terminal device that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, one or more selected from a CPU, a GPU, and memory circuitry. In one aspect of the present invention, a semiconductor device can be included as main memory in the electronic device 6500. Alternatively, in another aspect of the present invention, the semiconductor device can also be used for the display unit 6502, the control device 6509, etc.

[0290] Figure 14B The illustrated electronic device 6600 is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. The control device 6616 includes, for example, one or more selected from a CPU, a GPU, and memory circuitry. In one aspect of the present invention, a semiconductor device can be included as main memory in the electronic device 6600. Alternatively, in another aspect of the present invention, the semiconductor device can also be used in the display unit 6615, the control device 6616, etc.

[0291] By installing a semiconductor device according to one aspect of the present invention in the above-mentioned electronic devices 6500 and 6600, power consumption can be reduced, which is therefore preferred.

[0292] [Mainframe Computer] then, Figure 14C A 3D view of the 5600 mainframe computer is shown. Figure 14C In the mainframe computer 5600 shown, multiple rack-mounted computers 5620 are housed in rack 5610. Alternatively, the mainframe computer 5600 can also be referred to as a supercomputer.

[0293] Computer 5620, for example, can have Figure 14D The structure of the 3D diagram shown. Figure 14D In the computer 5620, a motherboard 5630 is included, which includes multiple slots 5631 and multiple connection terminals. A personal computer card 5621 is inserted into the slots 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0294] Figure 14E The personal computer card 5621 shown is an example of a processing board including a CPU, GPU, storage device, etc. The personal computer card 5621 includes a board 5622. Furthermore, the board 5622 includes connection terminals 5623, 5624, and 5625, semiconductor devices 5626, 5627, and 5628, and a connection terminal 5629. Note that... Figure 14E Semiconductor devices other than semiconductor devices 5626, 5627 and 5628 are shown. For a description of these semiconductor devices, please refer to the description of semiconductor devices 5626, 5627 and 5628 described below.

[0295] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 on the motherboard 5630. The connection terminal 5629 is used as an interface for connecting the personal computer card 5621 to the motherboard 5630. Examples of specifications for the connection terminal 5629 include PCIe.

[0296] Connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for powering or inputting signals to the personal computer card 5621. Furthermore, they can be used, for example, as interfaces for outputting signals calculated by the personal computer card 5621. Examples of specifications for connection terminals 5623, 5624, and 5625 include, for example, USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from connection terminals 5623, 5624, and 5625, examples of specifications include HDMI (registered trademark).

[0297] Semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting these terminals into a socket (not shown) included in board 5622, semiconductor device 5626 and board 5622 can be electrically connected.

[0298] Semiconductor device 5627 includes multiple terminals, which can be electrically connected to board 5622 by reflow soldering the terminals to wiring included in board 5622. Examples of semiconductor devices 5627 include FPGA, GPU, and CPU. Electronic component 700 can also be used as semiconductor device 5627.

[0299] Semiconductor device 5628 includes a plurality of terminals, which can be electrically connected to board 5622, for example, by reflow soldering the terminals to wiring included in board 5622. As semiconductor device 5628, for example, a memory device of one embodiment of the present invention can be used. Semiconductor device 5628 can, for example, use the electronic component 700 described above.

[0300] The 5600 mainframe computer can be used as a parallel computer. By using the 5600 mainframe computer as a parallel computer, large-scale computations required for artificial intelligence learning and inference can be performed, for example.

[0301] [Space Equipment] The semiconductor device of one aspect of the present invention can be applied to space devices such as equipment for processing and storing information.

[0302] exist Figure 15A The image shows an artificial satellite 6800 as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control unit 6807. Furthermore, Figure 15A An example of a planet 6804 in outer space is shown. Note that outer space, for example, refers to an altitude of 100 km or higher, but outer space as described in this specification sometimes includes the thermosphere, mesosphere, and stratosphere.

[0303] In addition, although Figure 15A Although not illustrated, a battery management system (also known as a BMS) or battery control circuit can also be installed in the secondary battery 6805.

[0304] Furthermore, outer space is an environment where the radiation dose is more than 100 times that of the Earth's surface. Examples of radiation include electromagnetic waves (electromagnetic radiation), represented by X-rays and gamma rays; and particle radiation, represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0305] The solar panel 6802 generates the power required for the satellite 6800 to operate when sunlight shines on it. However, the generated power decreases, for example, when sunlight does not reach the solar panel or when the amount of sunlight reaching the solar panel is low. Therefore, it is possible that the power required for the satellite 6800 to operate may not be generated. In order to enable the satellite 6800 to operate even when the generated power is low, it is preferable to provide a secondary battery 6805 in the satellite 6800. Furthermore, the solar panel is sometimes referred to as a solar cell module.

[0306] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received, for example, by a ground receiver or other satellites. By receiving the signal transmitted by satellite 6800, the position of the receiver can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0307] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 uses, for example, one or more selected from a CPU, GPU, and storage device. Additionally, a semiconductor device according to one aspect of the present invention is preferably used as the control device 6807.

[0308] Furthermore, satellite 6800 may include sensors. For example, by including a visible light sensor, satellite 6800 may be able to detect sunlight reflected by objects on the ground. Alternatively, by including a thermal infrared sensor, satellite 6800 may be able to detect thermal infrared radiation emitted from the Earth's surface. Thus, satellite 6800 can be used, for example, as an Earth observation satellite.

[0309] Note that in this embodiment, an artificial satellite is shown as an example of a space device, but the invention is not limited thereto. For example, a semiconductor device according to one aspect of the invention can be suitably applied to space devices such as spacecraft, space capsules, and space probes.

[0310] [Data Center] For example, the semiconductor device of one aspect of the present invention can be applied to storage systems used in data centers, etc. Data centers are required to manage data over long periods, ensuring data immutability, etc. Long-term data management necessitates large-scale facilities, such as installing storage and servers to store massive amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment is available for data retention.

[0311] By using the semiconductor device of one aspect of the present invention in a storage system employed in a data center, it is possible to reduce the power required to retain data and to miniaturize the semiconductor device used to retain data. Therefore, it is possible to miniaturize the storage system, reduce the size of the power supply used to retain data, and decrease the size of the cooling equipment. This, in turn, enables space-saving in data centers.

[0312] Furthermore, the semiconductor device according to one aspect of the present invention has low power consumption, thus reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Moreover, by using the semiconductor device according to one aspect of the present invention, data centers can operate stably even in high-temperature environments. Therefore, the reliability of data centers can be improved.

[0313] Figure 15B This illustrates a storage system that can be used in a data center. Figure 15B The storage system 7000 shown includes multiple servers 7001sb as hosts 7001 (illustrated as host computers). Additionally, multiple storage devices 7003md are included as storage (illustrated as storage). The host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as a SAN) and a storage control circuit 7002 (illustrated as a storage controller).

[0314] Host 7001 corresponds to the computer that accesses data stored in storage 7003. Hosts 7001 can also connect to each other via a network.

[0315] In the 7003 memory, flash memory is used to reduce data access speed, i.e., to shorten the time required for data storage and output. However, this time is much longer than that required by DRAM, which can be used as a cache memory in the memory. In memory systems, to address the issue of the long access speed of the 7003 memory, a cache memory is generally incorporated into the memory to further reduce the time required for data storage and output.

[0316] The aforementioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is output to the host 7001 or the storage 7003 after being stored in the cache memory in the storage control circuit 7002 and the storage 7003.

[0317] When OS transistors are used to maintain the voltage corresponding to the data in the aforementioned cache memory, the refresh frequency can be reduced to lower power consumption. Furthermore, miniaturization can be achieved through stacked memory cell arrays.

[0318] Note that by using the semiconductor device of one aspect of the present invention in any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers, a reduction in power consumption can be expected. Therefore, it is currently believed that with the increasing energy demands of high-performance or highly integrated semiconductor devices, the use of the semiconductor device of one aspect of the present invention can also reduce emissions of greenhouse gases, such as carbon dioxide (CO2). Furthermore, the semiconductor device of one aspect of the present invention has low power consumption, and is therefore effective as a measure against global warming.

[0319] Note that this embodiment can be appropriately combined with the same or other embodiments shown in this specification. For example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with other configurations, structures, methods, etc. shown in this embodiment. Furthermore, for example, the configurations, structures, methods, etc. shown in this embodiment can be appropriately combined with the configurations, structures, methods, etc. shown in other embodiments.

[0320] [Symbol Explanation] BL: Wiring, BS: Substrate, CFE: Capacitor, Cfe: Capacitor, DCF: Capacitor, FDI: Insulating Layer, GI: Insulating Layer, LRa: Low Resistance Region, LRb: Low Resistance Region, LRc: Low Resistance Region, MC: Memory Cell, MZ: Trench, PL: Wiring, SAb: Semiconductor Region, SAc: Semiconductor Region, SCD: Memory Device, ST: Component Separation Layer, T11: Time, T12: Time, T13: Time, T14: Time, T15: Time, T16: Time, T17: Time, T18: Time, T19: Time, TA: Transistor Region, Tr: Transistor, TrP: Transistor, TrQ: Transistor, WL: Wiring, 61: Curve, 62: Curve, 700: Electronic component, 700A: Electronic component, 700C: Electronic component, 701: Substrate, 710: Semiconductor device, 711: Mold, 712: Lead frame, 713: Electrode pad, 714: Lead, 715: Driver circuit layer, 716: Storage layer, 731: Through-hole board, 732: Conductive layer, 733: Electrode, 734: Packaging substrate, 735: Semiconductor device, 1100: USB memory, 1101: Frame, 1102: Cover, 1103: USB connector, 1104: Substrate, 1105: Memory chip, 1106: Controller chip, 1110: SD card, 1111: Frame, 1112: Connector, 1113: Substrate, 1114: Storage 1115: Controller chip; 1150: SSD; 1151: Frame; 1152: Connector; 1153: Substrate; 1154: Memory chip; 1155: Memory chip; 1156: Controller chip; 1200: Chip; 1201: Packaging substrate; 1202: Bump; 1203: Motherboard; 1204: GPU module; 1211: CPU; 1212: GPU; 1213: Analog processing unit; 1214: Memory controller; 1215: Interface; 1216: Network circuit; 1221: DRAM; 1222: Flash memory; 1400: Storage device; 1411: Peripheral circuit; 1420: Row circuit; 1430: Column circuit; 1440: Output circuit. 1460: Control logic circuit; 1470: Memory cell array; 1480: Memory cell; 5600: Mainframe computer; 5610: Rack; 5620: Computer; 5621: Personal computer card; 5622: Board; 5623: Connection terminal; 5624: Connection terminal; 5625: Connection terminal; 5626: Semiconductor device; 5627: Semiconductor device; 5628: Semiconductor device; 5629: Connection terminal; 5630: Motherboard; 5631: Slot; 6500: Electronic device; 6501: Frame; 6502: Display unit; 6503: Power button; 6504: Button; 6505: Speaker; 6506: Microphone; 6507: Camera; 6508: Light source.6509: Control device; 6600: Electronic device; 6611: Frame; 6612: Keyboard; 6613: Pointing device; 6614: External connection port; 6615: Display unit; 6616: Control device; 6800: Artificial satellite; 6801: Main body; 6802: Solar panel; 6803: Antenna; 6804: Planet; 6805: Secondary battery; 6807: Control device; 7000: Storage system; 7001: Host computer; 7001sb: Server; 7002: Storage control circuit; 7003: Storage; 7003md: Storage device.

Claims

1. A semiconductor device, comprising: Substrate; Component separation layer; First conductive layer; Second conductive layer; Third conductive layer; Fourth conductive layer; Fifth conductive layer; First insulating layer; First plug; Second plug; Third plug; Fourth plug; as well as Fifth plug, The substrate has a first low-resistance region serving as one of the source and drain of the transistor, a second low-resistance region serving as the other of the source and drain of the transistor, and a semiconductor region forming the channel of the transistor. The transistor includes a portion of the first conductive layer that serves as a gate. The first insulating layer comprises a material that can be ferroelectric. Viewed in cross-section, the height of the third conductive layer is greater than the width of the third conductive layer. Viewed in cross-section, the height of the fourth conductive layer is greater than the width of the fourth conductive layer. The first plug has a region that contacts the first low-resistance region. The second conductive layer has an area that contacts the first plug. The second plug has a region that contacts the second low-resistance region. The third plug has an area that contacts the second plug. Viewed from a plan view, the third conductive layer is located in the area that contacts the top surface of the third plug and overlaps with the first conductive layer. The fourth plug has an area that contacts the component separation layer. The fifth plug has an area that contacts the fourth plug. Viewed from the plan, the fourth conductive layer is located in the area that contacts the top surface of the fifth plug and overlaps with the component separation layer. The first insulating layer has areas that contact the side surfaces and top surfaces of the third and fourth conductive layers. When viewed from a plan view, the fifth conductive layer has an area that overlaps with the first conductive layer and contacts the side and top surfaces of the first insulating layer. The first conductive layer and the fifth conductive layer are each configured to extend in a first direction. The second conductive layer is configured to extend in a second direction. Furthermore, the first direction is approximately perpendicular to the second direction.

2. The semiconductor device according to claim 1, The ferroelectric material described herein comprises an oxide containing one or both of hafnium and zirconium.

3. The semiconductor device according to claim 1 or 2, further comprising: Second insulating layer, The substrate includes a trench. Viewed from the plan view, the groove is located between the first low-resistance region and the second low-resistance region. The second insulating layer is located in the area that contacts the side and bottom surfaces of the groove. Furthermore, the semiconductor region is located in the area opposite to the first conductive layer, separated by the second insulating layer.

Images