Integrated circuit with reduced contact area mimcap

Abstract

Integrated circuit devices (300, 400, 500, 600, 700, 800) and related manufacturing methods are disclosed. The integrated circuit devices include a metal-insulator-metal capacitor (MIMCAP) (305) in a dielectric layer (310) above a semiconductor substrate (315). The MIMCAP has a top plate (320, 335) and a bottom plate (325), the bottom plate having a lateral perimeter defining a lateral region of the bottom plate. A first metal interconnect layer (340) above the MIMCAP is connected to the top plate. A second metal interconnect layer (350, 405, 550, 650, 750, 850) below the MIMCAP contacts the bottom plate. The contact area (327) between the second metal interconnect layer and the bottom plate is smaller than the lateral region of the bottom plate.

Description

Background Technology

[0001] Integrated circuit (IC) devices typically contain transistors, capacitors, and other semiconductor-based components. For example, metal-insulator-metal capacitors (MIMCAPs) are generally considered important passive components in IC devices, including radio frequency (RF) and analog ICs. MIMCAPs allow for high capacitance density within a relatively small chip area, which increases circuit density and further reduces IC manufacturing costs. However, the manufacturing cost of such ICs is inversely proportional to product yield, as it can be reduced due to factors such as the low breakdown voltage of these capacitors. Summary of the Invention

[0002] The present invention is provided to introduce a series of concepts further described below in the detailed description. The present invention is not intended to identify essential features of the claimed subject matter, nor is it intended to help limit the scope of the claimed subject matter.

[0003] This disclosure introduces an IC comprising a MIMCAP in a dielectric layer above a semiconductor substrate, a first metal interconnect layer above the MIMCAP, and a second metal interconnect layer below the MIMCAP. The MIMCAP has a top plate and a bottom plate, the bottom plate having a lateral periphery defining a lateral region of the bottom plate. The first metal interconnect layer is connected to the top plate. The second metal interconnect layer contacts the bottom plate. The contact area between the second metal interconnect layer and the bottom plate is smaller than the lateral region of the bottom plate.

[0004] This disclosure also introduces a method of manufacturing an IC device, wherein a plurality of layers are formed over a semiconductor substrate, including a lower metal layer and at least one dielectric layer over the lower metal layer. A plurality of openings are formed in the at least one dielectric layer, thereby exposing portions of the upper surface of the lower metal layer. Each of the openings is lined with an outer conductive layer, an inner conductive layer, and a non-conductive layer inserted into the inner conductive layer and the outer conductive layer, all contacting the lower metal layer. The method further includes: forming a plurality of conductive plugs, each conductive plug filling a corresponding one of the lined openings; forming a plurality of vias, each via contacting a corresponding one of the conductive plugs; and forming an upper metal layer contacting each of the vias. The contact area between each outer conductive layer and the lower metal layer is smaller than the bottom surface area of ​​the outer conductive layer.

[0005] This disclosure also introduces an IC device comprising multiple layers formed above a semiconductor substrate, including a lower metal layer, an upper metal layer, and at least one dielectric layer interposed between the lower metal layer and the upper metal layer. The IC device further comprises multiple metal plates, each metal plate having a bottom surface. A contact area between each metal plate and the lower metal layer extends from a first side of the periphery of the metal plate to an opposite side of the periphery and is smaller than the bottom surface area of ​​the metal plate.

[0006] These and additional aspects of this disclosure are set forth in the following description and / or may be learned by those skilled in the art by reading the material herein and / or practicing the principles described herein. At least some aspects of this disclosure may be implemented by means of the means set forth in the appended claims. Attached Figure Description

[0007] This disclosure shall be understood in conjunction with the accompanying drawings and the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various features are not drawn to scale. In some cases, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 This is a floor plan diagram as part of an example implementation of an IC that includes MIMCAP.

[0009] Figure 2 yes Figure 1 The cross-sectional view of the IC portion shown.

[0010] Figure 3 yes Figure 1 and 2 The cross-sectional perspective view of the IC portion shown.

[0011] Figure 4 It is a description Figures 1 to 3 The graph depicts the cumulative probability of breakdown voltage for MIMCAP.

[0012] Figure 5 It is a plan view as part of an example implementation of an IC including MIMCAP according to one or more aspects introduced in this disclosure.

[0013] Figure 6 yes Figure 5 The cross-sectional view of the IC portion shown.

[0014] Figure 7 yes Figure 5 and 6 The cross-sectional perspective view of the IC portion shown.

[0015] Figure 8 It is a description Figures 5 to 7The graph depicts the cumulative probability of breakdown voltage for MIMCAP.

[0016] Figures 9 to 13 This is a cross-sectional view as part of an example embodiment of an IC at various manufacturing stages according to one or more aspects introduced in this disclosure.

[0017] Figures 14 to 17 It is a plan view of a portion of an additional example implementation of an IC including MIMCAP, based on one or more aspects introduced in this disclosure. Detailed Implementation

[0018] It should be understood that the following disclosure provides many different examples of various features for various embodiments. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these components and arrangements are merely examples and are not intended to be limiting. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself define the relationship between the various examples and / or configurations discussed. Additionally, in the following description, the formation of a first feature above or on a second feature may include examples where the first and second features are formed in direct contact, and may also include examples where additional features may be formed to insert the first and second features such that the first and second features are not in direct contact.

[0019] Figure 1 This is a plan view of a portion of IC 100, which includes a plurality of MIMCAP 105s interconnected in a dielectric layer 110 above a semiconductor substrate 115 and in a baseline embodiment. Figure 2 yes Figure 1 A cross-sectional side view of a portion of IC 100 shown. Figure 3 yes Figure 1 The diagram shows a perspective view of the portion of IC 100 excluding the dielectric layer 110. The following description commonly refers to... Figures 1 to 3 .

[0020] Each MIMCAP 105 may have one or more aspects as described in U.S. Patent No. 11,075,157, which is hereby incorporated herein by reference. For example, each MIMCAP 105 has a metal top plate 120 and a metal bottom plate 125. The bottom plate 125 is generally cup-shaped, having cylindrical walls 126 extending upward from a lower disc-shaped portion 127. An insulator 130 is lined to the inner surface of the bottom plate 125, thereby electrically insulating the bottom plate 125 from the top plate 120. Figure 2 and 3As depicted, the top plate 120 may also be the generally cup-shaped inner lining side surface and bottom surface of the conductive plug 135, but in other embodiments, the top plate 120 and the plug 135 may be an integral component.

[0021] The IC also includes an upper metal interconnect layer 140 above the MIMCAP 105 and connected to each MIMCAP 105 via corresponding vias 145. A lower metal interconnect layer 150 contacts the base plate 125 of each MIMCAP 105. The lower metal interconnect layer 150 interconnects the MIMCAP 105 to form a first terminal of the array capacitor, and the upper metal interconnect layer 140 interconnects the MIMCAP 105 to form a second terminal of the array capacitor. The lower interconnect layer 150 is a continuous plate such that the contact area between the lower interconnect layer 150 and each base plate 125 is equal to the surface area of ​​the bottom of the base plate 125.

[0022] Figure 4 It is a display similar to Figures 1 to 3 The graph depicts a normal probability plot of the cumulative probability (%) of the normalized breakdown voltage of those MIMCAPs. The graph shows that in the baseline embodiment, the breakdown voltage of a subset 200 (approximately 10%) of the tested MIMCAPs deviates significantly from a normal distribution. It is believed that the extension of the underlying interconnect layer 150 causes the breakdown voltage failure depicted in the graph by weakening the structure of MIMCAP 105. It is further believed that the periphery of the base plate 125 overlapping with the underlying interconnect layer 150 may also be causally related to the occurrence of MIMCAP 105 breakdown. As a result of their research, the inventors have determined that reducing the contact area between the underlying interconnect layer 150 and the bottom of MIMCAP 105 provides a surprising and unexpected improvement in the variability of the breakdown voltage of MIMCAP 105.

[0023] For example, Figure 5 This is a plan view as part of an example embodiment of IC 300 according to one or more aspects introduced in this disclosure. IC 300 includes a plurality of MIMCAP 305s in a dielectric layer 310 above a semiconductor substrate 315. Figure 6 yes Figure 5 A cross-sectional side view of a portion of the IC 300 shown. Figure 7 yes Figure 5 The diagram shows a perspective view of the portion of IC 300 excluding the dielectric layer 310. The following description commonly refers to... Figures 5 to 7 .

[0024] Each MIMCAP 305 may be the MIMCAP 105 described above, and is shown in the example as substantially similar to the MIMCAP 105 described above, including a metal top plate 320 and a bottom plate 325 similar to the respective top plate 120 and bottom plate 125, an insulator 330 similar to an insulator 130, and a conductive plug 335 similar to a conductive plug 135. However, instead of a continuous board formed by the lower metal interconnect layer 150, the IC 300 includes a plurality of straight or otherwise elongated lower metal interconnects 350 interconnecting a subset of the MIMCAP 305. That is, the lower metal interconnects 350 are metal traces that contact one or more bottom plates 325 and have a linewidth smaller than the diameter of the bottom plates 325. In some examples, and as shown, the linewidth is approximately equal to the width of the via 345 contacting the top of the MIMCAP 305.

[0025] Therefore, similar to the MIMCAP 105 described above, the base plate 325 of the MIMCAP 305 has a lateral periphery defining a lateral region 326. However, the contact area 327 between the lower metal interconnect 350 and the corresponding base plate 325 is smaller than the lateral region 326 of the base plate. For example, in Figures 5 to 7 In the embodiment depicted, the contact area 327 is approximately 40% of the transverse area 326 of the base plate. However, in other embodiments within the scope of this disclosure, the contact area 327 may be 20% to 80% of the transverse area 326 of the base plate, depending on, for example, the diameter of the base plate 325 and the width of the through hole 345. In other embodiments within the scope of this disclosure, the contact area 327 may be 30% to 50% of the transverse area 326 of the base plate, for example, to effectively reduce the overlap between the periphery 327 of the base plate 325 and the lower metal interconnect 350.

[0026] like Figure 5 As depicted, the MIMCAP 305 is arranged as a linear set, array, or "columns" 301, 302 and rows 303, 304. Such an arrangement may also be referred to as a hexagonal array. Each linear arrangement has one corresponding MIMCAP 305 in each of the columns 301, 302 of the metal interconnects 350. Each column 301, 302 is staggered relative to its adjacent columns 301, 302, such that each row 303, 304 does not include a MIMCAP 305 in its adjacent columns 301, 302. This arrangement allows for high capacitor density in a relatively small chip area, thereby increasing circuit density.

[0027] like Figure 6 As depicted, the interlayer dielectric 310 is laterally inserted into the lower metal interconnect 350, and the interlayer dielectric 351 is laterally inserted into the upper metal interconnect 340. Figure 7As depicted, the lower metal interconnect 350 can be interconnected via an additional portion 352 of the same metal layer.

[0028] Similar to IC 100 described above, IC 300 includes an upper metal interconnect layer connected to MIMCAP 305 via via 345. Figure 5 and 6 In this embodiment, the upper metal interconnect layer is depicted as a plurality of straight or otherwise elongated upper metal interconnects 340, each upper metal interconnect having the same dimensions as the lower metal interconnect 350. However, in other embodiments also within the scope of this disclosure, the upper metal interconnects 340 may be formed differently from the lower metal interconnect 350. For example, such as Figure 7 As depicted in the text, Figure 5 and 6 The upper metal interconnect 340 depicted herein can be similar to Figures 1 to 3 The continuous plate of the upper metal interconnect layer 140 depicted herein is replaced. In either case, the lower metal interconnect 350 interconnects the MIMCAP 305 to form the first terminal of the array capacitor, and the upper metal interconnect 340 interconnects the MIMCAP 305 to form the second terminal of the array capacitor.

[0029] Figure 8 It is a display similar to Figures 5 to 7 The diagram depicts a normal probability plot of the cumulative probability (%) of the breakdown voltage (normalized) of those MIMCAPs. The graph shows that, in embodiments according to this disclosure, the low breakdown voltage outliers described above can be reduced or eliminated due to the reduction of the contact area between the lower metal interconnect 350 and the MIMCAP 305.

[0030] Figure 9 This is a cross-sectional view as part of an example embodiment of IC 400 during an intermediate manufacturing stage according to one or more aspects of this disclosure. Upon completion, IC 400 will comprise multiple MIMCAPs having one or more aspects common to the MIMCAP 305 described above.

[0031] IC 400 includes metal interconnects 404, 405, and 406 formed in openings in a dielectric layer 410 above substrate 402. Metal interconnects 404-406 may be aluminum, copper, or other conductive materials deposited by chemical vapor deposition (CVD) and / or other deposition processes. Metal interconnect 405 will form the lower interconnect of the MIMCAP, for example... Figures 5 to 7 The interconnect 350 shown.

[0032] For example, silicon nitride (SiN) or other insulating layers 415 are formed on interconnects 404-406 and dielectric layer 410 by CVD and / or other processes. Another dielectric layer 420 is formed on insulating layer 415, for example, on silicon dioxide (SiO2) produced by tetraethyl orthosilicate (TEOS) or other CVD methods. Dielectric layer 420 and insulating layer 415 are patterned, for example, by photolithography and plasma etching to form openings (e.g., trenches) 425 in which MIMCAPs will be formed.

[0033] Figure 10 This is a cross-sectional view of IC 400 during subsequent manufacturing stages. A metal layer 430 is formed on the exposed surfaces of dielectric layer 420, insulating layer 415, metal interconnect 405, and dielectric layer 410 (including the sidewalls of opening 425). Metal layer 430 may be tantalum / tantalum nitride (Ta / TaN) and / or other metallic materials deposited by CVD and / or other deposition processes. Metal layer 430 will form the base plate of MIMCAP, for example... Figures 5 to 7 The base plate 325 shown in the figure.

[0034] An insulating layer 435 is formed on the exposed surface of the metal layer 430. The insulating layer 435 may be an oxide-nitride-oxide (ONO) dielectric, and / or other insulating materials deposited by CVD and / or other deposition processes. The insulating layer 435 will serve as the capacitor dielectric of the MIMCAP insulator, for example... Figures 5 to 7 The insulator 330 shown.

[0035] Another metal layer 440 is formed on the exposed surface of the insulating layer 435. The metal layer 440 may be Ta / TaN and titanium / titanium nitride, or other metallic materials deposited by CVD and / or other deposition processes. Optionally, the metal layers 430 and 440 may have approximately the same thickness. The metal layer 440 will form the top plate of the MIMCAP, for example... Figures 5 to 7 The top plate 320 shown.

[0036] Another metal layer 445 is formed on the exposed surface of metal layer 440. Metal layer 445 may be tungsten or other metallic materials deposited via CVD and / or other deposition processes. Metal layer 445 will form the conductive plug of the MIMCAP, for example... Figures 5 to 7 The conductive plug 335 shown is shown.

[0037] In subsequent manufacturing stages, such as Figure 11As described, chemical mechanical planarization and / or other material removal processes have removed portions of the metal layers 445, 440, 435, and 430 above the dielectric layer 420. Therefore, a MIMCAP 450 with a conductive plug 446 has been formed in the previously formed opening 425 in the dielectric layer 420 and the insulating layer 415.

[0038] Figure 12 This is a cross-sectional view of IC 400 during a subsequent manufacturing stage, where a dielectric layer 455 has already been formed above the exposed surfaces of MIMCAP 450 and dielectric layer 420. A patterned photoresist layer 460 is used to form openings 465 in the dielectric layer 455 to expose the top surface of each MIMCAP 450, and to form openings 470 extending through the dielectric layer 455, dielectric layer 420, and insulating layer 415 to expose the top surface of the metal interconnect 404.

[0039] Figure 13 This is a cross-sectional view of a portion of IC 400 during subsequent manufacturing stages, where metal has been deposited in openings 465 and 470 to form metal interconnects 475 connected to via 480 and 476 connected to via 481. Via 480 extends through dielectric layer 455 and contacts the conductive plug 446 of MIMCAP 450. Via 481 extends through dielectric layer 455, dielectric layer 420, and insulating layer 415 and contacts metal interconnect 404. Metal interconnect 404 is connected via corresponding contacts 485 to the source / drain regions 490 of a transistor formed in substrate 402. The gate 495 of the transistor is similarly connected to another metal interconnect 407.

[0040] As mentioned above Figures 5 to 7 As described, the contact area between the lower metal interconnect 405 and the base plate of each MIMCAP 450 is smaller than the surface area of ​​the base plate of the MIMCAP 450. Furthermore, although the interconnect to the MIMCAP 450 is... Figure 13 The MIMCAP 450 is depicted in the first metal layer (lower metal interconnect 405) and the second metal layer (upper metal interconnect 475) of IC 400, but other metal layers of IC 400 (not shown) may be used instead to interconnect MIMCAP 450 with each other, and / or to interconnect MIMCAP 450 with transistors and / or other devices integrated with IC 400.

[0041] Furthermore, although the MIMCAP 450 is typically coupled to a node in the circuit system of the IC 400, the MIMCAP 450 board can also be provided as a separate pin of the IC. Example circuit functions include analog (e.g., amplifier or power converter), radio frequency (RF), digital, or non-volatile memory functions. The capabilities of the IC 400 can vary, ranging from simple to complex devices.

[0042] Figure 14 This is a plan view of a portion of IC 500 according to one or more aspects introduced in this disclosure. IC 500 is another example embodiment of an IC having an array of capacitors including MIMCAP 305. Figures 5 to 7 In the IC 300 shown, each lower metal interconnect 350 has a straight shape extending along the longitudinal axis so that each corresponding MIMCAP 305 in the interconnect column 301. However, in the IC 500, each lower metal interconnect 550 interconnects two adjacent MIMCAP 305s in columns 301, 302, and thus extends along two non-collinear axes. The lower metal interconnect 550 can otherwise be substantially similar to Figures 5 to 7 The IC 300 shown has a lower metal interconnect 350. For example, the contact area between each MIMCAP 305 and its underlying interconnect 550 is smaller than the lateral area of ​​the base plate of the MIMCAP 305 and has approximately the same width as the through hole 345.

[0043] Figure 15 This is a plan view of a portion of IC 600 according to one or more aspects introduced in this disclosure. IC 600 is another example embodiment of an IC having an array of capacitors including MIMCAP 305. Figures 5 to 7 In the IC 300 shown, each lower metal interconnect 350 has a straight shape with a constant width. However, each lower metal interconnect 650 of the IC 600 contacts the bottom of each corresponding MIMCAP 305 and has a path and linewidth (perpendicular to axis 651) along a single longitudinal axis 651, the linewidth decreasing from greater than the width of the via 345 to approximately the width of the via 345, wherein the lower metal interconnect 650 contacts the base plate 325. That is, each lower metal interconnect 650 may have a varying width, including a wide portion 652 between adjacent interconnect MIMCAP 305s, a narrow portion 653 below the via 345, and a tapering transition portion 654 between each adjacent pair of wide portions 652 and narrow portions 653. Figure 15The narrow portion 653 depicted has the same linewidth as the via 345, but other widths are possible. The wide portion 652 has a linewidth greater than that of the narrow portion 653, but less than the lateral diameter of the MIMCAP 305. IC 600 is an example embodiment in which the portion of the lower interconnect directly below the MIMCAP is not constrained to a minimum width (e.g., the width of the via 345). The lower metal interconnect 650 can otherwise be substantially similar to... Figures 5 to 7 The lower metal interconnect 350 of IC 300 shown.

[0044] Figure 16 This is a plan view of a portion of IC 700 according to one or more aspects introduced in this disclosure. IC 700 is another example embodiment of an IC having an array of capacitors including MIMCAP 305. In IC 700, a lower metal interconnect 750 has a first width 751 within the lateral periphery of MIMCAP 305, a second, larger width 752 outside the lateral periphery of MIMCAP 305, and a tapered transition portion 753 between the first width 751 and the second width 752. The first width 751 may be as small as the width of the via 345, and the second width 752 is larger than the first width 751 and may be any width between MIMCAP 305. The lower metal interconnect 750 may otherwise be substantially similar to Figures 5 to 7 The lower metal interconnect 350 of IC 300 shown.

[0045] Figure 17 This is a plan view of a portion of IC 800 according to one or more aspects introduced in this disclosure. IC 800 is another example embodiment of an IC having an array of capacitors including MIMCAP 305. In IC 800, the lower metal interconnect includes trace portions 851 in a lower metal layer 850, each trace portion 851 being separated from a solid planar portion 852 by corresponding first cutouts 853 and second cutouts 854. The first cutout 853 and the second cutout 854 may each define a cutout perimeter 855, within which the lateral perimeter of the MIMCAP 305 is located. The lower metal interconnect of IC 800 may otherwise be substantially similar to Figures 5 to 7 The lower metal interconnect 350 of IC 300 shown.

[0046] Considering the entire disclosure including the accompanying drawings and technical solutions, those skilled in the art will readily recognize that the present disclosure introduces an IC comprising: a MIMCAP in a dielectric layer above a semiconductor substrate, the MIMCAP having a top plate and a bottom plate, the bottom plate having a lateral periphery defining a lateral region of the bottom plate; a first metal interconnect layer above the MIMCAP connected to the top plate; and a second metal interconnect layer below the MIMCAP contacting the bottom plate, the contact area between the second metal interconnect layer and the bottom plate being smaller than the lateral region of the bottom plate.

[0047] The second metal interconnect layer may include metal traces that contact the base plate and have a path and a linewidth, the linewidth being smaller than the lateral diameter of the base plate at the intersection of the path and the lateral perimeter.

[0048] The MIMCAP may be contained in an ONO dielectric layer between the top plate and the bottom plate.

[0049] The first interconnect layer can be connected to the MIMCAP via a via, and the second metal interconnect layer can include metal traces that contact the base plate and have a linewidth approximately equal to the width of the via.

[0050] The MIMCAP may be one of a plurality of MIMCAPs arranged in a linear array, with each MIMCAP in the linear array connected to one of a corresponding plurality of traces in the second interconnect layer. The plurality of traces may have a first width within the lateral periphery of the base plate and a second, larger width outside the lateral periphery of the base plate.

[0051] The second interconnect layer may include a solid planar portion having first and second cutouts separated by trace portions contacting the base plate. The first and second cutouts may describe cutout perimeters within which the lateral perimeter of the base plate lies.

[0052] The first and second metal interconnect layers may be copper interconnect layers.

[0053] The IC may further include transistors that extend into the semiconductor substrate and are interconnected with the MIMCAP.

[0054] This disclosure also introduces a method for manufacturing an IC device, the method comprising: forming a plurality of layers over a semiconductor substrate, including a lower metal layer and at least one dielectric layer over the lower metal layer; forming a plurality of openings in the at least one dielectric layer, thereby exposing a portion of an upper surface of the lower metal layer; lining each of the openings with an outer conductive layer, an inner conductive layer, and a non-conductive layer inserted into the inner conductive layer and the outer conductive layer; forming a plurality of conductive plugs, each conductive plug filling a corresponding one of the lined openings; forming a plurality of vias, each via contacting a corresponding one of the conductive plugs; and forming an upper metal layer, the upper metal layer contacting each of the vias; wherein the contact area between each outer conductive layer and the lower metal layer is smaller than the bottom surface area of ​​the outer conductive layer.

[0055] The vias and the upper metal layer can be formed together during a single deposition.

[0056] The outer conductive layer, the inner conductive layer, and the inserted non-conductive layer within each opening may collectively be one of a plurality of capacitors, each capacitor being formed in a corresponding one of the openings, and the method may further include forming a transistor at least partially in the semiconductor substrate and interconnected with at least one of the capacitors.

[0057] Each non-conductive layer can be an ONO dielectric layer.

[0058] Forming the lower metal layer may include depositing a solid planar portion having a pair of first and second cuts, each cut being separated by a corresponding trace portion, each trace portion contacting a corresponding one of the outer conductive layers.

[0059] This disclosure also introduces an IC device comprising: a plurality of layers formed over a semiconductor substrate and including a lower metal layer, an upper metal layer, and at least one dielectric layer inserted into the upper metal layer and the lower metal layer; and a plurality of metal plates, each metal plate having a bottom surface. The contact area between each metal plate and the lower metal layer extends from a first side of the periphery of the metal plate to an opposite side of the periphery and is smaller than the bottom surface area of ​​the metal plate.

[0060] Each metal plate may serve as the base plate for a corresponding one of a plurality of trench capacitors. The lower metal layer and the metal plates may form the first terminal of the array capacitors. The lower metal layer may include a plurality of linear components, the plurality of trench capacitors may comprise a plurality of capacitor sets, and the trench capacitors in each capacitor set may be interconnected via a corresponding one of the linear components. The lower metal layer may include a plurality of non-linear components, the plurality of trench capacitors may comprise a plurality of capacitor sets, and the trench capacitors in each capacitor set may be interconnected via a corresponding one of the non-linear components. The lower metal layer may include a plurality of components, the plurality of trench capacitors may comprise a plurality of capacitor sets, the trench capacitors in each capacitor set may be interconnected via a corresponding one of the components, and each component may have an alternating width of: a first width at a junction with a trench capacitor in a corresponding capacitor set; and a second width at a position between the trench capacitors in the corresponding capacitor set, wherein the second width is greater than the first width. The integrated circuit device may further include a transistor at least partially formed in a semiconductor substrate and interconnected with at least one of the trench capacitors.

[0061] Each non-conductive layer can be an ONO dielectric layer.

[0062] The contact area between each metal plate and the lower metal layer may be at least 20% smaller than the bottom surface area of ​​the metal plate.

[0063] The lower and upper metal layers can be made of aluminum.

[0064] The foregoing outlines the features of several examples to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures used to implement the same functionality and / or achieve the same benefits as the examples described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0065] An abstract is provided at the end of this disclosure to comply with 37 CFR §1.72(b), thereby allowing the reader to quickly confirm the nature of the technical disclosure. This abstract is provided under the understanding that it will not be used to limit or interpret the scope or meaning of the claims.

Claims

1. An integrated circuit (IC), comprising: A metal-insulator-metal capacitor (MIMCAP) in a dielectric layer above a semiconductor substrate, the MIMCAP having a top plate and a bottom plate, the bottom plate having a lateral periphery defining a lateral region of the bottom plate; A first metal interconnect layer above the MIMCAP is connected to the top plate; and A second metal interconnect layer below the MIMCAP contacts the base plate, and the contact area between the second metal interconnect layer and the base plate is smaller than the lateral area of ​​the base plate.

2. The IC of claim 1, wherein the second metal interconnect layer comprises a metal trace that contacts the substrate and has a path and a linewidth, the linewidth being smaller than the lateral diameter of the substrate at the intersection of the path and the lateral perimeter.

3. The IC of claim 1, wherein the MIMCAP is contained in an oxide-nitride-oxide (ONO) dielectric layer between the top plate and the bottom plate.

4. The IC of claim 1, wherein the first interconnect layer is connected to the MIMCAP via a via, and the second metal interconnect layer comprises metal traces that contact the base plate and have a linewidth approximately equal to the width of the via.

5. The IC of claim 1, wherein the MIMCAP is one of a plurality of MIMCAPs arranged in a linear array, and the MIMCAP of each linear array is connected to one of a corresponding plurality of traces in the second interconnect layer.

6. The IC of claim 5, wherein the plurality of traces have a first width within the lateral periphery of the base plate and a second, greater width outside the lateral periphery of the base plate.

7. The IC of claim 1, wherein the second interconnect layer includes a solid planar portion having first and second cutouts separated by trace portions contacting the substrate.

8. The IC of claim 7, wherein the first and second cuts describe a cut periphery, and the lateral periphery of the base plate is within the cut periphery.

9. The IC according to claim 1, wherein the first and second metal interconnect layers are copper interconnect layers.

10. The IC of claim 1, further comprising a transistor extending into the semiconductor substrate and interconnected with the MIMCAP.

11. A method for manufacturing an integrated circuit device, the method comprising: Multiple layers are formed over a semiconductor substrate, including a lower metal layer and at least one dielectric layer over the lower metal layer; A plurality of openings are formed in the at least one dielectric layer, thereby exposing a portion of the upper surface of the lower metal layer; Line each of the openings with the following: The outer conductive layer that contacts the lower metal layer; Inner conductive layer; and Insert a non-conductive layer into the inner conductive layer and the outer conductive layer; Multiple conductive plugs are formed, and each conductive plug fills the corresponding one in the liner-filled opening; Multiple through holes are formed, each through hole contacting a corresponding one of the conductive plugs; and An upper metal layer is formed, the upper metal layer contacting each of the vias; The contact area between each outer conductive layer and the lower metal layer is smaller than the bottom surface area of ​​the outer conductive layer.

12. The method of claim 11, wherein the via and the upper metal layer are formed together during a single deposition.

13. The method according to claim 11, wherein: The outer conductive layer, the inner conductive layer, and the inserted non-conductive layer within each opening collectively constitute one of a plurality of capacitors, each capacitor being formed in a corresponding one within the opening; and The method further includes forming a transistor that is at least partially in the semiconductor substrate and interconnected with at least one of the capacitors.

14. The method of claim 11, wherein each non-conductive layer is an oxide-nitride-oxide (ONO) dielectric layer.

15. The method of claim 11, wherein forming the lower metal layer comprises depositing a solid planar portion having a pair of first and second cuts, each cut being separated by a corresponding trace portion, each trace portion contacting a corresponding one of the outer conductive layers.

16. An integrated circuit device, comprising: Multiple layers are formed over a semiconductor substrate and include a lower metal layer, an upper metal layer and at least one dielectric layer inserted into the lower metal layer and the upper metal layer; and Multiple metal plates, each having a bottom surface, wherein the contact area between each metal plate and the underlying metal layer is: Extending from a first side of the perimeter of the metal plate to the opposite side of the perimeter; and Smaller than the bottom surface area of ​​the metal plate.

17. The integrated circuit device of claim 16, wherein each metal plate is a base plate of a corresponding one of a plurality of trench capacitors.

18. The integrated circuit device of claim 17, wherein the lower metal layer and the metal plate form a first terminal of the array capacitor.

19. The integrated circuit device of claim 17, further comprising a transistor at least partially formed in the semiconductor substrate and interconnected with at least one of the trench capacitors.

20. The integrated circuit device of claim 16, wherein the contact area between each metal plate and the lower metal layer is at least 20% smaller than the bottom surface area of ​​the metal plate.

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