Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device with small electrical characteristic fluctuations between transistors is provided. The semiconductor device includes transistors and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer is located on the first conductive layer and has a first region where the first insulating layer is disposed and a second region where the first insulating layer is not disposed. The second conductive layer is located on the first insulating layer and has a first side surface. The semiconductor layer is in contact with the top surface of the second conductive layer in the first region, a portion of the first side surface, and the top surface of the first conductive layer in the second region. The second insulating layer is in contact with the top surface and side surface of the first conductive layer, the top surface and side surface of the semiconductor layer, another portion of the first side surface, and the top surface and side surface of the second conductive layer. The second insulating layer has an elemental concentration of boron, phosphorus, or magnesium of 1.0 × 10⁻⁶. 19 atoms / cm 3 The above areas.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. A third aspect of the present invention relates to a display device including a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices including these devices, and methods for driving or manufacturing these devices.

[0003] In this specification, a semiconductor device refers to a device that utilizes the properties of semiconductors, and includes circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to any device capable of functioning by utilizing the properties of semiconductors. Examples of semiconductor devices include integrated circuits, chips containing integrated circuits, and electronic components that house chips in packages. Additionally, sometimes storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, or include semiconductor devices. Background Technology

[0004] Semiconductor devices, including transistors, are widely used in electronic devices. For example, in display devices, by reducing the area occupied by transistors, pixel size can be reduced, thereby improving resolution. Therefore, microtransistors are in demand.

[0005] The development of devices that require high-definition display devices, such as those for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), is very active.

[0006] As a display device, light-emitting devices, such as those including organic EL (Electro Luminescence) elements or light-emitting diodes (LEDs), are under development.

[0007] Patent document 1 discloses a high-definition display device using organic EL elements.

[0008] [Preliminary Technology Documents]

[0009] [Patent Literature]

[0010] [Patent Document 1] International Patent Application Publication No. 2016 / 038508

[0011] [Non-patent literature]

[0012] [Non-Patent Literature 1] Takashi Koita, "High Mobility Transparent Conductive Film", National Institute of Advanced Industrial Science and Technology (AIST), Japan, AIST Solar Power Generation Research Results Conference 2019, Website<URL:https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf> Summary of the Invention

[0013] The technical problem that the invention aims to solve

[0014] To further improve the clarity of display devices, the semiconductor devices included in the display devices need to be further miniaturized. On the other hand, the more miniaturization is pursued in the transistors included in the semiconductor devices, the more difficult it becomes to ensure good electrical characteristics, maintain manufacturing precision, and reduce the non-uniformity of electrical characteristics between transistors.

[0015] One objective of this invention is to provide a semiconductor device including micro-transistors and a method for manufacturing the same. Another objective of this invention is to provide a semiconductor device including transistors with short channel lengths and a method for manufacturing the same. Another objective of this invention is to provide a semiconductor device including transistors with large on-state currents and a method for manufacturing the same. Another objective of this invention is to provide a semiconductor device including transistors with high field-effect mobility and a method for manufacturing the same. Another objective of this invention is to provide a semiconductor device including transistors with good electrical characteristics and a method for manufacturing the same. Finally, an objective of this invention is to provide a semiconductor device and a method for manufacturing the same with small non-uniformity in electrical characteristics between transistors.

[0016] Furthermore, one objective of this invention is to provide a high-speed operating semiconductor device and a method for manufacturing the same. Another objective of this invention is to provide a semiconductor device with a small footprint and a method for manufacturing the same. Another objective of this invention is to provide a low-power semiconductor device or display device and a method for manufacturing the same. Another objective of this invention is to provide a high-definition display device. Another objective of this invention is to provide a method for manufacturing a semiconductor device or display device with high productivity. Finally, one objective of this invention is to provide a novel transistor, semiconductor device, display device, or method for manufacturing the same.

[0017] Note that the description of these objectives does not preclude the existence of other objectives. One aspect of the invention does not necessarily require achieving all of the above objectives. Objectives other than those described above can be extracted from the description, drawings, and claims.

[0018] means of solving technical problems

[0019] One aspect of the present invention is a semiconductor device comprising a transistor and a first insulating layer. The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer is located on the first conductive layer, and the second conductive layer is located on the first insulating layer. The first insulating layer has a first side surface in a region overlapping with the second conductive layer. The semiconductor layer is in contact with the top surface and side surface of the second conductive layer, a portion of the first side surface, and the top surface of the first conductive layer. The second insulating layer is in contact with the top surface and side surface of the first conductive layer, the top surface and side surface of the semiconductor layer, another portion of the first side surface, and the top surface and side surface of the second conductive layer. The second insulating layer contains a first element, which is boron, phosphorus, or magnesium, and the concentration of the first element in the second insulating layer is 1.0 × 10⁻⁶. 19 atoms / cm 3 The above areas.

[0020] In the above method, the first element is preferably boron.

[0021] In addition, in the above-described manner, it is preferred that the semiconductor layer has a first region, a second region, and a third region, the first region being in contact with a first conductive layer, the second region being in contact with a first side surface, and the third region being in contact with a second conductive layer. Both the first region and the third region contain a second element, which is one or more of boron, phosphorus, aluminum, magnesium, and silicon. The concentration of the second element in the first region and the third region is higher than the concentration of the second element in the second region.

[0022] In the above method, both the first region and the third region preferably have a concentration of the second element of 1×10⁻⁶. 19 atoms / cm 3 Above and 1×10 23 atoms / cm 3 The following areas.

[0023] In addition, in the above-described manner, it is preferred that the semiconductor layer is an indium oxide semiconductor layer, the first insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer and a fifth insulating layer on the fourth insulating layer, the third insulating layer and the fifth insulating layer both contain silicon and nitrogen, and the fourth insulating layer contains silicon and oxygen.

[0024] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; sequentially depositing a first insulating film and a first conductive film on the first conductive layer; processing the first conductive film and the first insulating film such that they have regions overlapping with the first conductive layer to respectively form a second conductive layer and a first insulating layer; forming a semiconductor layer in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer; forming a second insulating layer in contact with the top surface and side surface of the semiconductor layer, the top surface of the first conductive layer, and the top surface of the second conductive layer; and supplying a first element to the second insulating layer.

[0025] In addition, in the above-mentioned manner, the first element is preferably boron, phosphorus, magnesium, aluminum or silicon.

[0026] Furthermore, in the above-described method, it is preferable that the first element is boron, which is supplied using an ion doping method. In the ion doping method, the accelerating voltage is above 1 keV and below 10 keV, and the dose is 1.0 × 10⁻⁶. 15 ions / cm 2 Above and 1.0×10 16 ions / cm 2 the following.

[0027] Furthermore, in the above-described manner, it is preferable to supply the second element to the semiconductor layer through the second insulating layer after supplying the first element.

[0028] In the above manner, the second element is preferably one or more of boron, phosphorus, aluminum, magnesium and silicon.

[0029] Furthermore, in the above-described manner, it is preferable to supply the second element using an ion doping method.

[0030] In the above manner, it is preferable that, after forming the second insulating layer, the third element is supplied to the semiconductor layer through the second insulating layer, and then the first element is supplied to the second insulating layer.

[0031] In the above manner, the third element is preferably one or more of boron, phosphorus, aluminum, magnesium and silicon.

[0032] In addition, in the above-mentioned methods, it is preferable to use ion doping to supply the third element.

[0033] Invention Effects

[0034] According to one aspect of the present invention, a semiconductor device including micro-transistors and a method for manufacturing the same can be provided. Additionally, according to one aspect of the present invention, a semiconductor device including transistors with short channel lengths and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device including transistors with large on-state currents and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device including transistors with high field-effect mobility and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device including transistors with good electrical characteristics and a method for manufacturing the same can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with small non-uniformity in electrical characteristics between transistors and a method for manufacturing the same can be provided.

[0035] Furthermore, according to one aspect of the present invention, a high-speed operating semiconductor device and a method for manufacturing the same can be provided. Additionally, according to one aspect of the present invention, a semiconductor device with a small footprint and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a low-power semiconductor device or display device and a method for manufacturing the same can be provided. Furthermore, according to one aspect of the present invention, a high-definition display device can be provided. Furthermore, according to one aspect of the present invention, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Furthermore, according to one aspect of the present invention, a novel transistor, semiconductor device, display device, or method for manufacturing the same can be provided.

[0036] Note that the description of these effects does not preclude the existence of other effects. One aspect of the invention does not necessarily require all of the aforementioned effects. Effects other than those described above can be extracted from the specification, drawings, and claims.

[0037] Brief description of the attached figures

[0038] Figure 1A This is a plan view showing an example of a semiconductor device. Figure 1B and Figure 1C This is a cross-sectional view showing an example of a semiconductor device.

[0039] Figures 2A to 2C This is a perspective view showing an example of a semiconductor device.

[0040] Figures 3A to 3C This is a perspective view showing an example of a semiconductor device.

[0041] Figure 4A and Figure 4B This is a perspective view showing an example of a semiconductor device.

[0042] Figure 5A and Figure 5BThis is a cross-sectional view showing an example of a semiconductor device.

[0043] Figure 6 This is a cross-sectional view showing an example of a semiconductor device.

[0044] Figure 7A This is a cross-sectional view showing an example of a semiconductor device. Figure 7B This is a plan view showing an example of a semiconductor device.

[0045] Figure 8A This is a plan view showing an example of a semiconductor device. Figure 8B and Figure 8C This is a cross-sectional view showing an example of a semiconductor device.

[0046] Figures 9A to 9C This is a perspective view showing an example of a semiconductor device.

[0047] Figure 10A This is a plan view showing an example of a semiconductor device. Figure 10B and Figure 10C This is a cross-sectional view showing an example of a semiconductor device.

[0048] Figure 11A and Figure 11B This is a perspective view showing an example of a semiconductor device.

[0049] Figure 12 This is a perspective view showing an example of a semiconductor device.

[0050] Figure 13A This is a plan view showing an example of a semiconductor device. Figure 13B and Figure 13C This is a cross-sectional view showing an example of a semiconductor device.

[0051] Figure 14A and Figure 14B This is a perspective view showing an example of a semiconductor device.

[0052] Figure 15 This is a perspective view showing an example of a semiconductor device.

[0053] Figure 16A and Figure 16B This is a graph illustrating the carrier concentration dependence of Hall mobility. Figure 16C This is a cross-sectional view illustrating the indium oxide film.

[0054] Figures 17A to 17E This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0055] Figures 18A to 18DThis is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0056] Figures 19A to 19D This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0057] Figure 20 This is a perspective view showing an example of a display device.

[0058] Figure 21A and Figure 21B This is a cross-sectional view showing an example of a display device.

[0059] Figure 22 This is a cross-sectional view showing an example of a display device.

[0060] Figures 23A to 23C This is a cross-sectional view showing an example of a display device.

[0061] Figure 24A and Figure 24B This is a cross-sectional view showing an example of a display device.

[0062] Figure 25 This is a cross-sectional view showing an example of a display device.

[0063] Figures 26A to 26C This is a cross-sectional view showing an example of a display device.

[0064] Figure 27 This is a cross-sectional view showing an example of a display device.

[0065] Figure 28A and Figure 28B This is a cross-sectional view showing an example of a display device.

[0066] Figures 29A to 29D This is a diagram illustrating an example of an electronic device.

[0067] Figures 30A to 30F This is a diagram illustrating an example of an electronic device.

[0068] Figures 31A to 31G This is a diagram illustrating an example of an electronic device.

[0069] Figure 32A and Figure 32B This is a diagram illustrating the Id-Vg characteristics of a transistor according to an embodiment.

[0070] Methods of implementing the invention

[0071] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those skilled in the art will readily understand that its methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0072] Note that in the structure of the invention described below, the same symbols are used in different figures to represent the same parts or parts having the same function, and repeated descriptions are omitted. Additionally, when representing parts having the same function, the same shading lines are sometimes used without additional symbols.

[0073] Furthermore, for ease of understanding, the positions, sizes, and extents of the constituent elements shown in the accompanying drawings may not represent their actual positions, sizes, and extents. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the accompanying drawings.

[0074] Note that, for convenience, ordinal numbers such as "first" and "second" are used in this specification, etc., but these do not limit the number of constituent elements or the order of the constituent elements (e.g., process sequence or stacking sequence). Furthermore, the ordinal numbers used for constituent elements in one part of this specification may sometimes differ from those used for the same constituent element in other parts of this specification or in the claims.

[0075] Additionally, depending on the situation or circumstances, the "film" and "layer" can be interchanged. For example, a "conductive layer" can be replaced with a "conductive film." Similarly, an "insulating film" can be replaced with an "insulating layer."

[0076] A transistor is a type of semiconductor device that can amplify current or voltage and control switching operations, such as turning on or off. The transistors discussed in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0077] In cases where transistors with different polarities are used or the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the terms "source" and "drain" can be used interchangeably. Note that, depending on the situation, the source and drain of the transistor can be appropriately referred to as source terminal and drain terminal, or source electrode and drain electrode, etc.

[0078] Furthermore, the "gate" and "back gate" can be interchanged. Therefore, in this specification and other materials, the terms "gate" and "back gate" can be used interchangeably. Note that, depending on the circumstances, the gate and back gate of the transistor can be appropriately referred to as gate electrode and back gate electrode, etc.

[0079] In this specification, "connection" includes, for example, "electrical connection." Note that sometimes "electrical connection" is used to describe the connection relationship of circuit elements as an object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B directly connected" means that A and B are connected without any circuit elements (e.g., transistors, switches, etc. Note that wiring is not a circuit element). On the other hand, "A and B indirectly connected" means that A and B are connected through one or more circuit elements. Note that A, B, and C (described later) represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0080] For example, assuming a circuit including A and B is operating, if there are opportunities for the exchange of electrical signals or the interaction of electrical potentials between A and B during the circuit's operation, such a circuit can be defined as "A and B are indirectly connected." Furthermore, even if there are opportunities for the exchange of electrical signals or the interaction of electrical potentials between A and B during the circuit's operation, it can still be defined as "A and B are indirectly connected."

[0081] An example of "A and B being indirectly connected" is a case where A and B are connected through the source and drain of more than one transistor. On the other hand, an example where "A and B being indirectly connected" cannot be said is a case where there is an insulator in the path from A to B. Specifically, this includes cases where a capacitor is connected between A and B, and cases where there is a gate insulating film of a transistor between A and B. Therefore, it cannot be said that "the gate (A) of a transistor is indirectly connected to the source or drain (B) of the transistor."

[0082] As another example where it cannot be said that "A and B are indirectly connected", there is the following situation: multiple transistors are connected through the source and drain along the path from A to B, and a fixed potential V is supplied from the power supply, GND, etc. to the nodes between the transistors and other transistors.

[0083] In this specification and other documents, unless otherwise specified, the on-state current refers to the drain current (also denoted as Id) when the transistor is in the on-state (also called the conduction state). Unless otherwise specified, in an n-channel transistor, the on-state refers to the state where the voltage between the gate and source (also denoted as Vg or Vgs) is above the threshold voltage (also denoted as Vth), and in a p-channel transistor, the on-state refers to the state where the voltage is below the threshold voltage.

[0084] Furthermore, unless otherwise specified in this specification, the off-state current refers to the leakage current between the source and drain of a transistor when it is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to a state where the voltage between the gate and source is below the threshold voltage; in a p-channel transistor, the off state refers to a state where the voltage between the gate and source is above the threshold voltage.

[0085] In this specification, "parallel" refers to two straight lines arranged at an angle of -10 degrees or more but less than 10 degrees. Therefore, it also includes situations where the angle is -5 degrees or more but less than 5 degrees. "Approximately parallel" refers to two straight lines arranged at an angle of -30 degrees or more but less than 30 degrees. Furthermore, "perpendicular" refers to two straight lines arranged at an angle of 80 degrees or more but less than 100 degrees. Therefore, it also includes situations where the angle is 85 degrees or more but less than 95 degrees. "Approximately perpendicular" refers to two straight lines arranged at an angle of 60 degrees or more but less than 120 degrees.

[0086] In this specification and the like, the top surface shape of a constituent element refers to the edge shape of the constituent element when viewed from a plane (also known as from a top view). Furthermore, "viewed from a plane" means viewed from the normal direction of the surface on which the constituent element is formed or the surface of the support (e.g., a substrate) on which the constituent element is formed.

[0087] In this specification, "consistent or substantially consistent top surface shape" means that at least a portion of the edges of each layer in a stack overlaps. This includes cases where the upper and lower layers are processed using the same mask pattern or a portion thereof. However, there are actually cases where the edges do not overlap; sometimes the upper layer is inside or outside the lower layer. In these cases, it can also be said that the "top surface shape is consistent or substantially consistent." Furthermore, in cases where the top surface shape is consistent or substantially consistent, it can also be described as "consistent or substantially consistent end shape" or "end-aligned or substantially aligned end shape."

[0088] Note that in this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to the substrate surface or the surface to be formed. Additionally, the angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as the tapered angle.

[0089] In this specification, devices manufactured using metal masks or FMM (Fine Metal Mask) are sometimes referred to as devices with an MM (Metal Mask) structure. Conversely, devices manufactured without metal masks or FMM are sometimes referred to as devices with an MML (Metal Mask Less) structure. Note that because MML structure devices can be manufactured without metal masks, they can exceed the upper limit of sharpness due to the alignment accuracy of metal masks. Furthermore, MML structure devices eliminate the need for equipment required for metal mask manufacturing and the metal mask washing process. Additionally, MML structure devices reduce manufacturing costs, making them suitable for mass production.

[0090] In this specification and other materials, the structure in which light-emitting elements (also known as light-emitting devices) with different emission wavelengths are fabricated separately is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and structure in each light-emitting element, the freedom of material and structure selection is increased, and it is easy to achieve improvements in brightness and reliability.

[0091] In this specification and other materials, holes or electrons are sometimes referred to as "carriers." Specifically, the hole injection layer or electron injection layer in a light-emitting element is sometimes referred to as a "carrier injection layer," the hole transport layer or electron transport layer as a "carrier transport layer," and the hole blocking layer or electron blocking layer as a "carrier blocking layer." Note that sometimes it is not possible to clearly distinguish between the aforementioned carrier injection layer, carrier transport layer, and carrier blocking layer. In addition, sometimes a single layer performs the functions of two or three of the following: carrier injection layer, carrier transport layer, and carrier blocking layer.

[0092] In this specification, the light-emitting element includes an EL layer between a pair of electrodes. The EL layer includes at least a light-emitting layer. Examples of layers included in the EL layer (also referred to as functional layers) include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, the light-receiving element (also referred to as a light-receiving device) includes at least an active layer serving as a photoelectric conversion layer between a pair of electrodes. In this specification, sometimes one of the electrodes is referred to as the pixel electrode and the other as the common electrode.

[0093] In this specification and the like, "disconnection" refers to the phenomenon where a layer, film, or electrode is broken due to the shape of the surface on which it is formed (e.g., a step).

[0094] In this specification, etc., "island-like" refers to the state in which two or more layers made of the same material are physically separated in the same process.

[0095] In this specification, the sacrificial layer (also known as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape in the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0096] (Implementation Method 1)

[0097] In this embodiment, refer to Figures 1A to 15 A semiconductor device according to one aspect of the present invention is described.

[0098] One aspect of the present invention is a semiconductor device comprising a transistor, a first insulating layer, and a second insulating layer.

[0099] One embodiment of the transistor of the present invention includes a first conductive layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, and a third insulating layer on a first insulating layer. In the transistor, the first conductive layer serves as one of a source electrode and a drain electrode, and the second conductive layer serves as the other of a source electrode and a drain electrode. The third conductive layer serves as a gate electrode, and the third insulating layer serves as a gate insulating layer. In the oxide semiconductor layer, a region contacting the first conductive layer serves as one of a source region and a drain region, and a region contacting the second conductive layer serves as the other of a source region and a drain region. A channel formation region in the oxide semiconductor layer is located between the source region and the drain region.

[0100] A second insulating layer is located on the first conductive layer. The second insulating layer has regions that contact the top surface and side surface of the first conductive layer. A second conductive layer is located on the second insulating layer. An oxide semiconductor layer has regions that contact the top surface of the first conductive layer, regions that contact the side surface of the second insulating layer, regions that contact the side surface of the second conductive layer, and regions that contact the top surface of the second conductive layer. A third insulating layer has regions that contact the top surface and side surface of the oxide semiconductor layer, regions that contact the top surface and side surface of the first conductive layer, regions that contact the side surface of the second insulating layer, and regions that contact the top surface and side surface of the second conductive layer. The third conductive layer has a region that faces the side surface of the second insulating layer, separated by the third insulating layer and the oxide semiconductor layer.

[0101] The third insulating layer contains the first element. The first element is an element that readily bonds with oxygen or is stable when bonded with oxygen. For example, boron can be an example of a first element. When the third insulating layer contains the first element, the third insulating layer can have the function of capturing oxygen.

[0102] A portion of the side surface of the second insulating layer (the first region) is in contact with the oxide semiconductor layer, and other regions of the side surface of the second insulating layer (the second region) are in contact with the third insulating layer. That is, the side surface of the second insulating layer has a first region in contact with the oxide semiconductor layer and a second region in contact with the third insulating layer.

[0103] The second insulating layer preferably contains oxygen. The oxygen contained in the second insulating layer is supplied to the oxide semiconductor layer through the first region. This allows for the realization of oxygen vacancies (V0) in the oxide semiconductor (primarily the channel formation region). O (OxygenVacancy) is a transistor that has good electrical properties due to being filled.

[0104] On the other hand, oxygen contained in the second insulating layer may be released to the outside from the second region that is not in contact with the oxide semiconductor layer. As mentioned above, the second region is in contact with the third insulating layer. Therefore, when oxygen released from the second insulating layer to the outside through the second region diffuses into the third insulating layer, it may reach the first or second conductive layer, which has a region in contact with the third insulating layer, and cause them to oxidize, thus increasing resistance. In addition, this may lead to an increase in the contact resistance between the oxide semiconductor layer and the first conductive layer or between the oxide semiconductor layer and the second conductive layer, resulting in adverse effects such as the transistor's on-state current reaching its maximum (i.e., the drain current does not easily increase relative to the increase in gate voltage).

[0105] However, when the third insulating layer contains the aforementioned first element, oxygen diffusing from the second insulating layer through the second region to the third insulating layer can bond with the first element. In other words, oxygen diffusing to the third insulating layer can be trapped within that insulating layer. Therefore, the risk of oxygen diffusing to the third insulating layer reaching the first or second conductive layer can be suppressed, thus reducing the risk of the aforementioned adverse effects.

[0106] The source and drain regions of the oxide semiconductor layer preferably contain a second element. For example, the same element as the first element (such as boron) can be used as the second element. Alternatively, both the second element and hydrogen can be used. This generates oxygen vacancies (V0) in the source and drain regions of the oxide semiconductor layer. O ) or defects in oxygen vacancies where hydrogen enters (hereinafter referred to as V) O H), which can generate charge carriers (electrons). Therefore, the resistance of the source and drain regions in the semiconductor layer can be selectively reduced. In addition, the contact resistance between the source region and the source electrode, as well as the contact resistance between the drain region and the drain electrode, can be reduced. Therefore, the decrease in transistor on-state current due to the increase in the aforementioned contact resistance can be suppressed, thereby enabling the transistor to achieve a large on-state current.

[0107] The first insulating layer preferably contains hydrogen. The hydrogen contained in the first insulating layer diffuses through the first conductive layer to the oxide semiconductor layer. The region of the oxide semiconductor layer in contact with the first conductive layer, i.e., the source region and the drain region, contains hydrogen. As a result, the resistance of one of the source and drain regions becomes lower, thereby further increasing the on-state current of the transistor.

[0108] In one aspect of the present invention, the channel length of the transistor can be controlled based on the thickness of the second insulating layer sandwiched between the first conductive layer and the second conductive layer. That is, the channel length of the transistor is not affected by the exposure performance of the exposure apparatus used during manufacturing. Therefore, the channel length of the transistor can be made smaller than the minimum size (hereinafter also referred to as the minimum size) that the exposure apparatus can expose. By reducing the channel length, a transistor with a large on-state current can be realized. Therefore, a semiconductor device operating at high speed can be realized. Furthermore, since the source electrode, oxide semiconductor layer, and drain electrode can be stacked, the occupied area of ​​the transistor can be reduced. Therefore, the occupied area of ​​the semiconductor device including this transistor can be reduced.

[0109] <Structure Example 1>

[0110] A semiconductor device according to one aspect of the present invention will be described. Figure 1A This is a plan view (also known as a top view) of the semiconductor device 10. Figure 1B Show along Figure 1A The cross-sectional view shown is the dotted-dash line A1-A2. Figure 1C The cross-sectional view along the dashed line B1-B2 is shown. Note that in... Figure 1A Some components of the semiconductor device 10 (such as the gate insulating layer) are omitted in the plan view. In the plan view of the semiconductor device, and sometimes in subsequent figures, they are also omitted. Figure 1A Similarly, some constituent elements are omitted.

[0111] The semiconductor device 10 includes a transistor 100, an insulating layer 110, and an insulating layer 109. The insulating layer 109 is disposed on the substrate 102, and the transistor 100 is disposed on the insulating layer 109.

[0112] Notice, Figure 1B and Figure 1C An example is shown where the insulating layer 110 has a laminated structure comprising an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b. The insulating layer 110b uses an insulating material that contains oxygen and is capable of releasing oxygen. Furthermore, both the insulating layers 110a and 110c use insulating materials capable of inhibiting oxygen permeation (oxygen-barrier insulating materials).

[0113] Furthermore, in this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following: the ability of a substance to not diffuse easily and thus inhibit the permeation of the film (also known as low permeability) and the ability to trap or fix the substance (also known as gettering). For example, an insulating layer with barrier properties can be referred to as a barrier insulating layer.

[0114] Transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. Conductive layer 104 serves as the gate electrode, and a portion of the insulating layer 106 serves as the gate insulating layer. Conductive layer 112a serves as one of the source and drain electrodes, and conductive layer 112b serves as the other. In semiconductor layer 108, the region between the source and drain electrodes, separated by the gate insulating layer and overlapping with the gate electrode, serves as a channel forming region. Additionally, in semiconductor layer 108, the region in contact with the source electrode serves as the source region, and the region in contact with the drain electrode serves as the drain region.

[0115] Figures 2A to 2C A perspective view of the semiconductor device 10 is shown. Figure 2A This is a perspective view of semiconductor device 10. Note that portions of the insulating layers (insulating layer 110 and insulating layer 106) are shown in a transparent manner, while only the edges are shown with dashed lines. Figure 2B From Figure 2A The three-dimensional diagram shown omits the conductive layer 104 and the insulating layer 106. Figure 2C From Figure 2B The 3D view shown omits the semiconductor layer 108 and the conductive layer 112b. Note that in... Figure 2C In the perspective view shown, the edge of the insulating layer 110 is indicated by a solid line. In the subsequent perspective view of the semiconductor device, [the edge is shown in the image]. Figure 2A Similarly, portions of the insulation layer are shown transparently. Additionally, the edges of the insulation layer are sometimes shown as dashed lines.

[0116] A conductive layer 112a is provided on the insulating layer 109. An insulating layer 110 is provided on both the conductive layer 112a and the insulating layer 109, with a region overlapping the conductive layer 112a. A conductive layer 112b is provided on the insulating layer 110. The conductive layer 112a has a region that contacts the insulating layer 109. The insulating layer 110 has a region that contacts and is sandwiched between the conductive layers 112a and 112b. The conductive layer 112a has a region that overlaps with the conductive layer 112b across the insulating layer 110.

[0117] like Figure 1B As shown, the conductive layer 112a has a region where the insulating layer 110 is disposed and a region where the insulating layer 110 is not disposed. Furthermore, the insulating layer 110 has a side surface (side surface 70F) in the region overlapping with the conductive layer 112a. Note that in Figure 1B and Figure 1C In this context, the top surface of the insulating layer 110 that is in contact with the conductive layer 112b (here, the top surface of the insulating layer 110c) is referred to as the top surface 70T.

[0118] A semiconductor layer 108 is disposed on conductive layers 112a, 112b, and insulating layer 110. The semiconductor layer 108 has regions that contact the top and side surfaces of conductive layer 112b, the side surface (side surface 70F) of insulating layer 110, and the top surface of conductive layer 112a. The semiconductor layer 108 is connected to both conductive layer 112a and conductive layer 112b. The semiconductor layer 108 has shapes that extend along the top and side surfaces of conductive layer 112b, side surface 70F, and the top surface of conductive layer 112a. The semiconductor layer 108 is disposed across the region of conductive layer 112a where the insulating layer 110 is disposed and the region of conductive layer 112a where the insulating layer 110 is not disposed.

[0119] Semiconductor layer 108 has a first region contacting conductive layer 112a, a second region contacting side surface 70F, and a third region contacting conductive layer 112b. The first region is in contact with the second region, and the second region is in contact with the third region. Alternatively, the first region is continuous with the second region, and the second region is continuous with the third region. The first region is used as one of the source and drain regions, and the third region is used as the other of the source and drain regions. The channel formation region is located in the second region.

[0120] In addition, such as Figure 1C As shown, the insulating layer 110 has sides (side 70L and side 70R) that do not contact the semiconductor layer 108. These sides contact the insulating layer 106. That is, the insulating layer 110 has sides (side 70F) that contact the semiconductor layer 108 and the insulating layer 106 in the direction corresponding to the dashed lines A1-A2, and sides (side 70L and side 70R) that contact the insulating layer 106 in the direction corresponding to the dashed lines B1-B2.

[0121] Figures 3A to 3C These are perspective views showing the four sides (side 70F, side 70L, side 70R, and top 70T) of the aforementioned insulating layer 110. Figure 3A This is a perspective view showing the side surface 70F of the insulating layer 110. Figure 3B This is a perspective view showing the top surface 70T of the insulating layer 110. Figure 3C This is a perspective view showing the side surface 70L and side surface 70R of the insulating layer 110.

[0122] like Figure 1B As shown, Figure 3A The side surface 70F shown is a surface having a region in contact with the semiconductor layer 108. Therefore, oxygen contained in the insulating layer 110 (here, the insulating layer 110b) can be supplied to the semiconductor layer 108 (mainly the channel formation region) through the side surface 70F.

[0123] Figure 3BThe top surface 70T shown is the surface in contact with the conductive layer 112b. As described above, the insulating layer 110 has a structure in which the insulating layer 110b (containing and releasing oxygen) is sandwiched between insulating layers 110a and 110c (insulating layers that inhibit oxygen permeation). Therefore, the insulating layer 110a inhibits the diffusion of oxygen contained in the insulating layer 110b to the area below the insulating layer 110b (on the substrate 102 side). Similarly, the insulating layer 110c inhibits the diffusion of oxygen contained in the insulating layer 110b to the area above the insulating layer 110b. In other words, the possibility of oxygen contained in the insulating layer 110 being released to the outside through the top surface 70T is extremely low.

[0124] like Figure 1C As shown, Figure 3C Side surfaces 70L and 70R shown are the surfaces in contact with insulating layer 106. In side surfaces 70L and 70R, the sides of insulating layer 110b are exposed and not covered by insulating layers 110a or 110c. Therefore, oxygen contained in insulating layer 110 may be released to the outside from side surfaces 70L and 70R. This oxygen may diffuse into insulating layer 106 in contact with side surfaces 70L and 70R.

[0125] exist Figure 4A In this context, region 75 is defined as the area on the four faces of the insulating layer 110 that contacts the semiconductor layer 108 and the area where the possibility of oxygen release is extremely low. Additionally, in... Figure 4B In this context, the region other than region 75 of the four faces of the insulating layer 110 (the region in contact with the insulating layer 106) is referred to as region 85.

[0126] Region 85 is part of the surface (side 70F, side 70L, and side 70R) where oxygen may be released from insulating layer 110 to the outside. Therefore, it can be said that oxygen other than the oxygen supplied to semiconductor layer 108 in the oxygen contained in insulating layer 110 may diffuse to the insulating layer 106 side through region 85.

[0127] Oxygen diffused into the insulating layer 106 may move within the insulating layer 106 due to heat treatment or other processes during the manufacturing of the semiconductor device 10, and reach the conductive layer 112a or conductive layer 112b that are in contact with the insulating layer 106. Figure 5A A schematic diagram illustrating the above concepts is shown. Figure 5AIn the diagram, white circles represent oxygen (O), and dashed arrows indicate the direction of oxygen diffusion. For example, when oxygen released from insulating layer 110 through region 85 diffuses into insulating layer 106 and reaches conductive layer 112a or conductive layer 112b, this oxygen may cause oxidation and increased resistance in conductive layer 112a or conductive layer 112b. Furthermore, this may increase the contact resistance between semiconductor layer 108 and conductive layer 112a or between semiconductor layer 108 and conductive layer 112b, leading to malfunctions such as the transistor 100 reaching its maximum on-state current. Additionally, the aforementioned oxygen may diffuse into insulating layer 106 and also onto the conductive layer 104 side. This may cause oxidation and increased resistance in conductive layer 104.

[0128] On the other hand, in one embodiment of the present invention, the insulating layer 106, which serves as the gate insulating layer of the transistor 100, contains an element that readily bonds with oxygen or an element that is stable when bonded with oxygen. Therefore, oxygen diffused into the insulating layer 106 can be inertized by bonding with this element. Furthermore, since this element is stable when oxidized, the likelihood of oxygen that has broken and detached due to heating or other processes during semiconductor device manufacturing diffusing back into the insulating layer 106 is low. Thus, the diffusion of oxygen released from the insulating layer 110 into the insulating layer 106 and reaching the conductive layer 112a or conductive layer 112b can be suppressed. Figure 5B A schematic diagram illustrating the above concepts is provided. Figure 5B An example is shown below: Suppose boron (B) is the element (black circle in the figure), which is stabilized as an oxide such as B2O3 by bonding with oxygen (O) diffused into the insulating layer 106 (paired white and black circles in the figure).

[0129] The element is preferably an element that is stabilized by bonding with oxygen. In other words, the oxide of this element is preferably present in a solid state as a standard state. Specifically, typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals) can be mentioned as this element, such as boron, phosphorus, magnesium, aluminum, and silicon. Boron is particularly preferred as this element. Note that this element is an element other than the main component constituting the insulating layer 106. For example, it can be an element with a concentration of less than 0.1 atomic% in the insulating layer 106.

[0130] When boron is used as the element, insulating layer 106 preferably has a boron concentration of, for example, 1.0 × 10⁻⁶. 19 atoms / cm 3 The above, preferably 5.0×10 19 atoms / cm 3 The above, and more preferably 1.0×10 20 atoms / cm 3The above, and more preferably 2.0×10 20 atoms / cm 3 The above, and preferably 3.0×10 20 atoms / cm 3 The above areas.

[0131] For example, by supplying (or adding or implanting) the aforementioned elements into the insulating layer 106, which serves as the gate insulating layer of the transistor 100, the risk of the aforementioned defects can be reduced. Furthermore, when a semiconductor device according to one aspect of the present invention includes multiple transistors, the non-uniformity of electrical characteristics between transistors can be reduced.

[0132] In another embodiment of the present invention, the source and drain regions of the transistor 100 preferably contain impurity elements (elements other than the main components constituting the semiconductor layer 108. For example, elements with a concentration of less than 0.1 atomic% in the semiconductor layer 108).

[0133] Examples of impurity elements include one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and rare gases (helium, neon, argon, krypton, xenon, etc.).

[0134] In addition, the impurity element is not limited to the elements mentioned above, and may also be one or more of the elements included in the first transition element (3d transition element, 3d transition metal), the second transition element (4d transition element, 4d transition metal), the third transition element (5d transition element, 5d transition metal), alkaline earth metal elements and rare earth elements.

[0135] Alternatively, both the aforementioned element and hydrogen can be used as impurity elements.

[0136] The source and drain regions preferably have a concentration of the impurity element, for example, 1 × 10⁻⁶. 19 atoms / cm 3 Above and 1×10 23 atoms / cm 3 The following, preferably 5×10 19 atoms / cm 3 Above and 5×10 22 atoms / cm 3 The following, or more preferably, is 1×10 20 atoms / cm 3 Above and 1×10 22 atoms / cm 3 The following regions. In cases involving multiple impurity elements, the concentration of each impurity element is preferably within the range described above.

[0137] By supplying the aforementioned impurity element to the source and drain regions, this impurity element abstracts oxygen from these regions, creating oxygen vacancies (V0) in these regions. O The oxygen vacancy bonds with hydrogen in the film to generate charge carriers, thus reducing the resistance of the source and drain regions. Consequently, the resistance of the source and drain regions of transistor 100 can be lower than that of the channel formation region. Therefore, the contact resistance between the source region and the source electrode, and between the drain region and the drain electrode, of transistor 100 can be reduced, thereby increasing the on-state current of transistor 100. Furthermore, by increasing the on-state current of transistor 100, the operating voltage of transistor 100 can be reduced, thereby reducing the power consumption of semiconductor device 10.

[0138] Note that sometimes the aforementioned impurity elements are also supplied to the channel formation region in the semiconductor layer 108. Alternatively, due to the effects of heating during the manufacturing process, sometimes a portion of the impurity elements contained in the source and drain regions diffuses into the channel formation region. The concentration of impurity elements in the channel formation region is preferably less than one-tenth of the concentration of impurity elements in the source and drain regions, and more preferably less than one-hundredth.

[0139] The concentrations of elements in the insulating layer 106 that readily bond with oxygen or elements that are stable when bonded with oxygen, as well as the concentrations of impurity elements in the semiconductor layer 108, can be analyzed using methods such as secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When using XPS analysis, by combining ion sputtering from one side of the surface or the back side with XPS analysis, the concentration distribution along the depth direction can be determined.

[0140] Figure 6 Show along Figure 1B The image shows an enlarged cross-sectional view of transistor 100 along the dotted lines A1-A2. (See attached image.) Figure 6 As shown, the semiconductor layer 108 has region 108i, region 108na and region 108nb disposed in a manner that sandwiches region 108i.

[0141] Region 108na is a portion of the semiconductor layer 108 that contacts the conductive layer 112a. Region 108na can be used as one of the source and drain regions of the transistor 100. Region 108nb is a region that includes the area of ​​the semiconductor layer 108 that contacts the top surface of the conductive layer 112b. Region 108nb can be used as the other of the source and drain regions of the transistor 100.

[0142] The resistance of regions 108na and 108nb, which are used as the source and drain regions, is lower than that of region 108i, which is used as the channel forming region. That is to say, regions 108na and 108nb can also be said to be regions with higher oxygen vacancy density or higher impurity concentration compared to region 108i.

[0143] In one embodiment of the transistor 100 of the present invention, the concentration of impurity elements in regions 108na and 108nb is, for example, higher than the concentration of the impurity element in region 108i. In regions 108na and 108nb, for example, the concentration of one or more of boron, phosphorus, aluminum, magnesium, and silicon is preferably higher than the concentration of the impurity element in region 108i.

[0144] There are no particular limitations on the semiconductor material used for semiconductor layer 108. For example, a semiconductor composed of a single element or a compound semiconductor can be used. Examples of semiconductors composed of a single element include silicon or germanium. Examples of compound semiconductors include gallium arsenide and silicon-germanium. In addition, examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). Note that these semiconductor materials may also contain impurities used as dopants.

[0145] There are no particular restrictions on the crystallinity of the semiconductor material used for semiconductor layer 108; amorphous semiconductors, single-crystal semiconductors, or semiconductors with crystallinity other than single crystal (microcrystalline semiconductors, polycrystalline semiconductors, or semiconductors with crystalline regions in a portion thereof) can be used. When using single-crystal semiconductors or crystalline semiconductors, the degradation of transistor characteristics can be suppressed, so they are preferred.

[0146] Semiconductor layer 108 can be made of silicon, for example. Examples of silicon include monocrystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS). Transistors using amorphous silicon in the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon in the channel formation region have high field-effect mobility and can operate at high speeds. Furthermore, compared to transistors using amorphous silicon, transistors using microcrystalline silicon in the channel formation region have higher field-effect mobility and can operate at high speeds.

[0147] Semiconductor layer 108 preferably comprises a metal oxide (also known as an oxide semiconductor) exhibiting semiconductor properties. Compared to transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have very high field-effect mobility. Furthermore, OS transistors have extremely low off-state currents, allowing them to retain the charge stored in the capacitor connected in series with the transistor for extended periods. Additionally, the power consumption of the semiconductor device can be reduced by using OS transistors. Note that when an oxide semiconductor is used as the semiconductor layer, the semiconductor layer can be referred to as an oxide semiconductor layer or a metal oxide layer.

[0148] As the insulating layer 110, one or both of inorganic and organic insulating layers can be used. Examples of materials suitable for organic insulating layers include acrylic resin and polyimide resin. The insulating layer 110 preferably comprises one or more inorganic insulating layers. Examples of materials suitable for inorganic insulating layers include oxides, nitrides, oxynitrides, and oxynitrides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride. Examples of oxynitrides include silicon oxynitride and aluminum oxynitride.

[0149] Note that in this specification, oxynitrides refer to materials in which the oxygen content is greater than the nitrogen content. Nitrogen oxides refer to materials in which the nitrogen content is greater than the oxygen content.

[0150] The insulating layer 110 has a region that contacts the semiconductor layer 108. When a metal oxide is used as the semiconductor layer 108, at least a portion of the region of the insulating layer 110 that contacts the semiconductor layer 108 preferably contains oxygen in order to improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, the portion of the insulating layer 110 that contacts the channel forming region of the semiconductor layer 108 preferably contains oxygen. One or more oxides and oxynitrides can be applied to the portion of the insulating layer 110 that contacts the channel forming region of the semiconductor layer 108.

[0151] When a metal oxide is used as the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 110 in contact with the semiconductor layer 108 releases oxygen by heating. Therefore, oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, thus reducing the number of oxygen vacancies (V) in the semiconductor layer 108. O ) and V O H.

[0152] An insulating layer 106, serving as the gate insulating layer of transistor 100, is disposed such that it covers semiconductor layer 108. The insulating layer 106 has regions that contact the top and side surfaces of semiconductor layer 108 and the side surfaces (side surface 70F, side surface 70L, and side surface 70R; here referring to region 85) of insulating layer 110. Additionally, the insulating layer 106 has regions that contact the top and side surfaces of conductive layer 112a, conductive layer 112b, and the top surface of insulating layer 109.

[0153] A conductive layer 104, serving as the gate electrode of the transistor 100, is disposed on the insulating layer 106 and has a region that contacts the top surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 across the insulating layer 106. Additionally, the conductive layer 104 has a region that faces the side surface (side surface 70F) of the insulating layer 110 across the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 is disposed such that it at least covers the region of the semiconductor layer 108 that contacts the side surface 70F. Therefore, this region can be used as the channel formation region of the transistor 100.

[0154] The conductive layer 104 preferably covers the entire semiconductor layer 108. For example... Figure 1A As shown, the conductive layer 104 preferably includes a semiconductor layer 108 when viewed from a planar perspective. By covering the semiconductor layer 108 with the conductive layer 104, damage to the semiconductor layer 108 during the formation of layers on the transistor 100 can be suppressed. Thus, a transistor 100 exhibiting good electrical characteristics and high reliability can be realized. Alternatively, a structure can be adopted in which the semiconductor layer 108 has a region not covered by the conductive layer 104.

[0155] Alternatively, the following structure can be adopted: a step is formed between the region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are provided and the region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are not provided, and a semiconductor layer 108, an insulating layer 106 and a conductive layer 104 are provided along the step.

[0156] In transistor 100, the source electrode and drain electrode are located at different heights relative to the surface of substrate 102, and drain current flows in a direction perpendicular or substantially perpendicular to the surface of substrate 102. Alternatively, in transistor 100, drain current flows in a longitudinal direction or substantially longitudinal direction. Therefore, a transistor according to one aspect of the present invention can be described as a longitudinal channel transistor, a longitudinal transistor, or a VFET (Vertical Field Effect Transistor).

[0157] The channel length of transistor 100 can be controlled by the thickness of the insulating layer 110 disposed between conductive layers 112a and 112b. Therefore, transistors with channel lengths smaller than the minimum exposure dimensions of the exposure apparatus used for transistor manufacturing can be manufactured with high precision. Furthermore, the electrical characteristic non-uniformity among multiple transistors 100 can be reduced. Therefore, the semiconductor device 10 operates stably, improving reliability. Additionally, when the electrical characteristic non-uniformity of transistors 100 is reduced, the freedom of circuit design is increased, and the operating voltage of the semiconductor device 10 can be reduced. This, in turn, reduces the power consumption of the semiconductor device 10.

[0158] Because the source electrode, semiconductor layer, and drain electrode can be stacked, the area occupied by a transistor of one aspect of the present invention can be much smaller than that of a so-called planar transistor in which the semiconductor layer is configured as a planar shape.

[0159] Conductive layers 112a, 112b, and 104 can all be used as wiring, and transistor 100 can be disposed in the area where these wirings overlap. That is, in a circuit including transistor 100 and wiring, the area occupied by transistor 100 and wiring can be reduced. Therefore, a semiconductor device 10 with a small footprint can be realized.

[0160] For example, when a semiconductor device according to one aspect of the present invention is used in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, thereby realizing a high-definition display device. Additionally, for example, when a semiconductor device according to one aspect of the present invention is used in the driving circuit of a display device (e.g., one or both of a gate line driving circuit and a source line driving circuit), the occupied area of ​​the driving circuit can be reduced, thereby realizing a display device with a narrow bezel.

[0161] An insulating layer 109 is disposed between the transistor 100 and the insulating layer 110 and the substrate 102. The insulating layer 109 has a region that contacts the conductive layer 112a, the insulating layer 110, and the insulating layer 106. The insulating layer 109 can be made of a material used as the insulating layer 110.

[0162] The insulating layer 109 preferably has barrier properties. The insulating layer 109 is preferably made of a material from which impurities (e.g., water and hydrogen) contained in the substrate 102 do not easily diffuse. Thus, the diffusion of impurities from the substrate 102 to the transistor 100 can be suppressed.

[0163] As the insulating layer 109 used as a barrier film, one or more of the following can be used: an oxide containing one or both of aluminum and hafnium, an oxide containing magnesium, an oxide containing gallium, an aluminum nitride, a silicon nitride, and a silicon oxide oxynitride. Specifically, one or more of the following can be used for the insulating layer 109: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon oxynitride.

[0164] The insulating layer 109 is preferably made of a material that contains and releases impurities (e.g., water and hydrogen) that reduce the resistance of the semiconductor layer 108. The impurities released from the insulating layer 109 diffuse into the region of the conductive layer 112a that contacts the insulating layer 109. Furthermore, when the impurities diffuse into the conductive layer 112a and then into the region of the semiconductor layer 108 that contacts the conductive layer 112a, this region contains impurities, thereby reducing the resistance of that region. In other words, the resistance of one of the source and drain regions can be reduced. Therefore, a transistor with a large on-state current can be realized, enabling a semiconductor device to operate at high speed.

[0165] When a metal oxide is used in the semiconductor layer 108, the impurities released from the insulating layer 109 more preferably contain hydrogen. When hydrogen in the insulating layer 109 diffuses through the conductive layer 112a to the semiconductor layer 108, the region of the semiconductor layer 108 in contact with the conductive layer 112a contains hydrogen, and the carrier concentration in this region increases. That is, the resistance of one of the source and drain regions can be reduced. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, hydrogen-containing silicon nitride can be used for the insulating layer 109.

[0166] The insulating layer 109 is more preferably made of a material that releases impurities that reduce the resistance of the conductive layer 112a. This reduces the resistance of the conductive layer 112a.

[0167] The conductive layer 112a can, for example, use a conductive metal oxide (also known as an oxide conductor). Examples of oxide conductors (OC) include indium oxide (indium oxide, also known as IO), zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (ITO containing silicon, also known as ITSO), gallium-added zinc oxide, and In-Ga-Zn oxide. In particular, indium-containing oxide conductors have high conductivity and are therefore suitable for use in the conductive layer 112a.

[0168] When a metal oxide is used as the conductive layer 112a, the impurities released from the insulating layer 109 more preferably include hydrogen. When the impurities released from the insulating layer 109 diffuse into the conductive layer 112a, the conductive layer 112a contains impurities. This increases the carrier concentration in the conductive layer 112a, thereby reducing resistance. Furthermore, since the conductive layer 112a can be used for wiring, a semiconductor device with low wiring resistance can be realized. Additionally, the impurities that reduce the resistance of the conductive layer 112a can be the same as the impurities that reduce the resistance of the semiconductor layer 108. Alternatively, these impurities can have different structures. The conductive layer 112a is more preferably able to allow impurities to pass through. The conductive layer 112a is more preferably less prone to impurity adsorption.

[0169] The thickness of the insulating layer 109 is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, further preferably 20 nm or more and 100 nm or less, and even more preferably 20 nm or more and 50 nm or less. For example, Figure 7A As shown, the thickness T109 of the insulating layer 109 can be the shortest distance between the surface of the insulating layer 109 that is formed (here, the top surface of the substrate 102) and the top surface of the insulating layer 109 in cross-section.

[0170] When the thickness T109 is large and the amount of impurities released from the insulating layer 109 is excessive, the amount of impurities diffusing into the semiconductor layer 108 also increases, thus increasing the number of oxygen vacancies (V) generated by these impurities. O ) and V O The amount of H may exceed the oxygen vacancies repaired by oxygen supplied from the insulation layer 110b (V O ) and V O The amount of H. On the other hand, when the thickness T109 is small, the amount of impurities diffusing into the conductive layer 112a and the semiconductor layer 108 decreases, which may cause the resistance of the conductive layer 112a and the resistance of one of the source and drain regions to increase. By setting the thickness T109 within the above range, the oxygen vacancies (V) in the channel formation region can be suppressed. O ) and V O The increase in H reduces its resistance. Furthermore, the thickness T109 is not limited to the range described above.

[0171] Note that a structure without insulation layer 109 can also be used.

[0172] The insulating layer 110 preferably has a laminated structure. Figure 1B Examples are shown of insulating layer 110 including insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b. Insulating layer 110a, insulating layer 110b, and insulating layer 110c can all be made of materials mentioned in insulating layer 110.

[0173] In transistor 100, the region of semiconductor layer 108 in contact with insulating layer 110b is used as a channel formation region. As described above, insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides mentioned above. Typically, one or both of silicon oxide and silicon oxynitride can be applied to insulating layer 110b.

[0174] More preferably, the insulating layer 110b uses a material that releases oxygen upon application of heat. Oxygen is released from the insulating layer 110b by heat applied during the manufacturing process of the semiconductor device 10, thereby supplying oxygen to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region (region 108i) of the semiconductor layer 108, oxygen vacancies (Vi) in that region can be filled. O This can reduce oxygen vacancies (V) O Additionally, V in this region can be reduced. O H. Therefore, transistors exhibiting good electrical characteristics and high reliability can be realized.

[0175] For example, oxygen can be supplied to the insulating layer 110b by performing heat treatment or plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the insulating layer 110b by depositing a film on its top surface using a sputtering method in an oxygen-containing atmosphere. This film can then be removed. Note that the method of supplying oxygen to the insulating layer 110b is specifically described in Embodiment 3.

[0176] The insulating layer 110b is preferably deposited using sputtering or plasma-enhanced chemical vapor deposition (PECVD). In particular, by using sputtering as the deposition gas without using gases containing hydrogen (e.g., hydrogen and ammonia), a film with extremely low hydrogen content can be formed. This suppresses the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0177] An insulating layer 110a is disposed between the insulating layer 110b and the conductive layers 112a and 109. An insulating layer 110c is disposed between the insulating layer 110b and the conductive layer 112b. The amount of impurities (e.g., hydrogen and water) released from each of the insulating layers 110a and 110c is preferably minimal. Furthermore, the insulating layers 110a and 110c are preferably impermeable to substances. In other words, the insulating layers 110a and 110c are used as barrier films. Specifically, the insulating layers 110a and 110c are preferably impermeable to impurities. Thus, the diffusion of impurities contained in the insulating layers 110a and 110c into the channel formation region can be suppressed. Additionally, the diffusion of impurities present on the outside of the insulating layers 110 (insulating layers 110a, 110b, and 110c) into the channel formation region through the insulating layers 110 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0178] As described above, insulating layers 110a and 110c are preferably made of materials that do not readily allow oxygen to permeate. This suppresses the diffusion of oxygen contained in insulating layer 110b through insulating layer 110a to the conductive layer 112a side. Similarly, it suppresses the diffusion of oxygen contained in insulating layer 110b through insulating layer 110c to the conductive layer 112b side. Consequently, the amount of oxygen supplied from insulating layer 110b to the channel formation region of semiconductor layer 108 increases, reducing oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized. Furthermore, the oxidation of the conductive layer 112a due to oxygen contained in the insulating layer 110b, which would otherwise increase the resistance of the conductive layer 112a, can be suppressed. Similarly, the oxidation of the conductive layer 112b due to oxygen contained in the insulating layer 110b, which would otherwise increase the resistance of the conductive layer 112b, can be suppressed. Therefore, a transistor with a large on-state current can be realized.

[0179] Insulating layers 110a and 110c can use the materials shown above as barrier films. For example, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon oxynitride can be used for insulating layers 110a and 110c. Alternatively, insulating layers 110a and 110c can use the same material. Or, insulating layers 110a and 110c can use different materials.

[0180] In this specification, different materials refer to materials whose constituent elements are partially or wholly different, or materials whose constituent elements are the same but whose composition is different.

[0181] One or more of the insulating layers 110a, 110b, and 110c may also have a laminated structure. For example, insulating layer 110c may be a laminated structure of an alumina film and a silicon nitride film on the alumina film.

[0182] The thickness of the insulating layer 110c is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 50 nm or more and 300 nm or less, more preferably 100 nm or more and 300 nm or less, and more preferably 100 nm or more and 200 nm or less. For example, such as Figure 7A As shown, the thickness T110c of the insulating layer 110c can be the shortest distance between the surface of the insulating layer 110c that is formed (here, the top surface of the insulating layer 110b) and the top surface of the insulating layer 110c in cross-section.

[0183] The thickness T110c is preferably a value that at least serves as an oxygen barrier film. The thickness T110c can be smaller than the thickness of the insulating layer 110a. When the thickness T110c of the insulating layer 110c is large, sometimes the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing into the channel formation region also increases. On the other hand, when the thickness T110c is small, sometimes oxygen contained in the insulating layer 110b diffuses through the insulating layer 110c to the conductive layer 112b side, reducing the amount of oxygen supplied to the channel formation region. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. Additionally, it can suppress the increase in resistance of the conductive layer 112b due to oxidation of the conductive layer 112b caused by oxygen contained in the insulating layer 110b. Note that the thickness T110c is not limited to the range described above.

[0184] The thickness of the insulating layer 110a is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 50 nm or more and 300 nm or less, more preferably 100 nm or more and 300 nm or less, more preferably 100 nm or more and 250 nm or less, and more preferably 150 nm or more and 250 nm or less. For example, such as Figure 7A As shown, the thickness T110a of the insulating layer 110a can be the shortest distance between the surface of the insulating layer 110a that is formed (here, the top surface of the conductive layer 112a) and the top surface of the insulating layer 110a in cross-section.

[0185] When the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse through the insulating layer 110a to the conductive layer 112a side, reducing the amount of oxygen supplied to the channel formation region. On the other hand, when the thickness T110a is large, the amount of impurities released from the insulating layer 110a may increase, leading to an increase in the amount of impurities diffusing into the channel formation region. By setting the thickness T110a within the aforementioned range, the amount of oxygen supplied to the channel formation region can be increased, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. Additionally, it can suppress the increase in resistance of the conductive layer 112a due to oxidation caused by oxygen contained in the insulating layer 110b. Note that the thickness T110a is not limited to the range described above.

[0186] The thickness T110a can be greater than the thickness T110c. When the region of the semiconductor layer 108 that contacts the insulating layer 110a is used as the source region or the drain region, increasing the thickness T110a can make the distance between the source region or the drain region and the gate electrode more uniform. As a result, the electric field applied to the gate electrode in the channel formation region can be further made more uniform.

[0187] At least one of the regions of semiconductor layer 108 that contact the insulating layer 110a and the region that contact the insulating layer 110c can also be a region with a lower resistance than the channel formation region (hereinafter also referred to as a low-resistance region). This region can also be described as a region with a higher carrier concentration and a higher oxygen vacancy density compared to the channel formation region. By using a material that releases impurities (e.g., water and hydrogen) in the insulating layer 110a, the region of semiconductor layer 108 that contacts the insulating layer 110a contains impurities, making this region a low-resistance region. Semiconductor layer 108 can have a low-resistance region between the region that contacts the conductive layer 112a (one of the source region and drain region) and the channel formation region. Similarly, by using an impurity-releasing material as the insulating layer 110c, the region of semiconductor layer 108 that contacts the insulating layer 110c contains impurities, making this region a low-resistance region. Semiconductor layer 108 can also have a low-resistance region between the region that contacts the conductive layer 112b (the other of the source region and drain region) and the channel formation region. Low-resistance regions can be used as buffer regions to mitigate the drain electric field. Additionally, these low-resistance regions can also be used as source or drain regions.

[0188] Note that sometimes impurities released from insulating layer 110a diffuse into the channel formation region through either the source or drain region of insulating layer 110b or semiconductor layer 108. Similarly, sometimes impurities released from insulating layer 110c diffuse into the channel formation region through either the source or drain region of insulating layer 110b or semiconductor layer 108. However, oxygen is supplied from at least insulating layer 110b to the region of semiconductor layer 108 in contact with insulating layer 110b, thus reducing oxygen vacancies (V0) in the channel formation region. O ) and V O H. This suppresses threshold voltage drift, enabling transistors with low cutoff current and high on-state current. Therefore, low-power, high-performance semiconductor devices can be realized.

[0189] However, when the amount of impurities released from insulating layers 110a and 110c is excessive, the semiconductor layer 108 contains more impurities. As a result, oxygen vacancies (V0) are generated in the semiconductor layer 108. O ) and V O The amount of H may exceed the oxygen vacancies repaired by oxygen supplied from the insulation layer 110b (V O ) and V O The amount of H. When the material that releases impurities is used in insulating layers 110a and 110c, it is more preferable that they release less impurities.

[0190] The insulating layer 110a has regions that contact the top surface of the insulating layer 109 and the top and side surfaces of the conductive layer 112a. This suppresses the diffusion of impurities contained in each of the insulating layer 109 and the conductive layer 112a through the insulating layer 110b into the channel formation region of the semiconductor layer 108.

[0191] The insulating layer 109 preferably has a region with a higher hydrogen content than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109.

[0192] Note that sometimes impurities released from insulating layer 109 diffuse into the channel formation region through one of the source and drain regions of conductive layer 112a and semiconductor layer 108. However, oxygen is supplied from at least insulating layer 110b to the region of semiconductor layer 108 in contact with insulating layer 110b, thus reducing oxygen vacancies (V) in the channel formation region. O ) and V O H. This suppresses threshold voltage drift, enabling transistors with low cutoff current and high on-state current. Therefore, low-power, high-performance semiconductor devices can be realized.

[0193] The insulating layer 109 preferably has a region with a higher hydrogen content than the insulating layer 110a. The hydrogen content of the insulating layers 109 and 110 can be analyzed, for example, using SIMS.

[0194] The amount of hydrogen released can be adjusted by differentiating the deposition conditions of insulating layer 109 and insulating layer 110a. Specifically, one or more of the following can be different for the formation of insulating layer 109 and insulating layer 110a: deposition power (deposition power density), deposition pressure, type of deposition gas, deposition gas flow ratio, deposition temperature, and distance between the substrate and the electrode. For example, by making the deposition power density of insulating layer 109 lower than that of insulating layer 110a, the hydrogen content in insulating layer 109 can be higher than that in insulating layer 110a. This increases the amount of hydrogen released from insulating layer 109 when heated.

[0195] The hydrogen content in the deposition gas used to form the insulating layer 109 is preferably higher than that in the deposition gas used to form the insulating layer 110a. Specifically, when silicon nitride or silicon oxynitride films are deposited as insulating layers 109 and 110a respectively using PECVD, the flow rate ratio of ammonia gas relative to the total deposition gas used to form the insulating layer 109 (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the deposition gas used to form the insulating layer 110a. By depositing the insulating layer 109 under conditions of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 109 can be increased. In addition, the amount of hydrogen released from the insulating layer 109 when heated can be increased.

[0196] The film density of insulating layer 110a is preferably higher than that of insulating layer 109. This suppresses the diffusion of hydrogen contained in insulating layer 109 through insulating layers 110a and 110b into the channel formation region of semiconductor layer 108. Film density can be evaluated, for example, using Rutherford backscattering (RBS) or X-ray reflectance measurement (XRR). Differences in film density can sometimes be evaluated using cross-sectional transmission electron microscopy (TEM) images. In TEM observation, a high film density results in a dense (dark) transmission electron (TE) image, while a low film density results in a faint (bright) TE image. Therefore, in TE images, insulating layer 110a sometimes appears denser (darker) than insulating layer 109. Note that even if insulating layers 109 and 110a use the same material, their film densities differ, and therefore their boundaries can sometimes be observed in cross-sectional TEM images due to differences in contrast.

[0197] This illustration shows insulating layer 110 with a three-layer stacked structure, but the invention is not limited to this. Insulating layer 110 preferably includes at least insulating layer 110b. Alternatively, one or both of insulating layers 110a and 110c may be omitted. Furthermore, insulating layer 110 may also employ a stacked structure with four or more layers.

[0198] [Semiconductor layer 108]

[0199] Specifically, the metal oxide that can be used in semiconductor layer 108 is described. Examples of metal oxides include indium oxide. Other examples include gallium oxide and zinc oxide. The metal oxide preferably contains at least indium. Furthermore, the metal oxide preferably contains one or both of indium and zinc. Additionally, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. Furthermore, element M is a metallic or half-metallic element with a high bond energy with oxygen, for example, a metallic or half-metallic element with a higher bond energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M included in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements have high bond energies with oxygen, and their ionic radii are approximately the same as those of indium or zinc, making them more preferred. Furthermore, tin is more preferred because it is tetravalent, which improves carrier mobility. Note that in this specification, metallic elements and half-metallic elements are sometimes collectively referred to as "metallic elements," and the term "metallic element" as used in this specification sometimes includes half-metallic elements.

[0200] Semiconductor layer 108 may, for example, use indium oxide. Semiconductor layer 108 may also use indium zinc oxide (also known as In-Zn oxide or IZO (registered trademark)), indium tin oxide (also known as In-Sn oxide or ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (also known as In-W oxide or IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (also known as In-Ga-Sn oxide or IGTO), gallium zinc oxide (also known as Ga-Zn oxide or GZO), aluminum zinc oxide (also known as Al... Indium aluminum zinc oxide (also known as In-Al-Zn oxide or IAZO), indium tin zinc oxide (also known as In-Sn-Zn oxide or ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (also known as In-Ga-Zn oxide or IGZO), indium gallium tin zinc oxide (also known as In-Ga-Sn-Zn oxide or IGZTO), indium gallium aluminum zinc oxide (also known as In-Ga-Al-Zn oxide, IGAZO, IGZAO, or IAGZO), etc., can be used. Alternatively, silicon-containing indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0201] Note that metal oxides can also replace indium or contain one or more metals with high period numbers in the periodic table besides indium. The greater the orbital overlap of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including metals with high period numbers, the field-effect mobility of transistors can sometimes be improved. Examples of metals with high period numbers include those belonging to period 5 and period 6. Specifically, examples of such metals include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Furthermore, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are known as light rare earth elements.

[0202] Metal oxides can also contain one or more non-metallic elements. When metal oxides contain non-metallic elements, the field-effect mobility of transistors can sometimes be improved due to increased carrier concentration or narrower band gap. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0203] The field-effect mobility of a transistor can be improved by increasing the proportion of indium atoms relative to the sum of the atomic numbers of all metal elements contained in the metal oxide. Furthermore, transistors with high on-state currents can be realized.

[0204] In this specification, the ratio of the number of indium atoms to the total number of atoms of all contained metallic elements is sometimes described as the indium content. The same applies to other metallic elements. When element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the total number of atoms of all contained metallic elements can be described as the content of element M.

[0205] By increasing the zinc content in metal oxides, highly crystalline metal oxides are produced, thereby suppressing the diffusion of impurities within the metal oxide. Consequently, variations in the electrical characteristics of the transistor are suppressed, thus improving reliability.

[0206] Increasing the content of element M in metal oxides can result in metal oxides with large band gaps. Furthermore, suppressing the formation of oxygen vacancies (V) in metal oxides can also achieve this. O ), inhibition caused by oxygen vacancies (V O This process generates charge carriers, thereby suppressing threshold voltage drift in the transistor. Consequently, the cutoff current can be reduced, enabling normally-off transistors. Furthermore, transistors with low off-state current can be achieved. Additionally, variations in the transistor's electrical characteristics are suppressed, thereby improving reliability.

[0207] The electrical characteristics and reliability of a transistor vary depending on the composition of the metal oxide used in the semiconductor layer 108. Therefore, by changing the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, a semiconductor device with both excellent electrical characteristics and high reliability can be realized.

[0208] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in this In-M-Zn oxide is preferably greater than or equal to the atomic ratio of element M. Examples of such atomic ratios for the metal element in this In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, and In:M:Zn = 5:1:8. Compositions with indium (In:M:Zn) ratios of 5:1:9, 6:1:6, 10:1:1, 10:1:3, 10:1:4, 10:1:6, 10:1:7, 10:1:8, 5:2:5, 10:1:10, 20:1:10, and 40:1:10, as well as their vicinity, are considered. Furthermore, vicinity composition includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in metal oxides can improve the on-state current or field-effect mobility of transistors.

[0209] In In-M-Zn oxides, the atomic ratio of In can also be less than the atomic ratio of element M. Examples of such In-M-Zn oxide atomic ratios include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these ratios. By increasing the proportion of M atoms in the metal oxide, oxygen vacancies (V0) can be suppressed. O The generation of ).

[0210] Note that when element M contains multiple elements, the sum of the atomic ratios of these elements can be set as the atomic ratio of element M.

[0211] By using materials with a high indium content in semiconductor layer 108, the on-state current or field-effect mobility of the transistor can be improved. Furthermore, by including element M, oxygen vacancies (V0) can be suppressed. OThe content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metallic elements) is preferably 0.1% or more and 25% or less, more preferably 0.1% or more and 20% or less, more preferably 0.1% or more and 10% or less, more preferably 0.1% or more and 8% or less, more preferably 0.1% or more and 6% or less, and more preferably 0.1% or more and 4% or less. This allows for the realization of transistors with excellent electrical characteristics. For example, metal oxides with In:M:Zn = 40:1:10 or similar are preferred. Element M is preferably any one or more of the above-mentioned elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides with In:Sn:Zn = 40:1:10 or similar can be used. Alternatively, metal oxides with In:Al:Zn = 40:1:10 or similar can be used.

[0212] Here, by using a metal oxide with a polycrystalline structure for the semiconductor layer 108, grain boundaries become recombination centers, trapping charge carriers, thus sometimes reducing the on-state current of the transistor. Furthermore, by using a metal oxide with a polycrystalline structure for the semiconductor layer 108, sometimes the surface roughness of the semiconductor layer 108 increases. Consequently, the steps on the formed surfaces of layers (e.g., insulating layer 106) on the semiconductor layer 108 sometimes become larger, leading to problems such as breaks or voids in the layer. When using a metal oxide with a composition that easily becomes polycrystalline for the semiconductor layer 108, it is preferable to include elements that inhibit crystallization. This can suppress the semiconductor layer 108 from becoming polycrystalline, thereby enabling the realization of transistors with high on-state currents. Additionally, the coverage of the layers (e.g., insulating layer 106) formed on the semiconductor layer 108 can be improved, thereby suppressing problems such as breaks or voids in the layer.

[0213] For example, compared to indium tin oxide (ITO), silicon-containing indium tin oxide (ITSO) is less likely to form a polycrystalline structure, so it can be used for semiconductor layer 108. When using ITSO, the silicon content (the ratio of the number of silicon atoms to the sum of the number of atoms of all contained metal elements) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, more preferably 3% or more and 15% or less, and more preferably 5% or more and 15% or less. Specifically, In:Sn:Si = 45:5:4, In:Sn:Si = 95:5:8, and metal oxides near them can be used appropriately. When silicon-containing indium tin oxide (ITSO) is used as semiconductor layer 108, it is preferable to have crystallinity. In addition, semiconductor layer 108 can have amorphous regions or be amorphous.

[0214] Metal oxides that do not contain element M can be used for semiconductor layer 108. When the metal oxide is an In-Zn oxide, examples of the atomic ratios of the metal elements include In:Zn = 1:1, In:Zn = 2:1, In:Zn = 1:2, In:Zn = 3:1, In:Zn = 3:2, In:Zn = 2:3, In:Zn = 4:1, In:Zn = 4:3, In:Zn = 5:1, In:Zn = 5:2, In:Zn = 5:3, In:Zn = 5:4, In:Zn = 5:6, In:Zn = 5:7, In:Zn = 5:8, In:Zn = 5:9, In:Zn = 7:1, In:Zn = 10:1, In:Zn = 10:3, In:Zn = 10:7, and compositions near these ratios. Furthermore, the atomic ratio of In is more preferably greater than that of Zn. By increasing the atomic ratio of In in the metal oxide, the on-state current or field-effect mobility of the transistor can be improved.

[0215] In the analysis of the composition of semiconductor layer 108, methods such as energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS or ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, multiple methods can be combined. Peak separation of the obtained spectra is preferred to identify and quantify elements. Note that elements with low content may sometimes have different actual and analytically obtained content rates due to the influence of analytical precision. For example, when the content of element M is low, the analytically obtained content of element M may sometimes be lower than the actual content, making it difficult to quantify the content of element M, or even making element M undetectable.

[0216] Metal oxide films can be deposited using sputtering or atomic layer deposition (ALD). Note that when using sputtering to deposit metal oxide films, the composition of the deposited metal oxide film sometimes differs from that of the sputtering target. In particular, the zinc content in the deposited metal oxide film can sometimes be reduced to about 50% of that in the sputtering target.

[0217] As the semiconductor layer 108, a crystalline metal oxide is preferably used. Examples of crystalline metal oxide structures include CAAC (C-Axis Aligned Crystal), polycrystalline, and nano-crystal (nc) structures. By using a crystalline metal oxide, the defect state density in the semiconductor layer 108 can be reduced, thereby enabling a highly reliable semiconductor device.

[0218] Semiconductor layer 108 preferably uses CAAC-OS or nc-OS.

[0219] The CAAC-OS has multiple layered crystals. The c-axis of these crystals is oriented in the normal direction of the formed surface. Semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the formed surface. For example, semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the top surface of conductive layer 112b in the region contacting the top surface of conductive layer 112b, and layered crystals parallel to or substantially parallel to the side surface in the region contacting the side surface of conductive layer 112b. In particular, semiconductor layer 108 preferably has layered crystals parallel to or substantially parallel to the side surface 70F of the formed surface in the region contacting the side surface 70F of insulating layer 110. By employing this structure, the layered crystals of semiconductor layer 108 are parallel to or substantially parallel to the channel length direction of transistor 100, thus enabling the realization of a transistor with a large on-state current.

[0220] By using highly crystalline metal oxides in the channel formation region, the defect state density in the channel formation region can be reduced. On the other hand, by using low-crystallinity metal oxides, transistors capable of carrying large currents can be realized.

[0221] The higher the substrate temperature during metal oxide film deposition, the more crystalline the metal oxide film can be deposited. The substrate temperature during deposition can be adjusted, for example, according to the temperature of the stage on which the substrate is placed. Furthermore, the higher the oxygen flow rate ratio of the deposition gas or the higher the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide film can be deposited.

[0222] The crystallinity of the semiconductor layer 108 can be analyzed, for example, using X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, multiple of the above methods can be combined for analysis.

[0223] When a metal oxide is used as the semiconductor layer 108, it is preferable to minimize the Vc in the channel formation region. O H is made to be a high-purity intrinsic or substantially high-purity intrinsic. Thus, in order to obtain V... OFor metal oxides with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen from the metal oxide (sometimes described as dehydration or dehydrogenation); and supply oxygen to the metal oxide to repair oxygen vacancies (V). O ). By V O Metal oxides with sufficiently reduced defects such as hydrogen (H) can impart stable electrical characteristics when used in the channel formation region of transistors. Note that sometimes oxygen is supplied to the metal oxide to repair oxygen vacancies (V). O The treatment of ) is called oxidation treatment.

[0224] When a metal oxide is used as the semiconductor layer 108, the carrier concentration in the channel formation region is preferably 1 × 10⁻⁶. 18 cm -3 Below, less than 1×10 is preferred. 17 cm -3 Further optimization of less than 1×10 16 cm -3 It is also preferred to have a value of less than 1×10 13 cm -3 Furthermore, it is preferred to select those with a density lower than 1×10 12 cm -3 Note that there is no lower limit to the carrier concentration in the channel formation region; for example, it can be 1 × 10⁻⁶. -9 cm -3 .

[0225] OS transistors exhibit minimal changes in electrical characteristics due to radiation exposure, meaning they possess high radiation tolerance and are suitable for environments where radiation may be present. OS transistors can also be described as having high reliability against radiation. For example, OS transistors can be used as pixel circuits in X-ray flat panel detectors. Furthermore, OS transistors are suitable for semiconductor devices used in space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton radiation, and neutron radiation).

[0226] Semiconductor layer 108 may also contain layered materials used as semiconductors. Layered materials are a general term for a group of materials with layered crystal structures. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked through bonds weaker than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high conductivity per unit layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity in the channel formation region, transistors with large on-state currents can be realized.

[0227] Examples of the aforementioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen elements (elements belonging to Group 16). Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as channel forming regions in transistors include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0228] Semiconductor layer 108 can be a stacked structure comprising two or more metal oxide layers. The compositions of the two or more metal oxide layers included in semiconductor layer 108 can also be the same or substantially the same. When using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. When the compositions of the two or more metal oxide layers included in semiconductor layer 108 are the same or substantially the same, it is sometimes impossible to clearly identify the boundaries (interfaces) of these metal oxide layers.

[0229] Reference Figure 7A and Figure 7B Explain the channel length and channel width of transistor 100. Figure 7B This is a plan view of the semiconductor device 10. Here, the portion of the semiconductor layer 108 that contacts the side of the insulating layer 110b will be described as the channel formation region.

[0230] exist Figure 7A In the diagram, the channel length L100 of transistor 100 is represented by a dashed double arrow. In cross-section, the channel length L100 of transistor 100 corresponds to the length of the portion where the semiconductor layer 108 contacts the side of the insulating layer 110b. That is, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110b formed by the side of the semiconductor layer 108 of the insulating layer 110b and the surface of the insulating layer 110b to which it is formed (here, the top surface of the insulating layer 110a). Therefore, the channel length L100 can be made smaller than the minimum exposure size of the exposure apparatus, enabling the realization of micro-transistors. Specifically, transistors with extremely short channel lengths that cannot be achieved by existing mass production exposure apparatuses for flat panel displays (e.g., with a minimum size of approximately 2 μm or 1.5 μm) can be realized. Furthermore, transistors with channel lengths less than 10 nm can be achieved without the very expensive exposure apparatuses used in state-of-the-art LSI technologies.

[0231] The thickness of the channel length L100 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and less than 2.5 μm, 10 nm or more and less than 2 μm, 10 nm or more and less than 1.5 μm, 10 nm or more and less than 1.2 μm, 10 nm or more and less than 1 μm, 10 nm or more and less than 500 nm, 10 nm or more and less than 300 nm, 10 nm or more and less than 200 nm, 10 nm or more and less than 100 nm, 10 nm or more and less than 50 nm, 10 nm or more and less than 30 nm, or 10 nm or more and less than 20 nm. For example, the channel length L100 can also be set to 100 nm or more and less than 1 μm.

[0232] By shortening the channel length L100, the on-state current of the transistor 100 can be increased. Using the transistor 100, circuits capable of high-speed operation can be manufactured. Furthermore, the circuit's footprint can be reduced. Therefore, a miniaturized semiconductor device can be realized. For example, when the semiconductor device of one aspect of the present invention is used in a large display device or a high-definition display device, the signal delay of each wiring can be reduced even when the number of wirings increases, thereby suppressing display unevenness. Additionally, since the circuit's footprint can be reduced, the bezel of the display device can be minimized.

[0233] The channel length L100 can be controlled by adjusting the thickness T110b and angle θ110b of the insulating layer 110b.

[0234] The thickness T110b of the insulating layer 110b can be, for example, 5nm or more and less than 3μm, 7nm or more and less than 2.5μm, 10nm or more and less than 2μm, 10nm or more and less than 1.5μm, 10nm or more and less than 1.2μm, 10nm or more and less than 1μm, 10nm or more and less than 500nm, 10nm or more and less than 300nm, 10nm or more and less than 200nm, 10nm or more and less than 100nm, 10nm or more and less than 50nm, 10nm or more and less than 30nm, or 10nm or more and less than 20nm.

[0235] The side surface of the insulating layer 110 on the semiconductor layer 108 side is preferably tapered. The angle θ110b is preferably less than 90 degrees. By reducing the angle θ110b, the coverage of the layer (e.g., semiconductor layer 108) formed on the insulating layer 110 can be improved. In addition, the smaller the angle θ110b, the longer the channel length L100 can be, and the larger the angle θ110b, the shorter the channel length L100 can be.

[0236] Note that, although in Figure 1BThe isoelectric angle θ110b is less than 90 degrees, but one aspect of the invention is not limited to this. The angle θ110b can also be 90 degrees or approximately 90 degrees. Thus, the occupancy area of ​​the semiconductor device can be reduced while shortening the channel length L100 of the transistor 100.

[0237] Angle θ110b can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 75 degrees or less, 50 degrees or more and 70 degrees or less, 55 degrees or more and 70 degrees or less, 60 degrees or more and 70 degrees or less, or 65 degrees or more and 70 degrees or less.

[0238] exist Figure 1B In the cross-section, side surface 70F is shown as a straight line, but this is not the only aspect of the invention. In cross-section, side surface 70F may be curved. Alternatively, it may have both a region where side surface 70F is straight and a region where it is curved. The same applies to side surfaces 70L and 70R.

[0239] The top surface shape of the conductive layer 112b is preferably the same as or substantially the same as the top surface shape of the insulating layer 110. Figure 1A The diagram shows a structure where the top surface shape of the conductive layer 112b is identical to that of the insulating layer 110. The conductive layer 112b and the insulating layer 110 can be formed using the same mask layer. For example, an insulating film becoming the insulating layer 110 and a conductive film becoming the conductive layer 112b are deposited on the insulating film, and a mask layer (e.g., a photoresist mask) is formed on the conductive film. Furthermore, by processing the conductive film and the insulating film using the mask layer as a mask, a conductive layer 112b and an insulating layer 110 with identical or substantially identical top surface shapes can be formed. By processing the insulating film becoming the insulating layer 110 and the conductive film becoming the conductive layer 112b using the same process, manufacturing costs can be reduced. Note that in... Figure 1A In the above, the top surface of the conductive layer 112b and the insulating layer 110 is rectangular, but there are no special restrictions on the top surface shape of the conductive layer 112b and the insulating layer 110.

[0240] Preferably, the side surface of the conductive layer 112b on the semiconductor layer 108 side is flat and without steps (i.e., the two surfaces are identical or substantially identical). This improves the coverage of the layers (e.g., semiconductor layer 108) disposed on the insulating layer 110 and the conductive layer 112b. Alternatively, a structure in which the side surface of the conductive layer 112b on the semiconductor layer 108 side is discontinuous with the side surface 70F can also be used. Furthermore, a structure in which the top surface shape of the conductive layer 112b does not conform to the top surface shape of the insulating layer 110 can also be used.

[0241] Here, the conductive layer 112b preferably does not have a region in contact with the side surface 70F. When the conductive layer 112b is in contact with the side surface 70F, sometimes the channel length L100 of the transistor 100 is shorter than the length of the side surface of the insulating layer 110b, making it difficult to control the channel length L100. Therefore, the top surface shape of the conductive layer 112b is preferably the same as or substantially the same as the top surface shape of the insulating layer 110. Alternatively, when viewed from a planar perspective, the insulating layer 110 preferably includes the conductive layer 112b.

[0242] The channel width of transistor 100 is equivalent to the length of the region where the channel-forming region in semiconductor layer 108 overlaps with the conductive layer 104 when viewed from a planar perspective. Figure 7B In the diagram, the double-headed arrow with a double dotted line represents the channel width W100 of transistor 100.

[0243] When forming the semiconductor layer 108 and the conductive layer 104 using photolithography, the channel width W100 is at or above the limit resolution of the exposure apparatus. For example, the channel width W100 can be 20 nm or more and less than 500 μm, 50 nm or more and less than 200 μm, 100 nm or more and less than 100 μm, 200 nm or more and less than 50 μm, 500 nm or more and less than 20 μm, 1 μm or more and less than 10 μm, or 1 μm or more and less than 5 μm.

[0244] Note that this description uses the region of semiconductor layer 108 in contact with insulating layer 110b as an example of a channel forming region, but the invention is not limited to this. The region of semiconductor layer 108 in contact with insulating layer 110a can also be used as a channel forming region. Similarly, the region of semiconductor layer 108 in contact with insulating layer 110c can also be used as a channel forming region.

[0245] [Conductive layer 112a, conductive layer 112b, conductive layer 104]

[0246] Each of conductive layers 112a, 112b, and 104 can have a single-layer structure or a stacked structure of two or more layers. Examples of materials that can be used for conductive layers 112a, 112b, and 104 include one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive layers 112a, 112b, and 104 can suitably use conductive materials with low resistivity containing one or more of copper, silver, gold, and aluminum. Copper or aluminum is particularly advantageous in terms of mass production and is therefore preferred.

[0247] The conductive layers 112a, 112b, and 104 can all be made of oxide conductors. For details regarding oxide conductors, please refer to the above description.

[0248] Oxygen vacancies (V) are formed in metal oxides with semiconductor properties. O Adding hydrogen to the oxygen vacancy creates a donor level near the conduction band. As a result, the metal oxide's conductivity increases, making it a conductor. Metal oxides that can become conductors are called oxide conductors.

[0249] Conductive layers 112a, 112b, and 104 can all have a stacked structure comprising a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, wiring resistance can be reduced.

[0250] As conductive layers 112a, 112b, and 104, Cu-X alloy films (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be used. By using Cu-X alloy films, processing can be performed using wet etching, thereby reducing manufacturing costs.

[0251] Alternatively, conductive layers 112a, 112b, and 104 may be made of the same material. Or, different materials may be used for at least one of these materials.

[0252] Conductive layers 112a and 112b have regions that contact the semiconductor layer 108. When an oxide semiconductor is used as the semiconductor layer 108, if an easily oxidizable metal (e.g., aluminum) is used as the conductive layer 112a or 112b, an insulating oxide (e.g., aluminum oxide) may form between the conductive layer 112a or 112b and the semiconductor layer 108, potentially hindering their conduction. Therefore, it is preferable to use conductive materials that are not easily oxidized, conductive materials that maintain low resistance even when oxidized, or oxide conductors as the conductive layers 112a and 112b.

[0253] As conductive layers 112a and 112b, materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferably used. These materials are preferred because they are conductive materials that are not easily oxidized or maintain low resistance even when oxidized. Furthermore, when conductive layers 112a or 112b have a stacked structure, it is preferable to use at least the layer in contact with the semiconductor layer 108 using a conductive material that is not easily oxidized.

[0254] The conductive layers 112a and 112b can use the aforementioned oxide conductors. Specifically, indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, silicon-containing In-Sn oxide, or gallium-added zinc oxide, etc., can be used. In particular, indium-containing oxide conductors have high conductivity and are therefore suitable for use in conductive layers 112a and 112b.

[0255] The conductive layers 112a and 112b may also be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0256] [Insulation layer 106]

[0257] The insulating layer 106 preferably comprises one or more inorganic insulating layers. The insulating layer 106 may be made of a material that can be used for the insulating layer 110.

[0258] The insulating layer 106 has a region that contacts each of the semiconductor layer 108, conductive layers 112a, 112b, 104, insulating layer 109, and insulating layer 110. When a metal oxide is used for the semiconductor layer 108, the film constituting the insulating layer 106 that is at least in contact with the semiconductor layer 108 preferably uses the aforementioned oxide or oxynitride. When the insulating layer 106 has a monolayer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be applied to the insulating layer 106.

[0259] Note that when the thickness of the gate insulating layer in a microtransistor is small, leakage current sometimes increases. By using a material with a relatively high permittivity (also known as a high-k material) in the gate insulating layer, it is possible to achieve low voltage operation of the transistor while maintaining the physical thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0260] Figure 1B The diagram shows that the insulating layer 106 is a single-layer structure, but this is not the only aspect of the invention. The insulating layer 106 may also have a stacked structure of two or more layers.

[0261] When the insulating layer 106 has a stacked structure, an oxide or oxynitride is preferably used as the insulating layer on one side of the semiconductor layer 108. For example, one or more of silicon oxide, silicon oxynitride, and aluminum oxide can be used. Alternatively, nitrides or oxynitrides can be used. For example, aluminum nitride can be used.

[0262] Preferably, one or more of the layers constituting the insulating layer 106 are used as a barrier film. By providing the barrier film, the diffusion of metallic components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layers formed on the transistor 100 through the insulating layer 106 to the semiconductor layer 108 can be suppressed. Furthermore, the diffusion of oxygen contained in the insulating layer 110b through the insulating layer 106 to the conductive layer 104 side can be suppressed. As a result, the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108 increases, thereby reducing the oxygen vacancies (V) in the channel formation region. O ) and V O H. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized. Furthermore, the high resistance of the conductive layer 104 caused by oxidation of the conductive layer 104 due to oxygen contained in the insulating layer 110b can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be realized. The aforementioned materials can be used as the barrier film. For example, one or more of silicon nitride, aluminum oxide, and aluminum nitride can be used as one or more layers constituting the insulating layer 106.

[0263] [Substrate 102]

[0264] While there are no particular restrictions on the material of the substrate 102, it must at least possess heat resistance capable of withstanding subsequent heat treatments. For example, the substrate 102 can be a single-crystal semiconductor substrate or polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon-germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or a resin substrate. Alternatively, the substrate 102 can be a substrate on which semiconductor elements are disposed. The substrate 102 can also be a substrate with an insulating film formed on its surface. Note that there are no particular restrictions on the shape of the substrate 102; for example, it can be circular or angular.

[0265] The substrate 102 can be a flexible substrate, and transistors such as transistors 100 can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors such as transistors 100. By providing a release layer, a portion or all of a semiconductor device can be fabricated on the release layer and then separated from the substrate 102 and transferred to another substrate. In this case, transistors such as transistors 100 can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0266] In this specification and other materials, flexibility refers to the property of an object to be flexible and bendable. Flexibility is the property of an object to deform under an external force applied to it, regardless of whether it has elasticity or the ability to recover its original shape before deformation.

[0267] For example, flexible electronic devices can deform according to external forces. Flexible electronic devices can be used in a fixed deformed state, repeatedly deformed, or in a non-deformed state. Similarly, flexible display devices (also called flexible display devices, flexible displays, etc.) can deform according to external forces. Flexible display devices can be used in a fixed deformed state, repeatedly deformed, or in a non-deformed state. Furthermore, flexible substrates (also called flexible substrates, flexible substrates, soft substrates, etc.) can deform according to external forces. Flexible substrates can be used in a fixed deformed state, repeatedly deformed, or in a non-deformed state. Note that "deformation according to external forces" refers to the deformation caused by an ordinary adult's hand without significant force. Additionally, flexibility can be quantified by measuring the deformation of an object under external forces using stress-strain measurement machines (tensile testing machines, compression testing machines, etc.).

[0268] In this specification, the description of "an object being flexible" means that at least a portion of the object is flexible. That is to say, an object that is flexible may also have non-flexible parts (also called rigid parts).

[0269] In this specification, "high flexibility" means that when two objects are deformed by the same external force, the object that deforms more can be considered the object with higher flexibility. Additionally, when the first and second parts of an object are deformed by the same external force, the part that deforms more can also be considered the part with higher flexibility.

[0270] The following describes a semiconductor device whose structure differs from the structural example described above. Descriptions of parts that overlap with the structural example are sometimes omitted. Furthermore, in the accompanying drawings, parts having the same function as those in the structural example described above are depicted using the same shading lines, and sometimes reference numerals are not added.

[0271] <Structure Example 2>

[0272] Figure 8A A plan view of a semiconductor device 10A according to one aspect of the present invention is shown. Figure 8B Show along Figure 8A The cross-sectional view shown is the dotted-dash line A1-A2. Figure 8C The cross-sectional view along the dotted line B1-B2 is shown.

[0273] Figures 9A to 9C A perspective view of semiconductor device 10A is shown. Figure 9A This is a perspective view of semiconductor device 10A. Note that portions of the insulating layers (insulating layer 110 and insulating layer 106) are shown in a transparent manner, while only the edges are shown with dashed lines. Figure 9BFrom Figure 9A The three-dimensional diagram shown omits the conductive layer 104 and the insulating layer 106. Figure 9C From Figure 9B The 3D view shown omits the semiconductor layer 108 and the conductive layer 112b. Note that in... Figure 9C In the insulating layer 110 shown, the area where the insulating layer 110b is exposed in the region that contacts the insulating layer 106 is represented as region 85A, and other regions are shown only by dashed lines at their edges.

[0274] Semiconductor device 10A includes transistor 100A, insulating layer 110, and insulating layer 109. In semiconductor device 10A, insulating layer 106 contacts the top surface of insulating layer 110, primarily at this point. Figure 1B The semiconductor device 10 shown is different.

[0275] Figure 9A The diagram illustrates a structure where the top surface shape of the conductive layer 112b does not conform to the top surface shape of the insulating layer 110. A portion of the end of the conductive layer 112b contacts the top surface of the insulating layer 110. The insulating layer 110 has a region that protrudes beyond the conductive layer 112b. Viewed in plan, the insulating layer 110 preferably includes the conductive layer 112b. Figure 9B As shown, the insulating layer 110 has a region on its top surface where a conductive layer 112b is provided and a region where a conductive layer 112b is not provided. In the region where a conductive layer 112b is not provided, the insulating layer 106 is in contact with the top surface of the insulating layer 110.

[0276] For example, an insulating film is deposited to form an insulating layer 110, and an island-shaped conductive layer on the insulating film is deposited to form a conductive layer 112b. A mask layer (e.g., a photoresist mask) is formed on the conductive layer and the insulating film. Furthermore, by processing the conductive layer and the insulating film using the mask layer as a mask, the conductive layer 112b and the insulating layer 110 can be formed. Preferably, the side surface 70F on the semiconductor layer 108 side of the conductive layer 112b is flat without any steps (i.e., the two surfaces are consistent or substantially consistent). Alternatively, a structure in which the side surface 70F on the semiconductor layer 108 side of the conductive layer 112b is discontinuous can also be used.

[0277] When the insulating layer 110 and the conductive layer 112b are formed using different mask layers, the layout freedom of the insulating layer 110 can be increased. For example, the amount of oxygen supplied from the insulating layer 110 (e.g., the insulating layer 110b) to the semiconductor layer 108 can be increased by increasing the area of ​​the insulating layer 110. This reduces the oxygen vacancies (V) in the channel formation region. O ) and V O H.

[0278] In addition, although Figure 9AThe diagram shows a structure in which a transistor (here, transistor 100A) is disposed in the insulating layer 110, but one aspect of the invention is not limited thereto. The insulating layer 110 may also contain multiple transistors. For example, multiple transistors may be provided, including a semiconductor layer 108 in contact with side 70F. Furthermore, in addition to transistors including semiconductor layers 108 in contact with side 70F, transistors may also be provided that include semiconductor layers in contact with sides of the insulating layer 110 other than side 70F.

[0279] In the structure of semiconductor device 10A, region 85A is the region where insulating layer 110 (here, insulating layer 110b) contacts insulating layer 106, and is the region where oxygen contained in insulating layer 110 may diffuse into insulating layer 106. That is, region 85A in semiconductor device 10A is the region equivalent to region 85 in semiconductor device 10. Even if a semiconductor device of one aspect of the present invention has a structure like semiconductor device 10A, a semiconductor device with good electrical properties can be obtained by including the insulating layer 106 with the aforementioned elements that readily bond with oxygen or elements that are stable by bonding with oxygen.

[0280] <Structure Example 3>

[0281] Figure 10A A plan view of a semiconductor device 10B according to one aspect of the present invention is shown. Figure 10B Show along Figure 10A The cross-sectional view shown is the dotted-dash line A1-A2. Figure 10C The cross-sectional view along the dotted line B1-B2 is shown.

[0282] Figure 11A , Figure 11B and Figure 12 A perspective view of semiconductor device 10B is shown. Figure 11A This is a perspective view of semiconductor device 10B. Note that portions of the insulating layers (insulating layer 110 and insulating layer 106) are shown in a transparent manner, while only the edges are shown with dashed lines. Figure 11B From Figure 11A The three-dimensional diagram shown omits the conductive layer 104 and the insulating layer 106. Figure 12 From Figure 11B The 3D view shown omits the semiconductor layer 108 and the conductive layer 112b. Note that in... Figure 12 In the insulating layer 110 shown, the area of ​​the insulating layer 110b exposed in the region that contacts the insulating layer 106 is represented as region 85B, and other regions are shown only by dashed lines at their edges.

[0283] Semiconductor device 10B includes transistor 100B, insulating layer 110, and insulating layer 109. In semiconductor device 10B, insulating layer 110 is interrupted by a trench (also called a slit), primarily at this point... Figure 1B The semiconductor device 10 shown is different.

[0284] The insulating layer 110 has a slit 137 that reaches the conductive layer 112a and the insulating layer 109. For example... Figure 10B As shown, the insulating layer 110 has a pair of opposing sides (side 70F and side 70Fa) separated by a slit 137. Side 70F has a portion located on the conductive layer 112a and a portion located on the insulating layer 109. Similarly, side 70Fa has a portion located on the conductive layer 112a and a portion located on the insulating layer 109.

[0285] A conductive layer 112b and a conductive layer 112bS are provided on the insulating layer 110. The conductive layer 112bS is the remaining portion of the conductive layer 112b that was broken off when the slit 137 was formed. The conductive layer 112b is provided on the insulating layer 110 on the side 70F, and the conductive layer 112bS is provided on the insulating layer 110 on the side 70Fa. Note that the conductive layer 112bS may also be omitted.

[0286] Semiconductor layer 108 has a region that contacts the top and side surfaces of conductive layer 112b, the top and side surfaces of conductive layer 112bS, side surface 70F, side surface 70Fa, and the top surface of conductive layer 112a. Semiconductor layer 108 is connected to conductive layer 112a and conductive layer 112b. Semiconductor layer 108 has a shape that runs along the top and side surfaces of conductive layer 112b, conductive layer 112bS, side surface 70F, side surface 70Fa, and the top surface of conductive layer 112a. Semiconductor layer 108 is disposed such that it spans the region on conductive layer 112a where insulating layer 110 is disposed and the region on conductive layer 112a where insulating layer 110 is not disposed. Furthermore, semiconductor layer 108 is disposed not only on side surface 70F but also on side surface 70Fa.

[0287] An insulating layer 106 is disposed on the semiconductor layer 108, and a conductive layer 104 is disposed on the insulating layer 106. The conductive layer 104 has a region that faces the side surface 70F, separated from the insulating layer 106 and the semiconductor layer 108. Additionally, the conductive layer 104 has a region that faces the side surface 70Fa, separated from the insulating layer 106 and the semiconductor layer 108. Note that the conductive layer 112bS does not contact the conductive layer 112b, nor is it connected to the source electrode or the drain electrode; therefore, the region of the semiconductor layer 108 that contacts the side surface 70Fa is not used as the channel formation region of the transistor 100B. The region of the semiconductor layer 108 that contacts the side surface 70F is used as the channel formation region of the transistor 100B.

[0288] The conductive layer 104 preferably covers not only the channel formation region but also the entire semiconductor layer 108. This suppresses damage to the semiconductor layer 108 during the formation of the layer on the transistor 100B. Alternatively, the semiconductor layer 108 may have a structure in which regions are not covered by the conductive layer 104.

[0289] Figure 10A The diagram shows a structure in which the insulating layer 110 is divided into two by a slit 137 extending in one direction. Note that there are no particular restrictions on the shape of the top surface of the slit 137.

[0290] Although Figure 10A The diagram shows a structure in which a transistor (here, transistor 100B) is disposed in the insulating layer 110, but the present invention is not limited to this. The insulating layer 110 may also contain multiple transistors. For example, multiple transistors may be disposed in the region of the semiconductor layer 108 that contacts side 70F, serving as a channel formation region. In addition to the transistors in the region of the semiconductor layer 108 that contacts side 70F, transistors may also be disposed in the region of the semiconductor layer 108 that contacts side 70Fa, serving as a channel formation region. Transistors may also be disposed comprising semiconductor layers that contact sides of the insulating layer 110 other than side 70F and side 70Fa. Thus, a semiconductor device with high-density transistor integration can be realized.

[0291] In the structure of semiconductor device 10B, region 85B is the region where insulating layer 110 (here, insulating layer 110b) contacts insulating layer 106, and is the region where oxygen contained in insulating layer 110 may diffuse into insulating layer 106. That is, region 85B in semiconductor device 10B is the region equivalent to region 85 in semiconductor device 10. Even if a semiconductor device of one aspect of the present invention has a structure like semiconductor device 10B, a semiconductor device with good electrical properties can be obtained by including the insulating layer 106 with the aforementioned elements that readily bond with oxygen or elements that are stable by bonding with oxygen.

[0292] <Structure Example 4>

[0293] Figure 13A A plan view of a semiconductor device 10C according to one aspect of the present invention is shown. Figure 13B Show along Figure 13A The cross-sectional view shown is the dotted-dash line A1-A2. Figure 13C The cross-sectional view along the dotted line B1-B2 is shown.

[0294] Figure 14A , Figure 14B and Figure 15 A perspective view of semiconductor device 10C is shown. Figure 14AThis is a perspective view of semiconductor device 10C. Note that portions of the insulating layers (insulating layer 110 and insulating layer 106) are shown in a transparent manner, while only the edges are shown with dashed lines. Figure 14B From Figure 14A The three-dimensional diagram shown omits the conductive layer 104 and the insulating layer 106. Figure 15 From Figure 14B The 3D view shown omits the semiconductor layer 108 and the conductive layer 112b. Note that in... Figure 15 In the insulating layer 110 shown, the area of ​​the insulating layer 110b exposed in the region that contacts the insulating layer 106 is represented as region 85C, and other regions are shown only by dashed lines at their edges.

[0295] Semiconductor device 10C includes transistor 100C, insulating layer 110, and insulating layer 109. In semiconductor device 10C, conductive layer 112b and insulating layer 110 include openings, primarily in this respect... Figure 1B The semiconductor device 10 shown is different.

[0296] The conductive layer 112b and the insulating layer 110 have an opening 141 leading to the conductive layer 112a. The opening 141 includes the opening included in the conductive layer 112b and the opening included in the insulating layer 110. Alternatively, the side surface of the conductive layer 112b, the side surface of the insulating layer 110 (i.e., side surface 70F), and the top surface of the conductive layer 112a are exposed in the opening 141.

[0297] A semiconductor layer 108 is provided across the opening 141.

[0298] An insulating layer 106 is disposed on the semiconductor layer 108, and a conductive layer 104 is disposed on the insulating layer 106. The semiconductor layer 108, the insulating layer 106, and the conductive layer 104 all have regions located within the opening 141.

[0299] Figure 13A The top surface of the opening 141 is shown to be a rectangular structure with rounded corners, but this is not a limitation of the present invention. The shape of the top surface of the opening 141 is not limited; for example, it can be a circle, ellipse, triangle, quadrilateral (including rectangles, rhombuses, and squares), pentagon, or any of the aforementioned polygons with rounded corners. The polygon can also be a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees). Furthermore, when the top surface of the opening 141 is circular, the machining accuracy during the formation of the opening 141 can be improved, thereby enabling the formation of a fine opening 141. Note that in this specification, the circle is not limited to a perfect circle.

[0300] The opening 141 is provided only in the semiconductor layer 108 and its surrounding area, while the insulating layer 110 is provided in the remaining areas. Therefore, the area of ​​the region where the insulating layer 110 is provided can be increased, and the unevenness caused by the difference between the region where the insulating layer 110 is provided and the region where the insulating layer 110 is not provided can be reduced. This improves the coverage of the layer provided on the transistor 100C and the insulating layer 110, thereby suppressing defects such as breaks or voids in the layer.

[0301] In the structure of semiconductor device 10C, region 85C is the region where insulating layer 110 (here, insulating layer 110b) contacts insulating layer 106, and is the region where oxygen contained in insulating layer 110 may diffuse into insulating layer 106. That is, region 85C in semiconductor device 10C is the region equivalent to region 85 in semiconductor device 10. Even if a semiconductor device of one aspect of the present invention has a structure like semiconductor device 10C, a semiconductor device with good electrical properties can be obtained by including the insulating layer 106 with the aforementioned elements that readily bond with oxygen or elements that are stable by bonding with oxygen.

[0302] This embodiment can be appropriately combined with other embodiments. Furthermore, in this specification, where multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0303] (Implementation Method 2)

[0304] In this embodiment, an indium oxide film of the semiconductor layer of a transistor included in a semiconductor device that can be used in one aspect of the present invention is described.

[0305] Note that in this specification, etc., indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). For example, monocrystalline indium oxide, polycrystalline indium oxide, microcrystalline indium oxide, etc. can be cited as crystal IO or crystalline IO.

[0306] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also known as IGZO) and zinc oxide.

[0307] The carrier concentration dependence of Hall mobility for indium oxide, silicon, and IGZO is explained. Figure 16A It concerns silicon (Si) and indium oxide (InO). X A schematic diagram illustrating the carrier concentration dependence of Hall mobility. Figure 16B This is a schematic diagram showing the carrier concentration dependence of Hall mobility in IGZO.

[0308] First, such as Figure 16B As indicated by the arrows, IGZO tends to exhibit higher Hall mobility with higher carrier concentration. On the other hand, as... Figure 16A As indicated by the arrows, indium oxide (INO) tends to exhibit higher Hall mobility with lower carrier concentrations (see Non-Patent Literature 1). This tendency is similar to that of silicon; the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs, and the higher the Hall mobility. In other words, in INO, higher purity and more intrinsic properties result in higher Hall mobility. From this result, it can be concluded that, unlike IGZO, INO possesses properties close to those of silicon. Note that... Figure 16A The properties of indium oxide shown are those assuming a single crystal. Therefore, when indium oxide is not a single crystal (e.g., polycrystalline), its properties may differ. Figure 16A The characteristics shown are different.

[0309] exist Figure 16A In this context, the range R1, characterized by low carrier concentration, corresponds to a range with extremely high Hall mobility. Therefore, it can be considered, for example, a suitable range of carrier concentrations for the channel formation region of a transistor. For instance, in indium oxide, the range R1 includes carrier concentrations of 1 × 10⁻⁶. 15 cm -3 The range, for example, is 1×10 14 cm -3 Above and 1×10 18 cm -3 The following range. By sufficiently reducing the carrier concentration, it is expected that the Hall mobility value can be increased to 270 cm⁻¹. 2 Approximately / (V·s).

[0310] Furthermore, in indium oxide, the region with a carrier concentration in the range R1 can contain elements that reduce the carrier concentration. Examples of elements that reduce carrier concentration include magnesium, calcium, zinc, cadmium, and copper. Replacing indium with these elements reduces the carrier concentration. Other examples of elements that reduce carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, replacing oxygen with nitrogen, phosphorus, arsenic, or antimony reduces the carrier concentration.

[0311] On the other hand, the range of high carrier concentration R2 is the range of low resistance; for example, it can be said to be the range of carrier concentrations suitable for use in the source and drain regions of transistors, resistive bodies, or transparent conductive films. The range R2 includes carrier concentrations of 1 × 10⁻⁶. 20 cm -3 The range, for example, is 1×10 19 cm -3 Above and 1×10 22 cm -3The following range. By significantly increasing the carrier concentration, it is expected that the resistivity can be reduced to 1 × 10⁻⁶. -4 Below Ω·cm.

[0312] Furthermore, in indium oxide, the region with a carrier concentration in the range R2 can contain elements that increase the carrier concentration. For example, it is preferable to include the same elements as the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements whose oxides have conductive or semiconductor properties.

[0313] Thus, in indium oxide (IO), regions with low carrier concentration are used for the channel formation region of the transistor, while regions with high carrier concentration are used for the source and drain regions. In other words, IO can also be considered an oxide capable of controlling valence electrons. Note that in IGZO, strain sometimes forms in the source and drain regions due to the stress of the electrodes in contact with the IGZO, resulting in n-type regions. On the other hand, unlike IGZO, IO can control valence electrons, so strain can be formed in the film as little as in IGZO. When the strain in the film is low, improved reliability can be expected. For example, by forming carrier concentrations of [missing information] in the IO film... Figure 16A The regions R1 and R2 shown can form a so-called nin junction (a combination of n-type, i-type, and n-type regions). Note that valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technical concept that is not usually considered.

[0314] By utilizing the above-described technical concept, the indium oxide-containing transistor in this specification, etc., has two or more of the following features (1) to (5), preferably three or more, more preferably four or more, and most preferably five. (1) High on-state current (in other words, high mobility). (2) Low off-state current. (3) Capable of being normally off. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide-containing transistor in this specification, etc., has high mobility, low off-state current, and can be normally off. This transistor is different from a transistor with high mobility that is normally on.

[0315] Next, an indium oxide film for transistors will be described. The indium oxide film preferably has crystalline properties (i.e., contains grains). Examples of grain-containing films include monocrystalline films, polycrystalline films, and amorphous films containing grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a monocrystalline film. Monocrystalline films do not have grain boundaries (also called grain boundaries). Impurities that impede carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at grain boundaries. By using a monocrystalline film, carrier scattering at grain boundaries can be suppressed, thereby enabling transistors with high field-effect mobility. Furthermore, excellent effects such as suppressing inhomogeneities in transistor characteristics caused by grain boundaries are achieved.

[0316] Furthermore, compared to microcrystalline or amorphous films, polycrystalline films can reduce carrier scattering and exhibit high field-effect mobility, making them preferred. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. Note that in transistors using polycrystalline indium oxide films, if there are no grain boundaries or no grain boundaries can be observed in the channel formation region, since the channel formation region is located within the single-crystal region contained in the polycrystalline film, it can be considered as a single-crystal indium oxide transistor.

[0317] Note that the crystallinity of indium oxide can be analyzed using methods such as XRD, TEM, or ED. Alternatively, multiple methods described above can be combined for analysis.

[0318] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is included in a single grain, or a semiconductor layer in which the crystal axis orientation is the same in at least two regions of the channel formation region, can be referred to as a single crystal film. Additionally, a semiconductor layer in which the orientation of other crystal axes continuously changes within a single grain in the channel formation region, with a certain crystal axis or a certain crystal orientation as the axis of rotation, can also be referred to as a single crystal film.

[0319] Note that the channel formation region refers to the area in the semiconductor layer that overlaps (or is opposite) to the gate electrode across the gate insulating layer, and specifically the region located between the area contacting the source electrode and the area contacting the drain electrode. The current path in the channel formation region is the shortest distance between the source and drain electrodes. Therefore, in cross-sectional observation including the semiconductor layer, source electrode, and drain electrode, grains, grain boundaries, grain axes, crystal orientations, etc., can be identified in the channel formation region.

[0320] The lower the impurity concentration of the indium oxide film in the channel formation region, the better. Impurities in the indium oxide film in the channel formation region can act as sources of carrier scattering, thus potentially reducing the field-effect mobility. Furthermore, these impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, etc., are elements that may be contained in the deposition gas or precursors during deposition; sometimes, the amount of carbon, hydrogen, etc., remaining in the indium oxide film is greater than that of the aforementioned impurities.

[0321] Furthermore, the indium oxide film in the channel formation region can also contain elements that, like indium, are likely to become trivalent cations, within the range where its crystal structure remains cubic (manganese-iron oxide type). Examples include elements from Group 13 and Group 3 of the periodic table, such as gallium and aluminum. Because these elements are predominantly trivalent cations in oxides, the carrier concentration of indium oxide can be kept low.

[0322] By using this indium oxide film in transistors, 50cm transistors can be achieved. 2 / (V·s) or more, preferably 100cm 2 / (V·s) or more, more preferably 150cm 2 / (V·s) or more, preferably 200cm 2 / (V·s) or more, and further preferably 250cm 2 The field-effect mobility of transistors is above / (V·s).

[0323] One characteristic of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example... Figure 16C As shown, diffusion occurs into the indium oxide film (referred to as InO). X Oxygen (O) permeates through the indium oxide membrane and is released as oxygen molecules (O2). Additionally, it is sometimes released as water molecules (H2O) by reacting with hydrogen contained in the membrane. Furthermore, when oxygen vacancies (V) are present in the membrane... O When oxygen diffuses, it fills the oxygen vacancies. Because oxygen diffuses easily, indium oxide films can be said to fill oxygen vacancies more easily than IGZO films.

[0324] Thus, compared to IGZO films, indium oxide films are easier to reduce oxygen vacancies in the film. Therefore, by using this indium oxide film in transistors, transistors with extremely high reliability can be realized.

[0325] In addition, such as Figure 16CAs shown, hydrogen diffuses through the indium oxide membrane. Hydrogen diffuses from the outside into the indium oxide membrane and is released as hydrogen molecules (H2) through the membrane. Alternatively, the hydrogen reacts with oxygen contained in the membrane and is released as water molecules.

[0326] Transistors using indium oxide (IO) films are accumulation-type transistors where electrons are the majority carriers. Assuming a fixed relaxation time for the carriers, the smaller the effective mass of the electrons (charge carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective electron mass, in transistors, the on-state current or field-effect mobility of the transistor can be improved.

[0327] Table 1 shows the effective mass of single-crystal indium oxide (In₂O₃) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Furthermore, indium oxide also has the characteristic that the effective mass of electrons is almost independent of crystal orientation. Therefore, by using crystalline indium oxide in transistors, transistors with high field-effect mobility and high frequency characteristics (also known as f-characteristics) can be realized. Moreover, due to the large effective mass of holes, transistors with extremely low off-state currents can be realized. For example, by using an indium oxide film in a vertical transistor, the off-state current per channel width of 1 μm can be 1 fA (1 × 10⁻⁶) at 125°C. -15 A) or below or 1aA (1×10 -18 A) Below this, at room temperature (25°C), the off-state current per channel width of 1 μm can be 1 A (1 × 10⁻⁶). -18 A) or below or 1zA (1×10 -21 A) Below. Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes compared to silicon, making it possible to realize transistors with higher field-effect mobility and lower off-state current compared to Si transistors.

[0328] [Table 1]

[0329] Preferably, the seed layer is disposed in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference (also known as lattice mismatch) from the lattice constant of indium oxide. This improves the crystallinity of the indium oxide film. Alternatively, a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0330] One method for evaluating the degree of lattice mismatch is to use the lattice mismatch value shown below. The lattice mismatch Δa[%] of the crystal contained in the formed film (in this case, an indium oxide film) relative to the crystal contained in the seed layer is calculated as Δa = ((L1-L2) / L2) × 100. Here, L1 represents the length of the unit lattice vector or lattice constant of the crystal contained in the formed film, and L2 represents the length of the unit lattice vector or lattice constant of the crystal contained in the seed layer.

[0331] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the better, and most preferably 0. For example, Δa can be -5% or more and less than 5%, preferably -4% or more and less than 4%, more preferably -3% or more and less than 3%, and even more preferably -2% or more and less than 2%.

[0332] Here, indium oxide crystals have a cubic crystal structure (argentite-manganese type). For example, yttrium-stabilized zirconia (YSZ) crystals can have a cubic crystal structure (fluorite type). With a lattice mismatch between the indium oxide crystal and the cubic YSZ crystal, indium oxide single-crystal films can be epitaxially grown on a YSZ substrate in the range of -2% to 2%.

[0333] Note that sometimes the crystal system or crystal orientation of the seed layer may differ from that of the indium oxide film. For example, a film containing a hexagonal or trigonal crystal structure can be used under an indium oxide film containing a cubic crystal structure. For example, setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the bottom surface of the indium oxide film to

[111] can satisfy the crystal orientation conditions required for epitaxial growth. Examples of hexagonal or trigonal crystals include wurtzite-type structures, YbFe2O4-type structures, Yb2Fe3O7-type structures, and their variant structures. IGZO is an example of a crystal with a YbFe2O4-type or Yb2Fe3O7-type structure.

[0334] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0335] (Implementation Method 3)

[0336] In this embodiment, refer to Figures 17A to 19D This invention describes a method for manufacturing a semiconductor device according to one aspect of the present invention. Note that, regarding the materials and forming methods of each constituent element, some parts that are the same as those described in Embodiment 1 above are sometimes omitted.

[0337] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be deposited using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD. Additionally, metal-organic chemical vapor deposition (MOCVD) is one type of thermal CVD method.

[0338] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using wet deposition methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, or doctor blade coating.

[0339] When processing thin films that constitute semiconductor devices, photolithography and other methods can be used. Alternatively, nanoimprint lithography, sandblasting, and lift-off methods can be used to process the thin films. Furthermore, island-shaped thin films can be directly formed using deposition methods that utilize metal masks or similar masking techniques.

[0340] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film through etching, and then removing the resist mask. The other method involves depositing a photosensitive thin film, followed by exposure and development to process the film into the desired shape.

[0341] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these. Alternatively, ultraviolet light, KrF lasers, or ArF lasers can also be used. Immersion exposure can also be employed. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Alternatively, an electron beam can be used instead of the light for exposure. Extreme ultraviolet light, X-rays, or electron beams allow for extremely fine processing and are therefore preferred. Furthermore, when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0342] In thin film etching, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0343] <Example of Manufacturing Method>

[0344] Here, refer to Figures 17A to 19D illustrate Figures 1A to 1C An example of a method for manufacturing the semiconductor device 10 shown. Figures 17A to 19D Show Figure 1A The cross-sectional view between the dotted and dashed lines A1-A2 is shown.

[0345] First, an insulating layer 109 is deposited on the substrate 102. The insulating layer 109 can be deposited using sputtering or PECVD methods.

[0346] Next, a conductive film is deposited on the insulating layer 109 to form a conductive layer 112a, and this conductive film is processed to form the conductive layer 112a. Figure 17A This conductive film can be deposited using a sputtering method.

[0347] Next, an insulating film 110af, which forms an insulating layer 110a, and an insulating film 110bf, which forms an insulating layer 110b, are sequentially deposited on the conductive layer 112a. Figure 17B ).

[0348] Insulating films 110af and 110bf can be deposited using sputtering or PECVD methods. Preferably, insulating film 110bf is deposited after insulating film 110af without exposing the surface of insulating film 110af to the atmosphere. This suppresses the adhesion of atmospheric impurities to the surface of insulating film 110af. Examples of such impurities include water and organic matter. For example, it is preferable to continuously deposit insulating film 110bf using the same apparatus after depositing insulating film 110af.

[0349] The substrate temperature during the deposition of insulating films 110af and 110bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. By setting the substrate temperature during the deposition of insulating films 110af and 110bf within the above range, the amount of impurities (such as water and hydrogen) released from the insulating films 110af and 110bf themselves can be reduced, thereby suppressing impurity diffusion into the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0350] Note that insulating films 110af and 110bf are formed before the semiconductor layer 108 is formed, so there is no need to worry about oxygen being removed from the semiconductor layer 108 due to the heat applied during the deposition of insulating films 110af and 110bf.

[0351] After depositing insulating films 110af and 110bf, a heat treatment can be performed. By performing a heat treatment, impurities (such as water and hydrogen) can be removed from the film of insulating film 110af, the film of insulating film 110bf, and the surface.

[0352] After depositing the insulating film 110bf, oxygen can be supplied to the insulating film 110bf. Methods for supplying oxygen include, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment. For plasma treatment, a device that plasma-plasmizes oxygen gas at high-frequency power can be suitably used. Examples of devices that plasma-plasmize gas at high-frequency power include PECVD devices, plasma etching devices, and plasma ashing devices. Plasma treatment is preferably performed in an oxygen-containing atmosphere. For example, it is preferable to perform plasma treatment in an atmosphere containing one or more of oxygen, nitrous oxide (N2O), nitrogen dioxide (NO2), carbon monoxide, and carbon dioxide. The oxygen supply amount can be adjusted, for example, according to the power and processing time during plasma treatment. Figure 17C In the image, an arrow schematically illustrates the supply of oxygen (oxygen 180) to the insulating film 110bf.

[0353] After depositing the insulating film 110bf, nitrogen can be supplied to the insulating film 110bf. The method for supplying nitrogen can refer to the description of the oxygen supply method above. As a nitrogen supply method, plasma treatment in a nitrogen-containing atmosphere can be suitably used. For example, plasma treatment is preferably performed in an atmosphere containing one or more of nitrogen, nitrous oxide (N2O), and nitrogen dioxide (NO2). The nitrogen supply amount can be adjusted, for example, according to the power and treatment time in the plasma treatment.

[0354] In the insulating layer (here, insulating film 110bf or the subsequent insulating layer 110b), nitrogen oxides (NO) are generated through the reaction of nitrogen and oxygen. X (where X is a real number greater than 0). Examples of nitrogen oxides include N₂O, NO, and NO₂. In the insulating layer, the nitrogen oxide forms an energy level located within the band gap of the metal oxide. For example, the migration energy level that migrates between the 0 and -1 charge states of NO₂ is located within the band gap of indium oxide. Therefore, when a nitrogen oxide (e.g., NO₂) diffuses to or near the interface between the insulating layer and the semiconductor layer containing the metal oxide, this energy level traps electrons. As a result, a negative charge (also called a negative fixed charge) is formed at or near the interface between the insulating layer and the semiconductor layer, thus causing the threshold voltage of the transistor to drift in the positive direction. This allows for the realization of normally-off transistors (in the case of an n-channel transistor), thereby enabling low-power semiconductor devices.

[0355] Increasing the amount of oxide nitride can shift the threshold voltage towards the positive side. However, excessive amounts of oxide nitride can increase the fluctuation of the threshold voltage when a positive potential (positive bias) is applied to the transistor gate, potentially leading to decreased reliability. Therefore, the amount of oxide nitride is preferably within a range that does not affect reliability.

[0356] The amount of nitrogen oxides can be evaluated, for example, using thermal desorption spectroscopy (TDS) to measure the release amount or electron spin quantity using electron spin resonance (ESR). In TDS, the release amounts of NO (mass-to-charge ratio, also known as m / z = 30), N₂O (m / z = 44), and NO₂ (m / z = 46) can be evaluated. Note that it is sometimes difficult to quantify the amount of NO₂ released in TDS. In this case, the amount of NO₂ can be assessed by evaluating the release amounts of NO and N₂O. In ESR, the ESR signal derived from NO₂ can be used. Because there are seven electrons in a nitrogen atom and eight electrons in an oxygen atom, the electrons in the NO₂ molecule have an open-shell structure. Therefore, since the neutral NO₂ molecule has isolated electrons, it can be measured using ESR. Furthermore, because... 14 N has one nuclear spin, so it is related to 14 The peak of the ESR signal related to N splits into three. At this point, the split width of the ESR signal is the hyperfine coupling constant.

[0357] There are no particular restrictions on the order of oxygen and nitrogen supply processes. Oxygen can be supplied after nitrogen. Nitrogen can also be supplied after oxygen. Alternatively, oxygen and nitrogen can be supplied through the same process. For example, oxygen and nitrogen can be supplied by plasma treatment in an atmosphere containing nitrogen and oxygen. For example, plasma treatment using nitrous oxide (N2O) is preferred because it can efficiently generate nitrogen oxides.

[0358] Furthermore, this plasma treatment can be performed after the deposition of the insulating film 110bf without exposing the surface of the insulating film 110bf to the atmosphere. For example, when the insulating film 110bf is deposited using a PECVD apparatus, it is preferable to perform this plasma treatment within the PECVD apparatus. This can improve productivity. Specifically, N2O plasma treatment can be performed continuously after the insulating film 110bf is deposited using a PECVD apparatus.

[0359] Next, preferably, film 130 is deposited on insulating film 110bf. Figure 17D Sputtering can be appropriately used when depositing film 130. Oxygen can be supplied to insulating film 110bf by depositing film 130 in an oxygen-containing atmosphere.

[0360] There are no limitations on the conductivity of the film 130. The film 130 can be at least one of insulating films, semiconductor films, and conductive films. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 130.

[0361] The film 130 is preferably made of an oxide material containing one or more of the same elements as the semiconductor layer 108. In particular, an oxide semiconductor that can be used in the semiconductor layer 108 is preferred.

[0362] During the deposition of membrane 130, a higher oxygen flow rate ratio or oxygen partial pressure in the processing chamber of the deposition apparatus increases the amount of oxygen supplied to the insulating membrane 110bf. The oxygen flow rate ratio or oxygen partial pressure is preferably 50% or more and 100% or less, more preferably 60% or more and 100% or less, further preferably 70% or more and 100% or less, further preferably 80% or more and 100% or less, and further preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% so that the oxygen partial pressure is as close as possible to 100%.

[0363] Thus, by depositing film 130 using sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf during film deposition while preventing oxygen detachment from the insulating film 110bf. As a result, more oxygen can be confined within the insulating film 110bf. Furthermore, more oxygen can be supplied to the semiconductor layer 108 through subsequent heat treatment. As a result, the number of oxygen vacancies (V) in the semiconductor layer 108 can be reduced. O ) and V O H, thus enabling the realization of transistors that exhibit good electrical characteristics and high reliability.

[0364] Heating can be performed after the deposition of membrane 130. By performing heating after the deposition of membrane 130, oxygen can be effectively supplied from membrane 130 to insulating membrane 110bf.

[0365] The heat treatment temperature is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, more preferably 300°C or higher and 400°C or lower, and more preferably 350°C or higher and 400°C or lower. The heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, and oxygen. Dry air (CDA) can also be used as a nitrogen-containing or oxygen-containing atmosphere. Note that the content of hydrogen or water in this atmosphere is preferably as low as possible. As this atmosphere, a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, is preferred. By using an atmosphere with the lowest possible content of hydrogen, water, etc., the absorption of hydrogen, water, etc., by the insulating films 110af and 110bf can be prevented as much as possible. This heat treatment can be performed using an oven, a rapid thermal annealing (RTA) apparatus, etc. Using an RTA apparatus can shorten the heat treatment time.

[0366] Oxygen can also be supplied to the insulating film 110bf through film 130 after deposition of film 130 or after the above-described heat treatment. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. For details regarding plasma treatment, please refer to the above description; therefore, detailed explanation is omitted.

[0367] Next, remove membrane 130 ( Figure 17E There are no particular restrictions on the removal method for film 130; wet etching can be appropriately used. By using wet etching, the etching of insulating film 110bf during the removal of film 130 can be suppressed. Therefore, the thickness of insulating film 110bf can be prevented from decreasing, and the thickness of insulating layer 110b can be made uniform.

[0368] The treatment of supplying oxygen to the insulating film 110bf is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating film 110bf using ion doping, ion implantation, or plasma treatment. Alternatively, oxygen can be supplied to the insulating film 110bf through a film that inhibits oxygen desorption after depositing the film on the insulating film 110bf. Preferably, the film is removed after oxygen supply. As the aforementioned film that inhibits oxygen desorption, conductive or semiconductor films containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0369] Next, an insulating film 110cf (which becomes an insulating layer 110c) is deposited on the insulating film 110bf. Figure 18A The deposition of insulating film 110cf can be referred to the record concerning the deposition of insulating film 110af.

[0370] When an oxide or oxynitride is used in the insulating layer 110c, oxygen can be supplied to the insulating film 110bf by depositing the insulating film 110cf in an oxygen-containing atmosphere. The insulating film 110cf can be deposited using a sputtering method. For example, as the insulating film 110cf, an alumina film can be deposited using an aluminum target in an oxygen-containing atmosphere by sputtering. When depositing the insulating film 110cf, the higher the oxygen flow rate ratio of the deposition gas introduced into the processing chamber of the deposition apparatus or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 110bf. The oxygen flow rate ratio or oxygen partial pressure is preferably 50% or more and 100% or less, more preferably 60% or more and 100% or less, further preferably 70% or more and 100% or less, further preferably 80% or more and 100% or less, and further preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% so that the oxygen partial pressure is as close as possible to 100%.

[0371] By depositing the insulating film 110cf in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf during the deposition of the insulating film 110cf while preventing oxygen detachment from the insulating film 110bf. As a result, more oxygen can be confined within the insulating film 110bf. Furthermore, a greater amount of oxygen can be supplied to the semiconductor layer 108 through subsequent heat treatment. Consequently, the number of oxygen vacancies (V) in the semiconductor layer 108 can be reduced. O ) and V O H, thus enabling the realization of transistors that exhibit good electrical characteristics and high reliability.

[0372] Heat treatment can be performed after the deposition of insulating film 110cf. By performing heat treatment after the deposition of insulating film 110cf, oxygen can be effectively supplied from insulating film 110cf to insulating film 110bf.

[0373] Next, a conductive film 112bf is deposited on the insulating film 110cf to form a conductive layer 112b. Figure 18B The conductive film 112bf can be deposited using a suitable sputtering method.

[0374] Next, the conductive film 112bf, insulating film 110cf, insulating film 110bf, and insulating film 110af are processed to form conductive layer 112b, insulating layer 110c, insulating layer 110b, and insulating layer 110a, respectively. Figure 18C Thus, an insulating layer 110 is formed, comprising insulating layers 110a, 110b, and 110c. The insulating layer 110 and the conductive layer 112b are formed such that they overlap with the conductive layer 112a. The conductive layer 112b can be formed, for example, by wet etching. The insulating layer 110 can be formed, for example, by dry etching.

[0375] The conductive layer 112b and the insulating layer 110 can be formed, for example, using the same photoresist mask. After depositing the insulating films (insulating films 110af, 110bf, and 110cf) and the conductive film 112bf to form the insulating layer 110, a photoresist mask is formed on the conductive film 112bf. The conductive film 112bf and the insulating film are then processed using this photoresist mask, thereby forming the conductive layer 112b and the insulating layer 110 respectively. By using the same photoresist mask in the formation of each of the conductive layer 112b and the insulating layer 110, productivity can be improved. Furthermore, the top surfaces of the conductive layer 112b and the insulating layer 110 can be made to have the same or substantially the same shape. Alternatively, different photoresist masks can be used in the formation of the conductive layer 112b and the insulating layer 110.

[0376] Next, a metal oxide film 108f, forming a semiconductor layer 108, is deposited in a manner that covers conductive layers 112a, conductive layers 112b, and an insulating layer 110. Figure 18D The metal oxide film 108f is disposed in such a manner that it contacts the top surface of the conductive layer 112a, the top and side surfaces of the conductive layer 112b, and the side surface of the insulating layer 110.

[0377] The metal oxide film 108f is preferably deposited using a sputtering method with a metal oxide target. Alternatively, the metal oxide film 108f is preferably deposited using an ALD method. By using the ALD method, the metal oxide film 108f can be deposited with high coverage on the sides of the insulating layer 110 and the sides of the conductive layer 112b. In addition, the deposition rate is easily controlled by the ALD method, so thin films can be deposited with high yield. Therefore, the ALD method is particularly preferred when the thickness of the metal oxide film 108f is small. Alternatively, CVD can be used instead of sputtering and ALD methods when depositing the metal oxide film 108f.

[0378] The metal oxide film 108f is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film 108f is preferably a high-purity film, wherein hydrogen-containing impurities are minimized as much as possible. In particular, a crystalline metal oxide film is preferably used as the metal oxide film 108f.

[0379] Oxygen gas is preferably used when depositing the metal oxide film 108f. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or oxynitride is used in the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0380] By supplying oxygen to the insulating layer 110b, oxygen can be supplied from the insulating layer 110b to the semiconductor layer 108 in subsequent processes, thereby reducing oxygen vacancies (V) in the semiconductor layer 108. O) and V O H.

[0381] When depositing a metal oxide film 108f, oxygen gas and inactive gases (e.g., helium, argon, xenon, etc.) can be mixed. Note that the higher the oxygen flow rate or oxygen partial pressure of the deposition gas during metal oxide film deposition, the higher the crystallinity of the metal oxide film can be, thereby enabling transistors with high reliability. On the other hand, the lower the oxygen flow rate or oxygen partial pressure, the lower the crystallinity and the higher the conductivity of the metal oxide film can be formed, thereby enabling transistors with high on-state current.

[0382] Here, when the oxygen flow ratio or oxygen partial pressure is high, the metal oxide film sometimes exhibits a polycrystalline structure. When using a metal oxide film with a polycrystalline structure, grain boundaries become recombination centers and trap charge carriers, thus sometimes reducing the on-state current of the transistor. Therefore, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure to prevent the metal oxide film 108f from exhibiting a polycrystalline structure. Since the composition of the metal oxide film makes it prone to polycrystalline structures, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure according to the composition of the metal oxide film 108f. However, one aspect of the invention is not limited to this, and a metal oxide film with a polycrystalline structure can also be used. When the grain boundaries of the polycrystalline metal oxide film do not affect the transistor characteristics, a transistor using a metal oxide film with a polycrystalline structure can achieve a higher reliability compared to a transistor using a metal oxide film with low crystallinity.

[0383] Higher substrate temperatures during metal oxide film deposition result in denser, more crystalline metal oxide films, enabling the development of highly reliable transistors. Conversely, lower substrate temperatures allow for the formation of less crystalline metal oxide films with higher conductivity, enabling the development of transistors with higher on-state current.

[0384] The substrate temperature for depositing the metal oxide film 108f is preferably above room temperature and below 250°C, more preferably above room temperature and below 200°C, and even more preferably above room temperature and below 140°C. For example, the substrate temperature is preferably above room temperature and below 140°C, which can improve productivity. In addition, by depositing the metal oxide film at room temperature or without heating the substrate, crystallinity can be reduced.

[0385] Note that at high substrate temperatures, metal oxide films sometimes exhibit a polycrystalline structure. It is preferable to vary the substrate temperature according to the composition of the material used in the metal oxide film 108f.

[0386] When using ALD methods, thermal ALD or PEALD (Plasma Enhanced ALD) deposition methods are preferred. Thermal ALD is preferred because it offers extremely high coverage. PEALD is preferred because it not only offers high coverage but also allows for low-temperature deposition.

[0387] Metal oxide films can be deposited, for example, using a precursor containing the constituent metal element and an oxidant, and employing the ALD method.

[0388] For example, when depositing an In-Ga-Zn oxide film, three precursors can be used: one containing indium, one containing gallium, and one containing zinc. Alternatively, two precursors can be used: one containing indium and one containing both gallium and zinc.

[0389] Examples of indium-containing precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptadecanoic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0390] Examples of gallium-containing precursors include trimethyl gallium, triethyl gallium, gallium trichloride, tris(dimethylamide) gallium(III), gallium acetylacetonate(III), tris(2,2,6,6-tetramethyl-3,5-heptadecanoate) gallium, dimethyl gallium chloride, and diethyl gallium chloride.

[0391] As aluminum-containing precursors, aluminum chloride and trimethylaluminum can be used, for example.

[0392] Examples of tin-containing precursors include tin(IV) chloride and tetra(dimethylamide)tin.

[0393] Examples of zinc-containing precursors include dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptadecanoic acid) zinc, and zinc chloride.

[0394] Examples of oxidizing agents include ozone, oxygen, and water.

[0395] As a method for controlling the composition of the obtained membrane, one or more of the following can be adjusted: the type of source gas, the flow rate ratio of the source gas, the time the source gas flows through, and the order in which the source gas flows through. By adjusting these parameters, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these parameters, a metal oxide film 108f with a continuously varying composition can be deposited.

[0396] Before depositing the metal oxide film 108f, it is preferable to perform at least one of a treatment to remove water, hydrogen, organic matter, etc., adsorbed on the surface of the insulating layer 110 and a treatment to supply oxygen to the insulating layer 110. For example, a heating treatment can be performed at a temperature of 70°C or higher and 200°C or lower under a reduced pressure atmosphere. Alternatively, a plasma treatment in an oxygen-containing atmosphere can be performed. Alternatively, oxygen can be supplied to the insulating layer 110 by performing plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide (N2O). When performing plasma treatment containing nitrous oxide gas, organic matter on the surface of the insulating layer 110 can be appropriately removed and oxygen can be supplied. Preferably, after such treatment, the metal oxide film 108f is continuously deposited in a manner that does not expose the surface of the insulating layer 110 to the atmosphere.

[0397] Note that when the semiconductor layer 108 has a stacked structure, it is preferable to deposit the upper metal oxide film continuously after depositing the previously deposited metal oxide film in a manner that does not expose its surface to the atmosphere.

[0398] When the semiconductor layer 108 has a stacked structure, all layers constituting the semiconductor layer 108 can be deposited using the same method (e.g., sputtering or ALD). Alternatively, different deposition methods can be used depending on the layers. For example, a first metal oxide layer can be deposited using sputtering, and a second metal oxide layer can be deposited on the first metal oxide layer using ALD.

[0399] Next, the metal oxide film 108f is processed into islands to form the semiconductor layer 108. Figure 19A ).

[0400] The semiconductor layer 108 can be formed using a wet etching method. In this case, sometimes a portion of the conductive layer 112b in the region that does not overlap with the semiconductor layer 108 is etched, resulting in a reduced thickness. Similarly, sometimes a portion of the conductive layer 112a in the region that does not overlap with the semiconductor layer 108 is etched, resulting in a thinner layer. Additionally, in Figure 8A During the fabrication of the semiconductor device 10A shown, sometimes a portion of the insulating layer 110 in a region that does not overlap with both the semiconductor layer 108 and the conductive layer 112b is etched, resulting in a reduction in thickness. For example, sometimes the insulating layer 110c in the insulating layer 110 disappears due to etching, exposing the surface of the insulating layer 110b. Note that during the etching of the metal oxide film 108f, by using a material with a high selectivity as the insulating layer 110c, the reduction in the thickness of the insulating layer 110c can be suppressed.

[0401] Preferably, the heat treatment is performed after depositing the metal oxide film 108f or after processing the metal oxide film 108f into a semiconductor layer 108. Heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108 or adsorbed on its surface. Furthermore, heat treatment can sometimes improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (e.g., reduce defects or improve crystallinity).

[0402] Oxygen can also be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108 through heat treatment. More preferably, the heat treatment is performed before processing into the semiconductor layer 108. Details regarding the heat treatment can be found above, so further explanation is omitted.

[0403] Note that this heat treatment is not always necessary. Alternatively, a heat treatment performed in a later step can be used instead of this step. Furthermore, sometimes a heat treatment in a later step (e.g., a deposition step) can also serve as the heat treatment for this step.

[0404] Next, an insulating layer 106 is deposited in a manner that covers a semiconductor layer 108, a conductive layer 112a, a conductive layer 112b, and an insulating layer 110. Figure 19B The insulating layer 106 can be deposited, for example, using PECVD, sputtering, or ALD methods.

[0405] When an oxide semiconductor is used in the semiconductor layer 108, the insulating layer 106 is preferably used as a barrier film to suppress oxygen diffusion. By making the insulating layer 106 have the function of suppressing oxygen diffusion, it is possible to prevent oxygen from diffusing through the insulating layer 106 to the conductive layer 104 and causing the conductive layer 104 to be oxidized. As a result, transistors exhibiting good electrical characteristics and high reliability can be realized.

[0406] By increasing the temperature at which the insulating layer 106 is deposited as the gate insulating layer, an insulating layer with fewer defects can be formed. However, at higher temperatures when the insulating layer 106 is deposited, oxygen escapes from the semiconductor layer 108, and sometimes oxygen vacancies (V) in the semiconductor layer 108... O ) and V O H increases. The substrate temperature during the deposition of the insulating layer 106 is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 450°C or lower, more preferably 300°C or higher and 450°C or lower, and even more preferably 300°C or higher and 400°C or lower. By setting the substrate temperature during the deposition of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced, and oxygen detachment from the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0407] Plasma treatment can be performed on the surface of the semiconductor layer 108 before depositing the insulating layer 106. This plasma treatment reduces impurities such as water adsorbed on the surface of the semiconductor layer 108. Therefore, impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, thereby enabling the realization of a highly reliable transistor. In particular, this method is suitable for situations where the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the deposition of the insulating layer 106. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, etc. The plasma treatment and the deposition of the insulating layer 106 are preferably performed continuously without exposure to the atmosphere.

[0408] Next, impurity element 190 is supplied to insulating layer 106. Figure 19C ).

[0409] Impurity element 190 can be supplied using either ion doping or ion implantation. These methods allow for high-precision control of the concentration distribution along the depth direction based on factors such as ion acceleration voltage and dosage.

[0410] By using ion implantation, which involves mass separation of the ionized source gas, the purity of the supplied impurity element 190 can be improved. When using ion implantation, the aforementioned elements that readily bond with oxygen or elements that are stable when bonded with oxygen are preferably used as impurity element 190; boron is more preferably used.

[0411] Furthermore, productivity can be improved by using ion doping, which involves mass separation of the source gas without ionization. When using ion doping, the impurity element 190 preferably consists of an element that readily bonds with oxygen, or an element that is stable by bonding with oxygen, and hydrogen; more preferably, it consists of boron and hydrogen.

[0412] The ion implantation or ion doping apparatus used in supplying impurity element 190 is also used in the manufacture of Si transistors such as LTPS transistors. Therefore, it is preferred to use the apparatus from existing LTPS production lines without requiring new equipment investment. This reduces the initial equipment investment cost when manufacturing semiconductor devices.

[0413] When the supply method for impurity element 190 utilizes ion doping, for example, using B₂H₆ as the source gas and an accelerating voltage of 1 keV or higher and 10 keV or lower, a dose of 1.0 × 10⁻⁶ is applied. 15 ions / cm 2 Above and 1.0×10 16 ions / cm 2The following boron (B) is supplied to the insulating layer 106. Additionally, for example, the insulating layer 106 is made to have a boron concentration of 1.0 × 10⁻⁶. 19 atoms / cm 3 The above, preferably 5.0×10 19 atoms / cm 3 The above, and more preferably 1.0×10 20 atoms / cm 3 The above, and more preferably 2.0×10 20 atoms / cm 3 The above, and preferably 3.0×10 20 atoms / cm 3 Under the conditions of the above regions, 190 impurity elements are supplied.

[0414] Note that the source gas for impurity element 190 is not limited to B2H6; for example, BF3 can also be used.

[0415] Next, impurity element 191 is supplied to semiconductor layer 108 through insulating layer 106. Figure 19D As impurity element 191, an impurity element capable of reducing the resistance of the source and drain regions of the aforementioned transistor can be used.

[0416] Impurity element 191 can be supplied using either ion doping or ion implantation.

[0417] As described above, impurity element 190 is supplied to the insulating layer 106, while impurity element 191 is supplied to the semiconductor layer 108 through the insulating layer 106. Therefore, when both impurity element 190 and impurity element 191 are supplied using ion doping or ion implantation, it is preferable that the accelerating voltage for supplying impurity element 191 is higher than the accelerating voltage for supplying impurity element 190. This allows the concentration peak of the region where impurity element 191 is supplied to be located at a deeper position (closer to the substrate 102 side) than the concentration peak of the region where impurity element 190 is supplied.

[0418] When using ion implantation, the impurity element 191 is preferably an element that can reduce the resistance of the source and drain regions of the transistor, and more preferably boron or phosphorus.

[0419] Furthermore, when using ion doping, the impurity element 191 is preferably a combination of the element that can reduce the resistance of the source and drain regions of the transistor and hydrogen, and more preferably a combination of boron or phosphorus and hydrogen.

[0420] Furthermore, impurity element 191 is preferably supplied from a direction perpendicular to or substantially perpendicular to the top surface of substrate 102. In this case, the amount of impurity element 191 supplied to the region inclined to the top surface of substrate 102 in semiconductor layer 108 is less than that in the region parallel to or substantially parallel to the top surface of substrate 102. In other words, the amount of impurity element 191 supplied to the source and drain regions in semiconductor layer 108 is greater than that in the channel formation region. Therefore, the resistance of the source and drain regions can be selectively reduced.

[0421] In the supply processing of impurity element 191, it is preferable to control the processing conditions such that the concentration of the impurity element in the portion of the semiconductor layer 108 overlapping with the conductive layer 112a or conductive layer 112b is higher than the concentration of the impurity element in other regions. This allows for the supply of the most suitable concentration of impurity element 191 to the source and drain regions of the semiconductor layer 108.

[0422] As the source gas for impurity element 191, a gas containing the aforementioned impurity element can be used. When supplying boron, B₂H₆ gas or BF₃ gas is typically used. Similarly, when supplying phosphorus, PH₃ gas is typically used. Alternatively, a mixture of these source gases diluted with hydrogen or a rare gas can also be used.

[0423] In addition to the above, source gases can include CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, (C5H5)2Mg, and rare gases. Furthermore, the ion source is not limited to gases; solids or liquids can also be heated to vaporize them.

[0424] Note that there are no restrictions on the method of supplying impurity element 191; for example, plasma treatment or thermal diffusion treatment caused by heating can also be used. In the case of plasma treatment, plasma treatment is performed by generating plasma in a gas atmosphere containing the supplied impurity element 191, thereby supplying the impurity element 191. As the apparatus for generating the aforementioned plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, or high-density plasma CVD apparatus can be used, etc.

[0425] In one embodiment of the invention, impurity element 191 is supplied to semiconductor layer 108 through insulating layer 106. This suppresses the decrease in crystallinity of semiconductor layer 108 during the supply of impurity element 191. Therefore, the increase in resistance due to decreased crystallinity can be suppressed.

[0426] Furthermore, when the insulating layer 106 is deposited after the supply of impurity element 191, the deposition chamber of the insulating layer 106 may become contaminated. Therefore, it is preferable to supply impurity element 191 after the deposition of the insulating layer 106.

[0427] Alternatively, an insulating layer 106 can be deposited on the semiconductor layer 108 after the impurity element 191 is directly supplied to the semiconductor layer 108. This can suppress damage to the insulating layer 106 caused by the supply of the impurity element 191.

[0428] Furthermore, it is preferable to perform the impurity element 191 supply process simultaneously with heating the substrate 102. This allows for the repair of damage to the semiconductor layer 108 incurred during the supply of impurity element 191. In other words, the semiconductor layer 108 can be supplied with impurity element 191 and the damage resulting from this supply can be repaired in parallel. Additionally, damage to the insulating layer 106 incurred during the supply of impurity element 191 can also be repaired.

[0429] The substrate temperature in the supply process of impurity element 191 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and lower than 500°C, more preferably 200°C or higher and lower than 450°C, more preferably 250°C or higher and lower than 400°C, more preferably 250°C or higher and lower than 350°C, or more preferably 300°C or higher and lower than 400°C, more preferably 300°C or higher and lower than 350°C.

[0430] Heat treatment can also be performed after the supply of impurity element 191. By performing this heat treatment, damage to the semiconductor layer 108 and the insulating layer 106 during the supply process of impurity element 191 can be repaired.

[0431] The heat treatment temperature after supplying impurity element 191 is preferably 150°C or higher and lower than the strain point of the substrate, more preferably 200°C or higher and lower than 500°C, more preferably 200°C or higher and lower than 450°C, more preferably 250°C or higher and lower than 400°C, more preferably 250°C or higher and lower than 350°C, or preferably 300°C or higher and lower than 400°C, more preferably 300°C or higher and lower than 350°C.

[0432] Note that in this embodiment, impurity element 190 is supplied to insulating layer 106. Figure 19C Then, impurity element 191 is supplied to semiconductor layer 108. Figure 19D Examples are given, but not limited to. Alternatively, a manufacturing method can be used where impurity element 191 is supplied to semiconductor layer 108 first, followed by impurity element 190 to insulating layer 106.

[0433] Furthermore, when the resistance of the source and drain regions of the semiconductor layer 108 has been sufficiently reduced, it may be necessary not to supply the impurity element 191 to the semiconductor layer 108. This can reduce the number of manufacturing steps in the semiconductor device.

[0434] Next, a conductive layer 104 is formed on the insulating layer 106. Figure 1B When depositing the conductive film to form the conductive layer 104, methods such as sputtering, thermal CVD (including MOCVD), or ALD can be appropriately used.

[0435] Through the above-described process, a semiconductor device 10 according to one aspect of the present invention can be manufactured.

[0436] This implementation method can be appropriately combined with other implementation methods.

[0437] (Implementation Method 4)

[0438] In this embodiment, refer to Figures 20 to 28B This invention describes a display device according to one aspect of the present invention.

[0439] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used, for example, in the display section of the following devices: electronic devices with large screens such as television sets, desktop or laptop computers, monitors for computers, digital signage, and large game machines such as pinball machines; digital cameras; digital video cameras; digital photo frames; mobile phones; portable game consoles; portable information terminals; and sound reproduction devices.

[0440] The display device in this embodiment can be a high-definition display device. Therefore, for example, the display device in this embodiment can be used in the display section of information terminal devices (wearable devices) such as watch-type or bracelet-type devices, as well as in the display section of wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses-type devices.

[0441] One aspect of the semiconductor device of the present invention can be used in a display device or a module including the display device. Examples of modules including the display device include modules in which the display device is mounted with connectors such as Flexible Printed Circuit (FPC) or TCP (Tape Carrier Package), and modules in which integrated circuits (ICs) are mounted via COG (Chip On Glass) or COF (Chip On Film).

[0442] The display device of this embodiment can also have the function of a touch panel. For example, various detection elements (or sensor elements) capable of detecting the approach or contact of a detection object such as a finger can also be used in the display device.

[0443] Examples of sensor types include capacitive, resistive film, surface acoustic wave, infrared, optical, and pressure-sensitive types.

[0444] As electrostatic capacitive types, there are surface-type electrostatic capacitive types and projection-type electrostatic capacitive types. Furthermore, as projection-type electrostatic capacitive types, there are self-capacitance types and mutual-capacitance types. Mutual-capacitance types are preferred because they allow for simultaneous multi-point sensing.

[0445] Examples of touch panels include Out-Cell, On-Cell, and In-Cell types. Note that an In-Cell type touch panel refers to a structure in which one or both of the substrate supporting the display element and the opposing substrate are provided with electrodes constituting the detection element.

[0446] <Display Device 50A>

[0447] Figure 20 This is a 3D view of display device 50A.

[0448] The display device 50A has a structure that bonds substrate 152 and substrate 151. Figure 20 In the image, substrate 152 is represented by a dashed line.

[0449] The display device 50A includes a display section 162, a connection section 140, a circuit section 164, a conductive layer 165, etc. Figure 20 An example is shown where display device 50A is equipped with IC173 and FPC172. Therefore, it is also possible to... Figure 20 The structure shown is called a display module including display device 50A, IC and FPC.

[0450] The connecting portion 140 is disposed on the outer side of the display portion 162. The connecting portion 140 may be disposed along one or more edges of the display portion 162. There may also be one or more connecting portions 140. Figure 20 An example is shown in which the connection portion 140 is arranged around the four sides of the display portion 162. In the connection portion 140, the common electrode of the display element is connected to the conductive layer, and a potential can be supplied to the common electrode.

[0451] The circuit section 164 may include, for example, a scan line driving circuit (also known as a gate driver). Alternatively, the circuit section 164 may include both a scan line driving circuit and a signal line driving circuit (also known as a source driver).

[0452] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. The signals and power are input to the conductive layer 165 from the outside via FPC 172 or from IC 173.

[0453] Figure 20 An example is shown where IC 173 is mounted on substrate 151 using a COG or COF method. IC 173 can be, for example, an IC that includes one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module do not necessarily need to have an IC mounted on them. Alternatively, the IC can also be mounted on an FPC using a COF method or the like.

[0454] One aspect of the semiconductor device of the present invention can be used, for example, in one or both of the display section 162 and the circuit section 164 of the display device 50A. Oxide-semiconductor (OS) transistors can be applied to the channel formation region of the transistors included in the display device. By using OS transistors, a low-power display device can be realized. Alternatively, the semiconductor device of one aspect of the present invention can be used in both the display section 162 and the circuit section 164, meaning that all transistors included in the display device are OS transistors. Thus, by using OS transistors as all transistors included in the display device, the manufacturing cost can be reduced.

[0455] For example, when the semiconductor device of one aspect of the present invention is used in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, thereby realizing a high-definition display device. Furthermore, for example, when the semiconductor device of one aspect of the present invention is used in the driving circuit of a display device (e.g., one or both of a gate line driving circuit and a source line driving circuit), the occupied area of ​​the driving circuit can be reduced, thereby realizing a display device with a narrow bezel. In addition, the semiconductor device of one aspect of the present invention has excellent electrical characteristics; by using this semiconductor device in a display device, the reliability of the display device can be improved.

[0456] Display unit 162 is an image display area in display device 50A, including a plurality of pixels 201 arranged periodically. Figure 20 This shows a magnified view of pixel 201.

[0457] There are no particular limitations on the arrangement of pixels in the display device of this embodiment, and various methods can be used. Examples of pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, and Pentile arrangement.

[0458] Figure 20The pixel 201 shown includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that there is no particular limitation on the number of sub-pixels included in a pixel.

[0459] Subpixel 11R, subpixel 11G and subpixel 11B each include a display element and a circuit for controlling the drive of the display element.

[0460] Various components can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, MEMS (Micro Electro Mechanical Systems) elements using shutter-based or optical interference methods, as well as display elements employing microencapsulation, electrophoresis, electrowetting, or electronic powder fluid methods (registered trademark), can be used. Furthermore, QLED (Quantum-dot LED) technology, which utilizes a light source and employs quantum dot materials for color conversion, can also be used.

[0461] Examples of display devices using liquid crystal elements include transmissive liquid crystal displays, reflective liquid crystal displays, and transflective liquid crystal displays.

[0462] Examples of display device modes that can be used with liquid crystal elements include Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (Anti-Ferroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, and guest-host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0463] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, polymer-dispersed liquid crystals (PDLCs), polymer network liquid crystals (PNLCs), ferroelectric liquid crystals, and antiferroelectric liquid crystals. These liquid crystal materials exhibit cholesteric, smectic, cubic, chiral nematic, isotropic, and blue phases, depending on the conditions. Furthermore, either positive or negative liquid crystals can be used as liquid crystal materials, and the choice can be made based on the mode or design used.

[0464] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, Mini LEDs and Micro LEDs can be used as LEDs.

[0465] Light-emitting materials contained in light-emitting elements include, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).

[0466] The light-emitting element can emit colors such as infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, when the light-emitting element has a microcavity structure, the color purity can be further improved.

[0467] In the pair of electrodes included in the light-emitting element, one electrode is used as the anode and the other electrode is used as the cathode.

[0468] The display device of one aspect of the present invention may also adopt any of the following structures: a top emission type that emits light in the direction opposite to that of the substrate on which the light-emitting element is formed, a bottom emission type that emits light in the direction of the substrate on which the light-emitting element is formed, and a dual emission type that emits light in both directions.

[0469] Figure 21A An example of a cross-section of a portion of the display device 50A including the region of FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the region including the end is shown.

[0470] Figure 21A The display device 50A shown includes transistors 205D, 205R, 205G, and 205B, as well as light-emitting elements 130R, 130G, and 130B, located between substrates 151 and 152. Light-emitting element 130R is a display element included in sub-pixel 11R that emits red light; light-emitting element 130G is a display element included in sub-pixel 11G that emits green light; and light-emitting element 130B is a display element included in sub-pixel 11B that emits blue light.

[0471] The display device 50A adopts an SBS structure. Because the SBS structure allows for optimization of materials and structure in each light-emitting element, the freedom in material and structural selection is increased, making it easier to improve brightness and reliability.

[0472] The display device 50A adopts a top-emitting type. In the top-emitting type, transistors and the like can be arranged in a manner that overlaps with the light-emitting area of ​​the light-emitting element, so the pixel aperture ratio can be further improved compared with the bottom-emitting type.

[0473] Transistors 205D, 205R, 205G, and 205B are all formed on substrate 151. These transistors can be manufactured using the same process. Alternatively, transistors 205D, 205R, 205G, and 205B can also be transistors with different structures from each other.

[0474] In this embodiment, an example is shown where transistors 205D, 205R, 205G, and 205B all use OS transistors. Transistors 205D, 205R, 205G, and 205B can use transistors according to one aspect of the present invention. That is, in the display device 50A, both the display unit 162 and the circuit unit 164 include transistors according to one aspect of the present invention. By using transistors according to one aspect of the present invention in the display unit 162, pixel size can be reduced, thereby achieving high definition. Furthermore, by using transistors according to one aspect of the present invention in the circuit unit 164, the area occupied by the circuit unit 164 can be reduced, thereby achieving narrow bezels. For details regarding transistors according to one aspect of the present invention, please refer to the description of the above embodiment.

[0475] Specifically, transistors 205D, 205R, 205G, and 205B all include a conductive layer 104 serving as a gate, an insulating layer 106 serving as a gate insulating layer, conductive layers 112a and 112b serving as source and drain, and a semiconductor layer 108 comprising a metal oxide. Here, the multiple layers obtained by processing the same conductive film are shaded with the same lines. An insulating layer 110 is located between conductive layers 112a and 112b. An insulating layer 106 is located between conductive layer 104 and semiconductor layer 108.

[0476] Note that the transistors included in the display device of this embodiment are not limited to the transistors of one aspect of the present invention. For example, transistors including one aspect of the present invention and transistors with other structures may also be combined.

[0477] The display device of this embodiment may include, for example, any one or more of planar transistors, interleaved transistors, and anti-interleaved transistors. The transistors included in the display device of this embodiment have either a top-gate or bottom-gate structure. Alternatively, gates may be disposed on the top and bottom of the semiconductor layer forming the channel.

[0478] The display device in this embodiment may also include Si transistors.

[0479] To increase the luminous brightness of the light-emitting element included in a pixel circuit, it is necessary to increase the current flowing through the element. This requires increasing the source-drain voltage of the driving transistor included in the pixel circuit. Because the source-drain breakdown voltage of an OS transistor is higher than that of a Si transistor, a higher voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor in the pixel circuit, the current flowing through the light-emitting element can be increased, thereby improving its luminous brightness.

[0480] When a transistor operates in the saturation region, an OS transistor, compared to a Si transistor, allows for a smaller change in the source-drain current in response to changes in the gate-source voltage. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing through the source-drain can be precisely determined based on the gate-source voltage change, thus controlling the amount of current flowing through the light-emitting element. This, in turn, increases the grayscale level of the pixel circuit.

[0481] Regarding the saturation of current flowing through a transistor when it operates in the saturation region, compared to a Si transistor, an OS transistor can maintain a stable current (saturation current) even when the source-drain voltage is gradually increased. Therefore, by using an OS transistor as a driving transistor, a stable current can flow through the light-emitting element even if the current-voltage characteristics of the element, for example, become non-uniform. In other words, when an OS transistor operates in the saturation region, the source-drain current remains almost constant even when the source-drain voltage is changed, thus stabilizing the brightness of the light-emitting element.

[0482] The transistors included in the circuit section 164 and the transistors included in the display section 162 may have the same structure or different structures. The multiple transistors included in the circuit section 164 may have the same structure or two or more different structures. Similarly, the multiple transistors included in the display section 162 may have the same structure or two or more different structures.

[0483] All transistors included in the display unit 162 can be OS transistors, all transistors included in the display unit 162 can be Si transistors, some transistors included in the display unit 162 can be OS transistors and the remaining transistors can be Si transistors.

[0484] For example, by using both LTPS transistors and OS transistors in the display section 162, a display device with low power consumption and high driving capability can be realized. Furthermore, the structure combining LTPS transistors and OS transistors is sometimes referred to as LTPO. As a more preferred example, a structure can be described as follows: using an OS transistor as a switch to control the conduction / non-conduction between wirings, and using an LTPS transistor to control current.

[0485] For example, one of the transistors included in the display unit 162 is used as a transistor to control the current flowing through the light-emitting element and can also be called a driving transistor. One of the source and drain of the driving transistor is connected to the pixel electrode of the light-emitting element. An LTPS transistor is preferably used as this driving transistor. This increases the current flowing through the light-emitting element in the pixel circuit.

[0486] On the other hand, one of the other transistors included in the display unit 162 is used as a switch to control the selection and non-selection of pixels, and can also be referred to as a selection transistor. The gate of the selection transistor is connected to a gate line, and one of its source and drain is connected to a source line (signal line). An OS transistor is preferably used as the selection transistor. Therefore, even at significantly low frame rates (e.g., below 1 fps), the grayscale of the pixels can be maintained, thereby reducing power consumption by stopping the driver when displaying static images.

[0487] An insulating layer 218 is provided to cover transistors 205D, 205R, 205G and 205B, and an insulating layer 235 is provided on the insulating layer 218.

[0488] The insulating layer 218 is preferably used as a protective layer for the transistor. The insulating layer 218 is preferably made of a material from which impurities such as water and hydrogen do not easily diffuse. Therefore, the insulating layer 218 can be used as a barrier film. By employing this structure, the diffusion of impurities from the outside into the transistor can be effectively suppressed, thereby improving the reliability of the display device.

[0489] The insulating layer 218 preferably comprises one or more inorganic insulating layers. The insulating layer 218 may be made of a material that is also suitable for the insulating layer 110.

[0490] The insulating layer 235 is preferably used as a planarization layer, and an organic insulating film is suitable. Examples of materials suitable for use as organic insulating films include acrylic resins, polyimide resins, epoxy resins, polyamide resins, polyimide amide resins, silicone resins, benzocyclobutene resins, phenolic resins, and precursors of these resins. Alternatively, the insulating layer 235 can also be a laminated structure of organic and inorganic insulating films. The outermost layer of the insulating layer 235 is preferably used as an etching protection layer. Therefore, when processing pixel electrodes 111R, 111G, 111B, etc., the formation of recesses in the insulating layer 235 can be suppressed. Alternatively, recesses can be formed in the insulating layer 235 during the processing of pixel electrodes 111R, 111G, 111B, etc. Note that pixel electrodes 111R, 111G, and 111B are sometimes collectively referred to as pixel electrode 111.

[0491] Light-emitting elements 130R, 130G and 130B are disposed on the insulating layer 235.

[0492] The light-emitting element 130R includes a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. Figure 21A The light-emitting element 130R shown emits red light (R). The EL layer 113R includes a light-emitting layer that emits red light.

[0493] The light-emitting element 130G includes a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. Figure 21A The light-emitting element 130G shown emits green light (G). The EL layer 113G includes a light-emitting layer that emits green light.

[0494] The light-emitting element 130B includes a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. Figure 21A The light-emitting element 130B shown emits blue light (B). The EL layer 113B includes a light-emitting layer that emits blue light.

[0495] Note that in Figure 21A In this design, EL layers 113R, 113G, and 113B all have the same thickness, but are not limited to this. The thicknesses of EL layers 113R, 113G, and 113B can also be different. For example, it is preferable to set the thickness to enhance the optical path of the light emitted by EL layers 113R, 113G, and 113B. This allows for a microcavity structure to improve the color purity of the light emitted from each light-emitting element.

[0496] Pixel electrode 111R is connected to the conductive layer 112b of transistor 205R through an opening in insulating layer 106, insulating layer 218, and insulating layer 235. Similarly, pixel electrode 111G is connected to the conductive layer 112b of transistor 205G, and pixel electrode 111B is connected to the conductive layer 112b of transistor 205B.

[0497] Each end of pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B is covered by insulating layer 237. Insulating layer 237 serves as a partition wall. Insulating layer 237 can be configured as a single layer or a multilayer structure using one or both of inorganic and organic insulating materials. For example, insulating layer 237 can use materials suitable for insulating layer 218 and insulating layer 235. Insulating layer 237 electrically insulates the pixel electrodes from the common electrode. Furthermore, insulating layer 237 electrically insulates adjacent light-emitting elements.

[0498] An insulating layer 237 is provided at least in the display section 162. The insulating layer 237 can be provided not only in the display section 162, but also in the connection section 140 and the circuit section 164. Alternatively, the insulating layer 237 can extend to the end of the display device 50A.

[0499] The common electrode 115 is a continuous film shared by light-emitting elements 130R, 130G, and 130B. The common electrode 115, which is shared by multiple light-emitting elements, is connected to the conductive layer 123 disposed in the connection portion 140. The conductive layer 123 and the pixel electrodes 111R, 111G, and 111B are preferably conductive layers formed of the same material and using the same process.

[0500] In one aspect of the display device of the present invention, a conductive film that transmits visible light is used as the electrode on the light-extracting side of both the pixel electrode and the common electrode. Conversely, a conductive film that reflects visible light is preferably used as the electrode on the non-light-extracting side.

[0501] The electrode on the side that does not extract light can also be a conductive film that transmits visible light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can also be reflected by the reflective layer and extracted from the display device.

[0502] Metals, alloys, conductive compounds, and mixtures thereof can be appropriately used as materials for the pair of electrodes forming the light-emitting element. Specifically, examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys appropriately combined with them. Additionally, examples of such materials include indium tin oxide (also known as In-Sn oxide, ITO), In-Si-Sn oxide (also known as ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, examples of such materials include aluminum alloys (Al-Ni-La) and silver alloys (Al-Ni-La), as well as silver alloys (Al-Pd-Cu, APC), as well as silver alloys (Al-Ni-La). In addition, as materials, examples include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys of these elements in appropriate combinations, and graphene.

[0503] The light-emitting element preferably employs a microcavity resonator (microcavity) structure. Therefore, one of the pair of electrodes included in the light-emitting element preferably includes an electrode with visible light transmittance and reflectance (semi-transmittance-semi-reflectance electrode), and the other preferably includes an electrode with visible light reflectance (reflection electrode). When the light-emitting element has a microcavity structure, the light emitted from the light-emitting layer can resonate between the two electrodes, and the light emitted from the light-emitting element can be enhanced.

[0504] The transparent electrode has a light transmittance of 40% or more. For example, it is preferable to use an electrode with a visible light (light with a wavelength of 400 nm or more and less than 750 nm) transmittance of 40% or more as the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transmissive-semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1 × 10⁻⁶. -2 Below Ωcm.

[0505] EL layers 113R, EL layers 113G, and EL layers 113B are all configured as islands. Figure 21A In this process, the ends of adjacent EL layers 113R overlap with the ends of EL layer 113G, the ends of adjacent EL layers 113G overlap with the ends of EL layer 113B, and the ends of adjacent EL layers 113R overlap with the ends of EL layer 113B. When depositing island-shaped EL layers using a high-precision metal mask, such as... Figure 21AAs shown, the ends of adjacent EL layers sometimes overlap, but this is not a limitation. That is, adjacent EL layers can also be separated without overlapping. In addition, in a display device, there can be both portions where adjacent EL layers overlap and portions where adjacent EL layers are separated without overlapping.

[0506] EL layers 113R, EL layers 113G, and EL layers 113B all include at least a light-emitting layer. The light-emitting layer contains one or more light-emitting materials. Suitable light-emitting materials are those that emit light in colors such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red. Alternatively, materials that emit near-infrared light may also be used as light-emitting materials.

[0507] Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0508] In addition to the luminescent material (guest material), the luminescent layer may also contain one or more organic compounds (host material, auxiliary material, etc.). As one or more organic compounds, one or both of the following can be used: a material with high hole transport (hole transport material) and a material with high electron transport (electron transport material). Alternatively, as one or more organic compounds, bipolar materials (materials with both high electron and hole transport properties) or TADF materials can also be used.

[0509] For example, the luminescent layer preferably comprises a combination of a phosphorescent material, a hole transport material that readily forms exciton complexes, and an electron transport material. By employing such a structure, ExTET (Exciplex-Triplet Energy Transfer), which utilizes energy transfer from the exciton complex to the luminescent material (phosphorescent material), can be efficiently obtained. By selecting a combination of exciton complexes that emit light with wavelengths overlapping the absorption band on the lowest energy side of the luminescent material, energy transfer can be facilitated, resulting in efficient luminescence. By employing the above structure, high efficiency, low-voltage operation, and long lifetime of the luminescent element can be simultaneously achieved.

[0510] In addition to the light-emitting layer, the EL layer may also include one or more of the following: a layer containing a material with high hole injection capability (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking capability (electron blocking layer), a layer containing a material with high electron injection capability (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking capability (hole blocking layer). Furthermore, the EL layer may also include one or both of a bipolar material and a TADF material.

[0511] Light-emitting elements can use low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, and coating.

[0512] Light-emitting elements can be single-structured (including structures with only one light-emitting unit) or series-structured (including structures with multiple light-emitting units). Each light-emitting unit includes at least one light-emitting layer. A series structure has multiple light-emitting units connected in series via a charge-generating layer. The charge-generating layer functions to inject electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By employing a series structure, light-emitting elements capable of emitting light with high brightness can be realized. Furthermore, the series structure improves reliability because it reduces the current required to achieve the same brightness compared to a single structure. Additionally, the series structure can also be referred to as a stacked structure.

[0513] exist Figure 21A In the case of using a series-connected light-emitting element, it is preferable that the EL layer 113R includes a plurality of light-emitting units that emit red light, the EL layer 113G includes a plurality of light-emitting units that emit green light, and the EL layer 113B includes a plurality of light-emitting units that emit blue light.

[0514] A protective layer 131 is provided on light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded together by an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For example, a solid sealing structure or a hollow sealing structure can be used to seal the light-emitting elements. Figure 21A In this configuration, the space between substrate 152 and substrate 151 is filled with adhesive layer 142, thus employing a solid sealing structure. Alternatively, a hollow sealing structure can be used, where the space is filled with an inactive gas (such as nitrogen or argon). In this case, adhesive layer 142 can also be arranged in a manner that does not overlap with the light-emitting element. Furthermore, a resin different from that used for the frame-shaped adhesive layer 142 can be used to fill the space.

[0515] The protective layer 131 is provided at least in the display section 162, and preferably in a manner that covers the entire display section 162. The protective layer 131 is preferably provided in a manner that covers not only the display section 162 but also the connection section 140 and the circuit section 164. Furthermore, the protective layer 131 is preferably provided in a manner that extends to the end of the display device 50A. On the other hand, in order to enable electrical connection between the FPC 172 and the conductive layer 165, there is a portion in the connection section 197 where the protective layer 131 is not provided.

[0516] By providing a protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved.

[0517] The protective layer 131 can have a single-layer structure or a stacked structure of two or more layers. Furthermore, there are no limitations on the conductivity of the protective layer 131. At least one of insulating films, semiconductor films, and conductive films can be used as the protective layer 131.

[0518] When the protective layer 131 includes an inorganic film, it can suppress the deterioration of the light-emitting element, such as preventing the common electrode 115 from being oxidized and suppressing impurities (water, oxygen, etc.) from entering the light-emitting element, thereby improving the reliability of the display device.

[0519] The protective layer 131 preferably comprises one or more inorganic insulating layers. The protective layer 131 can be made of materials suitable for the insulating layer 110. In particular, the protective layer 131 preferably uses nitrides or oxynitrides, more preferably nitrides.

[0520] As the protective layer 131, an inorganic film comprising ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO may also be used. This inorganic film preferably has high resistance; specifically, it preferably has a higher resistance than the common electrode 115. The inorganic film may also contain nitrogen.

[0521] When the light emitted by the light-emitting element is extracted through the protective layer 131, the visible light transmittance of the protective layer 131 is preferably high. For example, ITO, IGZO and alumina are inorganic materials with high visible light transmittance, and are therefore preferred.

[0522] As a protective layer 131, for example, a stacked structure of an alumina film and a silicon nitride film on the alumina film, or a stacked structure of an alumina film and an IGZO film on the alumina film can be used. By using this stacked structure, impurities (water, oxygen, etc.) can be suppressed from entering the EL layer side.

[0523] Furthermore, the protective layer 131 may also include an organic film. For example, the protective layer 131 may include both an organic film and an inorganic film. Examples of organic films that can be used in the protective layer 131 include organic insulating films that can be used in the insulating layer 235.

[0524] A connection portion 197 is provided in a region of substrate 151 that does not overlap with substrate 152. In the connection portion 197, conductive layer 165 is connected to FPC 172 via conductive layer 166 and connection layer 242. Conductive layer 165 is shown as an example of a conductive layer obtained by processing the same conductive film as conductive layer 112b. Conductive layer 166 is shown as an example of a conductive layer obtained by processing the same conductive film as pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B. The connection portion between conductive layer 165 and conductive layer 166 can adopt the same structure as the connection portion between pixel electrode 111 and conductive layer 112b. Specifically, Figure 21A An example is shown where an opening is provided on the upper layer of conductive layer 165, and conductive layer 166 contacts the top surface of conductive layer 165 through this opening. Conductive layer 166 is exposed on the top surface of connection portion 197. Therefore, connection portion 197 can be connected to FPC 172 through connection layer 242.

[0525] The display device 50A is a top-emitting type. The light emitted by the light-emitting element is projected onto one side of the substrate 152. The substrate 152 is preferably made of a material with high visible light transmittance. The pixel electrodes 111R, 111G, and 111B contain materials that reflect visible light, and the counter electrode (common electrode 115) contains a material that allows visible light to pass through.

[0526] Preferably, a light-shielding layer 117 is provided on the surface of the substrate 152 on the substrate 151 side. The light-shielding layer 117 may be provided between adjacent light-emitting elements, in the connection portion 140, and in the circuit portion 164, etc.

[0527] Alternatively, a coloring layer such as a color filter can be provided on the surface of the substrate 151 side of the substrate 152 or on the protective layer 131. When a color filter is provided overlapping with the light-emitting element, the color purity of the light emitted from the pixel can be improved.

[0528] A coloring layer is a colored layer that selectively transmits light in a specific wavelength range while absorbing light in other wavelength ranges. For example, a red (R) filter that transmits light in the red wavelength range, a green (G) filter that transmits light in the green wavelength range, and a blue (B) filter that transmits light in the blue wavelength range can be used. Each coloring layer can be made of one or more of the following materials: metal, resin, pigment, and dye. The coloring layer is formed at the desired location using methods such as printing, inkjet printing, or etching using photolithography.

[0529] Furthermore, various optical components can be disposed on the outer side of the substrate 152 (the side opposite to the side of the substrate 151). Examples of optical components include polarizers, retardation plates, light diffusion layers (diffusion films, etc.), antireflective layers, and condensing films. Additionally, surface protective layers such as antistatic films to suppress dust adhesion, water-repellent films to prevent dirt accumulation, hard coatings to prevent damage during use, and impact absorption layers can also be disposed on the outer side of the substrate 152. For example, a glass layer or a silicon dioxide layer (SiO2) can be provided as a surface protective layer. x A protective layer (such as a diamond-like carbon layer) is preferred as it can prevent the surface from getting dirty or damaged. Alternatively, DLC (diamond-like carbon) and aluminum oxide (Al₂O₃) can also be used as surface protective layers. x Materials such as polyester or polycarbonate can be used. Furthermore, materials with high visible light transmittance are preferred as the surface protective layer. Additionally, materials with high hardness are preferred for the surface protective layer.

[0530] Substrates 151 and 152 can be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, etc. The substrate on the side from which light is extracted from the light-emitting element uses a material that allows the light to pass through. By using a flexible material for substrates 151 and 152, the flexibility of the display device can be improved, thereby enabling a flexible display. A polarizer can also be used as at least one of substrates 151 and 152.

[0531] The substrates 151 and 152 may be made of materials such as: polyester resins such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aromatic polyamide, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, and cellulose nanofibers. Alternatively, at least one of the substrates 151 and 152 may be made of glass with a flexible thickness.

[0532] When a circular polarizer is superimposed on a display device, it is preferable to use a substrate with high optical isotropy as the substrate included in the display device. A substrate with high optical isotropy has lower birefringence (or, in other words, less birefringence). Examples of thin films with high optical isotropy include cellulose triacetate (TAC) films, cyclic olefin polymer (COP) films, cyclic olefin copolymer (COC) films, and acrylic resin films.

[0533] As the adhesive layer 142, various curing adhesives can be used, such as UV-curing adhesives, reactive curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, materials with low moisture permeability, such as epoxy resins, are preferred. Two-component mixed resins can also be used. Adhesive sheets can also be used.

[0534] As the connecting layer 242, anisotropic conductive film (ACF) or anisotropic conductive paste (ACP) can be used.

[0535] <Display device 50B>

[0536] Figure 21B An example of a cross-section of the display section 162 of the display device 50B is shown. The main difference between the display device 50B and the display device 50A is that each color sub-pixel uses a light-emitting element including a common EL layer 113 and a coloring layer (color filter, etc.). Figure 21B The structure shown can be combined with Figure 21A The diagram shows the structure including the area of ​​FPC172, the circuit section 164, the stacked structure of the substrate 151 to the insulating layer 235 of the display section 162, the connection section 140, and the end section. Note that in the description of the display device described later, parts that are the same as those described previously are sometimes omitted.

[0537] Figure 21B The display device 50B shown includes a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a coloring layer 132R that transmits red light, a coloring layer 132G that transmits green light, and a coloring layer 132B that transmits blue light.

[0538] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130R is extracted as red light through the color layer 132R and sent to the outside of the display device 50B.

[0539] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130G is extracted as green light through the coloring layer 132G and emitted to the outside of the display device 50B.

[0540] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted by the light-emitting element 130B is extracted as blue light through the color layer 132B and emitted to the outside of the display device 50B.

[0541] Light-emitting elements 130R, 130G, and 130B all include an EL layer 113 and a common electrode 115. Compared to a structure where each color sub-pixel has a different EL layer, a structure where each color sub-pixel shares an EL layer 113 can reduce the number of manufacturing steps.

[0542] For example, Figure 21BThe light-emitting elements 130R, 130G, and 130B shown all emit white light. The white light emitted by each of the light-emitting elements 130R, 130G, and 130B is transmitted through the coloring layers 132R, 132G, and 132B, respectively, thereby obtaining light of the desired color.

[0543] White light-emitting elements preferably include two or more light-emitting layers. When white light emission is achieved using two light-emitting layers, the light-emitting layers can be selected such that the emission colors of the two light-emitting layers are complementary. For example, by making the emission colors of the first light-emitting layer and the second light-emitting layer complementary, a structure in which the entire light-emitting element emits white light can be obtained. Furthermore, when white light emission is achieved using three or more light-emitting layers, a structure in which the entire light-emitting element emits white light can be obtained by combining the emission colors of the three or more light-emitting layers.

[0544] The EL layer 113 preferably includes, for example, a light-emitting layer containing a light-emitting material that emits blue light and a light-emitting layer containing a light-emitting material that emits visible light with a wavelength longer than blue. The EL layer 113 preferably includes, for example, a light-emitting layer that emits yellow light and a light-emitting layer that emits blue light. Alternatively, the EL layer 113 preferably includes, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.

[0545] The light-emitting element emitting white light is preferably arranged in a series structure. Specifically, it can adopt: a two-stage series structure including a light-emitting unit emitting yellow light and a light-emitting unit emitting blue light; a two-stage series structure including a light-emitting unit emitting red and green light and a light-emitting unit emitting blue light; a three-stage series structure including a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light or green light and a light-emitting unit emitting blue light; or a three-stage series structure including a light-emitting unit emitting blue light, a light-emitting unit emitting yellow light, yellow-green light or green light and a light-emitting unit emitting red light and a light-emitting unit emitting blue light, etc. For example, regarding the number of layers and color order of the light-emitting units, examples include a two-level structure with B and Y stacked from the anode side, a two-level structure with B and light-emitting unit X stacked, a three-level structure with B, Y, and B stacked, and a three-level structure with B, X, and B stacked. Regarding the number of layers and color order of the light-emitting layers in light-emitting unit X, examples include a two-layer structure with R and Y stacked from the anode side, a two-layer structure with R and G stacked, a two-layer structure with G and R stacked, a three-layer structure with G, R, and G stacked, or a three-layer structure with R, G, and R stacked. Additionally, other layers can be placed between the two light-emitting layers.

[0546] In addition, by employing a microcavity structure, light-emitting elements that emit white light can sometimes enhance specific colors such as red, green, or blue to emit light.

[0547] Or, for example, Figure 21B The light-emitting elements 130R, 130G, and 130B shown all emit blue light. In this case, the EL layer 113 includes one or more light-emitting layers that emit blue light. Regarding the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, regarding the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or 130G can be converted into longer wavelength light and extracted as red or green light. Preferably, a color layer 132R is provided between the color conversion layer on the light-emitting element 130R and the substrate 152, and a color layer 132G is provided between the color conversion layer on the light-emitting element 130G and the substrate 152. Sometimes, a portion of the light emitted by the light-emitting element is transmitted without being converted by the color conversion layer. When light from the transmissive color conversion layer is extracted through the color layer, the color purity of the light presented by the sub-pixel can be improved by the color layer absorbing light other than the desired color light.

[0548] <Display Device 50C>

[0549] Figure 22 The main difference between the display device 50C and the display device 50B is that the display device 50C is a bottom-emitting type display device.

[0550] The light emitted by the light-emitting element is projected onto one side of the substrate 151. The substrate 151 is preferably made of a material with high visible light transmittance. On the other hand, there are no restrictions on the transmittance of the material used for the substrate 152.

[0551] Preferably, a light-shielding layer 117 is formed between the substrate 151 and the transistor. Figure 22 An example is shown below: A light-shielding layer 117 is disposed on a substrate 151, an insulating layer 153 is disposed on the light-shielding layer 117, and transistors 205D, 205R (not shown), 205G, and 205B are disposed on the insulating layer 153. Additionally, coloring layers 132R, 132G, and 132B are disposed on the insulating layer 218, and an insulating layer 235 is disposed on the coloring layers 132R, 132G, and 132B.

[0552] The light-emitting element 130R, which overlaps with the color layer 132R, includes a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0553] The light-emitting element 130G, which overlaps with the color layer 132G, includes a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0554] The light-emitting element 130B, which overlaps with the color layer 132B, includes a pixel electrode 111B, an EL layer 113, and a common electrode 115.

[0555] Pixel electrodes 111R, 111G, and 111B each use materials with high visible light transmittance. The common electrode 115 preferably uses a material that reflects visible light. Because low resistivity metals or the like can be used for the common electrode 115 in a bottom-emitting display device, voltage drops caused by the resistance of the common electrode 115 can be suppressed, thereby achieving high display quality.

[0556] One aspect of the transistor of the present invention can be miniaturized to reduce its footprint, thus enabling an increase in pixel aperture ratio or a reduction in pixel size in a bottom-emitting display device.

[0557] <Display Device 50D>

[0558] Figure 23A The main difference between the display device 50D shown and the display device 50A is that the display device 50D includes a light-receiving element 130S.

[0559] The display device 50D includes a light-emitting element and a light-receiving element in each pixel. Preferably, in the display device 50D, an organic EL element is used as the light-emitting element and an organic photodiode is used as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, the organic photodiode can be mounted in a display device using an organic EL element.

[0560] In the display device 50D, where each pixel includes a light-emitting element and a light-receiving element, the pixel has a light-receiving function, so the display device can detect the contact or proximity of an object while displaying an image. Therefore, the display unit 162 has one or both of the following functions: image display and sensing. For example, instead of displaying an image using all the sub-pixels included in the display device 50D, a portion of the sub-pixels can be used as a light source to emit light, another portion of the sub-pixels can be used for light detection, and the remaining sub-pixels can be used to display the image.

[0561] Therefore, since there is no need to separately provide a light-receiving part and a light source with the display device 50D, the number of components in the electronic device can be reduced. For example, there is no need to separately install biometric devices or electrostatic capacitive touch panels for scrolling, etc., in the electronic device. Therefore, by using the display device 50D, an electronic device with reduced manufacturing costs can be provided.

[0562] When a light-receiving element is used as an image sensor, the display device 50D can use the light-receiving element to capture images. For example, an image sensor can be used to capture images for personal identification using fingerprints, palm prints, irises, vein shapes (including vein shapes and artery shapes), or faces.

[0563] The light-receiving element can be used in touch sensors (also known as direct touch sensors) or non-contact sensors (also known as hover sensors, hover touch sensors, or non-touch sensors). Touch sensors can detect objects (fingers, hands, or pens, etc.) when they are in direct contact with the display device. Non-contact sensors, on the other hand, can detect objects even when they are not in contact with the display device.

[0564] The light-emitting element 130S includes a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

[0565] The pixel electrode 111S is connected to the conductive layer 112b of the transistor 205S in the openings provided in the insulating layer 106, the insulating layer 218 and the insulating layer 235.

[0566] The end of the pixel electrode 111S is covered by an insulating layer 237.

[0567] The common electrode 115 is a continuous film shared by the light-receiving element 130S, the light-emitting element 130R (not shown), the light-emitting element 130G, and the light-emitting element 130B. The common electrode 115, which is shared by the light-emitting element and the light-receiving element, is connected to the conductive layer 123 disposed in the connecting portion 140.

[0568] The functional layer 113S includes at least an active layer (also called a photoelectric conversion layer). The active layer contains a semiconductor. Examples of such semiconductors include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment, an example of using an organic semiconductor as the semiconductor contained in the active layer is shown. Because an organic semiconductor can be used, the light-emitting layer and the active layer can be formed in the same way (e.g., vacuum evaporation) and can share the same manufacturing equipment, which is preferred.

[0569] The functional layer 113S may also include a layer containing a material with high hole transport, a material with high electron transport, or a bipolar material as a layer other than the active layer. Furthermore, it is not limited to this; it may also include a layer containing a material with high hole injection, a hole blocking material, a material with high electron injection, or an electron blocking material. For example, the materials described above that can be used in light-emitting elements can be used as the functional layer 113S.

[0570] The light-receiving element can use low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-receiving element can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet printing, coating, etc.

[0571] Figure 23B and Figure 23C The display device 50D shown includes a layer 353 with light-receiving elements, a circuit layer 355, and a layer 357 with light-emitting elements between substrates 151 and 152.

[0572] Layer 353 includes, for example, a light-receiving element 130S. Layer 357 includes, for example, light-emitting elements 130R, 130G, and 130B.

[0573] Circuit layer 355 includes circuitry for driving the light-receiving element and circuitry for driving the light-emitting element. Circuit layer 355 may include, for example, transistors 205R, 205G, and 205B. In addition, one or more of switches, capacitors, resistors, wiring, and terminals may be disposed in circuit layer 355.

[0574] Figure 23B This is an example of using the light-receiving element 130S as a touch sensor. For example... Figure 23B As shown, when a finger 352 touches the display device 50D and reflects light emitted by the light-emitting element in layer 357, the light-receiving element in layer 353 detects the reflected light. Thus, it can be detected that the finger 352 is touching the display device 50D.

[0575] Figure 23C This is an example of using the light-receiving element 130S as a non-contact sensor. For example... Figure 23C As shown, when a finger 352 approaches (i.e. does not touch) the display device 50D and reflects light emitted by the light-emitting element in layer 357, the light-receiving element in layer 353 detects the reflected light.

[0576] <Display Device 50E>

[0577] Figure 24A The display device 50E shown is an example of a display device employing an MML structure. That is, the display device 50E includes light-emitting elements manufactured without high-precision metal masks.

[0578] In display devices employing the MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by depositing light-emitting layers across the entire surface and then processing them using photolithography. Therefore, it is possible to achieve high-definition or high-aperture-ratio display devices that were previously difficult to achieve. Furthermore, since light-emitting layers can be formed separately for each color, extremely vivid, high-contrast, and high-quality display devices can be realized. For example, in the case of using three types of light-emitting elements—one emitting blue light, one emitting green light, and one emitting red light—to construct a display device, three island-shaped light-emitting layers can be formed by repeatedly depositing light-emitting layers three times and processing them using photolithography.

[0579] Because MML (Metal-Layered Lithography) devices can be manufactured without metal masks, the resolution limitations imposed by the alignment accuracy of metal masks can be exceeded. Furthermore, manufacturing devices without metal masks eliminates the need for equipment and cleaning processes associated with metal mask production. Additionally, photolithography can utilize the same or shared equipment used in transistor manufacturing, eliminating the need for specialized equipment for MML devices. Thus, MML structures reduce manufacturing costs, making them suitable for mass production.

[0580] In display devices with MML structures, it is not necessary to use special pixel arrangements such as Pentile arrangement to improve sharpness in a pseudo-method. Thus, a display device can be realized in which a so-called stripe arrangement in which each sub-pixel of R, G, and B is arranged in one direction and has high sharpness (e.g., 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more).

[0581] By setting a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element.

[0582] By employing a deposition process using a range mask and a processing process using a resist mask, light-emitting elements can be manufactured with a simpler process.

[0583] Note that the stacked structure of substrate 151 to insulating layer 235 and the stacked structure of protective layer 131 to substrate 152 are the same as those of display device 50A, so the description is omitted.

[0584] exist Figure 24A In the middle, light-emitting elements 130R, 130G and 130B are provided on the insulating layer 235.

[0585] The light-emitting element 130R includes a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. Figure 24A The light-emitting element 130R shown emits red light (R). Layer 133R includes a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and common layer 114 can be collectively referred to as the EL layer. In addition, one or both of conductive layers 124R and conductive layers 126R can be referred to as pixel electrodes.

[0586] The light-emitting element 130G includes a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. Figure 24A The light-emitting element 130G shown emits green light (G). Layer 133G includes a light-emitting layer that emits green light. In the light-emitting element 130G, layer 133G and common layer 114 can be collectively referred to as the EL layer. In addition, one or both of conductive layer 124G and conductive layer 126G can be referred to as pixel electrode.

[0587] The light-emitting element 130B includes a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. Figure 24A The light-emitting element 130B shown emits blue light (B). Layer 133B includes a light-emitting layer that emits blue light. In the light-emitting element 130B, layer 133B and common layer 114 can be collectively referred to as the EL layer. Additionally, one or both of conductive layers 124B and 126B can be referred to as pixel electrodes.

[0588] In this specification, the island-shaped layers disposed for each light-emitting element in the EL layer included in the light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and the layer shared by multiple light-emitting elements is referred to as common layer 114. Additionally, in this specification, layers 133R, 133G, and 133B, which do not include common layer 114, are sometimes referred to as island-shaped EL layers or EL layers formed in an island shape. Furthermore, light-emitting elements manufactured without a metal mask may not include a common layer, and all layers constituting the EL layer may be formed in an island shape.

[0589] Layers 133R, 133G, and 133B are separated from each other. By providing island-shaped EL layers in each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. Therefore, unintentional light emission caused by crosstalk can be prevented, thereby enabling a display device with very high contrast.

[0590] Note that in Figure 24A In this design, layers 133R, 133G, and 133B all have the same thickness, but are not limited to this. Layers 133R, 133G, and 133B can also have different thicknesses.

[0591] The openings in the insulating layers 106, 218, and 235 of the conductive layer 124R are connected to the conductive layer 112b of the transistor 205R. Similarly, the conductive layer 124G is connected to the conductive layer 112b of the transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of the transistor 205B.

[0592] Conductive layers 124R, 124G, and 124B are all formed to cover the openings provided in the insulating layer 235. The recesses of conductive layers 124R, 124G, and 124B are respectively filled with layer 128.

[0593] Layer 128 has the function of planarizing the recesses of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B, respectively connected to conductive layers 124R, 124G, and 124B, are provided on conductive layers 124R, 124G, and 124B. Therefore, the area overlapping the recesses of conductive layers 124R, 124G, and 124B can also be used as a light-emitting area, thereby improving the pixel aperture ratio. Conductive layers 124R and 126R are preferably conductive layers used as reflective electrodes.

[0594] Layer 128 can also be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be suitably used for layer 128. In particular, layer 128 is preferably formed using an insulating material, and especially preferably using an organic insulating material. For example, an organic insulating material that can be used in the aforementioned insulating layer 237 can be used as layer 128.

[0595] Although Figure 24A An example is shown where the top surface of layer 128 has a flat portion, but there are no particular limitations on the shape of layer 128. The top surface of layer 128 may have at least one of a convex surface, a concave surface, and a plane.

[0596] The height of the top surface of layer 128 can be the same as or approximately the same as the height of the top surface of conductive layer 124R, or they can be different. For example, the height of the top surface of layer 128 can be lower or higher than the height of the top surface of conductive layer 124R.

[0597] The end of conductive layer 126R can also be aligned with the end of conductive layer 124R, and can also cover the side surface of the end of conductive layer 124R. Each end of conductive layer 124R and conductive layer 126R preferably has a tapered shape. Specifically, each end of conductive layer 124R and conductive layer 126R preferably has a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, layer 133R disposed along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, good coverage of the EL layer disposed along the side surface of the pixel electrode can be achieved.

[0598] The conductive layers 124G, 126G, 124B, and 126B are the same as the conductive layers 124R and 126R, so detailed descriptions are omitted.

[0599] The top and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the top and side surfaces of conductive layer 126G are covered by layer 133G, and the top and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area where conductive layers 126R, 126G, and 126B are disposed can be used as the light-emitting area of ​​light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B, respectively, thereby improving the pixel aperture ratio.

[0600] A portion of the top surface and side surface of each of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is disposed on layers 133R, 133G, 133B, insulating layer 125, and insulating layer 127, and a common electrode 115 is disposed on the common layer 114. Both the common layer 114 and the common electrode 115 are continuous films shared by multiple light-emitting elements.

[0601] exist Figure 24A In the middle, there is no space between conductive layer 126R and layer 133R. Figure 21A The insulating layer 237 is shown. In other words, the display device 50E does not have an insulating layer (also called a separator, dam, spacer, etc.) that contacts the pixel electrodes and covers the top surface of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be very small. Thus, a high-definition or high-resolution display device can be achieved. Furthermore, a mask for forming this insulating layer is not required, thereby reducing the manufacturing cost of the display device.

[0602] Layers 133R, 133G, and 133B all include a light-emitting layer. Preferably, layers 133R, 133G, and 133B include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer). Alternatively, layers 133R, 133G, and 133B preferably include a light-emitting layer and a carrier blocking layer (hole blocking layer or electron blocking layer). Alternatively, layers 133R, 133G, and 133B preferably all include a light-emitting layer, a carrier blocking layer, and a carrier transport layer on the carrier blocking layer. More preferably, the carrier transport layer is disposed on the light-emitting layer. More preferably, the carrier blocking layer is disposed on the light-emitting layer. Since the surfaces of layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier blocking layer on the light-emitting layer, the exposure of the light-emitting layer to the outermost surface can be suppressed, thereby reducing damage to the light-emitting layer. This improves the reliability of the light-emitting element.

[0603] The common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may be a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. Light-emitting elements 130R, 130G, and 130B share the common layer 114.

[0604] Each side of layer 133R, layer 133G, and layer 133B is covered by insulating layer 125. Insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B through insulating layer 125.

[0605] By covering the sides (and a portion of the top surface) of at least one of the insulating layers 125 and 127—layers 133R, 133G, and 133B—contact between the common layer 114 (or the common electrode 115) and the side surfaces of the pixel electrode, layers 133R, 133G, and 133B can be suppressed, thereby suppressing short circuits in the light-emitting element. This improves the reliability of the light-emitting element.

[0606] The insulating layer 125 preferably has areas that contact each side of layers 133R, 133G, and 133B. By adopting a structure in which the insulating layer 125 contacts layers 133R, 133G, and 133B, film peeling of layers 133R, 133G, and 133B can be prevented, thereby improving the reliability of the light-emitting element.

[0607] The insulating layer 127 is disposed on the insulating layer 125 in such a way that it fills the recess of the insulating layer 125. The insulating layer 127 preferably covers at least a portion of the side surface of the insulating layer 125.

[0608] By providing insulating layers 125 and 127, the spaces between adjacent island layers can be filled, thereby reducing the unevenness of the formed surfaces of layers (such as carrier injection layers, common electrodes, etc.) on the island layers and further achieving planarization. Therefore, the coverage of carrier injection layers, common electrodes, etc., can be improved.

[0609] A common layer 114 and a common electrode 115 are disposed on layers 133R, 133G, 133B, insulating layer 125, and insulating layer 127. Before the insulating layers 125 and 127 are disposed, a step is formed between the region where the pixel electrode and island EL layer are disposed and the region where the pixel electrode and island EL layer are not disposed (the region between light-emitting elements). A display device according to one aspect of the present invention can flatten this step by including insulating layers 125 and 127, thereby improving the coverage of the common layer 114 and the common electrode 115. Therefore, poor connection caused by the disconnection of the common electrode 115 can be suppressed. Alternatively, the increase in resistance caused by local thinning of the common electrode 115 due to the step can be suppressed.

[0610] The top surface of the insulating layer 127 preferably has a shape with higher flatness. The top surface of the insulating layer 127 may also have at least one of a planar surface, a convex surface, and a concave surface. For example, the top surface of the insulating layer 127 preferably has a convex surface shape with a large radius of curvature.

[0611] The insulating layer 125 can have a single-layer structure or a stacked structure of two or more layers. The insulating layer 125 preferably includes one or more inorganic insulating layers. The insulating layer 125 can use materials suitable for the insulating layer 110. In particular, a high selectivity ratio of alumina to the EL layer during etching is preferred, as it protects the EL layer during the formation of the insulating layer 127. Specifically, by using an inorganic insulating film such as an alumina film, hafnium oxide film, or silicon oxide film formed using the ALD method for the insulating layer 125, an insulating layer 125 with fewer pinholes and good protection of the EL layer can be formed. Alternatively, the insulating layer 125 can also employ a stacked structure of a film formed using the ALD method and a film formed using sputtering. For example, the insulating layer 125 can employ a stacked structure of an alumina film formed using the ALD method and a silicon nitride film formed using sputtering.

[0612] The insulating layer 125 is preferably used as a barrier insulating layer against at least one of water and oxygen. The insulating layer 125 preferably has the function of inhibiting the diffusion of at least one of water and oxygen. In addition, the insulating layer 125 preferably has the function of trapping or fixing (getting-in) at least one of water and oxygen.

[0613] When the insulating layer 125 is used as a barrier insulating layer, it can have a structure that inhibits the entry of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. By adopting this structure, a highly reliable light-emitting element can be provided, and a highly reliable display device can be provided.

[0614] The impurity concentration in the insulating layer 125 is preferably low. This prevents impurities from mixing into the EL layer from the insulating layer 125 and causing EL layer degradation. Furthermore, by reducing the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is preferable that one of the hydrogen concentration and carbon concentration in the insulating layer 125 is sufficiently low, and more preferably that both the hydrogen concentration and carbon concentration are sufficiently low.

[0615] The insulating layer 127 disposed on the insulating layer 125 has the function of flattening the unevenness of the insulating layer 125 formed between adjacent light-emitting elements where the height difference is large. In other words, by including the insulating layer 127, the flatness of the surface on which the common electrode 115 is formed is improved.

[0616] An insulating layer containing organic materials can be used as insulating layer 127. As the organic material, a photosensitive resin is preferred, for example, a photosensitive resin composition including acrylic resin is preferred. Note that in this specification, acrylic resin does not refer only to polymethacrylate or methacrylic resin, but sometimes also to acrylic polymers in a broader sense.

[0617] The insulating layer 127 can also be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins. Alternatively, the insulating layer 127 can also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. Furthermore, a photoresist can be used as the photosensitive resin. Both positive and negative photosensitive materials can be used as the photosensitive resin.

[0618] The insulating layer 127 can also be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element through the insulating layer 127, light leakage (stray light) from the light-emitting element to adjacent light-emitting elements can be suppressed. Therefore, the display quality of the display device can be improved. In addition, the display quality can be improved even without using a polarizer in the display device, so it is possible to achieve a lighter and thinner display device.

[0619] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used in color filters (color filter materials). In particular, resin materials made by mixing or layering two or more colors of color filter materials can improve the effect of blocking visible light, and are therefore preferred. Especially, by mixing three or more colors of color filter materials, a black or near-black resin layer can be achieved.

[0620] <Display Device 50F>

[0621] Figure 24B An example of a cross-section of the display section 162 of the display device 50F is shown. The main difference between the display device 50F and the display device 50E is that each color sub-pixel has a color layer (color filter, etc.). Figure 24B The structure shown can be combined with Figure 24A The structure shown includes the area of ​​FPC172, the circuit section 164, the stacked structure of the substrate 151 to the insulating layer 235 of the display section 162, the connection section 140, and the end section.

[0622] Figure 24B The display device 50F shown includes light-emitting elements 130R, 130G, and 130B, a coloring layer 132R that transmits red light, a coloring layer 132G that transmits green light, and a coloring layer 132B that transmits blue light.

[0623] The light emitted by the light-emitting element 130R is extracted as red light through the coloring layer 132R and emitted to the outside of the display device 50F. Similarly, the light emitted by the light-emitting element 130G is extracted as green light through the coloring layer 132G and emitted to the outside of the display device 50F. The light emitted by the light-emitting element 130B is extracted as blue light through the coloring layer 132B and emitted to the outside of the display device 50F.

[0624] Light-emitting elements 130R, 130G, and 130B each include a layer 133. These three layers 133 are formed using the same process and the same materials. Furthermore, these three layers 133 are separated from each other. By providing island-shaped EL layers in each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. Therefore, unintended light emission caused by crosstalk can be prevented, thereby enabling a display device with very high contrast.

[0625] For example, Figure 24BThe light-emitting elements 130R, 130G, and 130B shown all emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B is transmitted through the coloring layers 132R, 132G, and 132B, thereby obtaining light of the desired color.

[0626] Or, for example, Figure 24B The light-emitting elements 130R, 130G, and 130B shown all emit blue light. In this case, layer 133 includes one or more light-emitting layers that emit blue light. Regarding the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, regarding the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or 130G can be converted into longer wavelength light and extracted as red or green light. Preferably, a color layer 132R is provided between the color conversion layer on the light-emitting element 130R and the substrate 152, and a color layer 132G is provided between the color conversion layer on the light-emitting element 130G and the substrate 152. When light transmitted through the color conversion layer is extracted via the color layer, the color purity of the light emitted by the sub-pixel can be improved by absorbing light other than the desired color light through the color layer.

[0627] <Display device 50G>

[0628] Figure 25 The main difference between the display device 50G and the display device 50F is that the display device 50G is a bottom-emitting type display device.

[0629] The light emitted by the light-emitting element is projected onto one side of the substrate 151. The substrate 151 is preferably made of a material with high visible light transmittance. On the other hand, there are no restrictions on the transmittance of the material used for the substrate 152.

[0630] Preferably, a light-shielding layer 117 is formed between the substrate 151 and the transistor. Figure 25 An example is shown below: A light-shielding layer 117 is disposed on a substrate 151, an insulating layer 153 is disposed on the light-shielding layer 117, and transistors 205D, 205R (not shown), 205G, and 205B are disposed on the insulating layer 153. Additionally, coloring layers 132R, 132G, and 132B are disposed on the insulating layer 218, and an insulating layer 235 is disposed on the coloring layers 132R, 132G, and 132B.

[0631] The light-emitting element 130R, which overlaps with the coloring layer 132R, includes a conductive layer 124R, a conductive layer 126R, a layer 133, a common layer 114, and a common electrode 115.

[0632] The light-emitting element 130G, which overlaps with the coloring layer 132G, includes a conductive layer 124G, a conductive layer 126G, a layer 133, a common layer 114, and a common electrode 115.

[0633] The light-emitting element 130B, which overlaps with the coloring layer 132B, includes a conductive layer 124B, a conductive layer 126B, a layer 133, a common layer 114, and a common electrode 115.

[0634] Conductive layers 124R, 124G, 124B, 126R, 126G, and 126B each utilize materials with high visible light transmittance. The common electrode 115 preferably uses a material that reflects visible light. Because low-resistivity metals or similar materials can be used for the common electrode 115 in a bottom-emitting display device, voltage drops caused by the resistance of the common electrode 115 can be suppressed, thereby achieving high display quality.

[0635] One aspect of the transistor of the present invention can be miniaturized to reduce its footprint, thus enabling an increase in pixel aperture ratio or a reduction in pixel size in a bottom-emitting display device.

[0636] <Display device 50H>

[0637] Figure 26A The display device 50H shown is a VA mode liquid crystal display device.

[0638] The substrate 151 and substrate 152 are bonded together using an adhesive layer 144. Furthermore, liquid crystal 262 is sealed within the area surrounded by the substrate 151, substrate 152, and adhesive layer 144. Polarizer 260a is located on the outer surface of substrate 152, and polarizer 260b is located on the outer surface of substrate 151. Additionally, although not shown, a backlight source can be provided outside either polarizer 260a or polarizer 260b.

[0639] The substrate 151 is provided with transistors 205D, 205R, and 205G, a connection portion 197, spacers 224, etc. Transistor 205D is a transistor disposed in the circuit portion 164, while transistors 205R and 205G are transistors disposed in the display portion 162. The conductive layer 112b included in each of transistors 205R and 205G is used as a pixel electrode of the liquid crystal element 60.

[0640] The substrate 152 is provided with a coloring layer 132R, a coloring layer 132G, a light-shielding layer 117, an insulating layer 225, and a conductive layer 263. The conductive layer 263 is used as the common electrode of the liquid crystal element 60.

[0641] Transistors 205D, 205R, and 205G all include a conductive layer 112a, a semiconductor layer 108, an insulating layer 106, a conductive layer 104, and a conductive layer 112b. Conductive layer 112a is used as one of the source and drain electrodes, and conductive layer 112b is used as the other. Conductive layer 104 is used as the gate electrode. A portion of the insulating layer 106 is used as the gate insulating layer.

[0642] As described above, in this embodiment, an example is shown where transistors 205D, 205R, and 205G all use OS transistors. Transistors 205D, 205R, and 205G can use transistors according to one aspect of the present invention. That is, in the display device 50H, both the display unit 162 and the circuit unit 164 include transistors according to one aspect of the present invention. By using transistors according to one aspect of the present invention in the display unit 162, pixel size can be reduced, thereby achieving high definition. Furthermore, by using transistors according to one aspect of the present invention in the circuit unit 164, the area occupied by the circuit unit 164 can be reduced, thereby achieving narrow bezels. For details regarding transistors according to one aspect of the present invention, please refer to the description of the above embodiment.

[0643] Transistors 205D, 205R, and 205G are covered by insulating layer 218. Insulating layer 218 serves as a protective layer for transistors 205D, 205R, and 205G.

[0644] The sub-pixels included in the display unit 162 include transistors, liquid crystal elements 60, and coloring layers. For example, a sub-pixel that emits red light includes transistor 205R, liquid crystal elements 60, and a coloring layer 132R that transmits red light. Similarly, a sub-pixel that emits green light includes transistor 205G, liquid crystal elements 60, and a coloring layer 132G that transmits green light. Although not shown, a sub-pixel that emits blue light also similarly includes transistors, liquid crystal elements 60, and a coloring layer that transmits blue light.

[0645] The liquid crystal element 60 includes a conductive layer 112b, a conductive layer 263, and liquid crystal 262 sandwiched between them.

[0646] A conductive layer 264 is disposed on the substrate 151 on the same plane as the conductive layer 112a. The conductive layer 264 has a portion overlapping the conductive layer 112b, separated by insulating layers 110 (insulating layers 110a, 110b, and 110c). A storage capacitor is formed by the conductive layer 112b, the conductive layer 264, and the insulating layer 110 between them. Note that it is sufficient to have one or more insulating layers between the conductive layer 112b and the conductive layer 264; alternatively, one or both of the insulating layers 110 can be removed by etching.

[0647] An insulating layer 225 is provided on one side of the substrate 152 to cover the coloring layer 132R, the coloring layer 132G, and the light-shielding layer 117. The insulating layer 225 can also be used as a planarization layer. By using the insulating layer 225, the surface of the conductive layer 263 can be made approximately flat, so that the alignment state of the liquid crystal 262 can be made consistent.

[0648] Furthermore, in the conductive layer 263 and insulating layer 218, an alignment film for controlling the alignment of the liquid crystal 262 may also be provided on the surface in contact with the liquid crystal 262 (see reference). Figure 28A and Figure 28B Orientation film 265 in the middle.

[0649] Conductive layers 112b and 263 transmit visible light. In other words, a transmissive liquid crystal device can be realized. For example, when a backlight is positioned on one side of substrate 152, light from the backlight, polarized by polarizer 260a, passes through substrate 152, conductive layer 263, liquid crystal 262, conductive layer 112b, and substrate 151 to reach polarizer 260b. At this time, the orientation of liquid crystal 262 can be controlled by the voltage applied between conductive layer 112b and conductive layer 263, thereby controlling the optical modulation of the light. That is, the intensity of the light emitted through polarizer 260b can be controlled. Furthermore, since light outside the specified wavelength region of the incident light is absorbed by the coloring layer, the extracted light appears, for example, red.

[0650] Here, either a linear polarizer or a circular polarizer can be used as polarizer 260b. For example, a polarizer formed by stacking a linear polarizer and a quarter-wave phase difference plate can be used. By using a circular polarizer as polarizer 260b, external light reflection can be suppressed.

[0651] Furthermore, when a circular polarizer is used as polarizer 260b, a circular polarizer can also be used as polarizer 260a, or a general linear polarizer can be used. By adjusting the cell gap, orientation, and driving voltage of the liquid crystal element 60 according to the type of polarizer used for polarizer 260a and polarizer 260b, the desired contrast ratio can be achieved.

[0652] The conductive layer 263 is connected to the conductive layer 166b disposed on one side of the substrate 151 via the connector 223 in the connection portion 140. The conductive layer 166b is connected to the conductive layer 165b through an opening provided in the insulating layer 110. Thus, a potential or signal can be supplied to the conductive layer 263 from an FPC or IC disposed on one side of the substrate 151. Figure 26A The structure shown illustrates the following examples: conductive layer 165b is formed using the same material and the same process as conductive layer 112a; conductive layer 166b is formed using the same material and the same process as conductive layer 104.

[0653] For example, conductive particles can be used for connector 223. These conductive particles can be made of resin or silica, etc., with a surface coated with a metallic material. Nickel or gold is preferred as the metallic material because it reduces contact resistance. Furthermore, particles with two or more metallic materials layered together, such as nickel coated with gold, are preferred. Additionally, connector 223 is preferably made of a material capable of elastic or plastic deformation. In this case, the conductive particles sometimes exhibit… Figure 26A The connector 223 is flattened longitudinally as shown. This shape increases the contact area between the connector 223 and the conductive layer to which it is connected, thereby reducing contact resistance and suppressing problems such as poor contact. The connector 223 is preferably arranged to be covered by the adhesive layer 144. For example, it is preferable to disperse the connector 223 within the adhesive layer 144 before curing.

[0654] A connection porti...

Claims

1. A semiconductor device, comprising: transistor; as well as First insulating layer, The transistor includes a first conductive layer, a second conductive layer, a semiconductor layer, and a second insulating layer. The first insulating layer is located on the first conductive layer. The second conductive layer is located on the first insulating layer. The first insulating layer has a first side surface in the region overlapping with the second conductive layer. The semiconductor layer is in contact with the top and side surfaces of the second conductive layer, a portion of the first side surface, and the top surface of the first conductive layer. The second insulating layer is in contact with the top and side surfaces of the first conductive layer, the top and side surfaces of the semiconductor layer, another portion of the first side surface, and the top and side surfaces of the second conductive layer. The second insulating layer contains the first element. The first element is boron, phosphorus, or magnesium. Furthermore, the second insulating layer has a concentration of the first element of 1.0 × 10⁻⁶. 19 atoms / cm 3 The above areas.

2. The semiconductor device according to claim 1, The first element is boron.

3. The semiconductor device according to claim 1 or 2, The semiconductor layer has a first region, a second region, and a third region. The first region is in contact with the first conductive layer. The second region is in contact with the first side. The third region is in contact with the second conductive layer. Both the first region and the third region contain the second element. The second element is one or more of boron, phosphorus, aluminum, magnesium, and silicon. Furthermore, the concentration of the second element in both the first region and the third region is higher than the concentration of the second element in the second region.

4. The semiconductor device according to claim 3, Both the first region and the third region have a concentration of the second element of 1×10⁻⁶. 19 atoms / cm 3 Above and 1×10 23 atoms / cm 3 The following areas.

5. The semiconductor device according to any one of claims 1 to 4, The semiconductor layer is an indium-containing oxide semiconductor layer. The first insulating layer includes a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer. Both the third insulating layer and the fifth insulating layer contain silicon and nitrogen. Furthermore, the fourth insulating layer comprises silicon and oxygen.

6. A method for manufacturing a semiconductor device, comprising the following steps: Form the first conductive layer; A first insulating film and a first conductive film are sequentially deposited on the first conductive layer; The first conductive film and the first insulating film are processed in such a way that they have regions overlapping with the first conductive layer, so as to form the second conductive layer and the first insulating layer respectively. A semiconductor layer is formed in such a manner that it contacts the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. A second insulating layer is formed in such a way that it contacts the top and side surfaces of the semiconductor layer, the top surface of the first conductive layer, and the top surface of the second conductive layer; as well as The first element is supplied to the second insulating layer.

7. The method for manufacturing a semiconductor device according to claim 6, The first element is boron, phosphorus, magnesium, aluminum, or silicon.

8. The method for manufacturing a semiconductor device according to claim 6, The first element is boron. The boron is supplied using an ion doping method. Furthermore, in the ion doping method, the accelerating voltage is above 1 keV and below 10 keV, and the dose is 1.0 × 10⁻⁶. 15 ions / cm 2 Above and 1.0×10 16 ions / cm 2 the following.

9. A method for manufacturing a semiconductor device according to any one of claims 6 to 8, The second element is supplied to the semiconductor layer through the second insulating layer after the first element is supplied.

10. The method for manufacturing a semiconductor device according to claim 9, The second element is one or more of boron, phosphorus, aluminum, magnesium, and silicon.

11. The method for manufacturing a semiconductor device according to claim 10, The second element is supplied using ion doping.

12. The method for manufacturing a semiconductor device according to any one of claims 6 to 8, After the second insulating layer is formed, a third element is supplied to the semiconductor layer through the second insulating layer, and then the first element is supplied to the second insulating layer.

13. The method for manufacturing a semiconductor device according to claim 12, The third element is one or more of boron, phosphorus, aluminum, magnesium, and silicon.

14. The method for manufacturing a semiconductor device according to claim 13, The third element is supplied using ion doping.

Images