Systems and methods for sweeping magnetic flux from superconducting integrated circuits

Abstract

A system and method for eliminating flux trapping in superconducting integrated circuits. An array of control current lines is provided that are tightly thermally and magnetically coupled to a superconducting integrated circuit. These control lines are configured to produce both heat and magnetic fields, where the amplitude and sequence of the control currents are designed to sweep the magnetic flux from the superconducting circuit at cryogenic operating temperatures. Verification can be obtained using SQUID magnetic sensors located in the vicinity of the circuit. Similar methods can be applied to all superconducting integrated circuits that are sensitive to weak magnetic fields, including classical single flux quantum circuits, sensor arrays, and quantum computing circuits composed of superconducting qubits. The system can be scaled to superconducting circuits with up to millions of superconducting devices. The control currents can be configured to operate under automatic feedback control.

Description

[0001] Cross-references to related applications

[0002] This application is a non-provisional application of U.S. Provisional Patent Application No. 63 / 609,838, filed on December 13, 2023, and claims priority to that U.S. Provisional Patent Application under 35 USC §119(e), the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This invention relates to the field of superconducting integrated circuits, and more specifically to the removal of trapped magnetic flux from superconducting integrated circuits.

[0004] References merged

[0005] No reference or designation in this document or in any section of this application shall be construed as an admission that such references are prior art. The disclosures of each publication and patent listed or cited herein are hereby incorporated in their entirety into this application and shall be considered as forming part of this application in their entirety. Such references are provided to disclose the techniques that may be necessary to practice the invention, to provide a written description in the language of the claims, to clarify the applicant’s mastery of the invention with respect to various sets, combinations, permutations, and sub-combinations of the respective disclosures or portions thereof (within a particular reference or across multiple references) and combinations, permutations, and sub-combinations of the various disclosures provided herein, to demonstrate the non-abstract nature of the technical aspects of the invention protected by the claims, and for any other purpose. Unless expressly stated otherwise, the scope of this invention is inclusive, and therefore the disclosures of the techniques or teachings within these incorporated materials are intended to be covered as options or supplements to other disclosures of the invention. Similarly, combinations of incorporated teachings consistent with this disclosure are also covered. References are intended to be part of the disclosure of the invention, and not merely supplementary background information. While cited references may be prior art, combinations thereof, and combinations thereof with the materials disclosed herein, are not acknowledged as prior art.

[0006] Incorporation by reference does not extend to teachings that are inconsistent with the inventive content explicitly described as essential herein. Incorporated references are rebuttalable evidence that a person skilled in the art would correctly interpret the terms, phrases, and concepts used herein. No incorporated reference is acknowledged to be of a similar technical nature to the problem presented to the inventor, and the selection, combination, and disclosure of these different teachings are themselves part of the inventive content disclosed herein. Background Technology

[0007] In recent years, the scale and complexity of superconducting integrated circuits (ICs) have increased dramatically, with applications spanning sensors, digital data processors, classical computing, and quantum computing. These superconducting ICs consist of thousands of Josephson junctions integrated on a single chip along with inductors, capacitors, and resistors. They are typically made of superconducting thin films of niobium (Nb), niobium nitride (NbN), and aluminum (especially for quantum computing circuits) and are designed to operate at temperatures below 5K. However, these films are highly sensitive to the weak magnetic fields typically associated with multiple superconducting vortices, each possessing a quantized magnetic flux Φ0 = h / 2e = 2 x 10⁻⁶. -15 Wb, this magnetic flux can be trapped in superconducting films, including integrated circuits. These trapped magnetic flux quanta are collectively referred to as the flux trapping problem, and various techniques have been developed over the years to reduce this problem, including magnetic shielding and at the critical temperature T. c The above involves thermal cycling and patterning isolation trenches in the superconducting film. Flux trapping is a major problem faced in various superconducting integrated circuits, including classical superconducting digital processors, quantum superconducting systems, and large-scale superconducting sensor arrays.

[0008] See, for example, the following patents, published patent applications and non-patent documents that are incorporated herein by reference in their entirety: US Patent 4,392,148, "Moat-guarded Josephson devices".

[0009] US 4,409,579, "Superconducting magnetic shielding apparatus and method".

[0010] US 5,164,696, “Apparatus for eliminating trapping of magnetic flux from an object”.

[0011] US 5,173,620, "Device for eliminating trap of magnetic flux in a superconduction circuit".

[0012] US 8,644,898, "Superconducting device having a pattern of engineered defects for controlling magnetic flux".

[0013] US 9,913,414, "Method & apparatus of implementing a magnetic shieldflux sweeper".

[0014] US 9,982,935, "Cryogenic system with rapid thermal cycling".

[0015] US 11,064,637, "System and method for magnetic shielding for a superconducting computing system".

[0016] US 11,417,821, “Superconductor ground-plane patterning geometries that attract magnetic flux”.

[0017] US 2021 / 0068320, "Shielding for superconducting devices"

[0018] US 2022 / 0198310, "Semi-active magnetic shielding for qubit unit components of quantum computing apparatuses"

[0019] US 2023 / 0270020, "Superconducting chip package with improved magnetic shielding".

[0020] US 2023 / 0004851; US ​​11,417,821; US ​​2018 / 0240033; US 9,520,180; US 2012 / 0157319; US 2011 / 0065585; US 2004 / 0098443; US 6,469,880; US 6,332,324; US 5,323,344; US 5,287,058; US 5,173,620; US 5,164,696; US 5,053,707; US 5,051,787; US 4,392,148; US 4,051,393; US 3,706,064

[0021] "Heat Transfer Module User's Guide", Stockholm, 2018.

[0022] TM Fujimaki, T. Yamada, Y. Yamanashi, P. Heejoung and N. Yoshikawa, “Bit-serial single flux quantum microprocessor CORE”, IEICE transactions on electronics, Vol. 91, No. 3, pp. 342-349, 2008.

[0023] Al Luhaibi, A. Glatz, and JB Ketterson, “Driven responses of periodically patterned superconducting films,” Phys. Rev. B, Vol. 106, No. 22, Article No. 224516, December 2022.

[0024] D. Hernández and D. Dom nguez, “Dissipation spots generated by vortex nucleation points in mesoscopic superconductors driven by microwave magnetic fields,” Phys. Rev. B, Vol. 77, No. 22, Article No. 224505, June 2008.

[0025] I. Bezuglyj, VA Shklovskij, B. Budinská, B. Aichner, VM Bevz, MYMikhailov, DY Vodolazov, W. Lang and OV Dobrovolskiy, “Vortex jets generated by edge defects in current-carrying superconductor thin strips”, Phys. Rev. B, Vol. 105, No. 21, Article No. 214507, June 2022.

[0026] I. Blair and DP Hampshire, “Time-Dependent Ginzburg-Landau Simulations of the Critical Current in Superconducting Films and Junctions in Magnetic Fields”, IEEE Transactions on Applied Superconductivity, Vol. 28, pp. 1-5, 2018.

[0027] L. Pankratov and B. Spagnolo, “Suppression of timing errors in shortoverdamped Josephson junctions”, Physical Review Letters, Vol. 93, No. 17, Article No. 177001, 2004.

[0028] M. Herr, CA. Mancini, N. Vukovic, MF. Bocko, and MJ. Feldman, “High-speed operation of a 64-bit circular shift register,” IEEE Transactions on Applied Superconductivity, Vol. 8, No. 3, pp. 120-124, 1998.

[0029] M. Herr, MJ Feldman and MF Bocko, “Timing jitter and bit errors in a 64-bit circular shift register”, IEEE Transactions on Applied Superconductivity, Vol. 9, No. 2, pp. 3721-3724, 1999.

[0030] Matlashov et al., “AC defluxing of SQUIDs”, IEEE Trans. Appl. Supercond., Vol. 27, Article No. 1601605 (2017).

[0031] Mitrovic and E.G. Friedman, “Thermal Modeling of Rapid Single Flux Quantum Circuit Structures”, IEEE Transactions on Electron Devices, Vol. 69, pp. 2718-2724, 2022.

[0032] H. Venter and CJ Fourie, “Initial Numerical Simulation of the Thermodynamic Behaviour of a Superconducting Circuit”, 2019 IEEE International Superconducting Electronics Conference (ISEC).

[0033] Oripov and SM Anlage, “Time-dependent Ginzburg-Landau treatment of rfmagnetic vortices in superconductors: Vortex semiloops in a spatially nonuniform magnetic field,” Phys. Rev. E, Vol. 101, No. 3, Article No. 033306, March 2020.

[0034] Venter, “Development of a thermal analysis tool for superconducting circuits”, Stellenbosch: Stellenbosch University, March 2021.

[0035] Xu J. Franklin, H.-Y. Yang, F. Tafti and I. Sochnikov, “Directional field-dependence of tunable magnetic domains in noncentrosymmetric ferromagnetic Weyl semimetal CeAlSi”, 2021 IEEE International Magnetic Conference (INTERMAG).

[0036] A. a. VN Mancini, AM Herr, K. Gaj, MF Bocko and MJ Feldman, “RSFQ circular shift registers”, IEEE Transactions on Applied Superconductivity, Vol. 7, No. 2, pp. 2832-2835, 1997.

[0037] J. Fourie and K. Jackman, “Experimental Verification of Moat Design and Flux Trapping Analysis”, IEEE Transactions on Applied Superconductivity, Vol. 31, pp. 1-7, 2021.

[0038] J. Fourie and K. Jackman, “High-fidelity circuit simulation of AQFP circuits through compact models extracted from layout,” Journal of Physics: Conference Series, Vol. 2323, Article No. 012034, August 2022.

[0039] J. Fourie and K. Jackman, “Software Tools for Flux Trapping and Magnetic Field Analysis in Superconducting Circuits”, IEEE Transactions on Applied Superconductivity, Vol. 29, pp. 1–4, 2019.

[0040] J. Fourie, K. Jackman, M.M. Botha, S. Razmkhah, P. Febvre, C.L. Ayala, Q. Xu, N. Yoshikawa, E. Patrick, M. Law, Y. Wang, M. Annavaram, P. Beerel, S. Gupta, S. Nazarian and M. Pedram, “ColdFlux Superconducting EDA and TCAD Tools Project: Overview and Progress”, IEEE Transactions on Applied Superconductivity, Vol. 29, pp. 1–7, 2019.

[0041] J. Fourie, O. Wetzstein, T. Ortlepp and J. Kunert, “Three-dimensional multi-terminal superconductive integrated circuit inductance extraction”, Superconductor Science and Technology, Vol. 24, Article No. 125015, November 2011.

[0042] K. Teh and Y. Okabe, “A novel global self-timing methodology for BSFQ circuits”, IEEE Transactions on Applied Superconductivity, Vol. 13, No. 2, pp. 543-546, 2003.

[0043] Davino, J. Franklin and I. Sochnikov, “Millikelvin-compatible apparatus for studies of quantum materials under uniaxial stress”, AIP Advances, Vol. 9, Article No. 125244, December 2019.

[0044] Sto i D. Sto i T. Ludermir, B. Sto i and MV Milo evi “GPU-advanced 3D electromagnetic simulations of superconductors in the Ginzburg-Landau formalism”, Journal of Computational Physics, Vol. 322, pp. 183-198, 2016.

[0045] Marchiori, L. Ceccarelli, N. Rossi, G. Romagnoli, J. Herrmann, J.-C. Besse, S. Krinner, A. Wallraff, and M. Poggio, “Magnetic imaging of superconducting qubit devices with scanning SQUID-on-tip,” Applied Physics Letters, Vol. 121, Article No. 052601, August 2022.

[0046] Persky, I. Sochnikov and B. Kalisky, “Studying Quantum Materials with Scanning SQUID Microscopy”, Annual Review of Condensed Matter Physics, Vol. 13, pp. 385-405, 2022.

[0047] Sardella, AL Malvezzi, PN Lisboa-Filho, and WA Ortiz, “Temperature-dependent vortex motion in a square mesoscopic superconducting cylinder: Ginzburg-Landau calculations,” Phys. Rev. B, Vol. 74, No. 1, Article No. 014512, July 2006.

[0048] R. Berdiyorov, MV Milo evi He FM Peeters, “Spatially dependent sensitivity of superconducting meanders as single-photon detectors”, Applied Physics Letters, Vol. 100, No. 262603, June 2012.

[0049] R. Gerber, CJ Fourie, WJ Perold, and L.C. Muller, “Design of anasynchronous microprocessor using RSFQ-AT”, IEEE Transactions on Applied Superconductivity, Vol. 17, No. 2, pp. 490-493, 2007.

[0050] A. Sadovskyy, AE Koshelev, CL Phillips, DA Karpeyev and A. Glatz, “Stable large-scale solver for Ginzburg-Landau equations for superconductors”, Journal of Computational Physics, Vol. 294, pp. 639-654, 2015.

[0051] S. Aranson and L. Kramer, “The world of the complex Ginzburg-Landauequation”, Rev. Mod. Phys., Vol. 74, No. 1, pp. 99-143, February 2002.

[0052] S. Veshchunov et al., “Optical manipulation of single flux quanta”, Nature Communications, Vol. 7, September 2016.

[0053] S. Veshchunov, W. Magrini, SV Mironov, AG Godin, J.-B. Trebbia, AI Buzdin, P. Tamarat and B. Lounis, “Optical manipulation of single flux quanta”, Nature Communications, Vol. 7, September 2016.

[0054] A. Delport, K. Jackman, P. l. Roux and CJ Fourie, “JoSIM—Superconductor SPICE Simulator”, IEEE Transactions on Applied Superconductivity, Vol. 29, pp. 1–5, 2019.

[0055] Franklin, J. Bedard and I. Sochnikov, “Versatile Millikelvin Hybrid Cooling Platform for Superconductivity Research”, IEEE Transactions on Applied Superconductivity, Vol. 33, pp. 1-3, 2023.

[0056] R. Clem and KK Berggren, “Geometry-dependent critical currents in superconducting nanocircuits”, Phys. Rev. B, Vol. 84, No. 17, Article No. 174510, November 2011.

[0057] R. Clem, Y. Mawatari, GR Berdiyorov, and FM Peeters, “Predicted field-dependent increase of critical currents in asymmetric superconducting nanocircuits,” Phys. Rev. B, Vol. 85, No. 14, Article No. 144511, April 2012.

[0058] R. Kirtley and JP Wikswo, “Scanning Squid Microscopy”, Annual Review of Materials Science, Vol. 29, pp. 117–148, 1999.

[0059] JR Kirtley, “Fundamental studies of superconductors using scanning magnetic imaging,” Reports on Progress in Physics, Vol. 73, Article No. 126501, November 2010.

[0060] Gaj, C.-H. Cheah, E.G. Friedman and MJ Feldman, “Functional modeling of RSFQ circuits using Verilog HDL”, IEEE Transactions on Applied Superconductivity, Vol. 7, No. 2, pp. 3151-3154, 1997.

[0061] Gaj, E.G. Friedman, and MJ Feldman, “Timing of multi-gigahertz rapidsingle flux quantum digital circuits,” High Performance Clock Distribution Networks, Springer, 1997, pp. 135–164.

[0062] Gaj, E.G. Friedman, MJ Feldman and A. Krasniewski, “A clock distribution scheme for large RSFQ circuits”, IEEE Transactions on Applied Superconductivity, Vol. 5, No. 2, pp. 3320-3324, 1995.

[0063] K. Gaj, Q. Herr and M. Feldman, “Parameter variations and synchronization of RSFQ circuits”, Conference Series-Institute of Physics, Vol. 148, pp. 1733-1736, 1995.

[0064] K. Jackman and CJ Fourie, “Fast Multicore Fast Henry and a Tetrahedral Modeling Method for Inductance Extraction of Complex 3D Geometries”, 15th International Superconductive Electronics Conference (ISEC), 2015.

[0065] K. Jackman and CJ Fourie, “Flux Trapping Analysis in Superconducting Circuits”, IEEE Transactions on Applied Superconductivity, Vol. 27, pp. 1-5, 2017.

[0066] K. Jackman and CJ Fourie, “Flux trapping experiments to verify simulation models,” Superconductor Science and Technology, Vol. 33, Article No. 105001, August 2020.

[0067] K. Jackman and CJ Fourie, “Multipole accelerated magnetic field calculations for superconducting circuits”, Superconductor Science and Technology, Vol. 32, Article No. 015011, November 2018.

[0068] K. Jackman and CJ Fourie, “Tetrahedral Modeling Method for Inductance Extraction of Complex 3-D Superconducting Structures”, IEEE Transactions on Applied Superconductivity, Vol. 26, pp. 1-5, 2016.

[0069] KK Likharev and VK Semenov, “RSFQ logic / memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems,” IEEE Transactions on Applied Superconductivity, Vol. 1, No. 1, pp. 3-28, 1991.

[0070] K. Suzuki, R. Hosomizu, S. Adachi, U. Kawabe and K. Tanabe, “Investigation of flux trapping into moats with various moat depths by a scanning SQUID microscope,” Physica C: Superconductivity, Vol. 392-396, pp. 1446-1450, 2003.

[0071] K. Tanaka, T. Morooka, A. Odawara, Y. Mawatari, S. Nakayama, A. Nagata, K. Ikeda, K. Chinone and M. Koyanagi, “Study of trapped flux in a superconducting thin film-observation by scanning SQUID microscope and simulation”, IEEE Transactions on Applied Superconductivity, Vol. 11, pp. 230-233, 2001.

[0072] Bishop-Van Horn, “pyTDGL: Time-dependent Ginzburg-Landau in Python”, Computer Physics Communications, Vol. 291, No. 108799, 2023.

[0073] Bishop-Van Horn, E. Mueller and K.A. Moler, “Vortex dynamics induced by scanning SQUID susceptometry”, Phys. Rev. B, Vol. 107, No. 22, Article No. 224509, June 2023.

[0074] Kramer and RJ Watts-Tobin, “Theory of Dissipative Current-Carrying States in Superconducting Filaments,” Phys. Rev. Lett., Vol. 40, No. 15, pp. 1041-1044, April 1978.

[0075] L. Peng and C. Cai, “Finite Element Treatment of Vortex States in 3D Cubic Superconductors in a Tilted Magnetic Field”, Journal of Low Temperature Physics, Vol. 188, pp. 39-48, March 2017.

[0076] Alnæs, J. Blechta, J. Hake, A. Johansson, B. Kehlet, A. Logg, C. Richardson, J. Ring, ME Rognes and GN Wells, “The FEniCS project version 1.5”, Archive of numerical software, Vol. 3, 2015.

[0077] C. de Andrade et al., “Flux flushing in superconducting niobium films”, IEEE 14th International Superconducting Electronics Conference (ISEC 2013).

[0078] Dorojevets, P. Bunyk, and D. Zinoviev, “FLUX chip: Design of a 20-GHz 16-bit ultrapipelined RSFQ processor prototype based on 1.75μm LTS technology,” IEEE Transactions on Applied Superconductivity, Vol. 11, No. 1, pp. 326-332, 2001.

[0079] M. Jeffery, T. Van Duzer, JR Kirtley, and MB Ketchen, “Magnetic imaging of moat-guarded superconducting electronic circuits,” Applied Physics Letters, Vol. 67, pp. 1769-1771, September 1995.

[0080] M. Machida and H. Kaburaki, “Direct simulation of the time-dependent Ginzburg-Landau equation for type-II superconducting thin film: Vortex dynamics and VI characteristics,” Phys. Rev. Lett., Vol. 71, No. 19, pp. 3206-3209, November 1993.

[0081] M. Maezawa, I. Kurosawa, M. Aoyagi, H. Nakagawa, Y. Kameda and T. Nanya, “Rapid single-flux-quantum dual-rail logic for asynchronous circuits”, IEEE Transactions on Applied Superconductivity, Vol. 7, No. 2, pp. 2705-2708, 1997.

[0082] M. Maezawa, I. Kurosawa, Y. Kameda, and T. Nanya, “Pulse-driven dual-raillogic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits,” *Advanced Research in Asynchronous Circuits and Systems*, 1996. Proceedings, Second International Symposium, pp. 134–142, 1996.

[0083] Bunyk, K. Likharev and D. Zinoviev, “RSFQ technology: Physics and devices”, International journal of high speed electronics and systems, Vol. 11, No. 1, pp. 257-305, 2001.

[0084] Bunyk, M. Leung, J. Spargo and M. Dorojevets, “FLUX-1 RSFQ microprocessor: Physical design and test results”, IEEE Transactions on Applied Superconductivity, Vol. 13, No. 2, pp. 433-436, 2003.

[0085] Holmvall, N. Wall Wennerdal, M. Håkansson, P. Stadler, O. Shevtsov, T. Löfwander and M. Fogelström, “SuperConga: An open-source framework for mesoscopic superconductivity”, Applied Physics Reviews, Vol. 10, Article No. 011317, March 2023.

[0086] Geng et al., “Sweeping of trapped flux in superconducting films by a micro-heat-flushing method”, J. Appl. Phys., Vol. 72, pp. 2411-2417 (1992).

[0087] J. Watts-Tobin, Y. Krahenbuhl and L. Kramer, “Nonequilibrium theory of dirty, current-carrying superconductors: phase-slip oscillators in narrow filaments near T_c”, Journal of Low Temperature Physics, Vol. 42, pp. 459-501, March 1981.

[0088] R. Robertazzi et al., “Flux trapping experiments in single flux quantumshift registers”, IEEE Transactions on Applied Superconductivity, Vol. 7, pp. 3164-3167 (1997).

[0089] Narayana et al., “Evaluation of Flux Trapping in Superconducting Circuits”, IEEE Transactions on Applied Superconductivity, Vol. 19, pp. 640-643, 2009.

[0090] Golod, L. Morlet-Decarnin and V. Krasnov, “Word and bit line operation of a 1x1 μm2 superconducting vortex-based memory”, Nature Communications, Vol. 14, No. 4926, pp. 1-8, 2023.

[0091] T. Jabbari and E. Friedman, “Stripline topology for flux mitigation”, IEEE Trans. Appl. Supercond., Vol. 33, Article No. 1500604 (2023).

[0092] TS Alstrøm, MP Sørensen, NF Pedersen and S. Madsen, “Magnetic FluxLines in Complex Geometry Type-II Superconductors Studied by the Time-Dependent Ginzburg-Landau Equation”, Acta Applicandae Mathematicae, Vol. 115, pp. 63-74, August 2010.

[0093] T. Winiecki and C.S. Adams, “A Fast Semi-Implicit Finite-Difference Method for the TDGL Equations”, Journal of Computational Physics, Vol. 179, pp. 127-139, 2002.

[0094] K. Semenov and M.M. Khapaev, “How Moats Protect Superconductor Films From Flux Trapping”, IEEE Transactions on Applied Superconductivity, Vol. 26, pp. 1-10, 2016.

[0095] D. Gropp, HG Kaper, GK Leaf, DM Levine, M. Palumbo and VM Vinokur, “Numerical Simulation of Vortex Dynamics in Type-II Superconductors”, Journal of Computational Physics, Vol. 123, pp. 254-266, 1996.

[0096] W.-K. Kwok, U. Welp, A. Glatz, AE Koshelev, KJ Kihlstrom and GW Crabtree, “Vortices in high-performance high-temperature superconductors”, Reports on Progress in Physics, Vol. 79, Article No. 116501, September 2016.

[0097] Ando, ​​R. Sato, M. Tanaka, K. Takagi, N. Takagi and A. Fujimaki, “Design and Demonstration of an 8-bit Bit-Serial RSFQ Microprocessor: CORE e4”, IEEE Transactions on Applied Superconductivity, Vol. 26, No. 5, pp. 1-5, 2016.

[0098] Kameda, S. Polonsky, M. Maezawa, and T. Nanya, “Primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic,” *Advanced Research in Asynchronous Circuits and Systems*, 1998. Proceedings, 1998 Fourth International Symposium.

[0099] Polyakov et al., “3D active demagnetization of cold magnetic shields”, IEEE Trans. Appl. Supercond., Vol. 21, pp. 724-727 (2011).

[0100] Y. Yamanashi, H. Imai and N. Yoshikaw, “Influence of Magnetic Flux Trappedin Moats on Superconducting Integrated Circuit Operation”, IEEE Transactions on Applied Superconductivity, Vol. 28, pp. 1-5, 2018.

[0101] J. Deng, N. Yoshikawa, SR Whiteley and TV Duzer, “Data-driven self-timed RSFQ digital integrated circuit and system”, IEEE Transactions on Applied Superconductivity, Vol. 7, No. 2, pp. 3634-3637, 1997.

[0102] L. Jeli MV Milo evi And A.V. Silhanek, “Velocimetry of superconducting vortices based on stroboscopic resonances”, Scientific Reports, Vol. 6, October 2016.

[0103] Z.-C. Wang, JD Rogers, X. Yao, R. Nichols, K. Atay, B. Xu, J. Franklin, I. Sochnikov, PJ Ryan, D. Haskel and F. Tafti, “Colossal Magnetoresistance without Mixed Valence in a Layered Phosphide Crystal”, Advanced Materials, Vol. 33, No. 2005755, 2021.

[0104] Aull. S., O. Kugeler and J. Knobloch, “Trapped magnetic flux in superconducting niobium samples”, Physical Review Special Topics-Accelerators and Beams, Vol. 15, No. 6 (2012): 062001.

[0105] Aull. S., J. Knobloch and O. Kugeler, “Study of trapped magnetic flux in superconducting niobium samples”, Proc. 15th Int. Conf. on RF Superconductivity, pp. 702-706, 2011.

[0106] Gonnella Dan, John Kaufman, and Matthias Liepe, “Impact of nitrogen doping of niobium superconducting cavities on the sensitivity of surface resistance to trapped magnetic flux,” Journal of Applied Physics, Vol. 119, No. 7 (2016).

[0107] Jeon Kun-Rok, Chiara Ciccarelli, Hidekazu Kurebayashi, Lesley F. Cohen, Xavier Montiel, Matthias Eschrig, Thomas Wagner, et al., “Effect of meissnerscreening and trapped magnetic flux on magnetization dynamics in thick Nb / Ni80 Fe20 / Nb trilayers”, Physical Review Applied, Vol. 11, No. 1 (2019): 014061.

[0108] Tomkow Lukasz, Anis Smara, Vicente Climente-Alarcon, and Bartek A. Glowacki, “Distribution of trapped magnetic flux in superconducting stacks magnetized by angled field,” Journal of Superconductivity and Novel Magnetism, Vol. 33 (2020): 1299–1305.

[0109] Liarte, Danilo B., Daniel Hall, Peter N. Koufalis, Akira Miyazaki, Alen Senanian, Matthias Liepe, and James P. Sethna, “Vortex dynamics and losses due to pinning: Dissipation from trapped magnetic flux in resonant superconducting radio-frequency cavities,” Physical Review Applied, Vol. 10, No. 5 (2018): 054057.

[0110] Lousberg, Gregory P., Marcel Ausloos, Ph Vanderbemden and Benoît Vanderheyden, “Bulk high-Tc superconductors with drilled holes: how to arrange the holes to maximize the trapped magnetic flux?” Superconductor Science and Technology, Vol. 21, No. 2 (2008): 025010.

[0111] Watanabe Norimichi, Akiyoshi Nakayama, and Susumu Abe, “Influence of trapped magnetic flux quantum on two-dimensional magnetic field dependence of a Josephson junction,” Journal of Applied Physics, Vol. 101, No. 9 (2007).

[0112] Zhu BY, F. Marchesoni and Franco Nori, “Controlling the motion of magnetic flux quanta”, Physical Review Letters, Vol. 92, No. 18 (2004): 180602.

[0113] Kuzmin Yu I., “Dynamics of the magnetic flux trapped in fractalclusters of normal phase in a superconductor”, Physical Review B, Vol. 64, No. 9 (2001): 094519.

[0114] Mannhart J., J. Bosch, R. Gross and RP Huebener, “Two-dimensional imaging of trapped magnetic flux quanta in Josephson tunnel junctions”, Physical Review B, Vol. 35, No. 10 (1987): 5267.

[0115] Balachandran Shreyas, Anatolii Polyanskii, Santosh Chetri, Pashupati Dhakal, Yi-Feng Su, Zu-Hawn Sung, and Peter J. Lee, “Direct evidence of microstructure dependence of magnetic flux trapping in niobium,” Scientific Reports, Vol. 11, No. 1 (2021): 5364.

[0116] Parajuli, Ishwari Prasad, Gianluigi Ciovati, and Jean R. Delayen, “Magneticfield sensors for detection of trapped flux in superconducting radiofrequency cavities,” Review of Scientific Instruments, Vol. 92, No. 10 (2021).

[0117] Uchida N., K. Enpuku, Y. Matsugaki, S. Tomita, F. Irie and K. Yoshida, “Fluxtrapping in Josephson tunnel junctions”, Journal of Applied Physics, Vol. 54, No. 9 (1983): 5287-5292.

[0118] Nappi C., R. Cristiano and MP Lisitskii, “Fiske steps in annular Josephson junctions with trapped flux quanta”, Physical Review B, Vol. 58, No. 17 (1998): 11685.

[0119] Vernik IV, S. Keil, N. Thyssen, T. Doderer, A.V. Ustinov, H. Kohlstedt and R.P. Huebener, “Fluxon pinning in annular Josephson junctions by an external magnetic field,” Journal of Applied Physics, Vol. 81, No. 3 (1997): 1335-1340.

[0120] Tarte EJ, HW Lean, and JR Waldram, “The effect of trapped flux upon the magnetic field dependence of the critical current of Josephson junctions,” IEEE Transactions on Applied Superconductivity, Vol. 5, No. 2 (1995): 2388-2391.

[0121] Jackman Kyle and Coenrad J. Fourie, “Flux trapping experiments to verify simulation models”, Superconductor Science and Technology, Vol. 33, No. 10 (2020): 105001.

[0122] Nakayama Akiyoshi, Yohei Nishi, Norimichi Watanabe, Susumu Abe, and Yoichi Okabe, “Measurement of trapped flux magnetic field near the superconducting film by the dependence of superconducting current through a Josephson junction sensor,” Journal of Physics: Conference Series, Vol. 234, No. 4, Article No. 042023, IOP Press, 2010.

[0123] Fedorov Kirill G., Anastasia V. Shcherbakova, Roland Schäfer and Alexey V. Ustinov, “Josephson vortex coupled to a flux qubit”, Applied Physics Letters, Vol. 102, No. 13 (2013).

[0124] Aaroe M., R. Monaco, R. Rivers, V. Koshelets and Jesper Mygind, “Quench-induced trapping of magnetic flux in annular Josephson junctions,” Journal of Physics: Conference Series, Vol. 97, No. 1, Article No. 012279, IOP Press, 2008.

[0125] Despite years of in-depth research, flux trapping in superconducting integrated circuits remains a pervasive adverse factor affecting the reliable operation of various types of superconducting circuits (from quantum to classical, from analog to digital) fabricated using a wide range of processes and material choices. This difficulty stems from the fact that the probability of flux trapping depends on a vast set of parameters, including specific circuit design, isolation trench structure, local magnetic field configuration near the chip, manufacturing batch, materials, magnetic shielding quality, test setup, and more. Furthermore, determining the precise correlation between specific flux trapping patterns and circuit failure modes is also challenging. To date, flux trapping remains a major obstacle to extending superconducting electronics (SCE) to large-scale practical systems.

[0126] Typically, existing methods focus on various mitigation strategies for trapped flux, covering levels from circuit design to cryogenic packaging engineering, but none of these strategies can completely solve the problem. Furthermore, these methods are not particularly scalable or efficient, as they come at the cost of increased circuit density, overall complexity, limited architectural choices, or the need for more expensive and complex magnetic shielding. Even with excellent magnetic shielding, problems persist when magnetic field attenuation reaches six orders of magnitude or higher (shielding factor > 10). 6 In the case of superconducting electronic (SCE) integrated circuits (ICs), some flux remains even when cooled below the transition temperature. This flux is frozen as trapped magnetic flux quanta in the form of Abrikosov or Pearl vortices, which affect the operation of SCE circuits. Actual shielding efficiency is much lower, with typical shielding factors around 10. 4 Traditional mitigation methods utilize isolation trenches in a superconducting ground plane to "attract" vortices and rely on time-consuming repetitive SCE chip thermal cycling above a critical temperature to reposition the trapped flux into a more benign pattern.

[0127] Numerous studies have examined the optimal size and placement of isolation slots for flux trapping, but fewer have considered the impact of the magnetic flux quanta trapped by the isolation slots on circuit operation. As integration density increases, extensive networks of isolation slots become excessively large and unscalable. Even as isolation slots are squeezed smaller and integrated at higher densities, they can still trap critical fields for flux, and consequently, the uncertainty regarding the locations where flux pinning may occur increases.

[0128] It is known that superconductors repel magnetic fields from within themselves, except for Type II superconductors, which allow magnetic fields to enter in the form of vortices (en.wikipedia.org / wiki / Type-II_superconductor). These vortices, also known as fluxoids, consist of both the magnetic flux induced by an external magnetic field and the circulating supercurrent. Due to the single-valued nature of the superconducting order parameter, the fluxoids are quantized. The quantized value of the fluxoid (Φ) F ) by magnetic flux (Φ B ) and supercurrent flux (Φ J The sum of ) is determined and denoted as Φ. F =Φ B + Φ J = Φ0, where Φ0 = h / 2 e , h and e These are Planck's constant and the electron charge, respectively. When the contribution of the supercurrent is negligible (Φ... J When = 0), the quantization of magnetic flux-like properties is simplified to the quantization of magnetic flux (Φ). F =Φ B = Φ0). Conversely, in the presence of significant supercurrent, the quantized entity becomes a flux-like substance rather than a magnetic flux. Kim G., Yun J., Yang J., et al., Vortex confinement through an unquantized magnetic flux, NPG Asia Mater, Vol. 16, Article No. 44 (2024), doi.org / 10.1038 / s41427-024-00564-6.

[0129] To further extend integrated superconducting circuits to millions of Josephson junctions or even more, a new approach is needed. Summary of the Invention

[0130] Compared to existing technologies, the present invention provides a radical approach that completely solves the problem by removing the trapped flux from the active circuit region, rather than attempting to find better mitigation strategies as in conventional methods. The present invention is highly scalable and increases circuit integration density, thereby reducing wiring constraints, significantly simplifying magnetic shielding, and increasing the overall reliability and stability of SCE circuit operation. This technology eliminates the need for extensive isolation trench networks, repeated thermal cycling of the entire chip or cryogenic package, and cumbersome shielding or active magnetic shielding.

[0131] This technique is based on actively steering or sweeping vortices around the chip using a specially designed network of control lines. These control lines generate localized heating and localized magnetic gradients in the superconducting circuit of interest. The close proximity of these control lines to the circuit allows small currents to have a significant impact on generating substantial localized heating and magnetic forces in the trapped vortices. This proximity also allows for relatively large spatial gradients in the vicinity of the trapped flux.

[0132] Heating is balanced by cooling from a refrigerant or cryogenic cooler. Therefore, the circuit may include at least one of a thermal sensing structure, a magnetic field sensing structure (e.g., a SQUID), and a critical current sensing structure to allow for optimized local heating (and / or magnetic field) by limiting energy consumption and delays in returning to normal operating temperature due to unnecessary (over)heating of the structure. Similarly, sensors allow control lines to be adequately driven to achieve an effective state. This feedback-based optimization prevents unnecessary cooling while ensuring efficiency. Feedback processing may be performed on-chip (i.e., within the same integrated circuit), on different chips within the same cryogenic environment (e.g., a superconducting circuit), or on external circuitry (e.g., a room-temperature circuit).

[0133] Sensing can be functional, meaning the Josephson junction is constructed and biased to respond to temperature changes and magnetic fields near the unpinning temperature or critical temperature. A set of sensors with incrementally optimal sensing values ​​or thresholds can be provided to achieve narrow-range definition of the effect.

[0134] This combination of thermal and magnetic gradients is used to sweep away magnetic vortices from the superconducting circuit of interest. The magnetic flux can be transferred to a region of the chip (“flux discharge region”) where the effect of the magnetic flux on the circuit is negligible, or alternatively, completely eliminated from the chip. In this way, superconducting integrated circuits with up to millions of Josephson junctions that do not contain external magnetic flux quanta can be fabricated.

[0135] For example, for 1cm 2This circuit corresponds to an effective magnetic field of less than 20 pT. For comparison, the Earth's magnetic field is approximately 50 μT, making this circuit two million times larger. This exceeds what can be achieved using conventional magnetic shielding techniques.

[0136] Figures 1A to 1D Several preferred embodiments of the configuration of the control lines relative to the superconducting circuit are illustrated.

[0137] Figure 1A A cross-sectional view of a control line (labeled HS) array is shown, which is located on the same substrate as the superconducting circuit (labeled SFQ cct for a single flux quantum circuit), and the two are separated only by a thin insulating layer (“dielectric”).

[0138] Figure 1B The control lines are shown on the back side of the substrate (typically silicon), opposite to the superconducting circuitry.

[0139] Figure 1C Control lines on a separate chip (“ClearFlux”) are shown, which is flip-chip bonded to a chip with superconducting circuitry. Flip-chip bonding of superconducting ICs is well known in the art. See, for example, US11,711,985 “System and method for superconducting multi-chip module”, which is incorporated herein by reference.

[0140] Figure 1D It shows Figure 1A A top view of the configuration, showing a portion of the superconducting IC.

[0141] Array control lines can be evenly spaced on the chip, but periodic spacing is not required. Control lines are provided near the center of the chip, near the edge of the chip, and in the intermediate region between the center and the edge. The flux sweeping process involves moving the captured flux from the center of the chip towards the edge.

[0142] In one embodiment, the control line may comprise a thin metal film that is resistive (i.e., not superconducting) at the operating temperature of the circuit. Current flowing through such a line... I This will generate both localized Joule heating and a circumferential magnetic field around the line. Joule heating will raise the temperature of the nearby superconducting circuit, for example, from 4 K to about 8 to 9 K, but still below the critical temperature of niobium, T0. c = 9.2K. This will significantly reduce the pinning force required to move the trapped vortex. In this way, a current of approximately 1mA is expected in the control line. I The trapped magnetic flux quanta in the circuit near the line can be easily moved.

[0143] The circumferential magnetic field is given by B = μ0 I / 2π r Given, among which r Φ is the distance from the center of the line, and μ0 = 1.26 μH / m is the permeability of free space. This magnetic field will exert a transverse force (sometimes called the Lorentz force) on the trapped vortex, causing it to move in the transverse direction given by the vector product I × Φ0, where Φ0 points up or down, and I points in the direction of current flow. This is in Figure 2 As illustrated, this diagram distinguishes between vortices (pointing inwards from the page) and "anti-vortices" pointing outwards from the page. The current used to move the anti-vortices is in the opposite direction.

[0144] Figure 3 Indicates used for Figure 1A A conceptual diagram of an embodiment of the sequential steps in the flux sweep process. Assume the trapped vortex's Φ0 points upwards, the current on the left points outwards, and the current on the right points inwards. In the first time step (labeled T1), the current in the central heater line (H1) is switched on, generating diffused heat as indicated by the radial arrows. This forces the vortices below these lines to move outwards, as indicated by the red arrows in the section labeled "SFQ circuit". In the next time step T2, the heater current in H1 is maintained, and the current in H2 is switched on. This forces the vortex to move further outwards. At time steps T3 and T4, the currents in H3 and H4 are switched on, thus forcing the vortex to move further outwards, while lines H1 and H2 can be switched off. At the end of the process, the vortex has crossed the superconducting ground plane (the superconducting film without Josephson junctions) and is trapped in the "flux discharge region" at the outer edge.

[0145] These flux-dissipating regions may include holes in the superconducting ground plane or another structure designed to attract vortices. When all control currents are turned off and the superconducting film cools down (to approximately 4K), the spontaneously shielded supercurrent in the ground plane should prevent vortices from re-entering the superconducting circuitry. The superconducting integrated circuit can then operate without magnetic flux interference.

[0146] Flux sweeping effects can also be used to intentionally generate, maintain, and modify magnetic fields in certain regions of superconducting devices. For example, trapped flux can activate, deactivate, or modulate regions of an integrated circuit, allowing for fine control of circuit operation, particularly in the analog domain, while maintaining the trapped current. This can be achieved, for example, by requiring less energy to sweep the trapped flux around the device compared to the injection and removal of the current itself. Furthermore, given that the trapped flux current itself can be large, the sweeping system can operate faster than using quantum logic to modify the magnetic field. Trapped flux can also help calibrate circuit operation. For example, circuitry can be provided on a portion of the circuit to generate and modulate the intensity of the trapped magnetic flux, which can then be swept to the operating portion of the device that operates depending on the intensity of the trapped magnetic flux. In another embodiment, the trapped flux is used as an energy storage system, and the trapped flux can be swept to a coupler to replenish or utilize the stored energy. Therefore, flux sweeping techniques are not limited to applications where the presence of trapped flux is generally undesirable, but can also be utilized in the operation of devices.

[0147] Advantageously, both heat and magnetic field exist simultaneously at the same location in the circuit. Without heat, the pinning force would be too great to ensure effective sweeping of all vortices, thus the trapped flux is held in place. After the vortices are swept away, the control current can be turned off, thereby cooling the superconducting device and trapping the vortices at an alternative location sufficiently far from the device. While heating and magnetic field from the control lines can be correlated, in other cases, the magnetic field can be controlled by a superconducting element without correlated Joule heating. Heating can be performed using a pair of twisted (magnetic field canceling) control lines (which can be photolithographically formed on the surface of the integrated circuit). Therefore, heating and magnetic field application can be controlled independently, or at least partially independently. This, in turn, facilitates the multiplexing of control signals.

[0148] The magnitude and timing of the control current can be guided by accurate modeling of flux trapping and detrapping processes near the transition temperature, local heating in multilayer ICs with temperature fluctuations, and the effects of thermal gradients.

[0149] Verification of flux sweeping can be performed using a special SQUID monitor embedded in the magnetic field IC, which can also monitor localized heating.

[0150] The control lines for heat generation may comprise a resistive metal film having a resistance of approximately 1 ohm per square millimeter. These lines may be approximately 1 μm wide. The heater current may comprise a DC current of either polarity, or a high-frequency (e.g., in the GHz range) AC current, or any suitable pulse sequence. Of course, for magnetic field generation, the current polarity is critical; reversing the direction of the current will reverse the transverse direction of the flux flow. The magnetic field generation lines and heater lines may be optimized separately and may be interleaved. For example, a superconducting control line can generate a large magnetic field without generating heat. In a preferred embodiment, the magnetic field generation lines may comprise superconducting niobium or niobium nitride, while the heater lines may comprise resistive non-superconducting alloys or compounds, such as Ti-Pd or MoN.

[0151] The control currents for the heater and magnetic field generation lines can be generated externally under program control. Flux sweeps can be repeated multiple times for optimal performance. A single flux sweep can be very fast, taking approximately a few microseconds. Complete cooling to operating temperature (typically around 4K) may take longer, but subsequent flux sweeps do not require waiting for complete cooling. The circuitry can be optimized to operate at temperatures above full cooling. Throughout the process, care should be taken to prevent unintended reverse flux flow from the flux discharge region back into the superconducting circuitry and to avoid eddy currents in the control current. In a preferred embodiment, sensor signals from an embedded SQUID can provide feedback for automatic closed-loop control of the defluxing process.

[0152] One objective is to provide a system for sweeping trapped magnetic flux from a superconducting integrated circuit on a chip operating at a cryogenic operating temperature, the system comprising: a superconducting integrated circuit including a plurality of superconducting devices and at least one structure subjected to magnetic flux trapping; and a plurality of control lines configured to generate a timing sequence of control current pulses that generate a magnetic field and alter the operating margin of the at least one structure subjected to magnetic flux trapping relative to a critical state; the sequence of control current pulses being adapted to locally sweep away the magnetic flux trapped in the at least one structure by: reducing the affinity of the trapped magnetic flux to the at least one structure by decreasing the margin; and providing a magnetic field to induce repositioning of the trapped magnetic flux.

[0153] Another objective is to provide a system and method for sweeping trapped vortices from a superconducting integrated circuit on a chip operating at a cryogenic operating temperature, the system and method comprising: a superconducting integrated circuit including a plurality of superconducting devices and at least one structure subjected to vortex trapping; and a plurality of control lines configured to generate a timing sequence of control current pulses that generate a magnetic field and alter the operating margin of the at least one structure subjected to vortex trapping relative to a critical state; the sequence of control current pulses being adapted to locally sweep the trapped vortices from the at least one structure by: reducing the affinity of the trapped vortices to the at least one structure by decreasing the margin; and providing a magnetic field to induce the repositioning of the trapped vortices.

[0154] Another objective is to provide a method for sweeping trapped flux from a chip including a superconducting integrated circuit, the method comprising: operating the superconducting integrated circuit at a cryogenic temperature; and applying at least one first current pulse adapted to heat a first region of the superconducting integrated circuit to near the superconducting critical temperature to reduce the binding of magnetic flux to the first region and simultaneously generate a magnetic field gradient in the first region sufficient to sweep away the magnetic flux with reduced binding.

[0155] Another objective is to provide a method for sweeping trapped vortices from a chip including a superconducting integrated circuit, the method comprising: operating the superconducting integrated circuit at a cryogenic temperature; and applying at least one current pulse adapted to heat a region of the superconducting integrated circuit to near the superconducting critical temperature, thereby weakening the binding of trapped vortices to the region and simultaneously generating a magnetic field gradient in the region sufficient to sweep trapped vortices with weakened binding from the region. The method may further include receiving feedback from at least one superconducting quantum interference device (SQUID) sensor to track the progress of sweeping trapped vortices, wherein the superconducting integrated circuit is associated with multiple control lines configured to generate a timing sequence of multiple current pulses that generate a magnetic field gradient and alter the operating margin of at least one structure in the region subjected to vortex trapping relative to a critical state. The application includes sequencing the multiple current pulses according to feedback from the at least one SQUID sensor to locally sweep trapped vortices in at least one structure, achieved by: reducing the affinity of the trapped vortices to at least one structure by decreasing the margin; and providing a magnetic field gradient to cause the trapped vortices to reposition toward at least one of the periphery of the superconducting integrated circuit and a flux discharge region configured to keep the swept vortices away from at least one structure.

[0156] Another objective is to provide a system for sweeping trapped vortices from a superconducting integrated circuit structure, the system comprising: multiple control lines configured to generate a timing sequence of control current pulses that generate magnetic field gradients and Joule heating to alter vortex trapping within a region of the superconducting integrated circuit structure; and an automatic control device configured to generate a timing sequence of control current pulses to sweep trapped vortices from the region, achieved by reducing the affinity of the trapped vortices for the structure and exposing feasible paths for the trapped flux to be repositioned to another region of the superconducting integrated circuit structure.

[0157] Another objective is to provide a superconducting circuit system comprising: an integrated circuit including a plurality of superconducting devices and at least one structure configured to trap vortices; a plurality of control lines configured to generate heat and magnetic fields that alter the pinning of the trapped vortices in the at least one structure and generate a Lorentz force to reposition the trapped vortices; and a control device configured to generate a timing sequence of control current pulses in the plurality of control lines, the timing sequence of the control current pulses being adapted to reduce the pinning of the trapped vortices to the at least one structure and to use the generated Lorentz force to sweep the trapped vortices away from the at least one structure.

[0158] Control lines can be deposited on top of the superconducting integrated circuit, or on the side of the chip opposite to the superconducting integrated circuit, or on a separate chip separate from the chip with the superconducting integrated circuit, wherein the separate chip is mounted on the chip with the superconducting integrated circuit using a flip-chip bonding configuration.

[0159] A sequence of control current pulses can be first applied to the control lines in the central part of the superconducting integrated circuit, and then successively applied to the peripheral region of the superconducting integrated circuit to move outward toward the edge of the superconducting integrated circuit.

[0160] The control lines may be located on the chip above the superconducting integrated circuit and / or on the back of the chip and / or on a separate chip separate from the superconducting integrated circuit, wherein the separate chip is mounted on the superconducting integrated circuit using a flip-chip bonding configuration.

[0161] Control lines can exist near the center of the superconducting integrated circuit, near the outer edge of the superconducting integrated circuit, and in the region between the center and the outer edge of the superconducting integrated circuit.

[0162] A sequence of control current pulses can be first applied to the control lines in the central part of the superconducting integrated circuit, and the sequence moves outwards sequentially toward the edge of the superconducting integrated circuit.

[0163] The control current pulse can be configured to reduce the margin by locally heating the superconducting device to a temperature close to but not exceeding the critical temperature of the superconducting device.

[0164] The control pulse can also be configured to provide a magnetic field to generate a magnetic force on the trapped magnetic flux sufficient to remove the trapped magnetic flux from the superconducting device.

[0165] Control current pulses can be adapted to remove trapped magnetic flux from superconducting devices by discharging the trapped magnetic flux from the chip.

[0166] The control current pulse can be adapted to remove trapped magnetic flux from the superconducting device by transferring the trapped magnetic flux to one or more magnetic flux discharge regions located away from the superconducting device.

[0167] The control line may include a resistive metal thin film optimized for heat generation. The control line may be configured to generate heat on the superconducting integrated circuit via Joule heating. The control line comprises at least one of titanium-palladium and molybdenum nitride.

[0168] A control circuit can be provided, configured to generate a sequence of control pulses. The sequence of control pulses may have a predefined sequence. The control circuit can be configured to continuously generate multiple predefined sequences.

[0169] The control lines may include superconducting thin films optimized for magnetic field generation. The control lines may be formed of niobium, niobium nitride, or aluminum (specifically for quantum computing applications).

[0170] At least one structure subjected to magnetic flux trapping can be subjected to an external magnetic field (such as the Earth's magnetic field, an artificial magnetic field, or a magnetic field generated due to operation in an environment including changing currents), and the sequence of control current pulses can be adapted to reduce the effective magnetic field in at least one structure by at least three orders of magnitude, such as three, four, five, six, or more. In some embodiments, reducing the field to zero is not the goal; rather, a non-zero field can be sought. For example, a precise field strength or quantized vortex may be the optimal operating state. Therefore, the system and process seek to achieve a predetermined state, which can be zero or some other magnetic field or vortex state.

[0171] Superconducting devices may include superconducting qubits or single-flux quantum logic circuits or Josephson junction circuits.

[0172] Superconducting integrated circuits may include at least 100,000 Josephson junctions or at least one million Josephson junctions.

[0173] Superconducting devices may include superconducting sensors that respond to at least one of temperature and magnetic field.

[0174] Superconducting devices may include single-flux quantum logic circuits.

[0175] Superconducting devices may include superconducting sensors and / or superconducting quantum interference device (SQUID) sensors and / or superconducting quantum interference filter (SQUID) sensors. Superconducting devices may include superconducting sensors that respond to at least one of temperature and magnetic field.

[0176] The system may also include multiple superconducting quantum interference devices (SQUIDs) sensors configured to perform at least one of detecting trapped magnetic flux and monitoring magnetic flux sweeping.

[0177] The system may also include multiple superconducting quantum interference device (SQUID) sensors configured to monitor sweeps of magnetic flux, including the detection of magnetic field strength and temperature.

[0178] Control current pulses can be applied under feedback control based on superconducting quantum interference device (SQUID) sensors.

[0179] The sequence of control current pulses may include at least one pulse having an intensity or duration that varies according to the amount of captured flux.

[0180] The system may also include a control circuit configured to generate control current pulses.

[0181] The system may also include control circuitry, multiple sets of independently operable control lines, and at least one magnetic field sensor associated with each set of control lines. Each set of control lines, located on a corresponding portion of the chip, is operated by the control circuitry based on the associated at least one magnetic field sensor.

[0182] The control circuit can be located on the chip, in the superconducting integrated circuit, or in an integrated circuit adjacent to the superconducting integrated circuit.

[0183] The control circuit can be implemented using logic components that operate at room temperature.

[0184] Control circuits can rely on feedback.

[0185] The sequence of control current pulses can be applied sequentially multiple times to successively reduce the trapped flux.

[0186] Magnetic flux can be swept to the periphery of superconducting integrated circuits.

[0187] At least one first current pulse may include multiple pulses adapted to sequentially sweep magnetic flux toward the periphery of the superconducting integrated circuit.

[0188] The method may also include sweeping magnetic flux to at least one flux discharge region configured to capture magnetic flux from the superconducting device on the superconducting integrated circuit.

[0189] The method may also include receiving feedback from at least one superconducting quantum interference device (SQUID) sensor to track the progress of magnetic flux sweeping.

[0190] Superconducting integrated circuits can be associated with multiple control lines configured to generate a timing sequence of control current pulses that generate a magnetic field and alter the operating margin of at least one structure subjected to magnetic flux trapping relative to a critical state.

[0191] The application may include sequencing control current pulses to locally sweep away magnetic flux trapped in at least one structure, which is achieved by reducing the affinity of the trapped magnetic flux to at least one structure by decreasing the margin; and providing a magnetic field to cause the trapped magnetic flux to reposition.

[0192] The method may further include receiving feedback from at least one superconducting quantum interference device (SQUID) sensor to track the progress of magnetic flux sweeping, wherein the superconducting integrated circuit is associated with a plurality of control lines configured to generate a timing sequence of a plurality of pulses that generate a magnetic field and alter the operating margin of at least one structure subjected to magnetic flux trapping relative to a critical state. The application includes sequencing control current pulses according to the at least one SQUID sensor to locally sweep the magnetic flux trapped in at least one structure. This is achieved by: reducing the affinity of the trapped magnetic flux for at least one structure by decreasing the margin; and providing a magnetic field to cause the trapped magnetic flux to reorient towards at least one of the periphery of the superconducting integrated circuit and a flux discharge region configured to trap the magnetic flux from the superconducting device on the superconducting integrated circuit.

[0193] Another objective is to provide a superconducting circuit system comprising: an integrated circuit including a plurality of superconducting devices and at least one structure configured to trap magnetic flux; a plurality of control lines configured to generate heat and a magnetic field that alters the pinning of the trapped magnetic flux to the structure and generates a Lorentz force to reposition the magnetic flux; and a control device configured to generate a timing sequence of control current pulses in the control lines, the timing sequence of the control current pulses being adapted to reduce the pinning of the magnetic field to the structure and to sweep the trapped magnetic flux away from the structure using the generated Lorentz force. Attached Figure Description

[0194] Figures 1A to 1D Conceptual diagrams of several preferred embodiments of the flux sweeper assembly are shown.

[0195] Figure 1A A cross-sectional view of the control line located above the superconducting circuit is shown.

[0196] Figure 1B The control lines on the back of the superconducting IC chip are shown.

[0197] Figure 1C The control lines are shown on a separate chip bonded to a superconducting IC chip in a flip-chip manner.

[0198] Figure 1D It shows Figure 1A A top view showing the control lines positioned above a portion of the superconducting IC.

[0199] Figure 2 The relative orientations of the control current, vortex field, and transverse Lorentz force acting on the vortex or antivortex are shown.

[0200] Figure 3 It shows Figure 1A A conceptual diagram of the timing of the control current in the configuration, which is configured to sweep away magnetic vortices from the center of the superconducting IC.

[0201] Figure 4 A diagram showing the installation on a cryogenic cooler. Figure 1A A sectional view.

[0202] Figure 5A A top view of the control line array above the superconducting chip is shown, which also shows... Figure 2 A sequence of current pulses.

[0203] Figure 5B A top view of an alternative 2D configuration of the control lines is shown, which vortexes across all four edges of the chip.

[0204] Figures 6A to 6E Several alternative designs for the control lines are shown, which may include lines with separate designs for heat and magnetic field generation.

[0205] Figure 7 A block diagram of a programmable 20-channel current source is shown. Detailed Implementation

[0206] This technology can be used to remove trapped flux from the device regions of superconducting integrated circuits. This is achieved through flux sweeping structures that combine thermal and magnetic gradients to reduce trapped flux pinning at a location and sweep the trapped flux into flux discharge regions spaced apart on the die surface or sweep it out of the integrated circuit entirely.

[0207] This process aims to reduce the required magnetic shielding by four orders of magnitude to achieve vortex-free operation of superconducting integrated circuits. Implementations of this technology encompass the design, testing, and verification of on-chip or bonded active flux management, through which pinned vortices can migrate out of active circuit regions and / or be collected in flux-discharging regions where coupling with on-chip superconducting electronics is negligible. This goal is achieved by integrating a dedicated network of control lines, including heating wires, capable of generating localized thermal and electromagnetic gradients to move trapped vortices while the superconducting circuitry remains cooled below its critical temperature.

[0208] The design of the current pulse sequence is guided by modeling vortex dynamics within multilayer Nb and NbN superconducting films, which can be extended to other superconducting materials. This performance is validated using on-chip SQUID sensors. These SQUID sensors also serve as sensitive on-chip temperature monitors, tracking the density and movement of vortices on the chip before, during, and after flux sweeping to optimize the design of the heating network, as well as the thermal and magnetic gradient waveforms.

[0209] This completely solves the flux trapping problem, in stark contrast to common methods that mitigate flux trapping through various layout designs filled with isolation trenches and heavy shielding methods that compromise circuit density and overall cryogenic system complexity. This invention provides a highly practical and scalable technique for in-situ removal of trapped magnetic vortices from active superconducting circuit regions. Scalable thermal and magnetic gradient vortex control integrated circuits enable reliable, predictable, and stable operation of superconducting electronics (SCE) circuits, regardless of their type, design, or application. It also significantly simplifies SCE cryogenic systems by reducing the required magnetic shielding by four orders of magnitude (from one million to approximately 100) and ensures vortex-free operation of electronics on multilayer superconducting integrated circuits. This improvement significantly reduces the space occupied by shielding infrastructure and isolation trenches, freeing up chip space for higher integration density. This technique further improves the reliability of SCE operation by reducing SCE test time by eliminating the need for multiple time-consuming flux de-warm-ups with unpredictable results.

[0210] On the other hand, it includes a SQUID test structure for monitoring on-chip vortex behavior, which provides data on density and movement before, during, and after the application of flux management techniques, as well as during single flux quantum (SFQ) circuit operation. This ensures accurate model-hardware correlation under the precise environmental and shielding conditions under which SCE circuits typically operate. The SQUID test structure, along with the thermal and magnetic sensors, can be the same or different devices.

[0211] A preferred embodiment involves positioning the SQUID near the edge of the flux discharge region isolation slot to measure the magnetic coupling effect of trapped flux quanta on the SQUID loop. The SQUID is capable of measuring as few as a single flux quantum as well as up to hundreds of flux quanta in the flux discharge region.

[0212] These monitoring SQUIDs can also be used for real-time temperature monitoring to provide immediate and accurate feedback on the thermal environment within the superconducting film, due to the critical current of the Josephson junction in the SQUID. exist T c The surrounding area exhibits a strong temperature dependence. By measuring the self-inductance of each squid, they can be used for real-time temperature measurement. Furthermore, various squids with different self-inductances will be installed around the isolation tanks in each flux discharge zone. This strategy of utilizing multiple squids with different self-inductances improves measurement accuracy. T c The accuracy of nearby temperature changes.

[0213] Various other temperature measurement techniques can also be used. For example, the thermistor Josephson junction. See also: Zgirski M., Marek Foltyn, Alexander Savin, K. Norowski, Matthias Meschke and J. Pekola, “Nanosecond thermometry with Josephson junctions”, Physical Review Applied, Vol. 10, No. 4 (2018): 044068.

[0214] Wang LB, OP. Saira and JP Pekola, “Fast thermometry with aproximity Josephson junction”, Applied Physics Letters, Vol. 112, No. 1 (2018).

[0215] Soulen RJ, W.E. Fogle, and JH. Colwell, “Measurements of absolute temperature below 0.75 K using a Josephson-junction noise thermometer,” Journal of Low Temperature Physics, Vol. 94 (1994): 385–487.

[0216] Giazotto Francesco and María José Martínez-Pérez, “The Josephson heatinterferometer,” Nature, Vol. 492, No. 7429 (2012): 401-405.

[0217] Durandetto Paolo and Andrea Sosso, “Using a Josephson junction as an effective on-chip temperature sensor,” Superconductor Science and Technology, Vol. 34, No. 4 (2021): 045008.

[0218] Martinoli Piero and Chris Leemann, “Two dimensional Josephson junction arrays”, Journal of Low Temperature Physics, Vol. 118 (2000): 699-731.

[0219] Fox Anna E., Evan B. Golden, Paul D. Dresselhaus and Samuel P. Benz, “On-chip temperature distribution of Josephson voltage standard devices”, IEEE Transactions on Applied Superconductivity, Vol. 27, No. 4 (2016): pp. 1-5.

[0220] Proper calibration of the SQUID (or other temperature sensor) for both magnetic field and temperature enables automated program control of the flux sweep control current and the entire process, which can be repeated multiple times if necessary.

[0221] Automatic control can be self-contained within an integrated SCE IC, or controlled off-chip by another chip within the cryostat or by room temperature (RT) electronics located outside the cryostat. In the case of on-chip control, the sensor (e.g., a SQUID) interfaces with circuitry that determines the local temperature or the relationship between the thermal conditions of the corresponding SQUID and a threshold. A set of gates is configured to process the thermal measurement data and control the initiation and sequence of the flux sweep process. On the other hand, in off-chip implementations, and especially in the case of using RT electronics, the process can be implemented using computer software, which generally benefits from higher computational complexity and more sophisticated SCE operating models. However, transmitting information from or even within the cryostat introduces various penalties.

[0222] When managing trapped flux, it is generally desirable to sweep the flux to flux traps (e.g., isolation trenches) on the periphery of the IC. However, it is also possible to sweep the flux away from the IC die, for example, to an adjacent die that can be swept along the IC plane. x shaft or y axis or along z The axis is adjacent to the adjacent IC. In the latter case, it is advantageous to sweep the captured flux outside the periphery of the active IC, but within the region of the larger flux sweep IC.

[0223] In some cases, closed-loop feedback systems can operate to detect trapped flux and bring it to zero by selectively cancelling it. This does not directly remove the flux or its effect on adjacent circuitry, but rather exerts a force by the cancelling / balancing current and the corresponding flux, which reduces the stability of the trapped flux at its location and increases the tendency for the trapped flux to migrate along permissible paths to locations less affected or unaffected by the opposite influence. Therefore, the control signal can include not only the line carrying the current for Joule heating and / or the magnetic field generated around that line, but also current-carrying loops. These loops can be in the plane of the SCE IC or include loops along... z Current flows along the axis, for example, through the solder bumps and through adjacent ICs. Advantageously, the solder bumps can be non-superconducting and therefore dissipative. This will help reduce trapped flux in the sweep circuit itself.

[0224] In a typical scenario, when a sweep operation is triggered, a predetermined sequence, specific to the location on the SCE IC, is initiated. This sequence includes a specified line, current, and duration. At the end of the cycle, temperature and magnetic field can be measured, and a new cycle begins based on the initial conditions. The flux sweep process can be localized and adaptive within a region of the SCE IC, minimizing disruption to SCE operation. For example, a non-adaptive sweep might employ a relatively large thermal load to heat most of the SCE IC to 9°K, sweeping all trapped flux toward peripheral flux-tolerant structures of the sensitive SCE circuitry, away from the IC center. On the other hand, if trapped flux is detected only on a small portion of the SCE IC, the sweep operation might only require heating the path across the IC toward the peripheral isolation trench, while leaving the remaining portions of the IC without trapped flux unaffected, undisturbed, or minimally disturbed. This, in turn, allows the affected structures to cool back to operating temperature more quickly and applies a reduced thermal load to the cryogenic cooler.

[0225] The current required to drive the control line can be generated by a superconducting amplifier. See US 5,936,458, US 2023 / 0363292, US 202 / 30359915, US 11,804,275, US 11,730,066, US 11,533,032, US 11,411,159, US 10,491,178, US 7,724,083, US 2008 / 0290938, US 2008 / 0048762, US 6,917,216 and US 6,486,756.

[0226] The initial and subsequent cycles do not need to be identical, and in fact, due to the localized Joule heating and thermal diffusion of the SCE IC, subsequent cycles will typically have different heating currents. On the other hand, because the starting state of the SCE may differ, having a single cycle designed to complete the sweep may result in an excessive amount of basic process required, leading to an increased delay before the SCE temperature drops to normal operating conditions. It should be noted that the thermal sensor on the SCE can be used not only to initiate and control the sweep cycle but also to indicate that the SCE is ready for normal operation.

[0227] In some cases, the sweep cycle and the resulting thermal effects are confined to a portion of the SCE IC, and in practice, when the SCE IC comprises multiple redundant circuits (cores), processing operations on one portion of the SCE IC can occur simultaneously with the sweep of throughput on other portions of the SCE IC. In such cases, the SCE typically includes multiplexers to distribute signals and tasks to different cores. Similarly, the SCE IC may have multiple different functions, and it is not necessary to interrupt all of these functions when a sweep process is initiated or performed on a portion of the SCE IC.

[0228] When the process is optimized, the conventional requirements for passive or active magnetic shielding can be significantly relaxed. The Earth's magnetic field is approximately 50 μT, and it is easily reduced to less than 1 μT using conventional passive magnetic shielding (such as μ metals). This is still too high for the operation of sensitive single-flux quantum (SFQ) logic circuits, superconducting qubits, and superconducting sensor arrays (such as SQUIDs and superconducting microbolometers), but this invention provides a method to reduce the effective magnetic field by up to six orders of magnitude by sweeping away trapped magnetic flux in the active region of a superconducting integrated circuit.

[0229] In another embodiment, the flux sweeping process can be used to compensate for external fields. That is, the goal in this case is not to sweep the flux so that the residual flux from the trapped vortex is zero, but to establish a normalized field on the SCE IC that compensates for distortion. In this case, in the presence of an external or uncontrolled magnetic field, the flux can be swept to a specific isolation slot and maintained at a controlled level to establish the desired field conditions. In most cases, the desired field conditions will be a net field close to zero. However, in the case of junction arrays, it may be desirable to establish a varying magnetic field, such as a linearly varying field. The present invention allows for control of the local magnetic field and local temperature on the SCE IC, both of which change relatively rapidly during SCE operation. Therefore, the application of this technique is not limited to removing trapped flux.

[0230] Figures 1A to 1D Several alternative configurations are shown for integrating current-controlled line arrays close to the superconducting circuitry. Figure 1A and Figure 1D In this method, control lines can be deposited directly on top of the superconducting circuit, with only a thin insulating layer (such as silicon dioxide) between them. Alternatively, in some cases, it may be preferable to avoid damaging the superconducting IC or to keep the optical path at the front end of the IC unobstructed. In this case, Figure 1BAnother approach shown is to place the control lines on the back of the IC, but still close enough from both thermal and magnetic perspectives to achieve complete flux sweep from the IC. In other cases, it may be preferable to place the control current lines on a separate chip, where the control chip and the IC chip are mounted in a flip-chip geometry, such as... Figure 1C As shown, an array of solder bump joints (as known in the prior art) holds two chips together.

[0231] Figure 2 The geometry of the transverse force on a magnetic vortex caused by an electric current is shown. For a current pointing upwards (northwards) on the page and a vortex field perpendicular to the page, the Lorentz force pushes the vortex to the left. Reversing the direction of the current or field (“anti-vortex”) will reverse the direction of the force. In most cases, the residual magnetic field will have a single direction reflecting the residual Earth's magnetic field, but this method is general enough to handle arbitrary directions of flux, or even non-uniform flux directions.

[0232] Figure 3 The key steps of the flux sweep process are presented, with snapshots at sequential times T1, T2, T3, and T4. The process begins (T1) with currents at the center of the chip (the two lines labeled H1), which heat the central region of the superconducting circuit to near a temperature Tc and also exert a transverse Lorentz force on the trapped vortices, tending to move them away from the center and toward the two edges. If we assume here that the magnetic flux is pointing upwards, the left line H1 will have a current pointing outwards (pushing the vortices to the left), while the right line H1 will have the same current pointing inwards (pushing the vortices to the right). In the second time step shown (T2), the vortices have partially moved toward the edges on both sides, and the subsequent control currents (H2) are activated. They tend to push the vortices further out, as shown in the snapshot at time T3. By time T4, the vortices are below line H4, beyond the functional superconducting circuit (here labeled the SFQ circuit), and the central current in H1 can be turned off, thus cooling that part of the chip. This is the area marked "superconducting ground plane," and once the vortices traverse this area (driven by the current in H5), they will terminate in the "flux discharge regions" on the left and right. After this, all driving currents can be turned off, and the vortices will be trapped in the flux discharge regions, away from the active circuitry.

[0233] Figure 4Another problem addressed is how to remove heat from the chip due to the control current. In one implementation, the chip can be immersed in liquid helium, but in another implementation presented here, the chip is in a vacuum and cooled via a cooling stage mounted on a closed-loop refrigerator (also known as a cryocooler). Given that the substrate is typically monocrystalline silicon (which is a good thermal conductor at low temperatures), the cryocooler keeps the substrate cooled to approximately 4K, which limits the diffusion of localized hot spots from the control current.

[0234] In some other applications, such as quantum computing or certain sensor systems, cryogenic coolers may include dilution refrigerators that cool superconducting circuits to temperatures below 1 K.

[0235] Figure 5A and Figure 5B A top view shows two alternative configurations of control lines for superconducting chips, typically a few millimeters wide, with electrical contacts around the edges. Figure 5A It shows the relationship with Figure 3 A consistent set of parallel control lines, in which a sequence of current pulses forces trapped vortices to reach the flux discharge regions on the left and right sides of the chip. Figure 5B A set of 2D control lines is shown that tend to push the vortex from the center to the flux discharge areas on the four sides of the chip.

[0236] at last, Figures 6A to 6E Several designs for the control lines used in the flux sweeper are shown. Black represents normal metal heating / magnetic lines, and white represents superconducting magnetic lines. Figure 6A The black line in the diagram represents the simple, general line described earlier, namely the normal (non-superconducting) line that generates both heat and magnetic fields. Figure 6B and Figure 6C This indicates a side tab for more efficient heat transfer. Figure 6D The diagram shows two separately optimized lines: the black line represents heating, and the white line represents magnetic field generation. In this alternative, the field generation line can be superconducting, thus generating no heat. The heater line can be driven by current of any polarity, AC current, or a fast pulse sequence. Figure 6E As shown Figure 6B and Figure 6C The image shows a protrusion, and two separately optimized lines are shown: the black line represents heating, and the white line represents magnetic field generation, as shown. Figure 6D As shown. The heating wires will also generate a magnetic field, but their effect is negligible.

[0237] like Figure 7 As shown, a separate programmable current source can be used to allow flux sweep operations to be performed using dedicated pads on the SCE IC. This frees up all standard chip pads for controlling the SFQ circuitry and the SQUID sensor.

[0238] This disclosure has been described with reference to various specific implementations and techniques. However, many variations and modifications are possible while remaining within the scope of this disclosure.

[0239] The claims in this document define certain combinations and sub-combinations of elements, features, and steps or operations that are considered novel and non-obvious. Additional claims for other such combinations and sub-combinations may be set forth in this or related documents. These claims are intended to cover, within their scope, all changes and modifications to the true nature and scope of the subject matter described herein.

Claims

1. A system for sweeping trapped magnetic flux from a superconducting integrated circuit on a chip operating at a low temperature, the system comprising: A superconducting integrated circuit, the superconducting integrated circuit comprising a plurality of superconducting devices and at least one structure subjected to magnetic flux trapping; and Multiple control lines are configured to generate a timing sequence of control current pulses, which generate a magnetic field and change the operating margin of at least one structure subjected to magnetic flux trapping relative to a critical state. The sequence of control current pulses is adapted to locally sweep away magnetic flux trapped in the at least one structure, which is achieved by reducing the affinity of the trapped magnetic flux to the at least one structure by decreasing the margin; and by providing a magnetic field to cause the trapped magnetic flux to reposition.

2. The system of claim 1, wherein the control line is deposited above the superconducting integrated circuit.

3. The system of claim 1, wherein the control line is deposited on the side of the chip opposite to the superconducting integrated circuit.

4. The system of claim 1, wherein the control line is deposited on a separate chip from the chip having the superconducting integrated circuit, wherein the separate chip is mounted on the chip having the superconducting integrated circuit using a flip-chip bonding configuration.

5. The system of claim 1, wherein the sequence of control current pulses is first applied to a control line in the central portion of the superconducting integrated circuit, and subsequently applied to the peripheral region of the superconducting integrated circuit to move outward toward the edge of the superconducting integrated circuit.

6. The system of claim 1, wherein the control current pulse is configured to reduce the margin by locally heating the superconducting device to a temperature close to but not exceeding the critical temperature of the superconducting device.

7. The system of claim 6, wherein the control pulse is further configured to provide the magnetic field to generate a magnetic force on the trapped magnetic flux sufficient to remove the trapped magnetic flux from the superconducting device.

8. The system of claim 1, wherein the control current pulse is adapted to remove the trapped magnetic flux from the superconducting device by transferring the trapped magnetic flux to one or more magnetic flux discharge regions located away from the superconducting device.

9. The system of claim 1, further comprising a control circuit configured to generate the sequence of control pulses, wherein the sequence of control pulses has a predefined sequence, and the control circuit is configured to continuously generate a plurality of the predefined sequences.

10. The system of claim 1, wherein the control line comprises a resistive metal thin film optimized for heat generation and is configured to generate heat on the superconducting integrated circuit by Joule heating.

11. The system of claim 10, wherein the control line comprises at least one of titanium-palladium and molybdenum nitride.

12. The system of claim 1, wherein the control line comprises a superconducting thin film optimized for magnetic field generation.

13. The system of claim 12, wherein the control line comprises at least one of niobium, niobium nitride, and aluminum.

14. The system of claim 1, wherein the at least one structure subjected to magnetic flux trapping is subjected to an external magnetic field, and the sequence of control current pulses is adapted to reduce the effective magnetic field in the at least one structure by at least three orders of magnitude.

15. The system of claim 1, wherein the superconducting device comprises a superconducting quantum bit.

16. The system of claim 1, wherein the superconducting device comprises a single-flux quantum logic circuit.

17. The system of claim 1, wherein the superconducting device comprises a superconducting sensor that responds to at least one of temperature and magnetic field.

18. The system of claim 1, further comprising a plurality of superconducting quantum interference device (SQUID) sensors configured to perform at least one of detecting trapped magnetic flux and monitoring sweeping of said magnetic flux.

19. The system of claim 1, further comprising a control circuit configured to generate the control current pulse.

20. The system of claim 1, wherein the sequence of control current pulses comprises at least one pulse having an intensity or duration that varies according to the amount of captured flux.

21. The system of claim 1, further comprising a control circuit, a plurality of independently operable control lines, and at least one magnetic field sensor associated with each set of control lines, wherein each set of control lines disposed on a corresponding portion of the chip is operated by the control circuit according to the associated at least one magnetic field sensor.

22. A method for sweeping trapped vortices from a chip including a superconducting integrated circuit, the method comprising: Operating the superconducting integrated circuit at low temperatures; as well as At least one current pulse is applied, the at least one current pulse being adapted to heat a region of the superconducting integrated circuit to near the superconducting critical temperature, thereby weakening the binding of the trapped vortex to the region, and simultaneously generating a magnetic field gradient in the region sufficient to sweep the trapped vortex with weakened binding from the region.

23. The method according to claim 22, further comprising: Feedback is received from at least one superconducting quantum interference device (SQUID) sensor to track the progress of sweeping the trapped vortex. The superconducting integrated circuit is associated with multiple control lines configured to generate a timing sequence of multiple current pulses that generate a magnetic field gradient and alter the operating margin of at least one structure in the region subjected to vortex trapping relative to a critical state. The application includes sequencing the plurality of current pulses according to feedback from the at least one superconducting quantum interference device (SQUID) sensor to locally sweep away the trapped vortices in the at least one structure. This is achieved by reducing the affinity of the trapped vortices for the at least one structure by decreasing the margin; and by providing the magnetic field gradient to cause the trapped vortices to reposition toward at least one of the periphery of the superconducting integrated circuit and a flux discharge region configured to keep the swept vortices away from the at least one structure.

24. A superconducting circuit system, the superconducting circuit system comprising: An integrated circuit, the integrated circuit comprising a plurality of superconducting devices and at least one structure configured to trap vortices; Multiple control lines are configured to generate heat and magnetic fields, which alter the pinning of the trapped vortex in at least one structure and generate Lorentz force to reposition the trapped vortex. and A control device configured to generate a timing sequence of control current pulses in the plurality of control lines, the timing sequence of the control current pulses being adapted to reduce the pinning of the trapped vortex to the at least one structure and to use the generated Lorentz force to sweep the trapped vortex from the at least one structure.

25. A system for sweeping trapped vortices from a superconducting integrated circuit on a chip operating at a low temperature, the system comprising: A superconducting integrated circuit, the superconducting integrated circuit comprising a plurality of superconducting devices and at least one structure subjected to vortex trapping; and Multiple control lines are configured to generate a timing sequence of control current pulses that generate a magnetic field and alter the operating margin of the at least one structure subjected to vortex trapping relative to a critical state. The sequence of control current pulses is adapted to locally sweep away the trapped vortices from the at least one structure by reducing the affinity of the trapped vortices to the at least one structure by decreasing the margin; and by providing the magnetic field to induce the trapped vortices to reposition.

26. The system of claim 25, wherein the control line is located on the chip above the superconducting integrated circuit.

27. The system of claim 25, wherein the control line is located on the back side of the chip opposite to the superconducting integrated circuit.

28. The system of claim 25, wherein the control line is on a separate chip separate from the superconducting integrated circuit chip, wherein the separate chip is mounted on the superconducting integrated circuit chip using a flip-chip bonding configuration.

29. The system of claim 25, wherein the control lines are present in the following locations: The area near the center of the superconducting integrated circuit, the area near the outer edge of the superconducting integrated circuit, and the area between the center and the outer edge of the superconducting integrated circuit.

30. The system of claim 29, wherein the sequence of control current pulses is first applied to a control line in the central portion of the superconducting integrated circuit, and the sequence moves outward sequentially toward the edge of the superconducting integrated circuit.

31. The system of claim 25, wherein the control current pulse is configured to reduce the margin by locally heating the superconducting device to a temperature close to but not exceeding the critical temperature of the superconducting device.

32. The system of claim 31, wherein the control pulse is further configured to provide the magnetic field to generate a magnetic force on the trapped magnetic flux sufficient to remove the trapped magnetic flux from the superconducting device.

33. The system of claim 25, wherein the control current pulse is adapted to remove the trapped magnetic flux from the superconducting device by discharging the trapped magnetic flux from the chip.

34. The system of claim 25, wherein the control current pulse is adapted to remove the trapped magnetic flux from the superconducting device by transferring the trapped magnetic flux to one or more magnetic flux discharge regions located away from the superconducting device.

35. The system of claim 25, wherein the control line is configured to generate heat on the superconducting integrated circuit via Joule heating.

36. The system of claim 35, wherein the control line comprises a resistive metal thin film optimized for heat generation.

37. The system of claim 25, wherein the control line comprises a superconducting thin film optimized for magnetic field generation.

38. The system of claim 25, wherein the superconducting device comprises a superconducting quantum bit.

39. The system of claim 25, wherein the superconducting device comprises a single-flux quantum logic circuit.

40. The system of claim 25, wherein the superconducting device comprises a Josephson junction.

41. The system of claim 40, wherein the superconducting integrated circuit comprises at least 100,000 Josephson junctions.

42. The system of claim 40, wherein the superconducting integrated circuit comprises at least one million Josephson junctions.

43. The system of claim 25, wherein the superconducting device comprises a superconducting sensor.

44. The system of claim 25, wherein the superconducting device comprises a superconducting quantum interference device sensor.

45. The system of claim 25, wherein the superconducting device comprises a superconducting quantum interference filter sensor.

46. ​​The system of claim 25, further comprising a plurality of superconducting quantum interference devices (SQUIDs) sensors configured to detect the trapped magnetic flux.

47. The system of claim 25, further comprising a plurality of superconducting quantum interference device (SQUID) sensors configured to monitor the sweeping of magnetic flux.

48. The system of claim 25, further comprising a plurality of superconducting quantum interference device (SQUID) sensors configured to monitor sweeping magnetic flux, including monitoring magnetic field strength and temperature.

49. The system of claim 48, wherein the control current pulse is applied under feedback control based on the superconducting quantum interference device (SQUID) sensor.

50. The system of claim 49, further comprising a control circuit configured to generate the control current pulse.

51. The system of claim 49, wherein the control circuitry is located on the chip.

52. The system of claim 49, wherein the control circuit is located in the superconducting integrated circuit.

53. The system of claim 49, wherein the control circuit is located in an integrated circuit adjacent to the superconducting integrated circuit.

54. The system of claim 49, wherein the control circuitry is implemented by logic components that operate at room temperature.

55. The system of claim 49, wherein the control circuitry depends on feedback.

56. The system of claim 25, wherein the sequence of control current pulses is applied sequentially multiple times to successively reduce the captured flux.

57. The system of claim 25, wherein the sequence of control current pulses includes at least one pulse having an intensity that varies according to the amount of captured flux.

58. The system of claim 25, wherein the sequence of control current pulses includes at least one pulse having a duration that varies according to the amount of captured flux.

59. The system of claim 25, further comprising a plurality of independently operable control lines and at least one magnetic field sensor associated with each set of control lines, each set of control lines being disposed on a corresponding portion of the chip, wherein the control lines of the corresponding set are operated by a control circuit according to at least one corresponding magnetic field sensor.

60. A method for sweeping trapped flux from a chip including a superconducting integrated circuit, the method comprising: Operating the superconducting integrated circuit at low temperatures; At least one first current pulse is applied, the at least one first current pulse being adapted to heat a first region of the superconducting integrated circuit to near the superconducting critical temperature to reduce the binding of magnetic flux with the first region, and simultaneously generate a magnetic field gradient in the first region sufficient to sweep away the magnetic flux with reduced binding.

61. The method of claim 60, wherein the magnetic flux is swept to the periphery of the superconducting integrated circuit.

62. The method of claim 60, wherein the at least one first current pulse comprises a plurality of pulses adapted to sequentially sweep the magnetic flux toward the periphery of the superconducting integrated circuit.

63. The method of claim 60, further comprising sweeping the magnetic flux to at least one flux discharge region, the at least one flux discharge region being configured to capture the magnetic flux from the superconducting device on the superconducting integrated circuit.

64. The method of claim 60, further comprising receiving feedback from at least one superconducting quantum interference device (SQUID) sensor to track the progress of magnetic flux sweeping.

65. The method of claim 60, wherein the superconducting integrated circuit comprises a superconducting quantum bit.

66. The method of claim 60, wherein the superconducting integrated circuit comprises a single-flux quantum logic circuit.

67. The method of claim 60, wherein the superconducting integrated circuit comprises a Josephson junction.

68. The method of claim 60, wherein the superconducting integrated circuit comprises at least 100,000 Josephson junctions.

69. The method of claim 60, wherein the superconducting integrated circuit comprises at least one million Josephson junctions.

70. The method of claim 60, wherein the superconducting integrated circuit comprises a superconducting sensor.

71. The method of claim 60, wherein the superconducting integrated circuit comprises a superconducting quantum interference device sensor.

72. The method of claim 60, wherein the superconducting integrated circuit comprises a superconducting quantum interference filter sensor.

73. The method of claim 60, wherein the superconducting integrated circuit is associated with a plurality of control lines configured to generate a timing sequence of control current pulses, the control current pulses generating a magnetic field and altering the operating margin of at least one structure subjected to magnetic flux trapping relative to a critical state. The application includes sequencing the control current pulses to locally sweep away the magnetic flux trapped in the at least one structure, which is achieved by reducing the affinity of the trapped magnetic flux to the at least one structure by decreasing the margin; and providing a magnetic field to cause the trapped magnetic flux to reposition.

74. The method of claim 73, wherein the control line is located on the chip above the superconducting integrated circuit.

75. The method of claim 73, wherein the control line is located on the back side of the chip.

76. The method of claim 73, wherein the control line is on a separate chip separate from the superconducting integrated circuit, wherein the separate chip is mounted on the superconducting integrated circuit using a flip-chip bonding configuration.

77. The method of claim 73, wherein the control lines are present near the central portion of the superconducting integrated circuit, near the outer edge of the superconducting integrated circuit, and in the region between the central portion and the outer edge of the superconducting integrated circuit.

78. The method of claim 77, wherein the sequence of control current pulses is first applied to a control line in the central portion of the superconducting integrated circuit, and the sequence is subsequently moved outward toward the edge of the superconducting integrated circuit.

79. The method of claim 73, wherein the control current pulse reduces the margin by locally heating the superconducting device to a temperature close to but not exceeding the critical temperature of the superconducting device.

80. The method of claim 79, wherein a control pulse provides the magnetic field to generate a magnetic force on the trapped magnetic flux sufficient to remove the trapped magnetic flux from the superconducting device.

81. The method of claim 73, wherein the control current pulse removes the trapped magnetic flux from the superconducting device by discharging the trapped magnetic flux from the chip.

82. The method of claim 73, wherein the control current pulse removes the trapped magnetic flux from the superconducting device by transferring the trapped magnetic flux to one or more magnetic flux discharge regions located away from the superconducting device.

83. The method of claim 73, wherein the control line generates heat on the superconducting integrated circuit by Joule heating.

84. The method of claim 83, wherein the control line comprises a resistive metal thin film optimized for heat generation.

85. The method of claim 73, wherein the control line comprises a superconducting thin film optimized for magnetic field generation.

86. The method of claim 73, further comprising a plurality of superconducting quantum interference device (SQUID) sensors for detecting the trapped magnetic flux.

87. The method of claim 73, further comprising a plurality of superconducting quantum interference device (SQUID) sensors for monitoring the sweeping of the magnetic flux.

88. The method of claim 73, further comprising a plurality of superconducting quantum interference device (SQUID) sensors for monitoring the sweep of the magnetic flux, including monitoring magnetic field strength and temperature.

89. The method of claim 88, wherein the control current pulse is applied under feedback control based on the superconducting quantum interference device (SQUID) sensor.

90. The method of claim 73, further comprising generating the control current pulse using a control circuit.

91. The method of claim 90, wherein the control circuit is located on the chip.

92. The method of claim 90, wherein the control circuit is located in the superconducting integrated circuit.

93. The method of claim 90, wherein the control circuit is located in an integrated circuit adjacent to the superconducting integrated circuit.

94. The method of claim 90, wherein the control circuit is implemented by logic components that operate at room temperature.

95. The method of claim 90, wherein the control circuitry depends on feedback.

96. The method of claim 73, wherein the sequence of control current pulses is applied sequentially multiple times to successively reduce the trapped flux.

97. The method of claim 73, wherein the sequence of control current pulses includes at least one pulse having an intensity that varies according to the amount of the captured flux.

98. The method of claim 73, wherein the sequence of control current pulses includes at least one pulse having a duration that varies according to the amount of the captured flux.

99. The method of claim 73, further comprising a plurality of independently operable control lines and at least one magnetic field sensor associated with each set of control lines, each set of control lines being disposed on a corresponding portion of the chip, wherein the control lines of the corresponding set are operated by a control circuit according to at least one corresponding magnetic field sensor.

100. A system for removing trapped vortices from a superconducting integrated circuit structure, the system comprising: Multiple control lines are configured to generate a timing sequence of control current pulses that generate magnetic field gradients and Joule heating to alter the trapping of vortices within the region of the superconducting integrated circuit structure. An automatic control device is configured to generate the timing sequence of control current pulses to sweep away the trapped vortices from the region, which is achieved by reducing the affinity of the trapped vortices for the structure and exposing a feasible path for the trapped flux to be repositioned to another region of the superconducting integrated circuit structure.

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