Back-to-front connections between different metal tracks

Abstract

Embodiments of the present application provide a semiconductor structure. The semiconductor structure includes a deep trench via in a single diffusion break region; a front side metal line electrically connected to a top surface of the deep trench via; and a back side metal line electrically connected to a bottom surface of the deep trench via, wherein the front side metal line and the back side metal line are parallel to each other and perpendicular to the deep trench via. A method of forming the same is also provided.

Description

Background Technology

[0001] This application relates to the manufacture of semiconductor integrated circuits. More specifically, it relates to a method for forming a back-to-front connection between different metal tracks and the structure formed therefrom.

[0002] As the semiconductor industry moves towards smaller nodes, field-effect transistors (FETs) are being aggressively miniaturized to accommodate reduced footprint or land area, typically determined by node size, and resulting in increased device density. As one approach, back-side power distribution networks (BSPDNs) have been introduced as a means to further increase device density.

[0003] For semiconductor chips with multiple front-side metal tracks in a front-side back-end process (BEOL) structure and multiple back-side metal tracks in a back-side BEOL (BBEOL) structure, communication between different metal tracks on the front and back sides is often required. For example, front-side metal layer 1 (M1) may need to communicate with back-side metal layer 1 (BM1) on the back side. When the front-side M1 and the back-side BM1 are vertically aligned, this communication can be enabled by a deep vertical via formed between the two metal layers. However, the front and back metal layers are not always vertically aligned, and in fact, they may sometimes be misaligned for various reasons. In this case, a deep vertical via may not be able to connect the front and back metal layers for communication. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor structure. The semiconductor structure includes: a deep trench via located in a single-diffusion interruption region; a front metal line electrically connected to the top surface of the deep trench via; and a back metal line electrically connected to the bottom surface of the deep trench via, wherein the front and back metal lines are parallel to each other and perpendicular to the deep trench via. The deep trench via enables communication between the front and back metal lines.

[0005] According to one embodiment, the semiconductor structure further includes a metal gate and a gate-cut dielectric layer, wherein the deep trench via is located in the width direction of the metal gate, and the gate-cut dielectric layer insulates the deep trench via from the metal gate.

[0006] According to another embodiment, the semiconductor structure further includes a first set of internal spacers and a second set of internal spacers, the first set of internal spacers directly contacting a first side of the deep trench via, and the second set of internal spacers directly contacting a second side of the deep trench via, the first side of the deep trench via being opposite to the second side of the deep trench via.

[0007] According to yet another embodiment, the semiconductor structure further includes a first source / drain (S / D) region of the first nanosheet (NS) transistor and a second S / D region of the second NS transistor, wherein the first S / D region directly contacts the first set of inner spacers and the second S / D region directly contacts the second set of inner spacers.

[0008] According to one embodiment, the semiconductor structure further includes a front via, a back via, and a back contact, wherein the front metal line is electrically connected to the top surface of the deep trench via through the front via, and the back metal line is electrically connected to the bottom surface of the deep trench via through the back via and the back contact.

[0009] In one embodiment, the back contact portion is adjacent to the shallow trench insulator (STI), which is located directly below the deep trench via and embedded in the substrate.

[0010] In another embodiment, the front metal line and the back metal line are not perpendicularly aligned, and the horizontal distance between the front metal line and the back metal line is less than the length of the deep trench via.

[0011] Embodiments of the present invention also provide a method for forming a semiconductor structure. The method includes: forming a first sacrificial gate of a first NS transistor, a second sacrificial gate of a second NS transistor, and a third sacrificial gate on a substrate; forming a first S / D region of the first NS transistor between the first and third sacrificial gates; forming a second S / D region of the second NS transistor between the second and third sacrificial gates; forming a back contact portion in the substrate below a single diffusion interruption region; forming a deep trench via in the single diffusion interruption region directly above the back contact portion, the single diffusion interruption region being located between the first S / D region of the first NS transistor and the second S / D region of the second NS transistor; forming a front metal line electrically connected to the top surface of the deep trench via; and forming a back metal line electrically connected to the bottom surface of the deep trench via.

[0012] According to one embodiment, the method further includes forming a front via that directly contacts the top surface of the deep trench via, wherein the front metal wire directly contacts the front via.

[0013] According to another embodiment, the method further includes forming a back through-hole, the back through-hole directly contacting the back contact portion, wherein the back metal wire directly contacts the back through-hole.

[0014] According to yet another embodiment, the method further includes: forming a first set of inner spacers between a first S / D region of a first NS transistor and a first side of a deep trench via; and forming a second set of inner spacers between a second S / D region of a second NS transistor and a second side of a deep trench via, wherein the first side of the deep trench via is opposite to the second side of the deep trench via.

[0015] In one embodiment, forming a back contact includes: selectively removing a third sacrificial gate and one or more nanosheets exposed by the removal of the third sacrificial gate to create a first opening between a first S / D region of a first NS transistor and a second S / D region of a second NS transistor, the first opening exposing the substrate; recessing a portion of the substrate to create a second opening in the substrate; and filling the second opening with a conductive material to form a back contact.

[0016] In another embodiment, forming a deep trench via includes filling a first opening between a first S / D region and a second S / D region with a conductive material in a single diffusion interruption region to form a deep trench via.

[0017] In yet another embodiment, forming a front metal line includes forming a front metal line in a first direction perpendicular to the deep trench via; and forming a back metal line includes forming a back metal line from the back side of the substrate in a second direction perpendicular to the deep trench via and parallel to the first direction, wherein the back metal line is not perpendicularly aligned with the front metal line.

[0018] According to one embodiment, the method further includes forming a gate-cut dielectric layer that insulates the metal gate from a deep trench via, wherein the deep trench via is located in the width direction of the metal gate. Attached Figure Description

[0019] A more complete understanding of the present invention will be achieved by reading the following detailed description of embodiments of the invention in conjunction with the accompanying drawings, wherein: Figure 1A and Figures 1B to 13A and Figure 13B This is an exemplary illustration of cross-sectional views at various steps in the fabrication of a semiconductor structure according to embodiments of the present invention, and Figures 1C to 13C This is a simplified top view of various steps in the fabrication of a semiconductor structure according to embodiments of the present invention; and Figure 14 This is an exemplary illustration of a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0020] It should be understood that, for simplicity and clarity, the elements shown in the accompanying drawings are not necessarily drawn to scale. Furthermore, and where applicable, in various functional block diagrams, two connected devices and / or elements are not necessarily shown as connected. In some other instances, the grouping of certain elements in a functional block diagram is for descriptive purposes only and does not necessarily imply that they are in a single physical entity or that they are embodied in a single physical entity. Detailed Implementation

[0021] In the following detailed description and accompanying drawings, it should be understood that the various layers, structures, and regions shown in the drawings are exemplary and schematic illustrations, and not drawn to scale. Additionally, for ease of explanation, one or more layers, structures, and regions of the type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not mean that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structure. Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, regarding semiconductor processing steps, it should be emphasized that the description provided herein is not intended to cover all processing steps that may be necessary to form functional semiconductor integrated circuit devices. Rather, descriptions of certain processing steps commonly used in forming semiconductor devices (such as, for example, wet cleaning and annealing steps) have been intentionally omitted for brevity.

[0022] It should be understood that the terms “about” or “substantially” used herein to refer to thickness, width, percentage, range, etc., mean close to or approximately, rather than exactly. For example, the terms “about” or “substantially” used herein imply that there may be minor errors, such as, for example, no more than 1% of the stated quantity. Similarly, the terms “on,” “above,” or “on top” used herein to describe the positional relationship between two layers or structures are intended to be interpreted broadly and should not be construed as excluding the presence of one or more intermediate layers or structures.

[0023] Furthermore, although various reference numerals may be used in different figures, the same or similar reference numerals are used throughout the figures to denote the same or similar features, elements, or structures. Therefore, for the sake of economy of description, detailed explanations of the same or similar features, elements, or structures may not be repeated for each figure. To avoid making the figures too crowded, the labeling of the same or similar elements in some figures may also be omitted.

[0024] Figure 1A and Figure 1B This is an exemplary illustration of different cross-sectional views during the manufacturing process of a semiconductor structure according to an embodiment of the present invention, and Figure 1C This is a simplified top view of the semiconductor structure. More specifically, Figure 1A It shows along such Figure 1C The cross-sectional view of the semiconductor structure shown by the dashed line X. In other words, Figure 1A The cross-sectional view in the image is made across the gate along the length of the gate. Figure 1B It shows along such Figure 1C The cross-sectional view of the semiconductor structure shown by the dashed line Y. In other words, Figure 1B The cross-sectional view in the image is made across the gate along the width of the gate. This is because its purpose is to show... Figure 1A and Figure 1B The position of the cross section shown, therefore Figure 1C Only key elements such as nanosheets, gates, S / D regions, and components that are formed or to be formed and whose views may be covered or exposed are selectively shown. This is to avoid... Figure 1C Too crowded, and from its source Figure 1C Where the omissions do not impede the description of embodiments of the invention, other elements such as dielectric caps, sidewall spacers, etc., are not necessarily shown; these elements are primarily referred to below. Figure 1A and Figure 1B Provided.

[0025] Similarly, Figure 2A and Figures 2B to 13A and Figure 13B This is an exemplary cross-sectional view, and Figures 2C to 13C They are respectively in similar ways Figure 1A , Figure 1B and Figure 1C The diagram shows a simplified top view of the semiconductor structure at different manufacturing steps.

[0026] Back Figure 1A , Figure 1B and Figure 1C Embodiments of the present invention provide for forming a semiconductor structure 10, exemplarily shown as including a plurality of nanosheet groups 210 on top of a semiconductor substrate 100. The semiconductor substrate 100 may include a bulk silicon (Si) substrate 101, an etch stop layer 102 on top of the Si substrate 101, and a Si layer 103 on top of the etch stop layer 102. The etch stop layer 102 may be a layer of dielectric material such as silicon dioxide (SiO2) or silicon nitride (SiN), or may be a layer of silicon germanium (SiGe) having a material composition different from that of the Si substrate 101, which may enable a selective etching process based on material etch selectivity. One or more placeholders, such as placeholder 811, may be formed in the Si layer 103. Placeholder 811 may be made of a material different from that of the Si layer 103 (e.g., a dielectric material) such that it can be selectively removed later in a selective etching process. One or more shallow trench insulators (STIs) 111 may also be formed to be embedded in the Si layer 103.

[0027] The semiconductor structure 10 may further include a plurality of sacrificial gate structures 400 on top of and covering the plurality of nanosheet groups 210. Each of the sacrificial gate structures 400 may include a sacrificial gate 401 and a gate mask 402 on top thereof. Sidewall spacers 403 may be formed at the sidewalls of the sacrificial gate 401. The semiconductor structure 10 may further include a plurality of source / drain (S / D) regions, such as a first S / D region 311, a second S / D region 312, and a third S / D region 313 formed between the plurality of nanosheet groups 210 and at their end surfaces. The plurality of S / D regions are covered by a dielectric layer 510. The dielectric layer 510 fills the space between the plurality of sacrificial gate structures 400.

[0028] Figure 2A and Figure 2B This is an exemplary illustration of different cross-sectional views during the manufacturing process of a semiconductor structure according to an embodiment of the present invention, and Figure 2C This is a simplified top view of the semiconductor structure. More specifically, following... Figure 1A , Figure 1B and Figure 1C Following the steps shown, embodiments of the invention provide the performance of gate dicing of a plurality of sacrificial gates 401. For this purpose, the gate mask 402 can be optionally removed by, for example, a chemical mechanical polishing (CMP) process. Next, one or more deep trench openings can be created across the plurality of sacrificial gates 401 in a direction perpendicular to the width direction and parallel to the length direction of the plurality of sacrificial gates 401. The one or more deep trench openings can be formed in a region vertically away from the plurality of nanosheet groups 210 and can expose one or more STI 111 in the Si layer 103. Next, embodiments of the invention provide the filling of the one or more deep trench openings with a dielectric material (e.g., SiN, SiO2, or other suitable material) to form one or more gate-dicing dielectrics, such as a first gate-dicing dielectric 321 and a second gate-dicing dielectric 322.

[0029] After forming the first gate cut dielectric 321 and the second gate cut dielectric 322, a CMP process can be applied to planarize the top surface of the semiconductor structure 10. The CMP process can also remove the gate mask 402 (if the gate mask 402 has not been previously removed), thereby exposing the plurality of sacrificial gates 401 underneath for further processing.

[0030] Figure 3A and Figure 3B This is an exemplary illustration of different cross-sectional views during the manufacturing process of a semiconductor structure according to an embodiment of the present invention, and Figure 3C This is a simplified top view of the semiconductor structure. More specifically, following... Figure 2A , Figure 2B and Figure 2CFollowing the steps shown, embodiments of the invention provide processing a single-diffusion interruption region between two S / D regions (e.g., between the first S / D region 311 and the second S / D region 312). For example, embodiments of the invention provide forming a hard mask 501 on top of the semiconductor structure 10. The hard mask 501 may be, for example, an organic planarization (OPL) layer and may be patterned to have an opening in the region between the first gate cut dielectric 321 and the second gate cut dielectric 322 exposing one of the sacrificial gates 401 between the first S / D region 311 and the second S / D region 312. For example, the exposed sacrificial gate 401 can extend to two or more nanosheet groups 210 and have a length L1 ranging from about 100 nm to about 400 nm along the width direction of the sacrificial gate 401 (see...). Figure 3B The exposed sacrificial gate 401 is then selectively removed using, for example, a selective etching process, such as reactive ion etching (RIE). Removing the exposed sacrificial gate 401 reveals or exposes two or more nanosheet groups 210 beneath it.

[0031] like Figure 3A As exemplarily shown, each of the plurality of nanosheet groups 210 may include one or more nanosheets 211. The one or more nanosheets 211 may be separated from each other by one or more sacrificial sheets 212 and one or more sidewall spacers 213 between them. The sidewall spacers 213 may also be referred to as inner spacers. Next, the exposed portions of the one or more nanosheets 211 may be removed, for example, between the first S / D region 311 and the second S / D region 312, more specifically between the two sidewall spacers 403, by one or more selective etching processes. The removal process may also remove one or more sacrificial sheets 212 between them, thereby forming an opening 410 that exposes the remaining end surfaces of the one or more nanosheets 211. The opening 410 also exposes the top surface of the Si layer 103 and one or more STIs 111 embedded therein. It should be noted here that in some embodiments, the removal process may not completely remove the bottommost sacrificial sheet 212, resulting in a small portion of the sacrificial sheet 212 remaining on top of the Si layer 103.

[0032] Figure 4A and Figure 4B This is an exemplary illustration of different cross-sectional views during the manufacturing process of a semiconductor structure according to an embodiment of the present invention, and Figure 4C This is a simplified top view of the semiconductor structure. More specifically, following... Figure 3A , Figure 3B and Figure 3CFollowing the steps shown, embodiments of the invention provide a recess or removal of the remaining portion of one or more nanosheets 211 covered by the sidewall spacers 403 to form one or more recesses or indentations. Next, the one or more recesses or indentations can be filled with a dielectric material to form one or more inner spacers 214. The one or more inner spacers 214 can be formed by, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD) processes. Together with the sidewall spacers 213 (which are also inner spacers), the one or more inner spacers 214 can insulate the first S / D region 311 and the second S / D region 312 from the deep trench vias to be formed in the opening 410, which are typically used to form a single diffusion interruption.

[0033] In one embodiment, during the process of forming one or more inner spacers 214, when removing the remainder of one or more nanosheets 211, the exposed Si layer 103 may also be further recessed to create a deeper opening 411.

[0034] Figure 5A and Figure 5B This is an exemplary illustration of different cross-sectional views of a semiconductor structure in the process of manufacturing according to an embodiment of the present invention. Figure 5C This is a simplified top view of a semiconductor structure under manufacturing according to an embodiment of the present invention. More specifically, following Figure 4A , 4B Following the steps shown in 4C, embodiments of the invention provide the removal of the hard mask 501 to expose one or more remaining sacrificial gates 401. Next, embodiments of the invention provide the performance of a replacement-metal-gate (RMG) process to form one or more metal gates of one or more nanosheet transistors. For this purpose, a selective etching process may first be applied to remove one or more remaining sacrificial gates 401 between the sidewall spacers 403; and sacrificial sheets 212 between the nanosheets 211 of the plurality of nanosheet groups 210 below the sacrificial gates 401. The removal of the sacrificial gates 401 and sacrificial sheets 212 creates one or more openings 421 that expose portions of the one or more nanosheets 211 located in the regions between the sidewall spacers 403 and between the sidewall spacers 213.

[0035] Figure 6A and Figure 6B This is an exemplary illustration of different cross-sectional views of a semiconductor structure in the process of manufacturing according to an embodiment of the present invention. Figure 6C This is a simplified top view of a semiconductor structure under manufacturing according to an embodiment of the present invention. More specifically, following Figure 5A , 5BFollowing the steps shown in 5C, embodiments of the present invention provide forming a hard mask 511 by depositing an OPL layer and patterning the OPL layer to have an opening 412. Between the first S / D region 311 and the second S / D region 312, the opening 412 may be aligned with the opening 411 along... Figure 6A The gate length directions shown are substantially aligned. In the gate width direction, opening 412 can be much narrower than opening 411, such as... Figure 6B As shown. Opening 412 may represent a pattern of the back contact portion. Opening 412 may be on top of Si layer 103 away from any STI 111, or on top of Si layer 103 but adjacent to one of STI 111, or partially on top of Si layer 103 and covering a portion of one of STI 111. Meanwhile, hard mask 511 may cover one or more exposed nanosheets 211 in one or more openings 421, thereby protecting one or more nanosheets 211.

[0036] After the hard mask 511 is formed, a portion of the Si layer 103 exposed by the opening 412 can be recessed to create the opening 413 in the Si layer 103. In one embodiment, as Figure 6B As shown, opening 413 may be between two STIs 111 and fully embedded in the Si layer 103. In another embodiment, opening 413 may be adjacent to or adjacent to one of the STIs 111, although not shown here, but exposing a portion of the sidewalls and top surface of the STI 111. In any case, opening 413 may be formed to create a back contact portion, as described in more detail below.

[0037] Figure 7A and Figure 7B This is an exemplary illustration of different cross-sectional views of a semiconductor structure in the process of manufacturing according to an embodiment of the present invention. Figure 7C This is a simplified top view of a semiconductor structure under manufacturing according to an embodiment of the present invention. More specifically, following Figure 6A , 6BFollowing the steps shown in 6C, embodiments of the present invention provide metal gates for forming one or more nanosheet transistors in a replacement metal gate (RMG) process. For example, embodiments of the present invention provide removing a hard mask 511 to expose or re-expose an opening 413 for forming a back contact; exposing or re-exposing an opening 411 for forming a deep trench via; and exposing or re-exposing the central portions of one or more nanosheets 211 of one or more nanosheet groups 210 located between sidewall spacers 403 for forming one or more metal gates. Next, a back contact 820 may be formed in the opening 413, and a deep trench via 430 for a local interconnect (LI) may be formed in the opening 411. Simultaneously or individually, one or more metal gates may be formed, such as a first metal gate 431 of a first nanosheet transistor 441, a second metal gate 432 of a second nanosheet transistor 442, and a third metal gate 433 of a third nanosheet transistor. More specifically, one or more metal gates 431, 432, and 433 can be formed by the following steps: depositing or forming a gate dielectric layer covering the exposed portions of one or more nanosheets 211; depositing or forming one or more work function metal layers on top of the gate dielectric layer; and depositing or forming one or more gate metal layers on top of the work function metal layers. Alternatively, the back contact 820 and the deep trench via 430 can be formed by depositing one or more gate metals in the openings 413 and 411.

[0038] like Figure 7A As schematically shown, the first nanosheet transistor 441 is adjacent to the left side of the deep trench via 430 via a sidewall spacer 403; the second nanosheet transistor 442 is adjacent to the right side of the deep trench via 430 via another sidewall spacer 403; and the deep trench via 430 is formed in a single-diffusion interruption region. On the other hand, the third metal gate 433 is formed to be insulated from the deep trench via 430 by the second gate-cut dielectric 322.

[0039] The back contact 820 and the deep trench via 430 can be formed of a conductive material such as, for example, tungsten (W), cobalt (Co), ruthenium (Ru), copper (Cu), aluminum (Al), or other suitable materials, to serve as local interconnects. In one embodiment, the back contact 820 may be between two STIs 111. In another embodiment, the back contact 820 may be formed adjacent to or adjacent to one of the STIs 111. In other words, the back contact 820 may be formed to be self-aligned with one of the STIs 111.

[0040] A deep trench via 430 can be formed in a single-diffusion interruption region between the first nanosheet transistor 441 and the second nanosheet transistor 442; and has a length L1 along the width of the metal gate, such as... Figure 7BAs illustrated schematically, in addition to being insulated from the first S / D region 311 and the second S / D region 312 in the width direction, the deep trench via 430 is also insulated from other gate metals in the length direction, such as from the third metal gate 433, by one or more gate-cut dielectrics (such as the second gate-cut dielectric 322).

[0041] Figure 8A and Figure 8B This is an exemplary illustration of different cross-sectional views of a semiconductor structure in the process of manufacturing according to an embodiment of the present invention. Figure 8C This is a simplified top view of a semiconductor structure under manufacturing according to an embodiment of the present invention. More specifically, following Figure 7A , 7B Following the steps shown in 7C, embodiments of the present invention provide the following: forming an additional dielectric layer (such as dielectric layer 610) on top of the semiconductor structure 10, particularly on top of the dielectric layer 510, the deep trench via 430, and one or more metal gates 431, 432, and 433; forming one or more front-side S / D contacts, such as a first front-side S / D contact 601 and a second front-side S / D contact 602; and forming one or more front-side vias, such as a first front-side via 611, a second front-side via 612, and a third front-side via 613, wherein the first front-side via 611 is in direct contact with the top surface of the partially interconnected deep trench via 430, the second front-side via 612 is in contact with the first front-side S / D contact 601, and the third front-side via 613 is in contact with the third metal gate 433.

[0042] Embodiments of the present invention also provide forming a front metal level (such as a front metal level 620) on top of the dielectric layer 610. The front metal level 620 may include a plurality of metal tracks, such as a plurality of metal lines, including a first front metal line 621 and a second front metal line 622, oriented along a first direction perpendicular or orthogonal to the length direction of the deep trench via 430. The first front metal line 621 may be electrically connected to the top surface of the deep trench via 430 through a first front via 611.

[0043] Embodiments of the present invention provide an additional metal layer or back-end-of-line (BEOL) structure 630 formed on top of the front metal layer 620. Next, a carrier wafer 710 may be attached to the BEOL structure 630 (e.g., by bonding), such that the semiconductor structure 10 can be inverted for further processing from the back side of the semiconductor substrate 100.

[0044] Figure 9A and Figure 9B This is an exemplary illustration of different cross-sectional views of a semiconductor structure during the manufacturing process according to an embodiment of the present invention, and Figure 9CThis is a simplified top view of the semiconductor structure. More specifically, following Figure 8A , Figure 8B and Figure 8C Following the steps shown, embodiments of the present invention provide selective removal of the bulk Si substrate 101 from the back side of the semiconductor substrate 100. This removal can be performed by a polishing process, a wet or dry etching process, and / or a CMP process until the etch stop layer 102 is exposed.

[0045] Figure 10A and Figure 10B This is an exemplary illustration of different cross-sectional views of a semiconductor structure during the manufacturing process according to an embodiment of the present invention, and Figure 10C This is a simplified top view of the semiconductor structure. More specifically, following Figure 9A , Figure 9B and Figure 9C Following the steps shown, embodiments of the present invention provide the removal of the etch stop layer 102 to expose the Si layer 103 by a selective etching process, and the selective removal of the Si layer 103. The removal of the Si layer 103 exposes: one or more embedded STIs 111; one or more placeholders, such as placeholder 811; and back contact 820.

[0046] Figure 11A and Figure 11B This is an exemplary illustration of different cross-sectional views of a semiconductor structure during the manufacturing process according to an embodiment of the present invention, and Figure 11C This is a simplified top view of the semiconductor structure. More specifically, following Figure 10A , Figure 10B and Figure 10C Following the steps shown, embodiments of the invention provide depositing dielectric material to form a dielectric layer 810 replacing the removed Si layer 103, and subsequently applying a CMP process to planarize the top surface of the dielectric layer 810 until the occupant 811 is exposed.

[0047] Figure 12A and Figure 12B This is an exemplary illustration of different cross-sectional views of a semiconductor structure during the manufacturing process according to an embodiment of the present invention, and Figure 12C This is a simplified top view of the semiconductor structure. More specifically, following Figure 11A , Figure 11B and Figure 11CFollowing the steps shown, embodiments of the invention provide the removal of the occupier 811 in a selective etching process to create an opening on the bottom surface exposing the third S / D region 313; the opening is then filled with a conductive material such as W, Co, Ru, Cu, Al, or other suitable materials, thereby forming the backside S / D contact 821. Next, a CMP process can be applied to recess the dielectric layer 810 until the backside contact 820 is exposed.

[0048] Figure 13A and Figure 13B This is an exemplary illustration of different cross-sectional views of a semiconductor structure during the manufacturing process according to an embodiment of the present invention, and Figure 13C This is a simplified top view of the semiconductor structure. More specifically, following Figure 12A , Figure 12B and Figure 12C Following the steps shown, embodiments of the present invention provide forming a dielectric layer 830 on top of the backside S / D contact 821, the backside contact 820, and the dielectric layer 810; forming one or more backside vias, such as a first backside via 831 and a second backside via 832. The first backside via 831 is in direct contact with the backside contact 820, and the second backside via 832 is in direct contact with the backside S / D contact 821.

[0049] Embodiments of the present invention also provide forming a back metal layer, such as a back metal layer 840, on top of the dielectric layer 830. The back metal layer 840 may include a plurality of metal tracks, such as a plurality of metal lines, including a first back metal line 841 oriented along a second direction perpendicular or orthogonal to the length direction of the deep trench via 430. In other words, the first front metal line 621 and the first back metal line 841 may be parallel to each other. In one embodiment, the first front metal line 621 is not perpendicularly aligned with the first back metal line 841, and the horizontal distance L2 between the first front metal line 621 and the first back metal line 841 may be less than the length L1 of the deep trench via 430.

[0050] Embodiments of the present invention also provide forming an additional back metal layer or a back BEOL (BBEOL) structure 850 on top of the back metal layer 840, thereby forming a semiconductor structure 10.

[0051] Figure 14This is an exemplary illustration of a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. The method includes: (910) forming a first sacrificial gate of a first nanosheet (NS) transistor, a second sacrificial gate of a second NS transistor, and a third sacrificial gate on a substrate; (920) forming a first source / drain (S / D) region of the first NS transistor between the first sacrificial gate and the third sacrificial gate; (930) forming a second S / D region of the second NS transistor between the second sacrificial gate and the third sacrificial gate; (940) forming a back contact in the substrate below a single diffusion interruption region; (950) forming a deep trench via directly above the back contact in the single diffusion interruption region between the first S / D region of the first NS transistor and the second S / D region of the second NS transistor; (960) forming a front metal line electrically connected to the top surface of the deep trench via; and (970) forming a back metal line electrically connected to the bottom surface of the deep trench via.

[0052] Various examples can be described by one or more of the following features from the following numbered clauses: Clause 1: A semiconductor structure comprising: a deep trench via in a single diffusion interruption region; a front metal line electrically connected to a top surface of the deep trench via; and a back metal line electrically connected to a bottom surface of the deep trench via, wherein the front metal line and the back metal line are parallel to each other and perpendicular to the deep trench via.

[0053] Clause 2: The semiconductor structure of Clause 1 further includes a metal gate and a gate-cut dielectric layer, wherein the deep trench via is in the width direction of the metal gate, and the gate-cut dielectric layer insulates the deep trench via from the metal gate.

[0054] Clause 3: The semiconductor structure of Clause 1 further includes a first set of internal spacers and a second set of internal spacers, wherein the first set of internal spacers is in direct contact with a first side of the deep trench via, and the second set of internal spacers is in direct contact with a second side of the deep trench via, wherein the first side of the deep trench via is opposite to the second side of the deep trench via.

[0055] Clause 4: The semiconductor structure of Clause 3 further includes a first S / D region of the first NS transistor and a second S / D region of the second NS transistor, wherein the first S / D region is in direct contact with the first set of inner spacers and the second S / D region is in direct contact with the second set of inner spacers.

[0056] Clause 5: The semiconductor structure of Clause 1 further includes a front via, a back via, and a back contact, wherein the front metal line is electrically connected to the top surface of the deep trench via through the front via, and the back metal line is electrically connected to the bottom surface of the deep trench via through the back via and the back contact.

[0057] Clause 6: The semiconductor structure of Clause 5, wherein the back contact is adjacent to the shallow trench insulator (STI), the STI is embedded in the substrate and located directly below the deep trench via.

[0058] Clause 7: A semiconductor structure of Clause 1, wherein the front metal lines are not perpendicularly aligned with the back metal lines, and the horizontal distance between the front metal lines and the back metal lines is less than the length of the deep trench via.

[0059] Clause 8: A method of forming a semiconductor structure, the method comprising: forming a first sacrificial gate of a first nanosheet (NS) transistor, a second sacrificial gate of a second NS transistor, and a third sacrificial gate on a substrate; forming a first source / drain (S / D) region of the first NS transistor between the first sacrificial gate and the third sacrificial gate; forming a second S / D region of the second NS transistor between the second sacrificial gate and the third sacrificial gate; forming a back contact in a substrate below a single diffusion interruption region; forming a deep trench via directly above the back contact in the single diffusion interruption region, the single diffusion interruption region being between the first S / D region of the first NS transistor and the second S / D region of the second NS transistor; forming a front metal line electrically connected to the top surface of the deep trench via; and forming a back metal line electrically connected to the bottom surface of the deep trench via.

[0060] Clause 9: The method of Clause 8 further includes forming a front through-hole, the front through-hole being in direct contact with the top surface of the deep trench through-hole, wherein the front metal line is in direct contact with the front through-hole.

[0061] Clause 10: The method of Clause 8 further includes forming a back through-hole, the back through-hole being in direct contact with a back contact portion, wherein the back metal wire is in direct contact with the back through-hole.

[0062] Clause 11: The method according to Clause 8 further includes forming a first set of internal spacers between the first S / D region of the first NS transistor and the first side of the deep trench via; and forming a second set of internal spacers between the second S / D region of the second NS transistor and the second side of the deep trench via, wherein the first side of the deep trench via is opposite to the second side of the deep trench via.

[0063] Clause 12: The method according to Clause 8, wherein forming the back contact comprises: selectively removing the third sacrificial gate and one or more nanosheets exposed by the removal of the third sacrificial gate to create a first opening between a first S / D region of the first NS transistor and a second S / D region of the second NS transistor, the first opening exposing the substrate; recessing a portion of the substrate to create a second opening in the substrate; and filling the second opening with a conductive material to form the back contact.

[0064] Clause 13: The method according to Clause 12, wherein forming a deep trench via comprises: filling a first opening with a conductive material between a first S / D region and a second S / D region in a single diffusion interruption region to form a deep trench via.

[0065] Clause 14: The method according to Clause 8, wherein forming the front metal line includes: forming the front metal line in a first direction perpendicular to the deep trench via; and wherein forming the back metal line includes: forming the back metal line from the back side of the substrate in a second direction perpendicular to the deep trench via and parallel to the first direction, wherein the back metal line is not perpendicularly aligned with the front metal line.

[0066] Clause 15: The method according to Clause 8 further includes forming a gate-cut dielectric that insulates the metal gate from a deep trench via, wherein the deep trench via is located in the width direction of the metal gate.

[0067] Clause 16: A semiconductor structure comprising: a first source / drain (S / D) region of a first nanosheet (NS) transistor and a second S / D region of a second NS transistor; a deep trench via in a single-diffusion interrupt region; a front metal line electrically connected to a top surface of the deep trench via; and a back metal line electrically connected to a bottom surface of the deep trench via.

[0068] Clause 17: The semiconductor structure according to Clause 16 further includes a metal gate and a gate-cut dielectric, wherein the deep trench via is located in the width direction of the metal gate, and the gate-cut dielectric insulates the metal gate from the deep trench via.

[0069] Clause 18: The semiconductor structure according to Clause 17, wherein the front metal line and the back metal line are not perpendicularly aligned, and the horizontal distance between the front metal line and the back metal line is less than the length of the deep trench via, the length of which is along the width direction of the metal gate.

[0070] Clause 19: The semiconductor structure according to Clause 16 further includes a first set of inner spacers between the first S / D region and a first side of the deep trench via, and a second set of inner spacers between the second S / D region and a second side of the deep trench via, the first side being opposite to the second side.

[0071] Clause 20: The semiconductor structure according to Clause 16 further includes a front via, a back via, and a back contact, wherein the front metal line is electrically connected to the top surface of the deep trench via through the front via, and the back metal line is electrically connected to the bottom surface of the deep trench via through the back via and the back contact.

[0072] It should be understood that the exemplary methods discussed herein can be readily combined with other semiconductor processing flows, semiconductor devices, and integrated circuits having various analog and digital or mixed-signal circuits. Specifically, various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc., can be used to fabricate integrated circuit dies. Integrated circuits according to the invention can be employed in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones), solid-state media storage devices, functional circuits, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. In view of the teachings of the invention provided herein, those skilled in the art will be able to conceive of other implementations and applications of the technology of the invention.

[0073] Therefore, at least a portion of one or more semiconductor structures described herein can be implemented in an integrated circuit. The resulting integrated circuit chip can be distributed by the manufacturer in the form of a raw wafer (i.e., as a single wafer with multiple unpackaged chips), a bare die, or a package. In the latter case, the chip can be mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other advanced carrier) or in a multi-chip package (such as a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip can then be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate product (such as a motherboard) or a final product. The final product can be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0074] Various embodiments of the invention have been described for illustrative purposes; they are not exhaustive and the invention is not limited to the disclosed embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements relative to the technology on the market, and to enable those skilled in the art to understand the embodiments disclosed herein. Many modifications, substitutions, alterations, and equivalents will now be apparent to those skilled in the art. Such alterations, modifications, and / or substitutions may be made without departing from the spirit of the invention, and all of these are contemplated and considered within the scope of the invention. Therefore, it is to be understood that the appended claims are intended to cover all such modifications and variations falling within the spirit of the invention.

Claims

1. A semiconductor structure, comprising: Deep trench vias are located in a single diffusion interruption region. The front metal wire is electrically connected to the top surface of the deep trench through hole; as well as The back metal wire is electrically connected to the bottom surface of the deep trench through-hole. The front and back metal lines are parallel to each other and perpendicular to the deep trench through-hole.

2. The semiconductor structure according to claim 1 further includes a metal gate and a gate-cut dielectric, wherein the deep trench via is located in the width direction of the metal gate, and the gate-cut dielectric separates the deep trench via from the metal gate.

3. The semiconductor structure according to claim 1 further includes a first group of inner spacers and a second group of inner spacers, wherein the first group of inner spacers directly contacts the first side of the deep trench via, and the second group of inner spacers directly contacts the second side of the deep trench via, wherein the first side of the deep trench via is opposite to the second side of the deep trench via.

4. The semiconductor structure according to claim 3 further includes a first source / drain S / D region of the first nanosheet NS transistor and a second source / drain S / D region of the second nanosheet NS transistor, wherein the first source / drain S / D region directly contacts the first set of inner spacers, and the second source / drain S / D region directly contacts the second set of inner spacers.

5. The semiconductor structure according to claim 1 further includes a front via, a back via, and a back contact portion, wherein the front metal line is electrically connected to the top surface of the deep trench via through the front via, and the back metal line is electrically connected to the bottom surface of the deep trench via through the back via and the back contact portion.

6. The semiconductor structure according to claim 5, wherein the back contact portion is adjacent to the shallow trench isolation unit (STI), the shallow trench isolation unit (STI) is located directly below the deep trench via and embedded in the substrate.

7. The semiconductor structure of claim 1, wherein the front metal line and the back metal line are not vertically aligned, and the horizontal distance between the front metal line and the back metal line is less than the length of the deep trench via.

8. A method for forming a semiconductor structure, the method comprising: A first sacrificial gate of a first nanosheet NS transistor, a second sacrificial gate of a second nanosheet NS transistor, and a third sacrificial gate are formed on a substrate. A first source / drain S / D region of the first nanosheet NS transistor is formed between the first sacrificial gate and the third sacrificial gate; A second source / drain S / D region of the second nanosheet NS transistor is formed between the second sacrificial gate and the third sacrificial gate; A back contact portion is formed in the substrate below the single diffusion interruption region; A deep trench via is formed directly above the back contact portion in the single diffusion interruption region, and the single diffusion interruption region is located between the first source / drain S / D region of the first nanosheet NS transistor and the second source / drain S / D region of the second nanosheet NS transistor. Form a front metal line that is electrically connected to the top surface of the deep trench through-hole; as well as A back metal wire is formed that is electrically connected to the bottom surface of the deep trench through hole.

9. The method of claim 8 further comprises forming a front through-hole, the front through-hole directly contacting the top surface of the deep trench through-hole, wherein the front metal wire directly contacts the front through-hole.

10. The method of claim 8, further comprising forming a back through hole, the back through hole directly contacting the back contact portion, wherein the back metal wire directly contacts the back through hole.

11. The method of claim 8, further comprising: A first set of internal spacers is formed between the first source / drain S / D region of the first nanosheet NS transistor and the first side of the deep trench via. as well as A second set of internal spacers is formed between the second source / drain S / D region of the second nanosheet NS transistor and the second side of the deep trench via. The first side of the deep trench through hole is opposite to the second side of the deep trench through hole.

12. The method of claim 8, wherein forming the back contact portion comprises: The third sacrificial gate and one or more nanosheets exposed by the removal of the third sacrificial gate are selectively removed to form a first opening between the first source / drain S / D region of the first nanosheet NS transistor and the second source / drain S / D region of the second nanosheet NS transistor, the first opening exposing the substrate; A portion of the substrate is recessed to form a second opening in the substrate; as well as The second opening is filled with a conductive material to form the back contact portion.

13. The method of claim 12, wherein forming the deep trench through-hole comprises: In the single-diffusion interruption region, the first opening is filled with the conductive material between the first source / drain S / D region and the second source / drain S / D region to form the deep trench via.

14. The method of claim 8, wherein forming the front metal line comprises forming the front metal line in a first direction perpendicular to the deep trench via; and wherein forming the back metal line comprises: The back metal line is formed from the back side of the substrate in a second direction that is perpendicular to the deep trench via and parallel to the first direction, wherein the back metal line is not perpendicularly aligned with the front metal line.

15. The method of claim 8, further comprising forming a gate-cut dielectric layer that insulates the metal gate from the deep trench via, wherein the deep trench via is located in the width direction of the metal gate.

16. A semiconductor structure comprising: The first source / drain S / D region of the first nanosheet NS transistor and the second source / drain S / D region of the second nanosheet NS transistor; A deep trench via located in a single diffusion interruption region between the first source / drain S / D region and the second source / drain S / D region; A front metal wire electrically connected to the top surface of the deep trench through hole; as well as A back metal wire electrically connected to the bottom surface of the deep trench through hole.

17. The semiconductor structure of claim 16, further comprising a metal gate and a gate-cut dielectric layer, wherein the deep trench via is located in the width direction of the metal gate, and the gate-cut dielectric layer insulates the metal gate from the deep trench via.

18. The semiconductor structure of claim 17, wherein the front metal line is not perpendicularly aligned with the back metal line, and the horizontal distance between the front metal line and the back metal line is less than the length of the deep trench via, the length of the deep trench via being along the width direction of the metal gate.

19. The semiconductor structure of claim 16, further comprising a first set of inner spacers between the first source / drain S / D region and a first side of the deep trench via, and a second set of inner spacers between the second source / drain S / D region and a second side of the deep trench via, the first side being opposite to the second side.

20. The semiconductor structure of claim 16 further includes a front via, a back via, and a back contact portion, wherein the front metal line is electrically connected to the top surface of the deep trench via through the front via, and the back metal line is electrically connected to the bottom surface of the deep trench via through the back via and the back contact portion.

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