A broadband system amplitude imbalance automatic calibration system and implementation method

Abstract

This invention relates to an automatic amplitude imbalance calibration system and implementation method for broadband systems. The system includes a programmable four-channel signal source, a broadband signal receiving control processor, and a control computer. The system automatically completes the calibration process by forming a loop under computer control, consisting of the amplitude calibration source, the outputs of each channel of the processor, data calibration calculations, and the input of the amplitude calibration table. Specifically, in test mode, the programmable four-channel signal source, the broadband signal receiving control processor, and the control computer form a loop to establish the amplitude calibration table. In normal mode, the signal to be processed is input to the broadband signal receiving control processor, and in conjunction with the control computer, the amplitude of the signal is calibrated according to the amplitude calibration table. This allows the establishment of the calibration table and signal processing to be completed within a single system, significantly reducing workload, time, and the number of instruments used, improving efficiency and automation, and simplifying instrument control for easier engineering implementation.

Description

Technical Field

[0001] This invention belongs to the field of airborne electronic countermeasures, and in particular relates to an automatic amplitude imbalance calibration system and implementation method for broadband systems. Background Technology

[0002] Currently, in the field of airborne electronic countermeasures, due to the limitations of aircraft size and the need to achieve 360-degree azimuth coverage, a relatively simple and easily implemented four-channel amplitude comparison direction finding system is typically used to measure the azimuth angle of a target. A conventional four-channel amplitude comparison direction finding system consists of antennas, four frequency measurement receivers, and a signal processor. In this system, the frequency measurement receiver function is integrated into a broadband signal receiving and control processor. The signal receiving and control processor simultaneously receives radio frequency signals from four amplitude comparison antennas, completes the amplitude comparison direction finding results of the target, aligns the interference source with the direction of the threat target, and ensures that the maximum radiated power of the interference source is aligned with the threat signal, thereby achieving the best interference effect. As can be seen from the principle of amplitude comparison direction finding, the direction finding accuracy of the system is greatly affected by channel inconsistency. Amplitude inconsistency in the amplitude comparison direction finding system mainly consists of two parts: the amplitude inconsistency of the receiving antennas and the amplitude inconsistency of the receiving channels within the signal receiving and control processor. The amplitude inconsistency of the receiving antennas is mainly determined by the antenna itself. Theoretical analysis and engineering verification show that the amplitude response of different antennas at the same frequency is basically the same; therefore, the amplitude inconsistency caused by the antennas can be calculated from the antenna pattern. Because the receiving channel covers a wide frequency range (6GHz to 18GHz), the amplitude response of each channel varies greatly at different frequencies, which seriously affects the direction finding accuracy. Due to the large dynamic range of the received signal (greater than 40dB), it is difficult for the detector to achieve good consistency within the dynamic range of the received signal. In order to meet a certain system direction finding accuracy, it is necessary to correct the response of each channel at different frequencies and different input signal amplitudes.

[0003] Traditional calibration methods involve injecting excitation signals into the receiving channel at certain frequency and amplitude intervals, recording the output results of different channels at the output end, and thus obtaining correction parameters at different frequencies and amplitudes. In the past, due to the low requirements for direction finding accuracy, the size of frequency measurement receivers could not be made very large, resulting in poor frequency measurement accuracy. Therefore, when performing parameter correction, the frequency intervals were relatively large (above 100MHz), and the number of recorded frequency points was not very large. Consequently, much of the data recording was done manually.

[0004] Another solution is to add a frequency source inside the receiving channel to provide a calibration source for other channels. Although this can automatically calculate the data correction table, it is usually difficult to implement due to the size limitations of airborne equipment, which adds a transmitting channel. Furthermore, due to size limitations, the consistency of the frequency source itself is difficult to guarantee, which introduces new imbalances into the system and affects the direction finding accuracy. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned shortcomings of the prior art and provide an automatic calibration system for amplitude imbalance in broadband systems. By forming a loop with a programmable four-channel signal source, a broadband signal receiving control processor, and a control computer, an amplitude calibration table is established, thereby completing the automatic calibration of amplitude imbalance in broadband systems. This reduces the number of instruments, improves efficiency, enhances the level of automation, and simplifies the control of the instruments.

[0006] Another objective of this invention is to provide a method for implementing an automatic amplitude imbalance calibration system for broadband systems.

[0007] The above-mentioned objective of the present invention is achieved through the following technical solution:

[0008] An automatic amplitude imbalance calibration system for a broadband system, characterized in that it includes a programmable four-channel signal source, a broadband signal receiving and control processor, and a control computer. The broadband signal receiving and control processor consists of an envelope detector, an analog-to-digital converter (ADC), a down-converter, a high-speed ADC, an FPGA, and a DSP.

[0009] Control Computer: In test mode, the test mode control command is output to the DSP in the broadband signal receiving control processor via an asynchronous full-duplex serial port to start the test mode. At the same time, the control signal is output to the programmable four-channel signal source via the LAN interface. The signal amplitude and frequency output by the DSP are received in real time. Based on the control signal output to the programmable four-channel signal source, the amplitude calibration value is calculated. After the test is completed, an amplitude calibration table is established and output to the DSP. In normal mode, the normal mode control command is output to the DSP in the broadband signal receiving control processor via an asynchronous full-duplex serial port to start the normal mode.

[0010] Programmable four-channel signal source: Receives control signals output by the control computer through the LAN interface, generates four radio frequency signals, and outputs the four radio frequency signals to the envelope detector and downconverter in the broadband signal receiving control processor;

[0011] Envelope detector: In test mode, it receives four RF signals from a programmable four-channel signal source, performs envelope detection processing, and outputs the processed analog signal to the AD converter; in normal mode, it receives the input signal to be processed, performs envelope detection processing, and outputs the processed analog signal to the AD converter.

[0012] AD: In test mode and normal mode, receive the analog signal after envelope detection processing output by the envelope detector, and convert the analog signal into an envelope digital signal and output it to the FPGA;

[0013] Downconverter: In test mode, it receives four RF signals from a programmable four-channel signal source, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD converter; in normal mode, it receives the input signal to be processed, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD converter.

[0014] High-speed AD: Sampling rate > 500MHz. In test mode and normal mode, it receives the baseband signal after downconversion processing from the downconverter and converts the baseband signal into a digital quantized signal to be output to the FPGA.

[0015] FPGA: In test mode and normal mode, it receives the envelope digital signal output by AD and performs amplitude measurement, outputs the measured signal amplitude to DSP, and simultaneously receives the digital quantization signal output by high-speed AD and performs frequency measurement, outputs the measured signal frequency to DSP.

[0016] DSP: In test mode, it receives test mode control commands from the control computer via an asynchronous full-duplex serial port, starts the test mode, receives the signal amplitude and frequency output by the FPGA in real time, and outputs them to the control computer via the asynchronous full-duplex serial port. After the test is completed, it receives the amplitude calibration table output by the control computer and saves it permanently. In normal mode, it receives normal mode control commands from the control computer via an asynchronous full-duplex serial port, starts the normal mode, receives the signal amplitude and frequency output by the FPGA in real time, performs signal amplitude calibration according to the amplitude calibration table, and outputs the amplitude-calibrated signal.

[0017] In the aforementioned automatic amplitude imbalance calibration system for broadband systems, the FPGA includes a signal detection module, an FIR filtering module, an amplitude measurement module, and a frequency measurement module, wherein:

[0018] Signal detection module: Receives the envelope digital signal output by AD, detects it, and outputs the detected signal to the FIR filtering module;

[0019] FIR filtering module: Receives the signal output from the signal detection module, performs filtering processing, and outputs the filtered signal to the amplitude measurement module;

[0020] Amplitude measurement module: Receives the signal output from the FIR filtering module, measures the amplitude, and outputs the measured signal amplitude to the DSP;

[0021] Frequency measurement module: Receives the digital quantization signal output from the high-speed AD converter, performs frequency measurement, and outputs the measured signal frequency to the DSP.

[0022] In the aforementioned automatic amplitude imbalance calibration system for broadband systems, the DSP is equipped with FLASH memory. The DSP receives the amplitude calibration table output by the control computer and permanently stores it in the FLASH memory.

[0023] In the aforementioned automatic amplitude imbalance calibration system for broadband systems, the asynchronous full-duplex serial port is RS422.

[0024] A method for implementing an automatic amplitude imbalance calibration system for a broadband system, comprising the following steps:

[0025] (1) In test mode, the control computer outputs the test mode control command to the DSP in the broadband signal receiving control processor through the asynchronous full-duplex serial port to start the test mode. At the same time, it outputs the control signal to the programmable four-channel signal source through the LAN interface. The programmable four-channel signal source receives the control signal output by the control computer through the LAN interface, generates four radio frequency signals, and outputs the four radio frequency signals to the envelope detector and downconverter in the broadband signal receiving control processor.

[0026] (2) The envelope detector receives four radio frequency signals output from the programmable four-channel signal source, performs envelope detection processing, and outputs the processed analog signal to the AD; the AD receives the processed analog signal output from the envelope detector and converts the analog signal into an envelope digital signal, which is then output to the FPGA.

[0027] (3) The downconverter receives four radio frequency signals output from the programmable four-channel signal source, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD; the high-speed AD receives the downconverted baseband signal output from the downconverter and converts the baseband signal into a digital quantized signal and outputs it to the FPGA.

[0028] (4) The FPGA receives the envelope digital signal output by the AD and performs amplitude measurement. The measured signal amplitude is output to the DSP. At the same time, the FPGA receives the digital quantization signal output by the high-speed AD and performs frequency measurement. The measured signal frequency is output to the DSP.

[0029] (5) The DSP receives the signal amplitude and signal frequency output by the FPGA in real time and outputs them to the control computer through the asynchronous full-duplex serial port. The control computer calculates the amplitude calibration value according to the control signal output to the programmable four-channel signal source. After the test is completed, an amplitude calibration table is established and output to the DSP. The DSP receives the amplitude calibration table output by the control computer and saves it permanently.

[0030] (6) In normal mode, the control computer outputs the normal mode control command to the DSP in the broadband signal receiving and control processor through the asynchronous full-duplex serial port to start the normal mode;

[0031] (7) The envelope detector receives the input signal to be processed, performs envelope detection processing, and outputs the processed analog signal to the AD; the AD receives the processed analog signal output by the envelope detector and converts the analog signal into an envelope digital signal and outputs it to the FPGA;

[0032] (8) The downconverter receives the input signal to be processed, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD; the high-speed AD receives the downconverted baseband signal output by the downconverter and converts the baseband signal into a digital quantization signal and outputs it to the FPGA;

[0033] (9) The FPGA receives the envelope digital signal output by the AD and performs amplitude measurement, outputs the measured signal amplitude to the DSP, and simultaneously receives the digital quantization signal output by the high-speed AD and performs frequency measurement, outputs the measured signal frequency to the DSP.

[0034] (10) The DSP receives the signal amplitude and signal frequency output by the FPGA in real time, and performs signal amplitude calibration according to the amplitude calibration table permanently saved in step (5), and outputs the amplitude-calibrated signal.

[0035] Compared with the prior art, the present invention has the following advantages:

[0036] (1) The automatic calibration system of the present invention adopts an automatic method to automatically complete the amplitude calibration source, the output of each channel of the processor, the data calibration calculation and the input of the calibration table under computer control. That is, in the test mode, the amplitude calibration table is established by forming a loop through the programmable four-channel signal source, the broadband signal receiving control processor and the control computer. In the normal mode, the amplitude calibration of the signal is completed by inputting the signal to be processed into the broadband signal receiving control processor and the control computer, according to the amplitude calibration table established in the test mode. This makes the establishment of the calibration table and the signal processing completed in one system, which greatly reduces the workload and time, improves the level of automation and facilitates engineering implementation.

[0037] (2) The automatic calibration system of the present invention adopts a programmable four-channel signal source controlled by a control computer. The independent four channels reduce the number of instruments and improve efficiency, and simplify the control of the instruments.

[0038] (3) In the amplitude calibration process, the signal receiving control processor needs to detect the signals received by each channel in real time and smooth the amplitude data to calculate the amplitude and frequency of each channel. This process is completed by a high-performance, high-capacity FPGA, realizing fast and real-time measurement.

[0039] (4) The signal receiving control processor of the present invention has a non-volatile memory FLASH, which can store the amplitude calibration table after the automatic calibration method is completed in the signal receiving control processor for a long time.

[0040] (5) The signal receiving control processor of the present invention has two modes, namely normal mode and test mode. The control computer sends a test mode command through the asynchronous serial full-duplex serial port to put the signal receiving control processor into test mode, thereby facilitating the startup of the internal test program and preventing the test program from being started by mistake under normal operation, thus preventing incorrect operation of data.

[0041] (6) This invention is applicable to broadband, high dynamic range, and real-time signal processing, and has high calibration accuracy. It is mainly used in four-channel amplitude comparison and direction finding in the field of airborne electronic countermeasures. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the automatic amplitude imbalance calibration system for broadband systems according to the present invention;

[0043] Figure 2 This is a schematic diagram of the test mode of the broadband system amplitude imbalance automatic calibration system of the present invention;

[0044] Figure 3 This is a schematic diagram of the normal mode of the broadband system amplitude imbalance automatic calibration system of the present invention;

[0045] Figure 4 This is a schematic diagram of the internal FPGA structure of the broadband signal receiving control processor in the broadband system amplitude imbalance automatic calibration system of the present invention;

[0046] Figure 5 This is a flowchart illustrating the test mode of the automatic calibration system for amplitude imbalance in broadband systems according to the present invention. Detailed Implementation

[0047] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0048] like Figure 1 The diagram shows the structure of the automatic amplitude imbalance calibration system for broadband systems according to the present invention. As can be seen from the diagram, the calibration system consists of a programmable four-channel signal source, a broadband signal receiving and control processor, and a control computer. The broadband signal receiving and control processor consists of an envelope detector, an AD converter, a downconverter, a high-speed AD converter, an FPGA, and a DSP. The automatic amplitude imbalance calibration system for broadband systems of the present invention has two working modes: test mode and normal mode. The test mode is executed first to generate an amplitude calibration table that is permanently saved. Then, the normal mode is executed to calibrate the amplitude of the input signal according to the permanently saved amplitude calibration table.

[0049] In test mode, the control computer outputs test mode control commands to the DSP in the broadband signal receiving and control processor via RS422 serial port to start the test mode. At the same time, it outputs control signals to the programmable four-channel signal source via LAN interface. It receives the signal amplitude and signal frequency output by the DSP in real time, and calculates the amplitude calibration value based on the control signals output to the programmable four-channel signal source. After the test is completed, an amplitude calibration table is established and output to the DSP.

[0050] In normal mode, the control computer outputs the normal mode control command to the DSP in the broadband signal receiving and control processor through the RS422 interface to start the normal mode.

[0051] The programmable four-channel signal generator receives control signals from the control computer via a LAN interface, generates four radio frequency signals, and outputs the four radio frequency signals to the detector and downconverter in the broadband signal receiving and control processor.

[0052] In test mode, the envelope detector receives four RF signals from a programmable four-channel signal source, performs envelope detection processing, and outputs the processed analog signal to the AD converter. In normal mode, it receives the input signal to be processed, performs envelope detection processing, and outputs the processed analog signal to the AD converter.

[0053] In both test and normal modes, the AD receives the analog signal after envelope detection processing from the envelope detector and converts the analog signal into an envelope digital signal, which is then output to the FPGA.

[0054] In test mode, the downconverter receives four RF signals from a programmable four-channel signal source, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD converter. In normal mode, it receives the input signal to be processed, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD converter.

[0055] The high-speed AD has a sampling rate of >500MHz. In both test and normal modes, it receives the down-converted baseband signal from the downconverter and converts the baseband signal into a digital quantized signal for output to the FPGA.

[0056] like Figure 4The diagram shows the internal FPGA block diagram of the broadband signal receiving control processor in the broadband system amplitude imbalance automatic calibration device. The FPGA is a high-performance, high-capacity logic device that can achieve fast, real-time measurement. It consists of a signal detection module, an FIR filtering module, an amplitude measurement module, and a frequency measurement module. The signal detection module receives the envelope digital signal output from the AD converter, performs detection, and outputs the detected signal to the FIR filtering module. The FIR filtering module receives the signal output from the signal detection module, performs filtering, and outputs the filtered signal to the amplitude measurement module. The amplitude measurement module receives the signal output from the FIR filtering module, performs amplitude measurement, and outputs the measured signal amplitude value to the DSP. The frequency measurement module receives the digital quantized signal output from the high-speed AD converter, performs frequency measurement, and outputs the measured signal frequency value to the DSP. The FPGA operates in the same way in test mode and normal mode.

[0057] In test mode, the DSP receives test mode control commands from the control computer via RS422 serial port, initiates test mode, receives the signal amplitude and frequency output from the FPGA in real time, and outputs them to the control computer via RS422 serial port. After the test is completed, it receives the amplitude calibration table output from the control computer and saves it permanently. In normal mode, the DSP receives normal mode control commands from the control computer via RS422 serial port, initiates normal mode, receives the signal amplitude and frequency output from the FPGA in real time, performs signal amplitude calibration according to the amplitude calibration table, and outputs the amplitude-calibrated signal.

[0058] like Figure 2 The diagram shown is a schematic of the test mode of the broadband system amplitude imbalance automatic calibration system of the present invention. Figure 5 The diagram shows the workflow of the automatic amplitude imbalance calibration system for broadband systems in test mode. As shown, in test mode, the control computer sends control commands to the programmable four-channel signal source via the LAN interface, causing the source to generate four radio frequency (RF) signals of a specific frequency and amplitude. Simultaneously, the control computer outputs control commands via the asynchronous full-duplex RS422 serial port, putting the broadband signal receiving control processor into test mode. The four RF signals generated by the four-channel signal source are input to the broadband signal receiving control processor, which measures the amplitude and frequency values ​​of the signals and inputs them back to the control computer via the RS422 serial port. The control computer calculates the amplitude calibration value. This process is repeated until all frequency and amplitude data have been measured. The control computer then calculates all amplitude calibration values, completes the establishment of the amplitude calibration table, and inputs the table into the FLASH memory of the DSP in the broadband signal receiving control processor via the RS422 serial port for long-term storage. The specific process is as follows:

[0059] 1. The control computer outputs the test mode control command to the DSP in the broadband signal receiving control processor via RS422 to start the test mode. At the same time, it outputs the control signal to the programmable four-channel signal source through the LAN interface. The programmable four-channel signal source receives the control signal output by the control computer through the LAN interface, generates four radio frequency signals, and outputs the four radio frequency signals to the detector and downconverter in the broadband signal receiving control processor.

[0060] 2. The envelope detector receives four RF signals from a programmable four-channel signal source, performs envelope detection processing, and outputs the processed analog signal to the AD converter; the AD converter receives the processed analog signal from the envelope detector and converts it into an envelope digital signal, which is then output to the FPGA.

[0061] 3. The downconverter receives four RF signals from a programmable four-channel signal source, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD converter; the high-speed AD converter receives the downconverted baseband signal from the downconverter and converts the baseband signal into a digital quantized signal, which is then output to the FPGA.

[0062] 4. The FPGA receives the envelope digital signal output by the AD and performs amplitude measurement. The amplitude of the measured signal is then output to the DSP. At the same time, the FPGA receives the digital quantization signal output by the high-speed AD and performs frequency measurement. The frequency of the measured signal is then output to the DSP.

[0063] 5. The DSP receives the signal amplitude and frequency output from the FPGA in real time and outputs them to the control computer via RS422. The control computer calculates the amplitude calibration value based on the control signal output to the programmable four-channel signal source. After the test is completed, an amplitude calibration table is created and output to the DSP. The DSP receives the amplitude calibration table output by the control computer and saves it permanently.

[0064] like Figure 3 The diagram shows the normal mode of the automatic amplitude imbalance calibration device for broadband systems according to the present invention. As shown, the control computer sends control commands to the broadband signal receiving control processor via an asynchronous full-duplex RS422 serial port, putting the broadband signal receiving control processor into normal operating mode. The processor receives the signal to be processed, performs amplitude and frequency measurements, and outputs the amplitude-calibrated signal according to the amplitude calibration table. The specific process is as follows:

[0065] 1. The control computer outputs the normal mode control command to the DSP in the broadband signal receiving and control processor via RS422 to start the normal mode;

[0066] 2. The envelope detector receives the input signal to be processed, performs envelope detection processing, and outputs the processed analog signal to the AD converter; the AD converter receives the processed analog signal output from the envelope detector and converts the analog signal into an envelope digital signal, which is then output to the FPGA.

[0067] 3. In normal mode, the downconverter receives the input signal to be processed, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD converter; the high-speed AD converter receives the downconverted baseband signal output by the downconverter and converts the baseband signal into a digital quantized signal to be output to the FPGA.

[0068] 4. The FPGA receives the envelope digital signal output by the AD and performs amplitude measurement. The amplitude of the measured signal is then output to the DSP. At the same time, the FPGA receives the digital quantization signal output by the high-speed AD and performs frequency measurement. The frequency of the measured signal is then output to the DSP.

[0069] 5. The DSP receives the signal amplitude and frequency output from the FPGA in real time, performs signal amplitude calibration according to the permanently stored amplitude calibration table, and outputs the amplitude-calibrated signal.

[0070] This invention employs high-speed circuits combined with a fast frequency measurement algorithm to perform real-time frequency measurement of signals. During operation, the processor uses high-speed circuits to receive, digitize, and measure the signal frequency in real time. The measured frequency is used as the input to the amplitude calibration table to read the calibration value, which is then used in the amplitude comparison and direction finding circuit. Simultaneously, a LAN interface is used to program the signal source in real time. During the calibration process, the control computer is connected to the signal source via the LAN interface to control the output frequency, amplitude, pulse width, and repetition rate of the signal source in real time.

[0071] The above description is only the best specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention.

[0072] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. An automatic amplitude imbalance calibration system for a broadband system, characterized in that: It includes a programmable four-channel signal source, a wideband signal receiving and control processor, and a control computer. The wideband signal receiving and control processor consists of an envelope detector, an analog-to-digital converter (ADC), a down-converter, a high-speed ADC, an FPGA, and a DSP. Control Computer: In test mode, the test mode control command is output to the DSP in the broadband signal receiving control processor via an asynchronous full-duplex serial port to start the test mode. At the same time, the control signal is output to the programmable four-channel signal source via the LAN interface. The signal amplitude and frequency output by the DSP are received in real time. Based on the control signal output to the programmable four-channel signal source, the amplitude calibration value is calculated. After the test is completed, an amplitude calibration table is established and output to the DSP. In normal mode, the normal mode control command is output to the DSP in the broadband signal receiving control processor via an asynchronous full-duplex serial port to start the normal mode. Programmable four-channel signal source: Receives control signals output by the control computer through the LAN interface, generates four radio frequency signals, and outputs the four radio frequency signals to the envelope detector and downconverter in the broadband signal receiving control processor; Envelope detector: In test mode, it receives four RF signals from a programmable four-channel signal source, performs envelope detection processing, and outputs the processed analog signal to the AD converter; in normal mode, it receives the input signal to be processed, performs envelope detection processing, and outputs the processed analog signal to the AD converter. AD: In test mode and normal mode, it receives the analog signal after envelope detection processing output by the envelope detector, and converts the analog signal into an envelope digital signal and outputs it to the FPGA; Downconverter: In test mode, it receives four RF signals from a programmable four-channel signal source, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD converter; in normal mode, it receives the input signal to be processed, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD converter. High-speed AD: Sampling rate > 500MHz. In test mode and normal mode, it receives the baseband signal after downconversion processing from the downconverter and converts the baseband signal into a digital quantized signal for output to the FPGA. FPGA: In test mode and normal mode, it receives the envelope digital signal output by AD and performs amplitude measurement, outputs the measured signal amplitude to DSP, and simultaneously receives the digital quantization signal output by high-speed AD and performs frequency measurement, outputs the measured signal frequency to DSP. DSP: In test mode, it receives test mode control commands from the control computer via an asynchronous full-duplex serial port, starts the test mode, receives the signal amplitude and frequency output by the FPGA in real time, and outputs them to the control computer via the asynchronous full-duplex serial port. After the test is completed, it receives the amplitude calibration table output by the control computer and saves it permanently. In normal mode, it receives normal mode control commands from the control computer via an asynchronous full-duplex serial port, starts the normal mode, receives the signal amplitude and frequency output by the FPGA in real time, performs signal amplitude calibration according to the amplitude calibration table, and outputs the amplitude-calibrated signal.

2. The automatic amplitude imbalance calibration system for a broadband system according to claim 1, characterized in that: The FPGA includes a signal detection module, an FIR filtering module, an amplitude measurement module, and a frequency measurement module, wherein: Signal detection module: Receives the envelope digital signal output by AD, detects it, and outputs the detected signal to the FIR filtering module; FIR filtering module: Receives the signal output from the signal detection module, performs filtering processing, and outputs the filtered signal to the amplitude measurement module; Amplitude measurement module: Receives the signal output from the FIR filtering module, measures the amplitude, and outputs the measured signal amplitude to the DSP; Frequency measurement module: Receives the digital quantization signal output from the high-speed AD converter, performs frequency measurement, and outputs the measured signal frequency to the DSP.

3. The automatic amplitude imbalance calibration system for a broadband system according to claim 1, characterized in that: The DSP is equipped with FLASH memory. The DSP receives the amplitude calibration table output by the control computer and stores it permanently in the FLASH memory.

4. The automatic amplitude imbalance calibration system for a broadband system according to claim 1, characterized in that: The asynchronous full-duplex serial port is RS422.

5. The method for implementing an automatic amplitude imbalance calibration system for a broadband system according to claim 1, characterized in that: The steps are as follows: (1) In test mode, the control computer outputs the test mode control command to the DSP in the broadband signal receiving control processor through the asynchronous full-duplex serial port to start the test mode. At the same time, it outputs the control signal to the programmable four-channel signal source through the LAN interface. The programmable four-channel signal source receives the control signal output by the control computer through the LAN interface, generates four radio frequency signals, and outputs the four radio frequency signals to the envelope detector and downconverter in the broadband signal receiving control processor. (2) The envelope detector receives four radio frequency signals output from the programmable four-channel signal source, performs envelope detection processing, and outputs the processed analog signal to the AD; the AD receives the processed analog signal output from the envelope detector and converts the analog signal into an envelope digital signal, which is then output to the FPGA. (3) The downconverter receives four radio frequency signals from the programmable four-channel signal source, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD. The high-speed AD receives the down-converted baseband signal from the down-converter and converts the baseband signal into a digital quantized signal, which is then output to the FPGA. (4) The FPGA receives the envelope digital signal output by the AD and performs amplitude measurement. The measured signal amplitude is output to the DSP. At the same time, the FPGA receives the digital quantization signal output by the high-speed AD and performs frequency measurement. The measured signal frequency is output to the DSP. (5) The DSP receives the signal amplitude and signal frequency output by the FPGA in real time and outputs them to the control computer through the asynchronous full-duplex serial port. The control computer calculates the amplitude calibration value according to the control signal output to the programmable four-channel signal source. After the test is completed, an amplitude calibration table is established and output to the DSP. The DSP receives the amplitude calibration table output by the control computer and saves it permanently. (6) In normal mode, the control computer outputs the normal mode control command to the DSP in the broadband signal receiving and control processor through the asynchronous full-duplex serial port to start the normal mode; (7) The envelope detector receives the input signal to be processed, performs envelope detection processing, and outputs the analog signal after envelope detection processing to the AD. The AD receives the analog signal after envelope detection processing from the envelope detector and converts the analog signal into an envelope digital signal, which is then output to the FPGA. (8) The downconverter receives the input signal to be processed, performs downconversion processing, and outputs the downconverted baseband signal to the high-speed AD. The high-speed AD receives the down-converted baseband signal from the down-converter and converts the baseband signal into a digital quantized signal, which is then output to the FPGA. (9) The FPGA receives the envelope digital signal output by the AD and performs amplitude measurement, outputs the measured signal amplitude to the DSP, and simultaneously receives the digital quantization signal output by the high-speed AD and performs frequency measurement, outputs the measured signal frequency to the DSP. (10) The DSP receives the signal amplitude and signal frequency output by the FPGA in real time, and performs signal amplitude calibration according to the amplitude calibration table permanently saved in step (5), and outputs the amplitude-calibrated signal.

6. The method for implementing an automatic amplitude imbalance calibration system for a broadband system according to claim 5, characterized in that: The DSP in step (5) is equipped with FLASH. The DSP receives the amplitude calibration table output by the control computer and permanently stores it in FLASH.

7. The method for implementing an automatic amplitude imbalance calibration system for a broadband system according to claim 5, characterized in that: The asynchronous full-duplex serial port is RS422.

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