Parallel structure implementation method of a fast identification algorithm for CCSDS convolutional codes

Abstract

The application discloses a CCSDS convolution code fast identification method, which can correctly identify the convolution code sequence recommended in the CCSDS standard and obtain a deletion mode and a code length. The length of the intercepted sequence required for correct identification is related to the bit error rate of the sequence itself. The original serial structure of the CCSDS convolution code fast identification algorithm is realized through a parallel structure, so that the performance of the algorithm can be greatly improved.

Description

Technical Field

[0001] This invention relates to the field of channel coding identification, particularly in the reconnaissance application of electronic information countermeasures systems. It provides an easy-to-implement parallel structure for the CCSDS convolutional code fast identification algorithm, which can greatly improve the real-time performance of the algorithm. Background Technology

[0002] In the field of channel coding identification, significant progress has been made in the research of linear codes such as linear block codes, convolutional codes, and RS codes. This invention presents an engineering implementation method for a convolutional code identification algorithm. The CCSDS convolutional code fast identification algorithm is a fast algorithm for identifying convolutional codes and their four deletion codes at different rates recommended in the CCSDS standard. It exhibits good fault tolerance. Because this algorithm is based on the CCSDS standard, it possesses certain prior knowledge and only requires identifying the code rate (n0-1 / n0) (or code length n0) and deletion mode of the convolutional code. Moreover, the computational complexity is linearly related to the length of the binary bit sequence of the convolutional code, and the entire identification process is almost entirely binary multiplication and addition operations, making it easy to implement in engineering. Due to the algorithm's relatively recent development, no engineering implementation method has yet been proposed, and no relevant literature has been reported. Summary of the Invention

[0003] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a parallel structure implementation method for a fast CCSDS convolutional code recognition algorithm. The real-time fast CCSDS convolutional code recognition algorithm is implemented through a parallel structure to improve real-time performance.

[0004] The technical solution of this invention is: a parallel structure implementation method for the CCSDS convolutional code recognition algorithm, characterized in that: the method proposes a parallel structure implementation scheme for the fast recognition algorithm of CCSDS convolutional codes, which needs to be implemented on an FPGA platform; the method steps are as follows:

[0005] The first step is to serially input the binary bit sequence intercepted by the reconnaissance system into the parallel structure, inputting one binary bit on the rising edge of each working clock.

[0006] The second step involves the following code rate identification modules in the parallel structure: the 1 / 2 code rate identification module, the 2 / 3 code rate identification module, the 3 / 4 code rate identification module, the 5 / 6 code rate identification module, and the 7 / 8 code rate identification module. These modules simultaneously receive binary bit sequences and perform corresponding statistical operations. For each binary bit received, the sequence length counter inside each module increments by 1. When the length of the received bit sequence reaches the interception sequence length set internally by the program, each identification module outputs a statistical result. The statistical result is the difference between the number of true equations and the number of false equations in the following set of equations. The statistical result is then input into an external comparator for comparison with the optimal threshold of each module.

[0007]

[0008] in, The obtained sequence;

[0009] This is the basic verification matrix;

[0010] m is the storage constraint length, and according to the CCSDS standard, m = 6;

[0011] n0 is the length of the convolutional codeword. According to the CCSDS standard, n0∈{2, 3, 4, 6, 8}.

[0012] N is the number of equations in the system of equations;

[0013] The third step is that the optimal threshold for each module is generated by external calculation and is related to the interception sequence length set internally by the program.

[0014] The fourth step involves enabling each comparator in ascending order of bit rate. First, the comparator outside the 1 / 2 bit rate recognition module is enabled. If the statistical result output by this module meets the optimal threshold, the result after recognition is directly output. If the threshold is not met, the comparator outside the next bit rate recognition module (2 / 3 bit rate) is enabled. If the statistical result of this module meets the threshold, the recognition result is output. Otherwise, the comparator outside the next bit rate recognition module is enabled, and so on. If the statistical result of the last bit rate recognition module (7 / 8 bit rate recognition module) still does not meet the threshold, the recognition fails.

[0015] The optimal threshold in the third step is obtained from the intercept sequence length and false alarm probability set internally by the program, and the relationship between them is as follows:

[0016]

[0017] Among them, T opt The optimal threshold is defined by Q(t), where Q(t) is the right-tail probability of t, and t is a random variable.

[0018] α is the false alarm probability, set to 0.0013, hence we have

[0019] N is the number of equations in the system of equations;

[0020] With the sequence's own bit error rate being P e In this case, the minimum total number of equations and the minimum intercept sequence length required for correct identification under different code rates are:

[0021]

[0022] Lmin =(N min +6)n0

[0023] Among them, P e The bit error rate of the received sequence itself;

[0024] n0 is the length of the convolutional codeword. According to the CCSDS standard, n0∈{2, 3, 4, 6, 8}.

[0025] N min This represents the minimum total number of equations.

[0026] L min This is the minimum intercepted sequence length.

[0027] The comparator inputs in the fourth step are the statistical results of each bit rate identification module and their respective optimal thresholds. The external comparator of the lowest bit rate identification module is enabled by default, and its output is inverted and used as the enable of the external comparator of the next higher bit rate identification module adjacent to it.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] (1) This invention provides an in-depth analysis of a fast CCSDS convolutional code recognition algorithm, derives the relationship between the minimum length of the convolutional code binary bit sequence required for correct recognition and the bit error rate, and proposes a parallel implementation scheme for the algorithm to improve real-time performance;

[0030] (2) Easy to implement and saves memory resources. This invention can analyze data in a pipeline manner, without the need to store the received binary bit sequence, which is convenient to implement and greatly reduces memory resources. Attached Figure Description

[0031] Figure 1 Block diagram for the CCSDS convolutional code fast recognition algorithm;

[0032] Figure 2 This is the parallel structure used in this invention to implement the fast CCSDS convolutional code recognition algorithm;

[0033] Figure 3 This is a schematic diagram of the top-level module of a parallel program structure.

[0034] Figure 4 The simulation results are for the algorithm implemented using a parallel structure;

[0035] Figure 5 for Figure 4 An enlarged view of the simulation results. Detailed Implementation

[0036] The present invention will now be described in detail with reference to the accompanying drawings, as follows:

[0037] 1. Let the intercepted sequence be... The basic check matrix is:

[0038] h ∞ =[h m h m-1 ,…,h0,0,…] (1)

[0039] Where m is the encoded storage and here m = 6, let the basic parity check matrix be h, and...

[0040] h = [h] m h m-1 ,…,h0] (2)

[0041] Then there is

[0042]

[0043] Where N is the number of equations and n0 is the length of the convolutional codeword.

[0044] set up

[0045]

[0046] Then the system of equations (3) can be simplified to the form of equation (5).

[0047] Rh T =0 (5)

[0048] Based on this formula, the implementation principle block diagram of the CCSDS convolutional code fast recognition algorithm is given as follows: Figure 1 As shown.

[0049] 2. Figure 1 In this algorithm, the traversal of each code length n0 (i.e., the traversal of each code rate) is not sequential and can be regarded as an independent recognition module. Therefore, the parallel structure implementation block diagram of the real-time CCSDS convolutional code recognition algorithm can be obtained as follows: Figure 2 As shown, the serial convolutional code sequence is directly input into the recognition modules of the five code rates for statistical calculation. The calculation result is the difference between the number of valid and invalid equations in the equation set (3). A shift register with the same length as the number of columns R is set in the program. The traversal process of filling the number of zeros at the front of the sequence is completed by shifting to eliminate the influence of the ambiguity of the starting position on the recognition result. Finally, the largest difference under each code rate is statistically determined as the output result of the recognition module. The output result is output after the input binary bit sequence reaches the set value.

[0050] 3. The output of each bitrate identification module serves as the input to its external comparator, which is compared with its respective optimal threshold. The comparators are enabled high and in ascending order of bitrate. The lowest bitrate is 1 / 2, followed by 2 / 3, 3 / 4, 5 / 6, and 7 / 8. The external comparator for the 1 / 2 bitrate identification module is enabled by default. The output of each comparator is inverted and used as the enable input for the external comparator of the next higher bitrate identification module. If the statistical result of the bitrate identification module is greater than or equal to the corresponding optimal threshold, the comparator output is 1, the external comparator of the next higher bitrate identification module is disabled, and the entire parallel structure provides the final identification result. If the optimal threshold is not reached, the next comparator is enabled, and so on. If the external comparator output for the highest bitrate 7 / 8 identification module is still 0, i.e., the optimal threshold has not been reached, the final output is 0, and the identification fails. The reasons for failure may include using a non-CCSDS standard recommended convolutional code sequence, insufficient sequence length, or excessively high bit error rate.

[0051] 4. The optimal threshold is obtained from the intercept sequence length and the false alarm probability, and the relationship between them is as follows:

[0052]

[0053] Among them, T opt The optimal threshold;

[0054] α is the false alarm probability, typically set to 0.0013, hence...

[0055] With the sequence's own bit error rate being P e In this case, the minimum total number of equations and the minimum intercept sequence length required for correct identification under different code rates are:

[0056]

[0057] L min =(N min +6)n0 (8)

[0058] Among them, P e The bit error rate of the received sequence itself;

[0059] N min This represents the minimum total number of equations.

[0060] L min This is the minimum intercepted sequence length.

[0061] 5. In this invention, the intercept sequence length value set within each rate recognition module is uniform, set to 500 in the simulation, with a working clock of 100MHz. The entire parallel structure is implemented using Verilog language in the ISE 12.4 development environment, and the generated top-level module is as follows: Figure 3 As shown, the simulation results are as follows: Figure 4 , Figure 5 As shown, Figure 5 for Figure 4 The magnified image of the results shows that, theoretically, since the parallel structure performs one operation for each bit received, and outputs statistical results after the received sequence length reaches a set value, the time required for the recognition process should be approximately equal to the product of the operating clock cycle and the intercepted sequence length. Figure 5 It can be seen that the actual situation is consistent with the theoretical analysis, and the recognition of convolutional code sequences of each code rate is completed in about 5,000 ns.

[0062] The parts of this invention not described in detail are well-known to those skilled in the art.

Claims

1. A parallel structure implementation method for a fast CCSDS convolutional code recognition algorithm, characterized in that... The implementation steps are as follows: The first step is to serially input the binary bit sequence intercepted by the reconnaissance system into the parallel structure, inputting one binary bit on the rising edge of each working clock. In the second step, each code rate identification module in the parallel structure, namely the 1 / 2 code rate identification module, the 2 / 3 code rate identification module, the 3 / 4 code rate identification module, the 5 / 6 code rate identification module, and the 7 / 8 code rate identification module, simultaneously receives the binary bit sequence and performs the corresponding statistical operations. For each binary bit received, the sequence length counter inside each module is incremented by 1. When the length of the received bit sequence reaches the interception sequence length set inside the program, each identification module outputs the statistical results. The statistical results are the following formula (1): the difference between the number of valid equations and the number of invalid equations in the equation set. The statistical results are then input to the external comparator of each module for comparison with the best threshold of each module. in, The obtained sequence; This is the basic verification matrix; m is the storage constraint length, and according to the CCSDS standard, m = 6; n0 is the length of the convolutional codeword. According to the CCSDS standard, n0∈{2, 3, 4, 6, 8}. N is the number of equations in the system of equations; The third step is that the optimal threshold for each module is generated by external calculation and is related to the interception sequence length set internally by the program. The fourth step involves enabling the external comparators of each module in ascending order of bitrate. First, the comparator of the 1 / 2 bitrate recognition module is enabled. If the statistical result output by this module meets the optimal threshold, the result of the recognition is directly output. If the threshold is not met, the external comparator of the next bitrate 2 / 3 recognition module is enabled. If the statistical result of this module meets the threshold, the recognition result is output. Otherwise, the external comparator of the next bitrate recognition module is enabled, and so on. If the statistical result of the last bitrate recognition module, i.e., the 7 / 8 bitrate recognition module, still does not meet the threshold, the recognition fails.

2. The parallel structure implementation method of the CCSDS convolutional code fast recognition algorithm according to claim 1, characterized in that: The optimal threshold in the third step is obtained from the intercept sequence length and false alarm probability set internally by the program, and the relationship between them is as follows: Among them, T opt The threshold is the optimal threshold; Q(t) is the right-tailed probability function of t, where t is a random variable; α is the false alarm probability, set to 0.0013; N is the number of equations in the system of equations; The bit error rate of the received sequence itself is P e In this case, the minimum total number of equations and the minimum intercept sequence length required for correct identification under different code rates are: L min (N min +6)n0 Among them, P e The bit error rate of the received sequence itself; n0 is the length of the convolutional codeword. According to the CCSDS standard, n0∈{2, 3, 4, 6, 8}. N min L represents the minimum total number of equations. min This is the minimum intercepted sequence length.

3. The parallel structure implementation method of the CCSDS convolutional code fast recognition algorithm according to claim 1, characterized in that: In the fourth step, the input terminals of the external comparators of each module are the statistical results of each bit rate identification module and their respective optimal thresholds. The external comparator of the lowest bit rate identification module is enabled by default, and its output is inverted and used as the enable of the next higher bit rate identification module external comparator adjacent to it.

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