Semiconductor Devices

Abstract

The present application discloses a semiconductor device. The semiconductor device includes: a substrate, including a cell region and a peripheral region; a plurality of bit lines, located on the cell region; a plurality of gate structures, located on the peripheral region; a first dielectric layer, located between adjacent gate structures; a plurality of connectors, located in the first dielectric layer, connected to the substrate; a plurality of storage node contact structures, located between adjacent bit lines; a plurality of capacitor structures, located on the storage node contact structures; a hard mask layer, covering the top surface of the connector; a second dielectric layer, including a first portion located above the hard mask layer and a second portion located above the storage node contact structure, the vertex of the first portion of the second dielectric layer and the vertex of the second portion are located at different levels. The above semiconductor device is used to achieve the technical effect of improving the performance of the semiconductor device without increasing the process time and process cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device. Background Art

[0002] Dynamic random access memory is a type of volatile memory. A DRAM device generally includes a memory region consisting of a memory cell array and a peripheral region consisting of a control circuit. The control circuit in the peripheral region can address each memory cell in the memory region by passing through a plurality of column word lines and a plurality of row bit lines in the memory region, and is electrically connected to each memory cell to perform data reading, writing or erasing.

[0003] In current semiconductor manufacturing, semiconductor devices of memory cells and peripheral circuits are formed simultaneously through the same manufacturing process, which usually includes a patterning process. How to ensure device performance while forming memory cells and peripheral circuits through multiple processes such as patterning processes is a problem that urgently needs to be solved in the prior art. Utility Model Content

[0004] The present application provides a semiconductor device to solve the problem in the related art of how to ensure device performance while forming a memory cell and a peripheral circuit through multiple processes such as a patterning process.

[0005] According to one aspect of the present application, a semiconductor device is provided, comprising: a substrate, including a cell region and a peripheral region; a plurality of bit lines, located on the cell region; a plurality of gate structures, located on the peripheral region; a first dielectric layer, located between adjacent gate structures; a plurality of connectors, located within the first dielectric layer and connected to the substrate; a plurality of storage node contact structures, located between adjacent bit lines; a plurality of capacitor structures, located on the storage node contact structures; a hard mask layer, covering the top surfaces of the connectors; a second dielectric layer, comprising a first portion located above the hard mask layer and a second portion located above the storage node contact structures, the vertex of the first portion of the second dielectric layer and the vertex of the second portion being located at different levels.

[0006] According to another aspect of the present application, a semiconductor device is provided, comprising: a substrate, including a cell region and a peripheral region; a plurality of bit lines, located on the cell region; a plurality of gate structures, located on the peripheral region; a first dielectric layer, located between adjacent gate structures; a plurality of connectors, located within the first dielectric layer and connected to the substrate; a plurality of storage node contact structures, located between adjacent bit lines; a plurality of capacitor structures, located on the storage node contact structures; a hard mask layer, covering the top surface of the connector; and a second dielectric layer, covering the hard mask layer and directly contacting the top surface of the connector and the sidewalls of the capacitor structure.

[0007] Optionally, the apex of the first portion of the second dielectric layer is higher than the apex of the second portion.

[0008] Optionally, an apex of the hard mask layer is higher than an apex of the second portion of the second dielectric layer.

[0009] Optionally, the hard mask layer includes a first sub-mask covering the connector and a second sub-mask covering the storage node contact structure, and a vertex of the first sub-mask is higher than a vertex of the second sub-mask.

[0010] Optionally, the hard mask layer is completely isolated from the top surface of the storage node contact structure.

[0011] Optionally, the semiconductor device further includes a third dielectric layer located above the gate structure and between adjacent connectors, wherein a top point of the third dielectric layer is lower than a top point of the hard mask layer.

[0012] Optionally, the hard mask layer directly contacts the top surface of the connector and the sidewalls of the capacitor structure.

[0013] According to the present application, a semiconductor device includes a substrate and a bit line, a gate structure, a first dielectric layer, a connector, a hard mask layer, a second dielectric layer, a storage node contact structure and a capacitor structure located on the substrate. Since the hard mask layer covers the top surface of the connector, and the second dielectric layer includes a first portion located above the hard mask layer and a second portion located above the storage node contact structure, the vertex of the first portion of the second dielectric layer and the vertex of the second portion are located at different levels. The hard mask layer is formed by residual hard mask material in the process of forming the connector. In the process of forming the connector, the hard mask layer is formed by residual hard mask material. The mask material is deposited in the memory area and the surrounding area at the same time, and grooves are formed in the peripheral area through patterning and etching processes to separate multiple connectors. Grooves are also synchronously etched in the memory area. Due to the difference in materials, the depth of the grooves formed in the memory area will be greater than the depth of the grooves in the peripheral area. If the depth of the grooves in the memory area is large, over-etching may occur to the bit line to cause a short circuit. In the embodiment of the present application, by leaving hard mask material on the surface of the second connector, the depth of the grooves etched in the memory area can be avoided from being too large, thereby avoiding the risk of over-etching and improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0015] Figure 1 is a partial cross-sectional schematic diagram of a semiconductor device provided according to an embodiment of the present application;

[0016] Figure 2 is a cross-sectional schematic diagram of a first connecting member and a second connecting member in a semiconductor device provided according to an embodiment of the present application;

[0017] Figure 3 is a partial cross-sectional schematic diagram of another semiconductor device provided according to an embodiment of the present application;

[0018] Figure 4 is a process flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0019] Figure 5 It is a partial cross-sectional schematic diagram of a substrate after a bit line and a gate structure are formed on a substrate in a method for preparing a semiconductor device provided in an embodiment of the present application;

[0020] Figure 6 is Figure 5 A schematic partial cross-sectional view of a substrate after a contact hole is formed in a gate structure shown in FIG.

[0021] Figure 7 is Figure 6 A schematic partial cross-sectional view of a substrate after a conductive material and a mask material are deposited on the substrate shown in FIG.

[0022] Figure 8 Yes Figure 7 A schematic partial cross-sectional view of a substrate after etching the mask material shown in FIG. 1 to form a connector and a hard mask layer;

[0023] Fig. 9 Yes Figure 8 A partial cross-sectional schematic diagram of a substrate after the connecting member shown in FIG. 1 is covered with a dielectric material;

[0024] Fig.10 It is etching Fig. 9 A partial cross-sectional schematic diagram of a dielectric material rear substrate shown in FIG.

[0025] Fig.11 Yes Fig.10 FIG. 1 is a schematic partial cross-sectional view of a substrate after the dielectric material shown in FIG. 1 forms a second dielectric layer and a third dielectric layer.

[0026] The above drawings include the following reference numerals:

[0027] 10. substrate; 210. gate structure; 211. first semiconductor layer; 212. first metal layer; 213. first patterned mask; 220. bit line; 221. second semiconductor layer; 222. second metal layer; 223. second patterned mask; 30. barrier layer; 410. first spacer; 411. first insulating layer; 412. second insulating layer; 413. third insulating layer; 420. second spacer; 421. fourth insulating layer; 422. fifth insulating layer; 423. sixth insulating layer; 50. shallow trench isolation junction structure; 610, contact opening; 620, storage node contact opening; 70, semiconductor structure; 80, connector; 801, first connector; 802, second connector; 810, storage node contact structure; 820, contact pad; 821, conductive material; 811, first connection portion; 812, second connection portion; 90, hard mask layer; 910, mask material; 100, first dielectric layer; 101, dielectric material; 120, second dielectric layer; 130, capacitor structure; 140, support layer; 150, wire. DETAILED DESCRIPTION

[0028] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] According to an embodiment of the present application, a semiconductor device is provided. Figure 1 It is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present application.

[0032] like Figure 1 As shown, the semiconductor device includes a substrate 10, a plurality of bit lines 220, a plurality of gate structures 210, a first dielectric layer 100, a plurality of connectors 80, a plurality of storage node contact structures 810, a plurality of capacitor structures 130, a hard mask layer 90 and a second dielectric layer 120, wherein: the substrate 10 includes a cell region and a peripheral region; a plurality of bit lines 220 are located on the cell region; a plurality of gate structures 210 are located on the peripheral region; the first dielectric layer 100 is located between adjacent gate structures 210; a plurality of connectors 80 are located in the first dielectric layer 100 and connected to the substrate; a plurality of storage node contact structures 810 are located between adjacent bit lines 220; a plurality of capacitor structures 130 are located on the storage node contact structures 810; the hard mask layer 90 covers the top surface of the connector; the second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structures 810, and the vertex of the first portion of the second dielectric layer 120 and the vertex of the second portion are located at different levels.

[0033] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 1 As shown, since the hard mask layer 90 covers the top surface of the connector 80, and the second dielectric layer includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure, the vertex of the first portion and the vertex of the second portion of the second dielectric layer 120 are located at different levels. The hard mask layer 90 is formed by residual hard mask material in the process of forming the connector 80. In the process of forming the connector 80, the hard mask material is deposited in the memory area and the surrounding area at the same time. A groove is formed in the peripheral area through a patterning process and an etching process to separate a plurality of connectors 80. A groove is also formed by etching in the memory area simultaneously. Due to the difference in materials, the depth of the groove formed in the memory area is greater than the depth of the groove in the peripheral area. If the depth of the groove in the memory area is large, it may be over-etched to the bit line 220 to cause a short circuit. In the embodiment of the present application, by leaving the hard mask material on the surface of the second connector 802, the depth of the groove formed by etching in the memory area can be avoided, thereby avoiding the risk of over-etching and improving the reliability of the device.

[0034] Furthermore, the hard mask layer 90 may be formed by residual hard mask material on the top surface of the connector 80 while forming the storage node contact structure 810 and the connector 80 by a patterning process in the preparation process of the semiconductor device, thereby eliminating the need for additional process steps, thereby achieving the technical effect of improving the performance of the semiconductor device without increasing the process time and process cost.

[0035] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 1As shown, the semiconductor structure includes a substrate 10 , on which a peripheral region B and a memory region A are defined.

[0036] A shallow trench isolation structure 50 may be formed in the substrate 10 to define multiple active regions of the memory cell in the memory region A of the substrate 10, and multiple active regions of the semiconductor device in the peripheral region B of the substrate 10. The substrate 10 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-covered insulating substrate, which is not specifically limited in the embodiments of the present application.

[0037] The above-mentioned peripheral area B may be provided with peripheral circuits for controlling the operation and input / output of the memory cells in the memory area A, such as a driver, a buffer, an amplifier and a decoder. The peripheral area B may also include circuits for repairing abnormal memory cells, such as fuse circuits, which are not specifically limited in the embodiments of the present application. The memory area A may be provided with a memory cell array, such as a DRAM cell. According to an embodiment of the utility model, the semiconductor devices of the peripheral circuits in the peripheral area B and the DRAM cells in the memory area A are prepared on the substrate 10 by the same manufacturing process.

[0038] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 1 As shown, a plurality of bit lines 220 may be arranged at intervals along the x direction on the memory region A, a plurality of gate structures 210 may be arranged at intervals along the x direction on the peripheral region B, and the plurality of gate structures 210 formed on the peripheral region B and the plurality of bit lines 220 formed on the memory region A may be prepared by the same process steps. Exemplarily, a semiconductor material layer, a metal material layer and a hard mask material layer are sequentially formed on the peripheral region B and the memory region A of the substrate 10, and a patterning process is performed on the hard mask material layer to obtain a patterned mask, and then the metal material layer and the semiconductor material layer are sequentially etched using the patterned mask as a mask to transfer the pattern of the patterned hard mask material to the semiconductor material layer, thereby obtaining the gate structure 210 and the bit line 220.

[0039] The above-mentioned gate structure 210 may respectively include a first semiconductor layer 211, a first metal layer 212 and a first patterned mask 213 sequentially stacked in a direction away from the substrate 10, and the above-mentioned bit line 220 may respectively include a second semiconductor layer 221, a second metal layer 222 and a second patterned mask 223 sequentially stacked in a direction away from the substrate 10, wherein the material of the first semiconductor layer 211 and the second semiconductor layer 221 may include polycrystalline silicon; the material of the first metal layer 212 and the second metal layer 222 may include low-resistivity metal materials such as aluminum, tungsten, copper, titanium, and titanium-aluminum alloy; the material of the first patterned mask 213 and the second patterned mask 223 may include any one or more of silicon nitride, silicon oxynitride and silicon carbonitride, and may also include other dielectric materials. The embodiments of the present application do not specifically limit the types of the above-mentioned materials.

[0040] It should be noted that a gate oxide layer may be provided between the substrate 10 and the first semiconductor layer 211 of the gate structure 210 , and the material of the gate oxide layer may be silicon oxide.

[0041] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 1 As shown, the first dielectric layer 100 is located between adjacent gate structures 210, and the semiconductor device of the embodiment of the present application may further include a barrier layer 30 located on the gate structure 210 and the first dielectric layer 100. The materials of the first dielectric layer 100 and the barrier layer 30 may include any one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonitride, and may also include other types of dielectric materials, which are not specifically limited in the embodiment of the present application.

[0042] like Figure 1 As shown, the semiconductor device of the embodiment of the present application may further include a first spacer 410 located on both sides of the gate structure 210. Exemplarily, the first spacer 410 includes a first insulating layer 411, a second insulating layer 412 and a third insulating layer 413 sequentially covering the sidewalls of the gate structure 210 from the inside to the outside.

[0043] like Figure 1 As shown, the semiconductor device of the embodiment of the present application may further include a second spacer 420 located on both sides of the bit line 220. Exemplarily, the second spacer 420 includes a fourth insulating layer 421, a fifth insulating layer 422 and a sixth insulating layer 423 sequentially covering the sidewalls of the bit line 220 and the barrier layer 30 from the inside to the outside.

[0044] The first side wall 410 and the second side wall 420 may be prepared through the same process steps, and the material of each insulating layer in the first side wall 410 and the second side wall 420 may be a conventional insulating material in the prior art, such as silicon oxide, which is not specifically limited in the embodiments of the present application.

[0045] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 2 As shown, the connector 80 may include a plurality of first connectors 801 and at least one second connector 802, each connector 80 includes a first connector portion 811 and a second connector portion 812, the first connector portion 811 is located between at least one gate structure 210 and an adjacent first dielectric layer 100, the second connector portion 812 is located on a side of the first connector portion 811 away from the substrate 10, and a side surface of the second connector portion 812 in the second connector 802 away from the first connector portion 811 is a first surface. The material of the connector 80 may include metal, such as tungsten.

[0046] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 1 As shown, a plurality of storage node contact structures 810 are located between adjacent bit lines 220. The storage node contact structures 810 include a semiconductor structure 70 located between adjacent bit lines 220 and a contact pad 820 located on the semiconductor structure 70. The material of the semiconductor structure 70 may include polysilicon, and the material of the contact pad 820 may include metal, such as tungsten. Exemplarily, the semiconductor structure 70 is filled at the bottom of the storage node contact opening 620 between adjacent bit lines 220, a portion of the contact pad 820 is filled above the semiconductor structure 70, and another portion of the contact pad 820 is located outside the storage node contact opening, covering a portion of the top surface of the bit line.

[0047] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 1 As shown, the second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure 810. The vertex of the first portion of the second dielectric layer 120 and the vertex of the second portion are located at different levels. The hard mask layer 90 may be formed by removing the hard mask material on the top surface of the storage node contact structure 810 in a patterning process during the preparation process of the semiconductor device, and leaving a hard mask material on the top surface of the connector. The material of the second dielectric layer 120 may include any one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride, and may also include other types of dielectric materials, which are not specifically limited in the embodiments of the present application.

[0048] In some optional embodiments of the present application, such as Figure 1As shown, the second dielectric layer 120 includes a first portion located above the hard mask layer and a second portion located above the storage node contact structure 810, and the vertex of the first portion is higher than the vertex of the second portion. By depositing hard mask materials in the memory area A and the peripheral area B at the same time and sequentially performing patterning and etching processes, a groove is formed in the peripheral area B, and multiple connectors 80 are separated by the grooves. The memory area A is also simultaneously etched to form a groove. Due to the difference in materials, the depth of the groove formed in the memory area A is greater than the depth of the groove in the peripheral area B. If the depth of the groove in the memory area A is large, it may be over-etched to the bit line 220 to cause a short circuit. In the embodiment of the present application, by leaving the hard mask material on the surface of the second connector 802, the depth of the groove formed by etching in the memory area A can be avoided to be too large, thereby avoiding the risk of over-etching and improving the reliability of the device.

[0049] For example, Figure 1 As shown, the plurality of connectors 80 include a first connector 801 and a second connector 802, the top surface size of the first connector 801 is larger than the top surface size of the second connector 802, the hard mask layer 90 is located on the top surface of the first connector 801, the bottom surface size of the hard mask layer 90 in contact with the top surface of the first connector 801 is W3, and the height of the hard mask layer 90 is H3. Specifically, the hard mask layer 90 is formed by leaving a hard mask material at least on the top surface of the second connector 802 while forming the storage node contact structure 810 and the connector 80 by a patterning process in the preparation process of the semiconductor device, and at this time, the hard mask material on the top surface of the second connector 802 and the top surface of the storage node contact structure 810 can be removed.

[0050] In another example, if Figure 1 As shown, the hard mask layer 90 is also located on the top surface of the contact pad 820 in at least one storage node contact structure 810, the bottom surface of the hard mask layer 90 in contact with the top surface of the contact pad 820 has a size of W1, and the height of the hard mask layer 90 is H1. Specifically, in the manufacturing process of the semiconductor device, while the storage node contact structure 810 and the connector 80 are formed by a patterning process, the hard mask material remains on the top surface of the second connector 802 and the top surface of at least one storage node contact structure 810, and the hard mask material on the top surface of the second connector 802 and the top surfaces of the remaining storage node contact structures 810 is removed.

[0051] In another example, if Figure 1As shown, the hard mask layer 90 is also located on the top surface of the second connector 802, the bottom surface of the hard mask layer 90 in contact with the top surface of the first connector 801 has a size of W2, and the height of the hard mask layer 90 is H2. In the manufacturing process of the semiconductor device, when the storage node contact structure 810 and the connector 80 are formed by patterning, in addition to the hard mask material remaining on the top surface of the first connector 801 and the top surface of at least one storage node contact structure 810, the hard mask material also remains on the top surface of at least one second connector 802, and the remaining hard mask material forms the hard mask layer 90. Since the top surface size of the first connector 801 is larger than the top surface size of the second connector 802, the size of the hard mask layer 90 located on the top surface of the first connector 801 is larger than the size of the hard mask layer 90 located on the top surface of the second connector 802, wherein the bottom surface size of the hard mask layer 90 contacting the top surface of the first connector 801 is larger than the bottom surface size of the hard mask layer 90 contacting the top surface of the second connector 802, and the height of the hard mask layer 90 located on the top surface of the first connector 801 is also greater than the height of the hard mask layer 90 located on the top surface of the second connector 802.

[0052] In some optional embodiments of the present application, such as Figure 1 As shown, the hard mask layer 90 includes a first sub-mask covering the connector 80 and a second sub-mask covering the storage node contact structure 810, and the vertex of the first sub-mask is higher than the vertex of the second sub-mask. The first sub-mask is arranged on the top surface of at least one connector 80, and the second sub-mask is arranged on the top surface of at least one storage node contact structure 810. The first sub-mask and the second sub-mask can be formed by the hard mask material remaining on the top surface of the connector 80 while the storage node contact structure 810 and the connector 80 are formed by patterning in the manufacturing process of the semiconductor device.

[0053] In some optional embodiments of the present application, the hard mask layer is completely isolated from the top surface of the storage node contact structure. In this case, the hard mask layer is formed by removing the hard mask material on the top surface of the storage node contact structure in a patterning process during the preparation process of the semiconductor device, while leaving a hard mask material on the top surface of at least one connector.

[0054] like Figure 3 As shown, the hard mask layer 90 may also directly contact the top surface of the storage node contact structure 810 and the side wall of the capacitor structure 130 , and after the conductive line 150 is connected above the connector 80 , the hard mask layer 90 contacts the side wall of the conductive line 150 .

[0055] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 1 and Figure 3As shown, a plurality of capacitor structures 130 are located on the storage node contact structure 810 , and each capacitor structure 130 is connected to at least one adjacent capacitor structure 130 via a supporting layer 140 .

[0056] The plurality of capacitor structures 130 are disposed above the substrate 10 at intervals and are connected to the contact pads 820 in the storage node contact structure 810 in a one-to-one correspondence.

[0057] According to an embodiment of the present application, a semiconductor device is also provided, such as Figure 3 It is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present application.

[0058] like Figure 3 As shown, the semiconductor device includes a substrate 10, a plurality of bit lines 220, a plurality of gate structures 210, a first dielectric layer 100, a plurality of connectors 80, a plurality of storage node contact structures 810, a plurality of capacitor structures 130, a hard mask layer 90 and a second dielectric layer 120, wherein: the substrate 10 includes a cell region and a peripheral region; a plurality of bit lines 220 are located on the cell region; a plurality of gate structures 210 are located on the peripheral region; the first dielectric layer 100 is located between adjacent gate structures 210; a plurality of connectors 80 are located in the first dielectric layer 100 and connected to the substrate; a plurality of storage node contact structures 810 are located between adjacent bit lines 220; a plurality of capacitor structures 130 are located on the storage node contact structures 810; the hard mask layer 90 covers the top surface of the connector; the second dielectric layer 120 covers the hard mask layer 90 and directly contacts the top surface of the connector 80 and the side wall of the capacitor structure 130.

[0059] In the above-mentioned semiconductor device of the embodiment of the present application, if Figure 3 As shown, the hard mask layer 90 can be formed by removing the hard mask material on the top surface of the storage node contact structure 810 in the patterning process during the preparation process of the semiconductor device, and leaving residual hard mask material on the top surface of the above-mentioned connector. Specifically, the hard mask material is deposited in the memory area A and the peripheral area B at the same time, and the patterning process and the etching process are performed sequentially to form grooves in the peripheral area B to separate multiple connectors 80. The memory area A is also simultaneously etched to form grooves. Due to the difference in materials, the depth of the groove formed in the memory area A will be greater than the depth of the groove in the peripheral area B. If the depth of the groove in the memory area A is large, it may be over-etched to the bit line 220 to cause a short circuit. In the embodiment of the present application, by leaving the hard mask material on the surface of the second connector 802, the depth of the groove formed by etching in the memory area A can be avoided to be too large, thereby avoiding the risk of over-etching and improving the reliability of the device.

[0060] In the above-mentioned semiconductor device of the embodiment of the present application, the positional relationship and materials of the substrate 10, bit line 220, gate structure 210, first dielectric layer 100, connector 80, storage node contact structure 810, capacitor structure 130 and hard mask layer 90 may be the same as those of the semiconductor device provided in the aforementioned embodiment, and the embodiment of the present application will not be repeated.

[0061] According to an embodiment of the present application, a method for preparing a semiconductor device is also provided. Figure 4 It is a process flow chart of a method for preparing a semiconductor device according to an embodiment of the present application.

[0062] like Figures 4 to 11 As shown, the method for preparing the semiconductor device comprises the following steps:

[0063] A substrate 10 is provided, wherein the substrate 10 includes a cell region and a peripheral region:

[0064] A plurality of bit lines 220 are formed on the cell region, a plurality of gate structures 210 are formed on the peripheral region, and a first dielectric layer 100 is formed between adjacent gate structures 210;

[0065] forming a plurality of connectors 80 within the first dielectric layer 100;

[0066] forming a plurality of storage node contact structures 810 between adjacent bit lines 220;

[0067] forming a hard mask layer 90 covering a top surface of the connector 80;

[0068] A second dielectric layer 120 and a capacitor structure 130 are formed, wherein the capacitor structure 130 is located on the storage node contact structure 810, and the second dielectric layer 120 covers the hard mask layer 90, wherein the second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure 810, and the vertex of the first portion of the second dielectric layer 120 and the vertex of the second portion are located at different levels.

[0069] In the method for preparing the semiconductor device of the embodiment of the present application, since a hard mask layer 90 covering the top surface of the connector 80 is formed, and the second dielectric layer includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure, the vertex of the first portion and the vertex of the second portion of the second dielectric layer 120 are located at different levels, and the hard mask layer 90 is formed by residual hard mask material in the process of forming the connector 80. In the process of forming the connector 80, the hard mask material is simultaneously deposited in the memory area A and the surrounding area B. The patterning process and the etching process form grooves in the peripheral area B to separate multiple connectors 80, and grooves are also formed in the memory area A by etching simultaneously. Due to the difference in materials, the depth of the groove formed in the memory area A will be greater than the depth of the groove in the peripheral area B. If the depth of the groove in the memory area A is large, it may be over-etched to the bit line 220 to cause a short circuit. In the embodiment of the present application, by leaving a hard mask material on the surface of the second connector 802, the depth of the groove formed by etching in the memory area A can be avoided from being too large, thereby avoiding the risk of over-etching and improving the reliability of the device.

[0070] Furthermore, the hard mask layer 90 may be formed by residual hard mask material on the top surface of the connector 80 while forming the storage node contact structure 810 and the connector 80 by a patterning process in the preparation process of the semiconductor device, thereby eliminating the need for additional process steps, thereby achieving the technical effect of improving the performance of the semiconductor device without increasing the process time and process cost.

[0071] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0072] First, if Figure 5 As shown, a substrate 10 is provided, and the substrate 10 includes a cell region and a peripheral region.

[0073] The substrate 10 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate or a silicon-covered insulating substrate, and is not specifically limited in the embodiments of the present application.

[0074] In some optional embodiments, a shallow trench isolation structure 50 is formed in the substrate 10 to define multiple active regions of memory cells in the memory region A of the substrate 10 and multiple active regions of the semiconductor device in the peripheral region B of the substrate 10 .

[0075] After providing the substrate 10, as Figure 5 As shown, a plurality of bit lines 220 are formed on the cell region, a plurality of gate structures 210 are formed on the peripheral region, and a first dielectric layer 100 is formed between adjacent gate structures 210 .

[0076] In some optional embodiments, such as Figure 5 As shown, a plurality of gate structures 210 located on the peripheral region B and a plurality of bit lines 220 located on the memory region A are formed by the same process steps. Exemplarily, a semiconductor material layer, a metal material layer and a hard mask material layer are sequentially formed on the peripheral region B and the memory region A of the substrate 10, and a patterning process is performed on the hard mask material layer to obtain a patterned mask, and then the metal material layer and the semiconductor material layer are sequentially etched using the patterned mask as a mask to transfer the pattern of the patterned hard mask to the semiconductor material layer, thereby obtaining the gate structure 210 and the bit line 220.

[0077] The above-mentioned gate structure 210 may respectively include a first semiconductor layer 211, a first metal layer 212 and a first patterned mask 213 sequentially stacked in a direction away from the substrate 10, and the above-mentioned bit line 220 may respectively include a second semiconductor layer 221, a second metal layer 222 and a second patterned mask 223 sequentially stacked in a direction away from the substrate 10, wherein the material of the first semiconductor layer 211 and the second semiconductor layer 221 may include polycrystalline silicon; the material of the first metal layer 212 and the second metal layer 222 may include low-resistivity metal materials such as aluminum, tungsten, copper, titanium, and titanium-aluminum alloy; the material of the first patterned mask 213 and the second patterned mask 223 may include any one or more of silicon nitride, silicon oxynitride and silicon carbonitride, and may also include other dielectric materials. The embodiments of the present application do not specifically limit the types of the above-mentioned materials.

[0078] It should be noted that before forming the gate structure 210 , a gate oxide layer may be formed on the substrate 10 so that the gate oxide layer is located between the substrate 10 and the semiconductor portion 22 of the gate structure 210 . The material of the gate oxide layer may be silicon oxide.

[0079] After the step of forming the gate structure 210, as shown in FIG. Figure 5 As shown, a first dielectric layer 100 is formed between adjacent gate structures 210. After the step of forming the first dielectric layer 100, as shown in FIG. Figure 5 As shown, the preparation method provided in the embodiment of the present application may further include: forming a barrier layer 30 located on the gate structure 210 and the first dielectric layer 100. The materials of the first dielectric layer 100 and the barrier layer 30 may include any one or more of silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride, and may also include other types of dielectric materials, which are not specifically limited in the embodiment of the present application.

[0080] like Figure 5 As shown, the manufacturing method provided in the embodiment of the present application may further include: forming a first spacer 410 located on both sides of the gate structure 210 ; and forming a second spacer 420 located on both sides of the bit line 220 .

[0081] Exemplarily, the first sidewall 410 includes a first insulating layer 411, a second insulating layer 412 and a third insulating layer 413 sequentially covering the sidewalls of the gate structure 210 from the inside to the outside, and the second sidewall 420 includes a fourth insulating layer 421, a fifth insulating layer 422 and a sixth insulating layer 423 sequentially covering the sidewalls of the bit line 220 and the blocking layer 30 from the inside to the outside.

[0082] The first side wall 410 and the second side wall 420 may be prepared through the same process steps, and the material of each insulating layer in the first side wall 410 and the second side wall 420 may be a conventional insulating material in the prior art, such as silicon oxide, which is not specifically limited in the embodiments of the present application.

[0083] After the step of forming the first dielectric layer 100, as Figure 6 and Figure 7 As shown, a plurality of connectors 80 are formed within the first dielectric layer 100 .

[0084] In some optional embodiments, the step of forming the connecting member 80 includes: Figure 6 As shown, contact openings 610 are formed on both sides of at least one gate structure 210, and the contact openings 610 extend from both sides of the gate structure 210 into the substrate 10; Figure 7 As shown, a conductive material 821 is deposited on the substrate 10 so that a portion of the conductive material 821 fills the contact opening 610 to form a Figure 2 The first connecting portion 811 shown in FIG. 1 , the remaining conductive material 821 forms a conductive layer on the side of the gate structure 210 and the first dielectric layer 100 facing away from the substrate 10; Figure 8 and Fig. 9 As shown, a mask material 910 is deposited on the surface of the conductive layer, and the mask material is formed into a patterned mask, and then the conductive layer is etched through the patterned mask to form the conductive layer as shown in FIG. Figure 2 The second connecting portion 812 is shown, thereby obtaining the first connecting member 801 and the second connecting member 802.

[0085] In the above optional implementation, if Figure 6 As shown, while forming the contact opening 610, a storage node contact opening 620 located between adjacent bit lines 220 may also be formed. Figure 7 As shown, the conductive material 821 can be deposited in the peripheral region B and the memory region A at the same time, and part of the conductive material 821 deposited in the peripheral region B is filled into the contact opening 610, and part of the conductive material 821 deposited in the memory region A is filled into the storage node contact opening 620, as shown in FIG. Figure 8As shown, the mask material 910 deposited on the surface of the conductive layer also covers the surface of the conductive material 821 in the memory area A. After the mask material is formed into a patterned hard mask, the conductive material 821 is etched through the patterned hard mask located in the memory area A to form a contact pad 820.

[0086] In some optional embodiments, a conductive material covering the bit line and gate structure is first formed, a patterned hard mask is formed on the surface of the conductive material, and then the conductive material is partially removed to form a connector and a storage node contact structure, and then the patterned hard mask located on the storage node contact structure is completely removed to form a hard mask layer covering the top surface of the connector.

[0087] In the above optional embodiment, while completely removing the hard mask material on the top surface of the storage node contact structure in the patterning process, part of the hard mask material remains on the top surface of the above connector to form a hard mask layer, thereby avoiding the depth of the groove formed by etching in the memory area A, thereby avoiding the risk of over-etching and improving the reliability of the device.

[0088] In other optional embodiments, such as Figure 7 and Figure 8 As shown, a conductive material 821 is formed to cover the bit line 220 and the gate structure 210; a patterned hard mask is formed on the surface of the conductive material 821; the conductive material 821 is partially removed to form a connector 80 and a storage node contact structure 810; the patterned hard mask is partially removed to form a first sub-mask covering the connector 80 and a second sub-mask covering the storage node contact structure 810, and the vertex of the first sub-mask is higher than the vertex of the second sub-mask.

[0089] In the above optional embodiment, the first sub-mask is arranged on the top surface of at least one connector 80, and the second sub-mask is arranged on the top surface of at least one storage node contact structure 810. The above first sub-mask and the above second sub-mask can be formed by residual hard mask material on the top surface of the above connector 80 while forming the storage node contact structure 810 and the connector 80 by a patterning process in the preparation process of the semiconductor device. After the above patterning process, an etching process is performed to form a groove in the peripheral area B, and a plurality of connectors 80 are separated by the groove. A groove is also simultaneously etched to form a groove in the memory area A. Due to the difference in materials, the depth of the groove formed in the memory area A will be greater than the depth of the groove in the peripheral area B. If the depth of the groove in the memory area A is large, it may be over-etched to the bit line 220 to cause a short circuit. By making the height of the hard mask material remaining on the top surface of the connector 80 greater than the height of the hard mask material remaining on the top surface of the storage node contact structure 810, it is possible to avoid the depth of the groove formed by etching in the memory area A being too large, thereby avoiding the risk of over-etching and improving the reliability of the device.

[0090] After the steps of forming the connection member 80 and the storage node contact structure 810, as shown in FIG. Fig. 9 As shown, the preparation method provided in the embodiment of the present application may further include: depositing a dielectric material 101 on the substrate 10 to cover the connector 80, the storage node contact structure 810 and the hard mask layer 90, and filling between adjacent storage node contact structures 810 and between adjacent connectors 80, such as Fig.10 As shown, the portion of the dielectric material 101 covering the connector 80 , the storage node contact structure 810 and the hard mask layer 90 is removed.

[0091] After the step of forming the dielectric material 101, as Fig.11 As shown, a second dielectric layer 120 is formed, and the second dielectric layer 120 includes a first portion located above the hard mask layer 90 and a second portion located above the storage node contact structure 810. The vertex of the first portion of the second dielectric layer 120 and the vertex of the second portion are located at different levels, thereby preventing the depth of the groove formed by etching in the memory area A from being too large, thereby avoiding the risk of over-etching and improving device reliability.

[0092] Furthermore, the hard mask layer 90 may be formed by residual hard mask material on the top surface of the connector 80 while forming the storage node contact structure 810 and the connector 80 by a patterning process in the preparation process of the semiconductor device, thereby eliminating the need for additional process steps, thereby achieving the technical effect of improving the performance of the semiconductor device without increasing the process time and process cost.

[0093] After the step of forming the second dielectric layer 120, as Figure 1 As shown, a capacitor structure 130 is formed, and the capacitor structure 130 is located on the storage node contact structure 810 .

[0094] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0095] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A semiconductor device, characterized in that: include: A substrate including a cell region and a peripheral region; A plurality of bit lines located on the cell region; A plurality of gate structures are located on the peripheral region; A first dielectric layer, located between adjacent gate structures; a plurality of connectors, located in the first dielectric layer and connected to the substrate; A plurality of storage node contact structures are located between adjacent bit lines; A plurality of capacitor structures are located on the storage node contact structure; a hard mask layer covering a top surface of the connector; The second dielectric layer includes a first portion located above the hard mask layer and a second portion located above the storage node contact structure, wherein a vertex of the first portion of the second dielectric layer and a vertex of the second portion are located at different levels.

2. A semiconductor device, characterized in that: include: A substrate including a cell region and a peripheral region; A plurality of bit lines located on the cell region; A plurality of gate structures are located on the peripheral region; A first dielectric layer, located between adjacent gate structures; a plurality of connectors, located in the first dielectric layer and connected to the substrate; A plurality of storage node contact structures are located between adjacent bit lines; A plurality of capacitor structures are located on the storage node contact structure; a hard mask layer covering a top surface of the connector; The second dielectric layer covers the hard mask layer and directly contacts the top surface of the connecting element and the side wall of the capacitor structure.

3. The semiconductor device according to claim 1, wherein: The apex of the first portion of the second dielectric layer is higher than the apex of the second portion.

4. The semiconductor device according to claim 1, wherein: An apex of the hard mask layer is higher than an apex of the second portion of the second dielectric layer.

5. The semiconductor device according to claim 1 or 2, characterized in that: The hard mask layer includes a first sub-mask covering the connector and a second sub-mask covering the storage node contact structure, and a vertex of the first sub-mask is higher than a vertex of the second sub-mask.

6. The semiconductor device according to claim 1 or 2, characterized in that: The hard mask layer is completely isolated from a top surface of the storage node contact structure.

7. The semiconductor device according to claim 1 or 2, characterized in that: The method further includes a third dielectric layer located above the gate structure and between adjacent connecting members, wherein a top point of the third dielectric layer is lower than a top point of the hard mask layer.

8. The semiconductor device according to claim 5, characterized in that The hard mask layer directly contacts a top surface of the connector and a sidewall of the capacitor structure.

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