Memory package, operating components and computing devices

Abstract

The embodiment of the present application provides a memory package, a working component and a computing device, including: a substrate; at least one memory module, arranged on one side of the substrate, the memory module including a first die and a plurality of second dies; wherein the first die is arranged on one side of the substrate, and the plurality of second dies are arranged on a side of the first die away from the substrate in a direction parallel to the substrate; one of the first die and the second die is a memory die, and the other is a logic processing die; the sum of the orthographic projection areas of the plurality of second dies on the substrate is less than or equal to the orthographic projection area of ​​the first die on the substrate. The technical solution of the embodiment of the present application can achieve ultra-large computing power and ultra-high storage bandwidth by providing a 3D packaging solution.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a memory package, a working component and a computing device. Background Art

[0002] On the one hand, with the improvement of semiconductor manufacturing technology, transistor density is approaching its limit, which brings about problems such as heat generation, serious power consumption, and nonlinear increase in manufacturing costs. The improvement of semiconductor manufacturing technology nodes has slowed down and entered the "post-Moore era", and advanced packaging has become an important way to continue Moore's Law.

[0003] On the other hand, as the application scenarios of high-performance computing continue to expand, higher requirements are placed on the performance of computing chips. In related technologies, the memory wall is also a major challenge to traditional computing performance. Near-memory computing is a solution proposed to solve the memory wall problem. It improves computing performance by reducing the path length between the processor and the memory and increasing the path bandwidth. The improvement of chip technology and performance has driven the demand for advanced packaging. Utility Model Content

[0004] Embodiments of the present application provide a memory package, a working component, and a computing device to solve or alleviate one or more technical problems in the prior art.

[0005] As one aspect of an embodiment of the present application, an embodiment of the present application provides a memory package, comprising: a substrate; at least one memory module, the memory module comprising a first bare chip and a plurality of second bare chips; wherein the first bare chip is arranged on one side of the substrate, and the plurality of second bare chips are arranged on a side of the first bare chip away from the substrate in a direction parallel to the substrate; one of the first bare chip and the second bare chip is a memory bare chip, and the other is a logic processing bare chip; the sum of the orthographic projection areas of the plurality of second bare chips on the substrate is less than or equal to the orthographic projection area of ​​the first bare chip on the substrate.

[0006] In one embodiment, the plurality of second dies are arranged in rows and columns, and the plurality of second dies include second dies connected to each other in a first direction, wherein the first direction is a row direction or a column direction.

[0007] In one embodiment, the plurality of second dies further include second dies connected to each other in a second direction, wherein the second direction forms an angle with the first direction in a direction parallel to the substrate.

[0008] In one embodiment, during the packaging process, adjacent second dies are physically and / or electrically connected via wafer dicing lines.

[0009] In one embodiment, the second die and the first die are connected to each other by hybrid bonding, or the second die and the first die are connected to each other by micro bumps.

[0010] In one embodiment, a circuit element semiconductor layer is disposed between the plurality of second dies and the first die, and the circuit element semiconductor layer includes a filling medium and a plurality of circuit element dies surrounded by the filling medium.

[0011] In one embodiment, the multiple second bare chips are arranged in a one-to-one correspondence with the multiple circuit element bare chips, the orthographic projection of the second bare chip on the substrate covers the orthographic projection of the corresponding circuit element bare chip on the substrate, and the interconnection area between the second bare chip and the first bare chip is located outside the circuit element bare chip.

[0012] As one aspect of an embodiment of the present application, an embodiment of the present application provides a working component, including a memory package in any implementation manner of the embodiment of the present application and a printed circuit board, wherein the memory package is arranged on one side of the printed circuit board.

[0013] As one aspect of an embodiment of the present application, an embodiment of the present application provides a computing device, including a working component and a power supply module in any implementation manner of the embodiment of the present application.

[0014] The technical solution of the embodiment of the present application provides a 3D packaging solution for memory, which can stack a first die and a second die vertically while stacking multiple second dies in the horizontal direction, thereby reducing the chip area, achieving ultra-large computing power and ultra-high storage bandwidth, while achieving shorter interconnection distance and higher interconnection density.

[0015] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0017] Figure 1 A structural diagram of a memory package according to an embodiment of the present application is shown;

[0018] Figure 2A , Figure 2B , Figure 2C and Figure 2D A schematic diagram showing different topologies of a second die of a memory package according to an embodiment of the application;

[0019] Figure 3A and Figure 3B A structural diagram of a memory package according to an embodiment of the present application is shown;

[0020] Figure 3C A structural diagram showing a memory package in a packaging process according to an embodiment of the present application;

[0021] Figure 4A and Figure 4B A structural diagram of a memory package according to an embodiment of the present application is shown;

[0022] Figure 4C A structural diagram showing a memory package in a packaging process according to an embodiment of the present application;

[0023] Figure 5 A structural diagram of a memory package according to an embodiment of the present application is shown;

[0024] Fig. 6A and Figure 6B A structural diagram of a memory package according to an embodiment of the present application is shown;

[0025] Fig. 7A , Figure 7B , Figure 7C and Fig.7D A structural diagram of a memory package according to an embodiment of the present application is shown;

[0026] Figure 8 A structural diagram of working components according to an embodiment of the present application is shown.

[0027] Description of reference numerals:

[0028] 20: substrate;

[0029] 100: memory module; 101: first bare chip; 102: second bare chip;

[0030] 103: TSV; 104: C4 bump; 105: micro bump;

[0031] 110: RDL interposer; 106: RDL medium; 107: RDL wiring layer; 301: cutting path;

[0032] 200: circuit element semiconductor layer; 201: circuit element bare chip; 202: filling medium;

[0033] 30: PCB board; 50: connecting wire; 109: solder ball;

[0034] 40: Memory package. DETAILED DESCRIPTION

[0035] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0036] Application Scenario

[0037] As technology develops, the integration of chips becomes higher and higher, and the performance is constantly improving. However, as technology further develops, it becomes more and more challenging to integrate more functions and components on a single chip, which also increases the cost and complexity of manufacturing.

[0038] In order to overcome these challenges, the concept of chip modules (chiplets) began to emerge in the field of semiconductor manufacturing technology. A chiplet can be understood as a small, independent chip module, which usually contains a specific functional unit or processing unit. Unlike traditional single chips, chiplets split the entire system into multiple smaller and more focused parts. These chiplets can be designed, manufactured and tested independently, and then combined together in a package to form a complete functional system or processing system to achieve higher flexibility, performance optimization and cost reduction design and manufacturing methods. Chiplets are an innovative solution to the challenges of complexity and cost in the context of continuous improvement in chip technology and performance.

[0039] Under the technical concept of chiplet, 2.5D packaging solutions have emerged, such as chip-on-wafer-on-substrate (CoWoS). In an exemplary CoWoS solution, the logic processing die and the high bandwidth memory (HBM) stack can be integrated together to present a 3D package. The CoWoS solution usually arranges multiple HBM stacks around the Logic die to provide excellent computing and memory performance. Among them, the Logic die is the core computing unit of the CoWoS packaged chip, which contains a large number of graphics processing units (GPUs) for high-performance computing tasks; the HBM stack uses 3D stacking technology to stack multiple memory chip components together and communicate through silicon through holes (TSV) to provide high-bandwidth and low-latency memory access.

[0040] The CoWoS solution allows multiple chips with different functions to be integrated into a single package, providing higher performance and efficiency. However, compared with other packaging solutions with the same computing power and bandwidth, the chip packaging area of ​​its CoWoS solution will also be larger, and the power consumption and cost may be higher.

[0041] Therefore, mature 3D packaging technology is urgently needed in the field of memory packaging to achieve ultra-large computing power and ultra-high storage bandwidth without increasing the chip packaging area. The embodiment of the present application aims to provide a 3D packaging solution, which can stack a first die and a second die vertically while stacking multiple second dies in the horizontal direction, thereby reducing the chip area, ultra-large computing power and ultra-high storage bandwidth, while achieving shorter interconnection distance and higher interconnection density.

[0042] Figure 1 Schematic diagram of the memory package provided by the embodiment of the present application is shown. Figure 1 As shown, the memory package includes a substrate 20 and at least one memory module 100 , and the memory module 100 is arranged on one side of the substrate 20 .

[0043] The substrate 20 is used as a packaging substrate, and its material includes an organic substrate, a ceramic substrate, a sapphire substrate, etc. Different applications and requirements may select different types of materials, which are not limited in the embodiments of the present application.

[0044] The memory module 100 includes a first die 101 and a second die 102 . One of the first die 101 and the second die 102 is a memory die, and the other is a logic processing die.

[0045] The memory die may be a chip die of any type of memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NVRAM), flash memory, or electrically erasable programmable read-only memory (EEPROM). Exemplarily, the memory die may be a customized chip die or a standardized chip die, which is not limited in the embodiments of the present application.

[0046] The logic processing die may be a chip die responsible for the logic processing function. Exemplarily, the logic processing die may include a memory control unit, may include a processor unit, or may include a memory control unit and a processor unit. Wherein, the processor unit is, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processor (DPU), or a knowledge processor (KPU), a tensor processor (TPU), an intelligent processor (IPU), a reconfigurable dataflow unit (Reconfigurable Dataflow Unit), a neural network processor (NPU) or other types of processors (Any type Processing Unit, xPU), responsible for executing instructions and performing various calculations and data processing tasks, including simple arithmetic operations and complex logical operations, so as to realize functions such as calculation, control, and decision-making. The memory control unit is responsible for managing and coordinating part of the memory access, such as converting the memory operation requested by the processor into the operation of the memory, and ensuring the correct transmission and storage of data to achieve efficient memory access and data transmission.

[0047] Further, the first die 102 is arranged on one side of the substrate 20, and the plurality of second die 102 are arranged on the side of the first die 101 away from the substrate 20 in a direction parallel to the substrate 20. In the embodiment of the present application, in a memory module 100, there is one first die 101 and multiple second die 102, and the number of the second die 102 can be 2, 3, 4, 8, etc., which can be configured according to the application scenario and actual needs, and the embodiment of the present application does not limit this.

[0048] Exemplarily, the sum of the orthographic projection areas of the plurality of second dies 102 on the substrate 20 is less than or equal to the orthographic projection area of ​​the first die 101 on the substrate 20. In other words, the packaging method of the embodiment of the present application is applicable to the case where the area of ​​the first die 101 is much larger than the area of ​​the second die 102, so that the plurality of second dies 102 can be horizontally extended or horizontally arranged on the same side of the first die 101.

[0049] In the memory package provided in the embodiment of the present application, the memory module is a 3D packaging method based on the chiplet concept, which can stack the first die and the second die vertically while stacking multiple second dies in the horizontal direction, thereby realizing infinite stacking and customized stacking of memory dies and logic processing dies, thereby achieving expansion of storage bandwidth and improvement of computing power performance.

[0050] It should also be noted that compared with the CoWoS solution, the stacking method used by the memory module can achieve shorter interconnection distance and higher interconnection density while saving chip area, greatly improving interconnection efficiency and chip performance.

[0051] It should be noted that in the embodiments of the present application, interconnection (interconnection, referred to as interconnection) refers to the electrical connection between electronic components, chips, bare chips, circuit boards, etc., so as to transmit power and signals. For example, transistors on a chip are connected to other transistors, resistors, capacitors and other components through interconnection to form a complete circuit to achieve the required functions. At the same time, the chip also needs to be connected to the circuit board, other chips or systems through interconnection to receive power and input signals and send output signals.

[0052] Exemplarily, the memory package provided in the embodiments of the present application can be used in high-performance computing chips, sensor chips, micro-electro-mechanical systems (MEMS), optical communication chips, etc. It should be noted that the above application scenarios or application examples provided in the embodiments of the present application are for ease of understanding, and the embodiments of the present application do not specifically limit the application of the memory package.

[0053] It should be noted that in the embodiments of the present application, a chip (Chip) is a small silicon wafer (or other semiconductor materials) on which multiple electronic components (such as transistors, capacitors, resistors, etc.) and circuit connections are integrated. These components and connections form a complex circuit that can perform various functions, thereby achieving tasks such as computing, storage, control, and signal processing. That is, the chip is a highly integrated electronic device. A die (Die) refers to an unpackaged, single chip. In the chip manufacturing process, many identical chips are usually manufactured on a silicon wafer (or other materials), and each chip contains a specific circuit design and function. After test cutting, the silicon wafer forms a bare die, which can be further packaged into a finished chip or used for other applications.

[0054] The following describes the horizontal expansion of the plurality of second dies 102, that is, the arrangement of the plurality of second dies 102 on the side of the first die 101 away from the substrate 20. It should be noted that in the embodiment of the present application, the horizontal direction is a direction parallel to the substrate 20.

[0055] In one embodiment, the plurality of second dies 102 are arranged in rows and columns, that is, in the horizontal direction, the plurality of second dies 102 may be arranged in a single row, such as Figure 2A ; The plurality of second bare chips 102 may also be arranged in a single row, such as Figure 2B As shown; the plurality of second dies 102 may also be arranged in multiple rows and columns, such as Figure 2C As shown. Figure 2A , Figure 2B and Figure 2C In FIG. 1 , the row direction is represented by X, and the column direction is represented by Y. Therefore, a suitable arrangement can be adaptively configured according to the area difference between the first die 101 and the second die 102 to enrich the application scenarios of the memory module 100 .

[0056] In one example, the plurality of second dies 102 include second dies connected to each other in a first direction, wherein the first direction is a row direction X or a column direction Y. That is, there are adjacent die modules connected to each other in the plurality of second dies 102, so that the second dies that need to establish an interconnection relationship can be configured as adjacent positions in the row direction X or the column direction Y, or in other words, the adjacent second dies 102 can be connected to each other in the row direction X or the column direction Y, such as Figure 2A , Figure 2B or Figure 2C shown.

[0057] In another example, the plurality of second dies 102 may further include second dies connected to each other in a second direction, wherein the second direction Z forms an angle with the first direction in a direction parallel to the substrate 20, such as an angle of 135 degrees. Figure 2D shown.

[0058] It should be noted that the memory package may include multiple memory modules 100, and the multiple memory modules 100 are arranged on one side of the substrate 20 to facilitate horizontal expansion of the memory modules 100. The embodiments of the present application do not limit the horizontal expansion method and the method of interconnection of the memory modules 100, and can be configured according to actual needs.

[0059] The following describes in detail the interconnection method used by the memory package with specific embodiments. The listed specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0060] Embodiment 1

[0061] like Figure 3A and Figure 3B As shown, when the area of ​​the memory die is much larger than that of the logic processing die, which is sufficient to stack multiple logic processing dies horizontally on the memory die, the first die 101 is the memory die, represented as DRAM, and the second die 102 is the logic processing die, represented as Logic.

[0062] First, the logic processing wafer can be cut into individual logic processing dies; then, multiple cut logic processing dies are regarded as a unit, and the number of logic processing dies in each unit is equal and unlimited, and each unit is evenly placed on the memory wafer; then, the memory wafer is cut, so that after the memory wafer is cut, each memory die will correspond to a unit, that is, each memory die will correspond to an equal number of logic processing dies, which is convenient for production management.

[0063] As an optional implementation, during the packaging process, adjacent second dies 102 are physically and / or electrically connected via wafer scribe lines 301. That is, adjacent logic processing dies are physically and / or electrically connected via wafer scribe lines 301. Figure 3C Specifically, first, the multiple logic processing dies to be cut on the logic processing wafer can be regarded as a unit, and the adjacent logic processing dies in each unit are physically and / or electrically connected through the wafer cutting road 301, and then the logic processing wafer is cut in units of each unit. After the logic processing wafer is cut, the memory wafer is cut, and the same number of logic processing dies can be corresponding to each memory die.

[0064] Among them, wafer scribe lines 301 are lines used to separate individual integrated circuit chips (also called bare chips or dies) during semiconductor manufacturing. These lines are pre-marked on the wafer to indicate where to cut the wafer to separate the individual chips. The scribe lines usually do not contain any circuit elements because they may be damaged during the cutting process. However, they may contain test structures for testing and monitoring the process.

[0065] In one example, the second die 102 and the first die 101 may be connected to each other by hybrid bonding. In other words, each logic processing die may be connected to the memory die by hybrid bonding.

[0066] Specifically, a surface chemical reaction can be used to create a very strong atomic-level connection between the second die 102 and the first die 101, so that the die can be accurately aligned and connected at the micrometer scale on the wafer. Hybrid bonding can usually achieve the transmission of electrical signals and data without the use of solder or conductive materials, thereby reducing the loss of signal transmission. Due to the very close connection, high-density stacking can be achieved through hybrid bonding, thereby achieving more functions in a smaller package size.

[0067] In another example, the second die 102 and the first die 101 may be connected to each other via microbumps. Figure 3A and Figure 3B As shown, each logic processing die can be connected to the memory die via micro bumps 105.

[0068] The micro bump is a tiny protruding structure, usually made of metal material, so as to form mutual connection and communication between the second die 102 and the first die 101. Moreover, this structure is usually manufactured by microelectronics process, and its size, position and arrangement can be precisely controlled to achieve high-density connection.

[0069] Exemplarily, each logic processing die is connected to the memory wafer by micro-bump or hybrid bonding, and then the memory wafer is cut; in this way, the interconnection signals between the memory die and the logic processing die can be directly connected.

[0070] In one embodiment, after the first die 101 and the second die 102 are connected to each other, the remaining signals of the first die 101 and the remaining signals of the second die 102 can be connected to the substrate 20. Figure 3AAs shown, a through silicon via (TSV) 103 is provided in the first die 101 for interconnecting the second die 102 and the substrate 20. That is, the signal in the logic processing die can be connected to the substrate 20 through the TSV 103.

[0071] Exemplarily, a controlled collapse chip connection bump (Controlled Collapse Chip Connection, C4 bump or C4 bump for short) 104 is arranged between the memory die and the substrate 20, and each logic processing die connects the signal to TSV103 through a micro bump (ubump) or hybrid bonding (Hybrid Bonding), and the signal in TSV103 is connected to the substrate 20 through the C4 bump 104.

[0072] In one embodiment, Figure 3B As shown, a TSV 103 is provided in the first die 101, a redistribution layer (RDL) interposer 110 is provided on the side of the first die 101 facing the substrate 20, a C4 bump 104 is provided on the side of the RDL interposer 110 facing the substrate 20, and a signal in the TSV 103 is connected to the substrate 20 through the RDL interposer 110 and the C4 bump 104. In other words, the signal in the logic processing die can be connected to the substrate 20 through the TSV 103, the RDL interposer 110 and the C4 bump 104.

[0073] The RDL interposer 110 includes an RDL medium 106 and an RDL wiring layer 107 in the RDL medium 106. The RDL medium 106 is usually made of organic materials; the common material of the RDL wiring layer 107 is electroplated copper (Plated Cu) supplemented with a titanium and copper sputtering layer as a primer; the surface of the copper layer is then covered with a corresponding protective layer ink as needed.

[0074] Exemplarily, the RDL wiring layer 107 is used to connect the signal in the TSV 103 to the C4 bump 104, thereby connecting the signal of the memory die to the substrate 20 and connecting the logic processing die to the substrate 20, or realizing the interconnection between the memory die and the substrate 20, or realizing the interconnection between the logic processing die and the substrate 20, and enabling high-density, high-speed signal transmission.

[0075] Furthermore, in the first embodiment of the present application, the first die 101 is a memory die (represented as DRAM in the figure), and the second die 102 is a logic processing die (represented as Logic in the figure). The second die 102 (logic processing die) may be interconnected, thereby increasing the computing power and storage bandwidth of the chip.

[0076] like Figure 3A and 3B As shown, the interconnection signals between the second dies 102 can be connected to the first die 101 through micro bumps 105 or hybrid bonding, so that the second dies 102 can be connected to each other based on the first die 101.

[0077] like Figure 3A and 3B As shown, the interconnection signals between the second dies 102 can be connected to the TSV103 in the first die 101 through micro bumps 105 or hybrid bonding, and then connected to the C4 bumps through TSV103, and then connected to the substrate 20, so that the second dies 102 can be interconnected based on the substrate 20.

[0078] like Figure 3B As shown, the interconnection signals between the second dies 102 can be connected to the TSV 103 in the first die 101 through micro bumps 105 or hybrid bonding, and then connected to the RDL interposer 110 through the TSV 103, so that the second dies 102 can be interconnected based on the RDL interposer 110.

[0079] like Figure 3B As shown, the interconnection signals between the second dies 102 can be connected to the TSV 103 in the first die 101 through micro bumps 105 or hybrid bonding, and then connected to the RDL interposer 110 through TSV 103, and then connected to the substrate 20 through C4 bumps, so that the second dies 102 can be interconnected based on the substrate 20.

[0080] The above provides a variety of interconnection modes between the second dies 102 when the second dies 102 are logic processing dies, so that the configuration can be selected according to actual needs to expand the application scenarios and use scope of the chip.

[0081] Embodiment 2

[0082] like Figure 4A and Figure 4B As shown, when the area of ​​the logic processing die is much larger than that of the memory die, which is sufficient to stack multiple memory dies horizontally on the logic processing die, the first die 101 is the logic processing die, denoted as Logic, and the second die 102 is the memory die, denoted as DRAM.

[0083] First, the memory wafer can be cut into individual memory dies; then, multiple cut memory dies are regarded as a unit, and the number of memory dies in each unit is equal and unlimited, and each unit is evenly placed above the logic processing wafer; then, the logic processing wafer is cut, so that after the logic processing wafer is cut, each logic processing die will correspond to a unit, that is, each logic processing die will correspond to an equal number of memory dies, which is convenient for production management.

[0084] As an optional implementation, during the packaging process, adjacent second dies 102 are physically and / or electrically connected via wafer dicing lanes 301. That is, adjacent memory dies are physically and / or electrically connected via wafer dicing lanes 301. Figure 4C Specifically, first, the multiple memory dies to be cut on the memory wafer can be regarded as a unit, and the adjacent memory dies in each unit are physically and / or electrically connected through the wafer cutting road 301, and then the memory wafer is cut in units of each unit. After the cutting of the memory wafer is completed, the logic processing wafer is cut, and the same number of memory dies can be corresponding to each logic processing die.

[0085] In one example, the second die 102 and the first die 101 may be connected to each other by hybrid bonding. In other words, each memory die may be connected to the logic processing die by hybrid bonding.

[0086] Specifically, surface chemical reactions can be used to create a very strong atomic-level connection between the memory die and the logic processing die, so that the memory die and the logic processing die can be precisely aligned and connected at the micron scale on the wafer, and the transmission of electrical signals and data between the memory die and the logic processing die can be achieved without the use of solder or conductive materials, thereby reducing the loss of signal transmission between the memory die and the logic processing die.

[0087] In another example, the second die 102 and the first die 101 may be connected to each other via microbumps. Figure 4A and Figure 4B As shown, each memory die can be connected to the logic processing die through micro bumps 105, so that the interconnection position and arrangement can be precisely controlled to achieve high-density connection.

[0088] Exemplarily, each memory die is connected to the logic processing wafer by micro-bump or hybrid bonding, and then the logic processing wafer is cut; in this way, the interconnection signals between the logic processing die and the memory die can be directly connected.

[0089] In one embodiment, after the first die 101 and the second die 102 are connected to each other, the remaining signals of the first die 101 and the remaining signals of the second die 102 can be connected to the substrate 20. Figure 4A As shown, a TSV 103 is provided in the first die 101 for interconnecting the second die 102 and the substrate 20. That is, the signal in the memory die can be connected to the substrate 20 through the TSV 103.

[0090] Exemplarily, a C4 bump 104 is disposed between the logic processing die and the substrate 20 , and a signal of each memory die is connected to the TSV 103 , and a signal in the TSV 103 is connected to the substrate 20 through the C4 bump 104 .

[0091] In one embodiment, Figure 4B As shown, a TSV 103 is provided in the logic processing die, an RDL interposer 110 is provided on the side of the logic processing die facing the substrate 20 , and a C4 bump 104 is provided on the side of the RDL interposer 110 facing the substrate 20 . The signal in the TSV 103 is connected to the substrate 20 through the RDL interposer 110 and the C4 bump 104 .

[0092] Based on this, the signal of the memory die can be connected to the substrate 20 and the logic processing die can be connected to the substrate 20, or the memory die and the substrate 20 can be interconnected, or the logic processing die and the substrate 20 can be interconnected, and high-density and high-speed signal transmission can be achieved.

[0093] In one embodiment, a plurality of memory modules 100 may be arranged above the substrate 20. In the memory module 100, the first die 101 is a logic processing die (Logic), and the second die 102 is a memory die (DRAM), that is, a plurality of logic processing dies may be arranged above the substrate 20, and there may be interconnected logic processing dies among the plurality of logic processing dies. The embodiment of the present application does not limit the interconnection mode between the logic processing dies, for example, the interconnection may be achieved through the substrate 20, or through the RDL interposer between the logic processing die and the substrate 20, or through the RDL interposer between the logic processing die and the substrate 20 and the C4 bump 104.

[0094] Embodiment 3

[0095] This embodiment provides a memory package. Compared with the first and second embodiments, in this embodiment, the memory package further includes a circuit element semiconductor layer, wherein the technical solutions and corresponding technical effects in the first and second embodiments can be fully or partially referenced to this embodiment.

[0096] like Figure 5 As shown, the memory package of the embodiment of the present application further includes a circuit element semiconductor layer 200 disposed between the plurality of second dies 102 and the first die 101 . The circuit element semiconductor layer 200 includes a filling medium 202 and a plurality of circuit element dies 201 surrounded by the filling medium 202 .

[0097] Exemplarily, the material of the filling medium 202 may be a molding material, an underfill material, or other materials used for protective filling, including organic materials or inorganic materials, as long as the filling medium 202 can protect the circuit element die 201 .

[0098] The circuit element die 201 may be a Deep Trench Capacitor (DTC) die. DTC is a capacitor whose capacitance value can be controlled by a digital signal and is widely used in the design of radio frequency and microwave frequency circuits, such as high frequency filters, oscillators, etc.

[0099] The circuit element die 201 may also be a resistance-inductance-capacitance (RLC) die. The RLC die is an RLC circuit implemented by semiconductor technology and can be used for filters, tuning circuits, oscillators, impedance matching, power management, noise elimination, etc.

[0100] In one implementation, the plurality of second dies 102 are arranged in one-to-one correspondence with the plurality of circuit element dies 201 , and therefore, the horizontal expansion method of the plurality of second dies 102 is also applicable to the circuit element dies 201 .

[0101] In order to reduce the chip area or package volume, in the embodiment of the present application, the orthographic projection of the second die 102 on the substrate 20 covers the orthographic projection of the corresponding circuit element die 201 on the substrate 20 .

[0102] In one embodiment, the second die 102 and the circuit element die 201 are connected to each other by hybrid bonding, or the second die 102 and the circuit element die 201 are connected to each other by micro bumps 105. Fig. 6A shown.

[0103] In one example, when the area of ​​the memory die is much larger than that of the logic processing die and is sufficient to stack multiple logic processing dies horizontally on the memory die, the first die 101 is the memory die and the second die 102 is the logic processing die.

[0104] First, the logic processing wafer is cut into single logic processing dies, and each circuit element die 201 is interconnected with the logic processing die through micro-bumps 105 or hybrid bonding. Each logic processing die and circuit element die 201 can be regarded as an integral unit, and interconnected on the memory wafer through micro-bumps 105 on the logic processing die or hybrid bonding. Each memory die formed by cutting the memory wafer can be connected to multiple such units, and the number is not limited. Then, the area between the logic processing die and the circuit element die 201 is filled with a filling medium 202, wherein the micro-bumps 105 or hybrid bonding interface of the logic processing die will not be covered by the filling medium 202. Then, the memory wafer is cut, and each memory die after cutting will be connected to the same number of units, that is, multiple logic processing dies and circuit element dies 201 are interconnected on each memory die.

[0105] The logic processing die connects the signals to the memory die through micro bumps 105 or hybrid bonding, and the interconnected signals can be directly connected; the remaining signals are connected to the C4 bumps through the TSV 103 in the memory die, and then connected to the substrate by the C4 bumps.

[0106] In another example, when the area of ​​the logic processing die is much larger than that of the memory die, and is sufficient to stack multiple memory dies horizontally on the logic processing die, the first die 101 is the logic processing die, and the second die 102 is the memory die. The corresponding interconnection method can be referred to the above description, which will not be repeated here.

[0107] In another interconnection method, the first die 101 and the circuit element die 201 are interconnected by hybrid bonding, or the first die 101 and the circuit element die 201 are interconnected by micro bumps 105. Figure 6B shown.

[0108] In one example, when the area of ​​the memory die is much larger than that of the logic processing die, and is sufficient to stack multiple logic processing die horizontally on the memory die, the first die 101 is the memory die, and the second die 102 is the logic processing die. Wherein, the circuit element die 201 is interconnected with the memory die by means of micro-bumps 105 or hybrid bonding, and after the logic processing die is interconnected with the memory die by means of micro-bumps 105 or hybrid bonding, the area between the logic processing die and the circuit element die 201 is filled with a filling medium 201, wherein the micro-bumps 105 or hybrid bonding interface of the logic processing die will not be covered by the filling medium 201; then, the memory wafer is cut, and each memory die after the cutting is completed is connected to the same number of units. The remaining signals are connected to the C4 bumps through the TSV103 in the memory die, and then connected to the substrate by the C4 bumps.

[0109] Furthermore, in this example, when the first die 101 is a memory die and the second die 102 is a logic processing die, the second die 102 (logic processing die) may be interconnected, thereby increasing the computing power and storage bandwidth of the chip.

[0110] like Fig. 7A , 7B As shown in 7C and 7D, the interconnection signals between the second dies 102 can be connected to the first die 101 through micro bumps 105 or hybrid bonding, so that the second dies 102 can be interconnected based on the first die 101.

[0111] like Fig. 7A and 7B As shown, the interconnection signals between the second dies 102 can be connected to the TSV103 in the first die 101 through micro bumps 105 or hybrid bonding, and then connected to the C4 bumps through TSV103, and then connected to the substrate 20, so that the second dies 102 can be interconnected based on the substrate 20.

[0112] like Figure 7C and 7D As shown, the interconnection signals between the second dies 102 can be connected to the TSV 103 in the first die 101 through micro bumps 105 or hybrid bonding, and then connected to the RDL interposer 110 through the TSV 103, so that the second dies 102 can be interconnected based on the RDL interposer 110.

[0113] like Figure 7C and 7DAs shown, the interconnection signals between the second dies 102 can be connected to the TSV 103 in the first die 101 through micro bumps 105 or hybrid bonding, and then connected to the RDL interposer 110 through TSV 103, and then connected to the substrate 20 through C4 bumps, so that the second dies 102 can be interconnected based on the substrate 20.

[0114] The above provides a variety of interconnection modes between the second bare chips 102, so that the configuration can be selected according to actual needs to expand the application scenarios and use scope of the chip.

[0115] In another example, when the area of ​​the logic processing die is much larger than that of the memory die and is sufficient to stack multiple memory dies horizontally on the logic processing die, the first die 101 is the logic processing die and the second die 102 is the memory die.

[0116] It can be seen that in the above embodiment, the projection of the first die 101 on the substrate 20 covers the projection of the circuit element die 201 on the substrate 20, and the projection of the second die 102 on the substrate 20 also covers the projection of the circuit element die 201 on the substrate 20, that is, compared with the second die 102, the circuit element die 201 is centrally arranged, so that the interconnection area between the second die 102 and the first die 101 is located on the outside (periphery or periphery) of the circuit element die 201. Therefore, this compact positioning method ensures that the interconnection between the die will not lead to additional packaging volume increase.

[0117] Embodiment 4

[0118] like Figure 8 As shown, an embodiment of the present application provides a working component, including a printed circuit board (PCB) 30 and a memory package 40, wherein at least one memory package 40 is arranged on one side of the PCB 30.

[0119] The memory package 40 may be any of the memory packages described in the above application scenarios or embodiments. It should be noted that the working component may include one memory package or multiple memory packages, and the embodiment of the present application does not specifically limit the type, quantity, and interconnection topology of the memory package 40.

[0120] Exemplarily, the memory package 40 can be directly arranged on one side of the PCB board 30 without molding the memory package 40 , that is, the memory module 100 does not need to be plastic-encapsulated on the side of the substrate 20 away from the PCB board 30 .

[0121] Exemplarily, the memory package 40 is connected to the PCB board 30 via the solder balls 109 , so that the memory modules inside different memory packages 40 are connected to each other on the PCB board 30 .

[0122] There may be multiple memory packages 40, and there are interconnected memory packages among the multiple memory packages 40. For example, a mutual connection relationship can be established between adjacent memory packages through a PCB board 30, thereby realizing PCB board-level interconnection between the memory packages 40.

[0123] In one embodiment, the memory packages 40 are interconnected on the PCB board 30 via connecting wires 50. Exemplarily, the connecting wires 50 may be any type of interconnection intellectual property (IP) components or modules such as Peripheral Component Interconnect Express (PCIE), Serializer / Deserializer (Serdes), Universal Chiplet Interconnect Express (UCIe), Compute Express Link (CXL), Remote Direct Memory Access (RDMA), Ethernet, etc.

[0124] According to the working components provided in the embodiments of the present application, the disadvantages of small storage bandwidth and small computing power of traditional packaging solutions can be avoided, and advanced packaging technology can be provided to increase storage bandwidth, thereby improving chip computing power.

[0125] Other components of the memory package or working components of the above embodiments may adopt various technical solutions known to ordinary technicians in the field now and in the future, and will not be described in detail here.

[0126] Embodiment 5

[0127] The embodiment of the present application further provides a computing device, including any working component of the above embodiment and a power supply module, wherein the power supply module is used to provide power to the working component, and the number of the working components can be one or more, which is not limited in the embodiment of the present application. Exemplarily, at least some of the multiple working components are interconnected, which can be electrically connected or physically connected, which is not limited in the embodiment of the present application.

[0128] Illustratively, the computing device provided in the embodiments of the present application can be used in devices and systems that require a large amount of computing power, such as supercomputers, servers in data centers, high-performance workstations, scientific research equipment, etc., and can be applied in the fields of artificial intelligence, deep learning, big data analysis, etc.

[0129] Illustratively, the computing device provided in the embodiments of the present application can be used in various devices that need to monitor and measure physical or chemical changes, such as smart phones, automobiles, industrial automation equipment, medical equipment, and other fields that require high-performance sensor chips.

[0130] Illustratively, the computing device provided in the embodiments of the present application can be used in micro-electromechanical systems, such as gyroscopes and accelerometers of smartphones, airbag triggering systems of cars, micro-lens arrays of projectors, etc.

[0131] Illustratively, the computing device provided in the embodiments of the present application can be used in fiber-optic communication systems, such as fiber-optic network equipment, optical interconnection in data centers, long-distance fiber-optic transmission systems, and other fields that require high-speed data transmission.

[0132] When the computing device is used in different systems or fields, other components of the computing device may be different. Other components of the computing device in the above embodiment may adopt various technical solutions known to ordinary technicians in this field now and in the future, which will not be described in detail here.

[0133] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0134] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0135] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0136] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0137] The disclosure above provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0138] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory package, characterized in that: include: substrate; at least one memory module, the memory module comprising a first die and a plurality of second dies; The first die is arranged on one side of the substrate, and the plurality of second dies are arranged on a side of the first die away from the substrate in a direction parallel to the substrate; one of the first die and the second die is a memory die, and the other is a logic processing die; The sum of the orthographic projection areas of the plurality of second die on the substrate is less than or equal to the orthographic projection area of ​​the first die on the substrate.

2. The memory package according to claim 1, wherein: The plurality of second bare chips are arranged in rows and columns, and the plurality of second bare chips include second bare chips connected to each other in a first direction, wherein the first direction is a row direction or a column direction.

3. The memory package according to claim 2, wherein: The plurality of second dies also include second dies connected to each other in a second direction, wherein the second direction forms an angle with the first direction in a direction parallel to the substrate.

4. The memory package according to claim 1, wherein: During the packaging process, adjacent second dies are physically and / or electrically connected via wafer dicing lines.

5. The memory package according to claim 1, wherein: The second die and the first die are connected to each other by hybrid bonding, or the second die and the first die are connected to each other by micro bumps.

6. The memory package according to any one of claims 1 to 5, characterized in that: A circuit element semiconductor layer is disposed between the plurality of second dies and the first die, and the circuit element semiconductor layer includes a filling medium and a plurality of circuit element dies surrounded by the filling medium.

7. The memory package according to claim 6, wherein: The plurality of second dies are arranged in one-to-one correspondence with the plurality of circuit element dies, and the orthographic projections of the second dies on the substrate cover the orthographic projections of the corresponding circuit element dies on the substrate.

8. The memory package according to claim 7, wherein: The interconnection area between the second die and the first die is located outside the circuit element die.

9. A working component, characterized in that: include: The memory package according to any one of claims 1 to 8; A printed circuit board is provided on one side of which the memory package is arranged.

10. A computing device, characterized in that: It comprises the working component and power supply module as described in claim 9.

Images