A semiconductor device
By setting an auxiliary field plate between the gate electrode and the drain electrode of the gallium nitride HEMT device, the problem of low breakdown voltage caused by the spike electric field when the gate electrode is turned off is solved, and higher breakdown voltage and better reliability are achieved.
Patent Information
- Application Number
- CN202421307368.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-07
- Publication Date
- 2025-04-01
- Estimated Expiration
- 2034-06-07
AI Technical Summary
GaN HEMT devices will form a spike electric field when the gate electrode is turned off, resulting in a low breakdown voltage. There are reliability problems or process complexity in the prior art methods.
A first auxiliary field plate is provided between the gate electrode and the drain electrode, and the first auxiliary field plate is connected to the gate electrode. This structure weakens the peak electric field near the gate pin of the drain electrode and increases the breakdown voltage of the device.
By setting up an auxiliary field plate, the peak electric field under the gate is effectively weakened, the breakdown voltage of the device is improved, the reliability problem is alleviated, and the process is simplified.
Smart Images
Figure CN222706891U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of microelectronics manufacturing, and more specifically, to a semiconductor device. Background Art
[0002] Gallium nitride (GaN) is favored in the field of high-speed and high-power devices due to its advantages such as high critical breakdown electric field, high concentration of two-dimensional electron gas, high electron mobility and good high-temperature working ability. At present, high electron mobility transistor HEMT (or heterojunction field effect transistor HFET) based on AlGaN / GaN heterojunction has been initially commercialized.
[0003] When the gate electrode of a gallium nitride HEMT device is turned off, a spike electric field will be formed at the gate foot near the drain. In order to weaken the intensity of the spike electric field and increase the breakdown voltage of the device, there are two methods in the existing technical means to solve the problem. First, a method of combining a T-shaped gate with P-GaN is used to form p-GaN on both sides of the gate electrode. The p-GaN layer stretches the energy band of the AlGaN barrier layer below, thereby affecting the electric field distribution at the edge of the gate electrode. Combined with the effect of the T-shaped gate field plate, the electric field peak near the edge of the gate electrode on the drain side is reduced to increase the breakdown voltage of the device. Second, a source field plate array field plate is used to set a number of field plates inside or above the passivation layer structure between the gate electrode and the drain. The field plates form an array with each other to evenly balance the spike electric field. The former P-GaN has poor reliability due to its high doping concentration and is prone to reliability problems; the latter has a small spacing between the gate and the drain. If the field plate size is set too large, multiple field plates cannot be set, and the effect is limited. If the field plate size is set too small, the complexity of the process is increased. Utility Model Content
[0004] The embodiments of the present application provide a semiconductor device that can weaken the peak electric field under the gate and increase the breakdown voltage of the device.
[0005] A semiconductor device provided in this application adopts the following technical solution:
[0006] A semiconductor device, comprising:
[0007] Basal layer;
[0008] A source electrode, a drain electrode and a gate electrode, all of which are disposed on the base layer, and the gate electrode is located between the drain electrode and the source electrode and connected to the base layer;
[0009] A first auxiliary field plate is disposed between the gate electrode and the drain electrode, and the first auxiliary field plate is connected to the gate electrode, and there is a gap between the first auxiliary field plate and the base layer;
[0010] An insulating dielectric layer is disposed on the surface of the base layer and covers the source electrode, the drain electrode, the gate electrode, and the first auxiliary field plate.
[0011] Optionally, the base layer includes a substrate and an epitaxial layer. The insulating dielectric layer is located on the end face of the epitaxial layer away from the substrate, and the gate electrode is in Schottky contact with the epitaxial layer.
[0012] Optionally, a second auxiliary field plate is further included. The second auxiliary field plate is disposed between the gate electrode and the source electrode, and the second auxiliary field plate is connected to the gate electrode. There is a gap between the second auxiliary field plate and the base layer.
[0013] Optionally, the distance between the first auxiliary field plate and / or the second auxiliary field plate and the epitaxial layer is less than the distance between the gate cap of the gate electrode and the epitaxial layer.
[0014] Optionally, the first auxiliary field plate and the second auxiliary field plate are located on both sides of the gate electrode and are symmetrically arranged.
[0015] Optionally, the first auxiliary field plate and the second auxiliary field plate are respectively disposed at both ends of the gate electrode, and both the first auxiliary field plate and the second auxiliary field plate are in direct contact with the gate electrode.
[0016] Optionally, the first auxiliary field plate and the second auxiliary field plate are connected to the gate electrode through an opening in the dielectric. The first auxiliary field plate and the second auxiliary field plate enclose an accommodation cavity, and the gate electrode is located in the accommodation cavity.
[0017] Optionally, the gate electrode, the first auxiliary field plate, and the second auxiliary field plate are integrally formed.
[0018] Optionally, the insulating dielectric layer includes an insulating base layer. The insulating base layer is disposed close to the base layer. The insulating base layer is provided with a first gate etching region and an auxiliary field plate etching region. The thickness of the insulating base layer is y, the depth of the first gate etching region is x (0 < x < y), and the depth of the auxiliary field plate etching region is y - x.
[0019] Optionally, the insulating base layer is provided with a second gate etching region and a third gate etching region. Along a first direction, the length of the second gate etching region is k2, the distances between the second gate etching region and the two side auxiliary field plate etching regions are j1 and j2 respectively, and the length of the third gate etching region is g. Then g > k2 + j1 + j2. The first direction points from the source electrode to the drain electrode.
[0020] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:
[0021] When the gate electrode is turned off, a spike electric field is formed at the gate foot near the drain electrode. By setting a first auxiliary field plate between the gate electrode and the drain electrode, the first auxiliary field plate is connected to the gate electrode, and the electric field strength of the first auxiliary field plate in the epitaxial layer close to the drain electrode is increased. At this time, the peak electric field at the gate foot close to the drain electrode is weakened to weaken the intensity of the peak electric field at the gate foot close to the drain electrode, alleviate the spike electric field under the gate, and increase the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 It is a cross-sectional view of the overall structure of Example 1 of a semiconductor device disclosed in the embodiments of the present application;
[0023] Figure 2 A schematic diagram highlighting a first gate etching region in Example 1 of a semiconductor device disclosed in an embodiment of the present application;
[0024] Figure 3 This is a schematic diagram highlighting the second gate etching region and the auxiliary field plate etching region of Example 1 of a semiconductor device disclosed in the embodiments of the present application;
[0025] Figure 4 A schematic diagram highlighting the third gate etching region of Example 1 of a semiconductor device disclosed in the embodiments of the present application;
[0026] Figure 5 This is a cross-sectional view of the overall structure of Example 2 of a semiconductor device disclosed in the embodiments of the present application.
[0027] Description of reference numerals:
[0028] 1. Base layer; 2. Source electrode; 3. Drain electrode; 4. Gate electrode; 5. First auxiliary field plate; 6. Second auxiliary field plate; 7. Insulating dielectric layer; 71. Insulating base layer; 72. First gate etching region; 73. Second gate etching region; 74. Third gate etching region; 75. Auxiliary field plate etching region. DETAILED DESCRIPTION
[0029] The present application is further described in detail below in conjunction with the accompanying drawings.
[0030] The embodiments of the present application provide a semiconductor device that can weaken the peak electric field under the gate and increase the breakdown voltage of the device.
[0031] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0032] The terms "first", "second", "third", "fourth", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0033] For ease of understanding, the semiconductor device in the embodiment of the present application is described below. Figure 1 An embodiment of the semiconductor device in the embodiment of the present application includes: a base layer 1, a source electrode 2, a drain electrode 3, a gate electrode 4 and an insulating dielectric layer 7; the source electrode 2, the drain electrode 3 and the gate electrode 4 are all arranged on the base layer 1, and the gate electrode 4 is located between the drain electrode 3 and the source electrode 2 and connected to the base layer 1; the insulating dielectric layer 7 is arranged on the surface of the base layer 1 and covers the source electrode 2, the drain electrode 3 and the gate electrode 4.
[0034] See also Figure 2 In this embodiment, the base layer 1 includes a substrate and an epitaxial layer, the insulating dielectric layer 7 is located on the end surface of the epitaxial layer away from the substrate, and the gate electrode 4 is in Schottky contact with the epitaxial layer; the gate electrode 4 is a T-shaped gate.
[0035] Please continue reading Figure 1 When the gate electrode 4 is turned off, a spike electric field will be formed at the gate foot close to the drain electrode 3. In order to weaken the intensity of the spike electric field at the gate foot close to the drain electrode 3, the gate electrode 4 is provided with a first auxiliary field plate 5. The first auxiliary field plate 5 is provided between the gate electrode 4 and the drain electrode 3, and the first auxiliary field plate 5 is connected to the gate electrode 4. There is a gap between the first auxiliary field plate 5 and the epitaxial layer. By providing the first auxiliary field plate 5 between the gate electrode 4 and the drain electrode 3, the first auxiliary field plate 5 is connected to the gate electrode 4 to weaken the intensity of the spike electric field at the gate foot close to the drain electrode 3, relieve the spike electric field under the gate, and improve the device breakdown voltage.
[0036] Further, the gate electrode 4 is provided with a second auxiliary field plate 6. The second auxiliary field plate 6 is disposed between the gate electrode 4 and the source electrode 2, and the second auxiliary field plate 6 is connected to the gate electrode 4. There is a gap between the second auxiliary field plate 6 and the epitaxial layer, so as to weaken the intensity of the peak electric field at the gate foot near the source electrode 2. The setting of the first auxiliary field plate 5 and / or the second auxiliary field plate 6 reduces the series resistance of the gate electrode 4 and increases the maximum oscillation frequency. The distance between the first auxiliary field plate 5 and / or the second auxiliary field plate 6 and the epitaxial layer is less than the distance between the gate cap of the gate electrode 4 and the epitaxial layer. Since the first auxiliary field plate 5 and / or the second auxiliary field plate 6 is closer to the surface of the epitaxial layer, the gate control ability is improved, the leakage current in the off state is smaller, and the switching ratio is increased.
[0037] In this embodiment, the first auxiliary field plate 5 and the second auxiliary field plate 6 are located on both sides of the gate electrode 4 and are symmetrically arranged. The first auxiliary field plate 5 and the second auxiliary field plate 6 are respectively disposed at both ends of the gate electrode 4, and both the first auxiliary field plate 5 and the second auxiliary field plate 6 are in direct contact with the gate electrode 4. In other embodiments, the first auxiliary field plate 5 and the second auxiliary field plate 6 are located on both sides of the gate electrode 4, and the distances between the first auxiliary field plate 5 and the second auxiliary field plate 6 and the base layer 1 are different.
[0038] Please refer to Figures 2 to 4 , the insulating dielectric layer 7 includes an insulating base layer 71 and an insulating surface layer. The insulating base layer 71 is disposed close to the base layer 1. The setting of the insulating base layer 71 is for facilitating the setting of the gate electrode 4, the first auxiliary field plate 5, and the second auxiliary field plate 6. The insulating surface layer and the insulating base layer 71 jointly wrap each electrode to protect each electrode and prevent the semiconductor device from short - circuiting. The gate electrode 4, the first auxiliary field plate 5, and the second auxiliary field plate 6 are obtained by filling after multiple etching processes on the insulating base layer 71.
[0039] Specifically, the thickness of the insulating base layer 71 is y. The insulating base layer 71 is provided with a first gate etching area 72, and the first gate etching area 72 is used to determine the setting position of the gate electrode 4. The first gate etching area 72 is obtained by developing the first photoresist coating on the insulating base layer 71. After etching, the depth of the first gate etching area 72 is x (0 < x < y). In this embodiment, the second gate etching area 73 and the auxiliary field plate etching area 75 are set synchronously. The second gate etching area 73 and the auxiliary field plate etching area 75 are obtained by developing the second photoresist coating on the insulating base layer 71. There are two auxiliary field plate etching areas 75. After etching, the auxiliary field plate etching areas 75 are used to fill materials to form the first auxiliary field plate 5 and the second auxiliary field plate 6. The depth of the auxiliary field plate etching area 75 is y - x, that is, the thickness of the first auxiliary field plate 5 and the second auxiliary field plate 6 is y - x.
[0040] Furthermore, the insulating base layer 71 is subjected to a third photoresist coating and development to obtain a third gate etched area 74, which is used for subsequent gate cap production. The first direction is from the source electrode 2 to the drain electrode 3. Along the first direction, the length of the first gate etched area 72 is k1, the length of the second gate etched area 73 is k2, and the length of the third gate etched area 74 is g. In this embodiment, k2 ≥ k1, the depth of the second gate etched area 73 is yx, and the second gate etched area 73 is etched to expose the surface of the epitaxial layer, so that the formed gate electrode 4 is in Schottky contact with the epitaxial layer.
[0041] The spacing between the second gate etching area 73 and the auxiliary field plate etching areas 75 on both sides is j1 and j2, respectively. In order to ensure that the gate electrode 4 is electrically connected to the first auxiliary field plate 5 and the second auxiliary field plate 6, g>k2+j1+j2. In this embodiment, the gate electrode 4 is integrally formed with the first auxiliary field plate 5 and the second auxiliary field plate 6. In other embodiments, the gate electrode 4, the first auxiliary field plate 5 and the second auxiliary field plate 6 can also be separately formed according to actual needs. The materials of the gate electrode 4, the first auxiliary field plate 5 and the second auxiliary field plate 6 are set according to actual needs and are not limited here.
[0042] See also Figure 5 In another embodiment, different from the present embodiment, the first auxiliary field plate 5 and the second auxiliary field plate 6 are connected to the gate electrode 4 through the dielectric opening, and the first auxiliary field plate 5 and the second auxiliary field plate 6 enclose a receiving cavity, and the gate electrode 4 is located in the receiving cavity. It is more advantageous to be applied to devices with small gate lengths. By setting the first auxiliary field plate 5 and the second auxiliary field plate 6, the T-shaped gate is completely wrapped in the first auxiliary field plate 5 and the second auxiliary field plate 6, thereby increasing the cross-sectional area and reducing the gate resistance.
[0043] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor device, characterized in that: Comprising: A base layer (1); A source electrode (2), a drain electrode (3), and a gate electrode (4), all of which are disposed on the base layer (1), and the gate electrode (4) is located between the drain electrode (3) and the source electrode (2) and is connected to the base layer (1); A first auxiliary field plate (5), disposed between the gate electrode (4) and the drain electrode (3), and the first auxiliary field plate (5) is connected to the gate electrode (4), and there is a gap between the first auxiliary field plate (5) and the base layer (1); An insulating dielectric layer (7), disposed on the surface of the base layer (1) and covering the source electrode (2), the drain electrode (3), the gate electrode (4), and the first auxiliary field plate (5).
2. A semiconductor device according to claim 1, characterized in that: The base layer (1) includes a substrate and an epitaxial layer, the insulating dielectric layer (7) is located on the end face of the epitaxial layer away from the substrate, and the gate electrode (4) is in Schottky contact with the epitaxial layer.
3. A semiconductor device according to claim 2, characterized in that: It further includes a second auxiliary field plate (6), the second auxiliary field plate (6) is disposed between the gate electrode (4) and the source electrode (2), and the second auxiliary field plate (6) is connected to the gate electrode (4), and there is a gap between the second auxiliary field plate (6) and the base layer (1).
4. A semiconductor device according to claim 3, characterized in that: The distance between the first auxiliary field plate (5) and / or the second auxiliary field plate (6) and the epitaxial layer is less than the distance between the gate cap of the gate electrode (4) and the epitaxial layer.
5. A semiconductor device according to claim 3, characterized in that: The first auxiliary field plate (5) and the second auxiliary field plate (6) are located on both sides of the gate electrode (4) and are symmetrically arranged.
6. A semiconductor device according to claim 5, characterized in that: The first auxiliary field plate (5) and the second auxiliary field plate (6) are respectively disposed at both ends of the gate electrode (4), and both the first auxiliary field plate (5) and the second auxiliary field plate (6) are in direct contact with the gate electrode (4).
7. A semiconductor device according to claim 5, characterized in that: The first auxiliary field plate (5) and the second auxiliary field plate (6) are connected to the gate electrode (4) through an opening between dielectrics, and the first auxiliary field plate (5) and the second auxiliary field plate (6) enclose a receiving cavity, and the gate electrode (4) is located in the receiving cavity.
8. A semiconductor device according to claim 3, characterized in that: The gate electrode (4) is integrally formed with the first auxiliary field plate (5) and the second auxiliary field plate (6).
9. A semiconductor device according to claim 3, characterized in that: The insulating dielectric layer (7) includes an insulating base layer (71), the insulating base layer (71) is disposed close to the base layer (1), the insulating base layer (71) is provided with a first gate etching area (72) and an auxiliary field plate etching area (75), the thickness of the insulating base layer (71) is y, the depth of the first gate etching area (72) is x, where 0 < x < y, and the depth of the auxiliary field plate etching area (75) is y - x.
10. A semiconductor device according to claim 9, characterized in that: The insulating base layer (71) is provided with a second gate etching region (73) and a third gate etching region (74); along the first direction, the length of the second gate etching region (73) is k2; the spacings between the second gate etching region (73) and the auxiliary field plate etching regions (75) on both sides are j1 and j2 respectively; the length of the third gate etching region (74) is g, and g>k2+j1+j2; the first direction is directed from the source electrode (2) to the drain electrode (3).