SiC device for improving long-term use reliability of device

Abstract

The utility model discloses a SiC device capable of improving long-term use reliability, and relates to the technical field of semiconductors. According to the utility model, a layer of thicker oxide is formed at the bottom of the trench of the trench gate SiC MOSFET by adopting a medium deposition mode, the coupling area between the gate and drain electrodes of the device is reduced, the gate-drain capacitance of the device is reduced, the switching performance is improved, and the deposited oxide fills the corners of the bottom of the trench gate oxide, so that the reliability of the device is improved. The phenomenon of breakdown failure caused by electric field concentration easily caused by a gate oxide layer of a conventional trench gate SiC MOSFET is avoided, and the long-term use reliability of the device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC device capable of improving the long-term use reliability of the device. Background Art

[0002] Compared with silicon materials, the advantages of silicon carbide (SiC) materials make them more suitable for applications such as high voltage, high temperature, and high frequency. Therefore, SiC MOSFET, as a voltage-controlled device, is often used as a switch tube in rectifiers and inverters. In order to better exert the efficiency of power conversion, reducing the power consumption of power devices has become the current focus. During the use of SiCMOSFET devices, power consumption will be generated during the conduction and switching processes. In low-frequency applications, static power consumption is the main factor, and an effective measure is to reduce the device's specific on-resistance. In high-frequency applications, the switching loss of the device accounts for the main part, and the excessively high di / dt can easily cause the SiC MOSFET device to be turned on by mistake. Therefore, reducing parasitic capacitance and gate charge is an effective way to reduce the dynamic power consumption of SiCMOSFET devices.

[0003] The parasitic capacitance of SiC MOSFET includes gate-source capacitance C GS , gate-drain capacitance C GD and drain-source capacitance C DS , among which the gate-drain capacitance C has a significant impact on the switching characteristics GD In practical applications, the gate-drain capacitance C is usually minimized. GD To achieve better switching performance of the device, the most commonly used methods are:

[0004] (1) Increase the thickness of the gate dielectric to reduce the gate-drain capacitance;

[0005] (2) Reduce the coupling area between the gate and drain electrodes, thereby reducing the gate-drain capacitance.

[0006] In trench gate SiC MOSFET devices, since they have smaller chip size and higher power density than planar gate MOS, how to reduce the gate-drain capacitance of trench gate SiC MOSFET and thus reduce its switching power consumption is of great benefit to its practical application.

[0007] In view of the above problems, in the existing patent documents, such as the "Structure and method for forming a thick bottom dielectric (TBD) for a trench gate device" published on April 30, 2014, the application number is: 201410005313.6; a mask is used to form multiple trenches in a semiconductor region. The mask includes (i) a first insulating layer on the surface of the semiconductor region, (ii) a first oxidation barrier layer on the first insulating layer, and (iii) a second insulating layer on the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents the formation of a dielectric layer along the surface of the semiconductor region during the formation of the TBD. Although the patent forms a thick dielectric layer at the bottom of the trench well, the patent uses the first insulating layer as a mask layer on the sidewalls and corners of the trench, which can easily cause the deposited thick dielectric layer to fail to cover the corner position at the bottom of the trench, forming defects such as holes.

[0008] In the existing patent literature, such as the "A shielded gate device structure and its manufacturing method" applied for and published on August 19, 2022, with application number 2022106174887, it includes a substrate of a first doping type, an epitaxial layer of the first doping type located on one side of the substrate, a trench located in the epitaxial layer, a first dielectric layer located on the inner wall of the trench, a gate electrode and a shielding electrode located in the trench, wherein the shielding electrode is located under the gate electrode, a second dielectric layer between the shielding electrode and the first dielectric layer, and a dielectric layer between the gate electrode and the shielding electrode. Although the patent improves the electric field concentration at the bottom of the trench gate oxide and the gate-drain capacitance Cgd, the design of two layers of dielectric plus shielding electrode in the patent has obvious problems such as complex process and high production cost. Utility Model Content

[0009] The utility model designs a SiC device which reduces the coupling area and gate-drain capacitance between the gate and drain electrodes of the device, avoids the breakdown failure phenomenon caused by the electric field concentration at the gate oxide layer of the conventional trench gate SiCMOSFET, and improves the long-term reliability of the device.

[0010] The technical solution of the utility model is:

[0011] SiC devices that improve long-term reliability of devices include an N+Sub layer, an N-Drift layer, an ohmic contact alloy layer, and a front electrode metal layer arranged in sequence from bottom to top;

[0012] The N-Drift layer includes:

[0013] P-base region;

[0014] An N+ region, located on the top surface of the P-base region;

[0015] A P+ region extending downward from the top surface of the N+ region to a P-base region;

[0016] A trench region is located in the middle of the N+ region and extends downward from the top surface of the N+ region to below the P-base region; an oxide layer is provided at the bottom of the trench region, and a gate oxide layer connected to the oxide layer, the P-base region and the N+ region is provided in the trench region, and the trench region is filled with a polysilicon Poly layer, and the polysilicon Poly layer is connected to the oxide layer and the gate oxide layer respectively; the oxide layer is located below the P-base region;

[0017] The front electrode metal layer and the ohmic contact alloy layer are separated from the trench area by isolation dielectric layers respectively; the trench area isolation dielectric layer extends outward from the top surface of the trench to the N+ area and contacts the side surface of the ohmic contact alloy layer.

[0018] Specifically, the thickness of the oxide is 0.5um-1um.

[0019] Specifically, the gate oxide layer (8) has a thickness of 60 nm to 70 nm.

[0020] Specifically, the sputtered metal is Ni, and the thickness is 100 nm.

[0021] Specifically, the sputtered metal is Ti or AlSiCu, and has a thickness of 100nm-5000nm.

[0022] The utility model forms a thicker oxide layer at the bottom of the trench by depositing dielectric in the trench gate SiC MOSFET device, which reduces the coupling area between the gate and drain electrodes of the device, thereby reducing the gate-drain capacitance of the device and improving the switching performance. In addition, the deposited oxide fills the bottom corner of the trench gate oxide, avoiding the phenomenon that the gate oxide layer of the conventional trench gate SiC MOSFET is prone to cause electric field concentration and breakdown failure, thereby improving the long-term reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a structural schematic diagram of step S100 of the utility model;

[0024] Figure 2 It is a structural schematic diagram of step S200 of the utility model;

[0025] Figure 3 It is a structural schematic diagram of step S300 of the utility model;

[0026] Figure 4 It is a structural schematic diagram of step S400 of the utility model;

[0027] Figure 5It is a schematic diagram of the structure of step S500 of the utility model;

[0028] Figure 6 It is a structural schematic diagram of step S600 of the utility model;

[0029] Figure 7 It is a structural schematic diagram of step S700 of the utility model;

[0030] Figure 8 It is a structural schematic diagram of step S800 of the utility model;

[0031] Fig. 9 It is a structural schematic diagram of step S900 of the utility model;

[0032] Fig.10 It is a structural schematic diagram of step S1000 of the utility model;

[0033] Fig.11 It is a structural schematic diagram of step S1100 of the utility model;

[0034] In the figure, 1 is the N+Sub layer, 2 is the N-Drift layer, 3 is the P-base region, 4 is the N+ region, 5 is the P+ region, 6 is the trench region, 7 is the oxide, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0035] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0036] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0037] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] A method for preparing a SiC device for improving the long-term reliability of the device comprises the following steps:

[0039] S100, refer to Figure 1 As shown, an N-Drift layer 2 is epitaxially grown on the N+Sub layer 1;

[0040] In this case, the concentration of N-Drift layer 2 is 5E15cm -2 -1E16cm -2 .

[0041] S200, refer to Figure 2 As shown, a P-base region 3 is formed on the N-Drift layer 2 by Al ion implantation;

[0042] The P-base region 3 in step S200 has an N+ region 4 and a P+ region 5 inside, wherein the concentration of the P-base region 3 is 1E17cm -2 -1E18cm -2 .

[0043] S300, refer to Figure 3 As shown, an N+ region 4 is formed on the P-base region 3 by N ion implantation;

[0044] S400, refer to Figure 4 As shown, a P+ region 5 extending into the P-base region 3 is formed on the N+ region 4 by Al ion implantation;

[0045] The bottom of the P+ region 5 is located in the P-base region 3, achieving the same potential among the N+ region, the P+ region, and the P-base region, and forming a PN junction diode at the same time.

[0046] S500, refer to Figure 5 As shown, a trench region 6 extending into the N-Drift layer 2 is formed by etching downward on the top surface of the N+ region 4;

[0047] S600, refer to Figure 6 As shown, a layer of oxide 7 is formed at the bottom of the trench by depositing a dielectric in the trench region 6;

[0048] The thickness of the oxide 7 in step S600 is 0.5um-1um;

[0049] The distance between the bottom of the trench region 6 and the bottom of the P-base region 3 is ≥1 um to ensure that the deposited oxide 7 is below the P-base region and that a channel is formed in the device.

[0050] S700, reference Figure 7 As shown, a gate oxide layer 8 connected to the oxide 7 is grown on the sidewall of the trench by dry oxygen oxidation;

[0051] The thickness of the gate oxide layer in step S700 is 60 nm-70 nm to improve the reliability of the gate oxide layer of the device.

[0052] S800, reference Figure 8 As shown, a Poly layer 9 is formed inside the trench region by depositing polysilicon;

[0053] The bottom of the Poly layer 9 in step S800 is in contact with the oxide 7 , and the side surface is in contact with the gate oxide layer 6 .

[0054] S900, refer to Fig. 9 As shown, an isolation dielectric layer 10 connected to the N+ region 4 and the gate oxide layer 8 is deposited on the top surface of the Poly layer 9 to prevent the gate electrode and the source electrode of the device from contacting and forming a short circuit;

[0055] S1000, refer to Fig.10 As shown, on the side of the Poly layer 9, an ohmic contact alloy layer 11 connected to the N+ region 4 and the P+ region 5 respectively is formed by metal sputtering and then annealing;

[0056] The sputtered metal in step S1000 is Ni, and the thickness is 100 nm.

[0057] S1100, reference Fig.11 As shown, a front electrode metal layer is formed again on the device by metal sputtering;

[0058] The sputtered metal in step S1100 is Ti / AlSiCu with a thickness of 100 nm / 5000 nm.

[0059] A SiC device for improving the long-term reliability of the device comprises an N+Sub layer 1, an N-Drift layer 2, an ohmic contact alloy layer 11 and a front electrode metal layer 12 arranged in sequence from bottom to top;

[0060] The N-Drift layer 2 includes:

[0061] P-base region 3;

[0062] N+ region 4, located on the top surface of the P-base region 3;

[0063] A P+ region 5 extending downward from the top surface of the N+ region 4 to the P-base region 3;

[0064] A trench region 6 is located in the middle of the N+ region 4 and extends downward from the top surface of the N+ region 4 to below the P-base region 3; an oxide layer 7 is provided at the bottom of the trench region 6, and a gate oxide layer 8 connected to the oxide layer 7 is provided on the inner sidewall of the trench region 6; the trench region 6 is filled with a polysilicon Poly layer 9, and the polysilicon Poly layer 9 is respectively connected to the oxide layer 7 and the gate oxide layer 8;

[0065] The front electrode metal layer 12 and the ohmic contact alloy layer 11 are separated from the trench area 6 by an isolation dielectric layer 10 ; the trench area isolation dielectric layer 10 extends outward from the top surface of the trench to the N+ area 4 and contacts the side surface of the ohmic contact alloy layer 11 .

[0066] Beneficial effects of the utility model:

[0067] 1. Improve the switching performance of the device and reduce the switching power consumption: SiC MOSFET has internal parasitic capacitance that affects the switching performance of the device, among which the gate-drain capacitance C has the most significant impact. GD This utility model patent deposits oxide at the bottom of the trench of the trench gate SiC MOSFET by depositing dielectric, which reduces the coupling area between the gate and drain electrodes of the device. Compared with conventional trench gate SiC MOSFET, the coupling area can be reduced by 60%-80%, so the gate-drain capacitance of the device can also be reduced by 60%-80%, thereby improving the switching performance of the device and reducing the switching power consumption.

[0068] 2. Improve the reliability of the device: The corner at the bottom of the trench of the trench gate SiC MOSFET is prone to electric field concentration due to the curvature effect, and the SiC material itself has a large interface state density and poor quality in the gate oxide layer grown by oxidation. Therefore, during use, the gate oxide layer at the corner at the bottom of the trench is prone to premature breakdown failure, affecting the long-term reliability of the device. The oxide deposited at the bottom of the trench of the trench gate SiC MOSFET in this utility model completely fills the corner, avoiding the growth of the gate oxide layer here, and the quality of the deposited oxide is better, thereby reducing the probability of premature breakdown failure at this point during use of the device, thereby improving the reliability of the device.

Claims

1. A SiC device for improving the long-term reliability of the device, characterized in that: It comprises an N+Sub layer (1), an N-Drift layer (2), an ohmic contact alloy layer (11) and a front electrode metal layer (12) which are arranged in sequence from bottom to top; The N-Drift layer (2) includes: P-base region (3); An N+ region (4) located on the top surface of the P-base region (3); A P+ region (5) extending downward from the top surface of the N+ region (4) to the P-base region (3); A trench region (6) is located in the middle of the N+ region (4) and extends downward from the top surface of the N+ region (4) to below the P-base region (3); an oxide layer (7) is provided at the bottom of the trench region (6); a gate oxide layer (8) is provided in the trench region (6) and is connected to the oxide layer (7), the P-base region (3) and the N+ region (4) respectively; the trench region (6) is filled with a polysilicon Poly layer (9), and the polysilicon Poly layer (9) is connected to the oxide layer (7) and the gate oxide layer (8) respectively; the oxide layer (7) is located below the P-base region (3); The front electrode metal layer (12) and the ohmic contact alloy layer (11) are respectively separated from the groove area (6) by an isolation dielectric layer (10); the groove area isolation dielectric layer (10) extends outward from the top surface of the groove to the N+ area (4) and contacts the side surface of the ohmic contact alloy layer (11).

2. The SiC device for improving the long-term reliability of the device according to claim 1, characterized in that: The thickness of the oxide (7) is 0.5 um-1 um.

3. The SiC device for improving the long-term reliability of the device according to claim 1, characterized in that: The gate oxide layer (8) has a thickness of 60nm-70nm.

4. The SiC device for improving the long-term reliability of the device according to claim 1, characterized in that: The sputtered metal is Ni, and the thickness is 100 nm.

5. The SiC device for improving the long-term reliability of the device according to claim 1, characterized in that: The sputtered metal is Ti or AlSiCu, and has a thickness of 100nm-5000nm.

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