Optoelectronic device with photodiode comprising quantum dot material

Abstract

The present disclosure relates to an optoelectronic device having a photodiode comprising a quantum dot material. Some embodiments described herein include a complementary metal oxide semiconductor image sensor device for an image detection system used in a low-light environment. The complementary metal oxide semiconductor image sensor device comprises a photodiode used for detecting near-infrared light waves and / or short-wave infrared light waves. The photodiode includes a layer of quantum dot material and a transparent electrode over the layer of quantum dot material. In addition to the photodiode having improved quantum efficiency relative to a silicon-based photodiode, the photodiode is also integrated within a filter array structure to eliminate the need to separate a separate visible light complementary metal oxide semiconductor image sensor device in an image detection system.

Description

Technical Field

[0001] The present disclosure relates to an optoelectronic device having a photodiode including quantum dot material. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) image sensor may include a plurality of pixel sensors. A pixel sensor of a CMOS image sensor may include a transfer transistor, which may include a photodiode for converting incident light photons into electron photocurrent and a transfer gate for controlling the flow of the photocurrent between the photodiode and a drain region. The drain region may be used to receive the photocurrent so that the photocurrent may be measured and / or transferred to other areas of the CMOS image sensor. Utility Model Content

[0003] Some embodiments described in the present disclosure provide an optoelectronic device. The optoelectronic device includes a first photodiode, which includes: a semiconductor material layer and a p-type dopant or an n-type dopant located in the semiconductor material layer. The device includes a second photodiode, which includes: a quantum dot material layer; a first conductive material layer located above the quantum dot material layer and in contact with the quantum dot material layer; and a second conductive material layer located below the quantum dot material layer and in contact with the quantum dot material layer.

[0004] Some embodiments described in the present disclosure provide an optoelectronic device. The optoelectronic device includes an array of metal pillar structures. The device includes a photodiode located above the outline of the array of metal pillar structures. The photodiode includes a first conductive material layer that conforms to the outline of the array of metal pillar structures; a quantum dot material layer located on the first conductive material layer; and a second conductive material layer located on the quantum dot material.

[0005] Some embodiments described in the present disclosure provide an optoelectronic device, including a photodiode, wherein the photodiode includes a layer of a first conductive material disposed along a contour of a metal pillar located above a deep trench isolation structure included in the optoelectronic device, a layer of a quantum dot material located on the layer of the first conductive material, and a layer of a second conductive material located on the layer of the quantum dot material, wherein the second conductive material is transparent to near infrared light or short-wave infrared light. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a diagram of an exemplary environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2A and Figure 2B is a diagram of an embodiment of an exemplary optoelectronic device including a pixel sensor array described herein;

[0009] Figure 3 is a diagram of an exemplary optoelectronic device described herein;

[0010] FIG. 4A to FIG. 4O For forming Figure 3 A series of diagrams illustrating exemplary operations of an optoelectronic device;

[0011] Figure 5 is a diagram of an exemplary optoelectronic device described herein;

[0012] Figure 6 is a diagram of an exemplary optoelectronic device described herein;

[0013] 7A to 7I To form Figure 5 Figure 1 is a diagram of an exemplary embodiment of an optoelectronic device;

[0014] Figure 8 For the purpose described in this article Figure 1 diagrams of exemplary elements of one or more devices;

[0015] Fig. 9 is a flow chart of an exemplary process associated with forming an optoelectronic device having a photodiode including quantum dot material.

[0016]

Explanation of symbols

[0017] 100: Environment

[0018] 102:Deposition tools

[0019] 104:Exposure Tools

[0020] 106: Development Tools

[0021] 108: Etching tools

[0022] 110: Flattening tool

[0023] 112:Electroplating tools

[0024] 114:Ion implantation tool

[0025] 116:Joining tool

[0026] 118: Wafer / die transport tool

[0027] 200,300,500,600: Photoelectric devices

[0028] 202: Pixel sensor array

[0029] 204a-204d: Pixel sensor

[0030] 206: Application Specific Integrated Circuit (ASIC) Device

[0031] 208: System-on-Chip Integrated Circuit (SoC) Device

[0032] 210: filter layer

[0033] 212,220,220a,220b,220c,220d: Photodiode

[0034] 214, 214a, 214b, 214c, 214d: quantum dot material layer

[0035] 216,218: Conductive material layer

[0036] 302:Substrate

[0037] 304a, 304b: semiconductor material layer

[0038] 306a, 306b: Gate structure

[0039] 308a, 308b: dielectric region

[0040] 310a, 310b: Interconnection structure

[0041] 312a, 312b: metallization layer

[0042] 314a, 314b: source / drain region

[0043] 318: Shallow Trench Isolation Region (STI Region)

[0044] 320,508:Oxide layer

[0045] 322,504:DTI structure

[0046] 324: High Absorption Area (HA Area)

[0047] 326:BSI oxide layer

[0048] 328: Buffer oxide layer

[0049] 330: Bonding pad

[0050] 332: Microlens layer

[0051] 400,700: Implementation method

[0052] 402,404,406,408: Cavity

[0053] 502: substrate layer

[0054] 506:ARC layer

[0055] 510: Column structure array

[0056] 512: ground node

[0057] 702,704: Photoresist layer

[0058] 800: Device

[0059] 810: Bus

[0060] 820: Processor

[0061] 830: Memory

[0062] 840: Input element

[0063] 850: Output element

[0064] 860: Communication components

[0065] 900: Craftsmanship

[0066] 910,920,930: Blocks

[0067] D1: Thickness DETAILED DESCRIPTION

[0068] The following disclosure provides many different embodiments or exemplary embodiments for realizing the different features of the provided subject matter. The specific exemplary embodiments of the components and configurations described below are for simplifying the disclosure. Of course, these are exemplary only and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the disclosure may repeat reference numerals and / or letters in various exemplary embodiments. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0069] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0070] In some cases, complementary metal oxide semiconductor (CMOS) image sensor (CIS) devices utilize light-sensitive CMOS circuitry to convert light energy into electrical energy. In such cases, the light-sensitive CMOS circuitry includes a photodiode formed in a silicon substrate. When the photodiode is exposed to light, a charge (referred to as a photocurrent) is induced in the photodiode. Additionally, in such cases, a switching transistor coupled to the photodiode is used to sample the charge of the photodiode. Color is determined by placing a filter above the light-sensitive CMOS circuitry.

[0071] CIS devices in low-light applications include dedicated pixels with silicon-based photodiodes for absorbing reflected near infrared (NIR) light waves or short-wave infrared (SWIR) light waves. Such silicon-based photodiodes may have low quantum efficiency (QE) performance. Solutions to improve the NIR / SWIR QE performance of silicon-based photodiodes (such as high absorption (HA) structures, deep trench isolation (DTI) structures and / or thicker silicon) increase the complexity of manufacturing CIS devices and reduce the yield of CIS devices relative to another CIS device that does not include such solutions. In addition, the silicon-based photodiodes for absorbing NIR / SWIR light waves consume additional space within the CIS device.

[0072] Some embodiments described herein include a CIS device for an image detection system used in a low-light environment. The CIS device includes a photodiode for detecting NIR and / or SWIR light waves. The photodiode includes a quantum dot material layer and a transparent electrode located above the quantum dot material layer. In addition to the photodiode having an improved QE relative to silicon-based photodiodes, the photodiode is also integrated into a filter array structure to eliminate the need for a separate visible light (VIS) CIS device in the image detection system.

[0073] In this way, the performance (e.g., NIR / SWIR QE) of a CIS device that includes a photodiode is improved relative to another CIS device that does not include a photodiode. Improving the performance of the CIS device increases the manufacturing yield of the CIS device to a certain performance threshold. By improving the manufacturing yield and eliminating the need for a separate VIS device, the amount of resources (e.g., semiconductor manufacturing tools, labor, raw materials, and / or computing resources) required to support a market that consumes a large number of image detection systems with NIR / SWIR and VIS light detection capabilities is reduced.

[0074] Figure 1 FIG. 1 is a diagram of an exemplary environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown in , environment 100 may include multiple semiconductor processing tools 102-116 and wafer / die transport tools 118. Multiple semiconductor processing tools 102-116 may include deposition tools 102, exposure tools 104, development tools 106, etching tools 108, planarization tools 110, plating tools 112, ion implantation tools 114, bonding tools 116 and / or another type of semiconductor processing tool. The tools included in the exemplary environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility and / or a manufacturing facility, among other exemplary.

[0075] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer onto a substrate such as a wafer. In some embodiments, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, exemplary environment 100 includes multiple types of deposition tools 102 .

[0076] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source such as an ultraviolet (UV) source (e.g., a deep UV light source, an extreme UV (EUV) source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 may expose the photoresist layer to the radiation source to transfer a pattern from a mask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0077] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving exposed or unexposed portions of the photoresist layer using a chemical developer.

[0078] The etching tool 108 is a semiconductor processing tool capable of etching various types of substrates, wafers, or semiconductor device materials. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0079] The planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that grinds or planarizes a layer or surface of a deposited or plated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free grinding) to grind or planarize the surface of a semiconductor device. The planarization tool 110 may utilize abrasive and corrosive chemical slurries in conjunction with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be squeezed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate with different rotation axes to remove material and flatten any irregular topography of the semiconductor device, thereby smoothing or flattening the semiconductor device.

[0080] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0081] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions onto a substrate. The ion implantation tool 114 may generate ions from a source material such as a gas or a solid in an arc chamber. The source material may be provided into the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes may be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam may be directed toward the substrate so that the ions are implanted below the surface of the substrate.

[0082] The bonding tool 116 is a semiconductor processing tool capable of bonding two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices) together. For example, the bonding tool 116 may include a eutectic bonding tool capable of forming a eutectic bond between two or more wafers. In these exemplary embodiments, the bonding tool may heat the two or more wafers to form a eutectic system between the materials of the two or more wafers. As another exemplary embodiment, the bonding tool 116 may include a hybrid bonding tool, a direct bonding tool, and / or another type of bonding tool.

[0083] The wafer / die transport tool 118 may be included in a cluster tool or another type of tool (which includes multiple processing chambers) and may be used to transport substrates and / or semiconductor devices between multiple processing chambers; between a processing chamber and a buffer area; between a processing chamber and an interface tool such as an equipment frontend module (EFEM); and / or between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some embodiments, the wafer / die transport tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations).

[0084] One or more of the semiconductor processing tools 102-116 and / or the wafer / die transport tool 118 may perform a series of one or more semiconductor processing operations described herein. In some embodiments and by way of example, the series of one or more semiconductor processing operations includes forming a first conductive material layer on a surface. The series of one or more semiconductor processing operations includes forming a quantum dot material layer on the first conductive material layer. The series of one or more semiconductor processing operations includes forming a second conductive material layer on the quantum dot material layer, wherein the second conductive material is transparent to near infrared light waves or is transparent to short-wave infrared light waves. In some embodiments, one or more of the semiconductor processing operations performed by the semiconductor processing tools 102-116 and / or the wafer / die transport tool 118 may correspond to a combination of FIG. 4A to FIG. 4O , 7A to 7I and one or more semiconductor processing operations described elsewhere herein and other exemplary embodiments.

[0085] Figure 1 The number and configuration of the devices shown in the figure are provided as one or more examples. In practice, there may be more than Figure 1 The devices shown in the figure may be more devices, fewer devices, different devices, or devices configured differently. In addition, Figure 1 Two or more of the devices shown in may be implemented in a single device, or Figure 1 The single device shown in the example environment 100 may be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0086] Figure 2A and Figure 2B is a diagram of an exemplary optoelectronic device 200 embodiment including a pixel sensor array 202 as described herein. The optoelectronic device 200 may be deployed in various embodiments such as digital cameras, video recorders, night vision cameras, automotive sensors and cameras, and / or other types of low-light embodiments.

[0087] like Figure 2A As shown in the top-down view of FIG. 1 , the optoelectronic device 200 includes a pixel sensor array 202. The pixel sensor array 202 may include pixel sensors 204a-204d. Figure 2A As further shown in FIG. 1 , the pixel sensors 204a-204d are arranged in a grid. In some embodiments, the pixel sensors 204a-204d are square (eg, Figure 2A In some embodiments, the pixel sensors 204a-204d include other shapes, such as circles, octagons, diamonds, and / or other shapes.

[0088] The pixel sensor array 202 may include an optical filter array that enables the pixel sensors 204a-204d to sense and / or accumulate incident light of a particular wavelength (e.g., light directed toward the pixel sensor array 202). For example, the pixel sensor 204a may include an optical filter that limits the pixel sensor 204a to absorb and accumulate photons of incident light corresponding to NIR light (e.g., electromagnetic waves having a wavelength in a range of about 800 nanometers to about 2500 nanometers) or shortwave infrared (SWIR) light (e.g., electromagnetic waves having a wavelength in a range of 900 nanometers to about 2500 nanometers). Additionally or alternatively, the pixel sensor 204b may include an optical filter that limits the pixel sensor 204b to absorb and accumulate photons of incident light corresponding to red visible light (e.g., electromagnetic waves having a wavelength in a range of about 620 nanometers to about 850 nanometers). Additionally or alternatively, pixel sensor 204c may include a filter that limits pixel sensor 204c to absorbing and accumulating photons of incident light corresponding to green visible light (e.g., electromagnetic waves having a wavelength in a range of about 490 nanometers to about 570 nanometers). Additionally or alternatively, pixel sensor 204d may include a filter that limits pixel sensor 204d to absorbing and accumulating photons of incident light corresponding to blue visible light (e.g., electromagnetic waves having a wavelength in a range of about 450 nanometers to about 490 nanometers). The photodiode of each pixel sensor 204a-204d in pixel sensor array 202 may generate a charge representing the intensity or brightness of the incident light (e.g., a larger amount of charge may correspond to a larger intensity or brightness, while a smaller amount of charge may correspond to a smaller intensity or brightness).

[0089] like Figure 2B As shown in the isometric view of FIG. 1 , the optoelectronic device 200 may include an application specific integrated circuit device 206 (ASIC device) connected to a system chip integrated circuit device 208 (SoC device). Figures 3 to 4O As described in greater detail elsewhere herein, the ASIC device 206 may include a combination of metallization layers and integrated circuitry (eg, transistor structures).

[0090] exist Figure 2B In the embodiment, SoC device 208 includes filter layer 210 (e.g., a filter array including visible color filters and NIR filters) and photodiode 212. In some embodiments, photodiode 212 is an organic photodiode formed in a semiconductor layer of SoC device 208 (e.g., a region including a p-type dopant or an n-type dopant within a semiconductor material layer in SoC device 208). Photodiode 212 is located below the visible color filter of filter layer 210.

[0091] like Figure 2B As further shown in FIG. 1 , a multilayer structure (e.g., an interface structure) including a quantum dot material layer 214, a conductive material layer 216 (e.g., a top electrode layer), and a conductive material layer 218 (e.g., a bottom electrode layer) is located between the ASIC device 206 and the SoC device 208. A photodiode 220 (e.g., a photodiode included as part of the multilayer structure, including a portion of the quantum dot material layer 214, a portion of the conductive material layer 216, and a portion of the conductive material layer 218) is located below the NIR filter of the filter layer 210.

[0092] The quantum dot material layer 214 may include quantum dots to form a pn junction region between the conductive material layer 216 and the conductive material layer 218 (e.g., between electrodes). The quantum dots may include a lead sulfide core (PbS), a cadmium selenide core (CdSe), a cadmium telluride core (CdTe), an indium phosphide core, and / or a zinc selenide core (ZnSe), among other exemplary embodiments.

[0093] Photodiodes made using quantum dot material layer 214 take advantage of the unique properties of quantum dots to enhance their effectiveness. Quantum dots are nanoscale particles made of semiconductor materials such as cadmium selenide or indium arsenide. Quantum dots absorb photons, thereby generating excitons that separate into electron-hole pairs when an electric field is applied. In a photodiode made using quantum dot material, the quantum dots form a pn junction layer between two electrodes. When light enters the device and is absorbed by the quantum dots, the light generates electron-hole pairs that are separated by the electric field at the pn junction. The resulting current indicates the intensity of the incident light.

[0094] Photodiodes made using quantum dots have several advantages over conventional photodiodes. Photodiodes made using quantum dots detect low-order light with high absorption efficiency, and the spectral sensitivity of the photodiode can be tuned by adjusting the size and composition of the quantum dots. In addition, photodiodes made using quantum dots are easier to use in a wide range of applications because they can be manufactured using low-cost solution-based methods. Such applications include optical communications, sensing, and imaging.

[0095] The conductive material layer 216 may include a material that is permeable to electromagnetic waves corresponding to NIR light waves. For example, the conductive material layer 216 may include a tin oxide material (SnO2) containing an indium dopant (In), a tin oxide material containing an antimony dopant (Ps), and / or a tin oxide material containing a fluorine dopant (Fl). In some embodiments, the conductive material layer 218 includes the same type of material as the conductive material layer 216 (e.g., a material layer that is permeable to electromagnetic waves corresponding to NIR light waves). Alternatively, the conductive material layer 218 may include another conductive material that is not permeable to electromagnetic waves corresponding to NIR light waves (e.g., aluminum (Al), titanium (Ti), or copper (Cu)).

[0096] As indicated above, Figure 2A and Figure 2B Other examples may differ from those provided for Figure 2A and Figure 2B The content described.

[0097] Figure 3 is a diagram of an exemplary optoelectronic device 300 described herein. Figure 3 The optoelectronic device 300 in the side view may include Figure 2A and Figure 2B One or more parts of the optoelectronic device 200 include an ASIC device 206 and a SoC device 208 located above the ASIC device 206.

[0098] like Figure 3 As shown in FIG. 1 , the ASIC device 206 includes a substrate 302. The substrate 302 may include a semiconductor material such as a silicon material. The ASIC device 206 further includes a semiconductor material layer 304a located above the substrate 302. The semiconductor material layer 304a may include a semiconductor material such as silicon (Si). In some embodiments and as shown in FIG. Figure 3 As shown in FIG, semiconductor material layer 304a includes a portion of transistor circuitry. For example, semiconductor material layer 304a may include a gate structure 306a of the transistor circuitry.

[0099] like Figure 3 As further shown in FIG. 2 , the ASIC device 206 may include a dielectric region 308a located above and / or on the substrate 302. The dielectric region 308a (eg, an intermetallic dielectric region) may include one or more layers of dielectric material (eg, silicon oxide (SiO x ), silicon nitride (Si x N y), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, or another dielectric material. Various interconnect structures 310a (e.g., vertical interconnect access structures or vias) and metallization layers 312a may be formed in and / or between layers of the dielectric region 308a. The metallization layers 312a may include bonding pads, wires, and / or other types of conductive structures that electrically connect various regions of the ASIC device 206 and / or electrically connect various regions of the ASIC device 206, one or more external devices, and / or external packages. The interconnect structures 310a and the metallization layers 312a may be referred to as a BEOL metallization stack and may include conductive materials such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof, as well as other exemplary embodiments.

[0100] In some embodiments, portions of the transistor circuitry may be included in the dielectric region 308a. For example, one or more source / drain regions 314a (e.g., doped semiconductor material such as silicon (Si) or silicon germanium (SiGe)) may be included in the dielectric region 308a. The source / drain regions 314a may be connected to the gate structure 306a.

[0101] like Figure 3 As shown in FIG. 1 , the SoC device 208 includes a dielectric region 308 b. The dielectric region 308 b (eg, an intermetallic dielectric region) may include one or more layers of dielectric material (eg, silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, or another dielectric material). Various interconnect structures 310b (e.g., vertical interconnect access structures or vias) and metallization layers 312b may be formed in and / or between layers of the dielectric region 308b. The metallization layer 312b may include bonding pads, wires, and / or other types of conductive structures that electrically connect various regions of the SoC device 208 and / or electrically connect various regions of the SoC device 208 to one or more external devices and / or external packages. The interconnect structures 310a and the metallization layers 312a may be referred to as a BEOL metallization stack and may include conductive materials such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof, as well as other exemplary embodiments.

[0102] In some embodiments, portions of transistor circuitry may be included in dielectric region 308b. For example, one or more source / drain regions 314b (eg, doped semiconductor material such as silicon (Si) or silicon germanium (SiGe)) may be included in dielectric region 308b.

[0103] The SoC device 208 may further include a semiconductor material layer 304b. The semiconductor material layer 304b may include a semiconductor material such as silicon, a III-V compound such as gallium arsenide (GaAs), a silicon on insulator (SOI) layer, or another type of semiconductor material layer capable of generating charge from photons of incident light.

[0104] A photodiode 212 for visible light (VIS photodiode) may be included in the semiconductor material layer 304b. The photodiode 212 may include multiple types of ions to form a pn junction or a pin junction (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, the semiconductor material layer 304b may be doped with an n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 212 and doped with a p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 212.

[0105] In some embodiments, the semiconductor material layer 304b may further include portions of a transistor circuit system. For example, the semiconductor material layer 304b may include a gate structure 306b. The gate structure 306b, which may be located between the source / drain regions 314b, may include materials such as polysilicon and other exemplary conductive materials. In some embodiments, the transistor formed by the source / drain regions 314b and the gate structure 306b may be associated with the photodiode 212.

[0106] Additionally and in some implementations of the SoC device 208 , a shallow trench isolation (STI) region 318 may be located above the dielectric region 308 b . The STI region 318 may electrically isolate the photodiode 212 from other regions of the SoC device 208 .

[0107] like Figure 3 As shown in FIG. 1 , an oxide layer 320 may be located above the semiconductor material layer 304 b. The oxide layer 320 may be used as a passivation layer between the semiconductor material layer 304 b and the upper layers of the pixel sensors 204 a to 204 d. In some embodiments, the oxide layer 320 may include a silicon oxide (SiO x ) oxide material. In some embodiments, silicon nitride (SiN x), Silicon Carbide (SiC x ) or a mixture thereof (such as silicon carbonitride (SiCN), silicon oxynitride (SiON) or another dielectric material) instead of the oxide layer 320 as the passivation layer.

[0108] The oxide layer 320 may fill a deep trench isolation (DTI) structure 322 included in the semiconductor material layer 304b. In particular, the DTI structure 322 may be formed between each of the photodiodes 212. The DTI structure 322 may include a trench (e.g., a deep trench) extending down into the semiconductor material layer 304b between the photodiodes 212. The DTI structure 322 may provide optical isolation between the photodiodes 212 to reduce the amount of optical crosstalk between adjacent photodiodes.

[0109] One or more high absorption (HA) regions 324 may be located above one or more photodiodes 212. Each HA region 324 may be defined by a shallow trench. Multiple adjacent HA regions 324 may form a periodic or zigzag structure in the semiconductor material layer 304b and / or the photodiode 212. One or more HA regions 324 may be formed on the same side of the semiconductor material layer 304b as the DTI structure 322.

[0110] The HA region 324 can increase the absorption of incident light by the photodiode 212 (thereby improving the quantum efficiency of the photodiode 212) by modifying or changing the orientation of the refractive interface between the photodiode and the semiconductor material layer 304b. The angled walls of the HA region 324 change the orientation of the interface between the photodiode 212 and the semiconductor material layer 304b by making the interface diagonal relative to the orientation of the top surface of the semiconductor material layer 304b. For incident light of the same incident angle, this orientation change can produce a smaller refraction angle relative to the flat surface of the top surface of the semiconductor material layer 304b. Therefore, the HA region 324 is able to direct incident light at a wider angle toward the center of the photodiode 212 than if the HA region 324 was not included in the optoelectronic device 300.

[0111] In some embodiments, the top surface of the semiconductor material layer 304 b, the surface of the DTI structure 322 , and the surface of the HA region 324 may be coated with an antireflective coating (ARC) layer to reduce reflection of incident light away from the photodiode 212 , thereby increasing the transmission of incident light into the semiconductor material layer 304 b and the photodiode 212 .

[0112] like Figure 3As further shown in FIG. 1 , one or more passivation layers may be formed over and / or on oxide layer 320. For example, a backside illumination (BSI) oxide layer 326 may be located over and / or on a portion of oxide layer 320. As another example, a buffer oxide layer 328 may be located over and / or on BSI oxide layer 326. In some embodiments, BSI oxide layer 326 and / or buffer oxide layer 328 may include silicon oxide (SiO x ) oxide material. In some embodiments, silicon nitride (SiN x ), Silicon Carbide (SiC x ) or a mixture thereof (such as silicon carbonitride (SiCN), silicon oxynitride (SiON) or another dielectric material) replaces the BSI oxide layer 326 and / or the buffer oxide layer 328 as a passivation layer.

[0113] The bonding pad 330 may be located above the STI region 318 and / or above and / or on the buffer oxide layer 328. The bonding pad 330 may extend through the buffer oxide layer 328, through the STI region 318 and to the dielectric region 308b, and may contact one or more metallization layers 312b in the dielectric region 308b. The bonding pad 330 may include a conductive material such as gold, silver, aluminum, copper, aluminum-copper, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, a metal alloy, other metals, or a combination thereof. The bonding pad 330 may provide an electrical connection between the metallization layer 312b of the optoelectronic device 300 and an external device and / or external package.

[0114] The filter layer 210 (e.g., a portion corresponding to a filter array or a near infrared filter array) is included above and / or on the buffer oxide layer 328 of one or more pixel sensors 204. The filter layer 210 may include one or more visible light filter regions for filtering visible light of a specific wavelength or wavelength range (e.g., allowing visible light of a specific wavelength or wavelength range to pass through the filter layer 210), one or more near infrared (NIR) filter regions (e.g., NIR bandpass filter regions), one or more NIR cut-off filter regions for allowing wavelengths associated with NIR light to pass through the filter layer 210 and blocking light of other wavelengths, NIR cut-off filter regions for blocking NIR light from passing through the filter layer 210, and / or other types of filter regions.

[0115] In some embodiments, one or more pixel sensors 204 are each configured with a filter region of filter layer 210. In some embodiments, microlens layer 332 is included above and / or on filter layer 210. Microlens layer 332 can include a plurality of microlenses. In particular, microlens layer 332 can include a respective microlens for a pixel sensor in a pixel sensor array, such as each of pixel sensors 204 included in pixel sensor array 202.

[0116] like Figure 3 As further shown in FIG. 2 , a multi-layer structure including a quantum dot material layer 214, a conductive material layer 216, and a conductive material layer 218 is located between the ASIC device 206 and the SoC device 208. A photodiode 220 (e.g., a photodiode including a portion of the quantum dot material layer 214, a portion of the conductive material layer 216, and a portion of the conductive material layer 218) is located below the NIR filter of the filter layer 210.

[0117] Figure 3 The number and arrangement of elements, structures and / or layers shown in the optoelectronic device 300 are provided as examples. In practice, the optoelectronic device 300 may include more than Figure 3 The elements, structures and / or layers shown in the figure may include more elements, structures and / or layers; fewer elements, structures and / or layers; different elements, structures and / or layers; and / or elements, structures and / or layers configured in a different manner.

[0118] As combined Figure 3 As described, a device (e.g., optoelectronic device 200) includes a first photodiode (e.g., photodiode 212) including a semiconductor material layer (e.g., semiconductor material layer 304b) and a p-type dopant or an n-type dopant within the semiconductor material layer. The device includes a second photodiode (e.g., photodiode 220) including a quantum dot material layer (e.g., quantum dot material layer 214); a first conductive material layer (e.g., conductive material layer 216) located above and in contact with the quantum dot material layer; and a second conductive material layer (e.g., conductive material layer 218) located below and in contact with the quantum dot material layer.

[0119] The performance of an optoelectronic device 300 (e.g., a CIS device) including a photodiode 220 is improved relative to another optoelectronic device that does not include a photodiode. Improving the performance of the optoelectronic device 300 improves the manufacturing yield of the optoelectronic device 300 to a certain performance threshold. In addition to improving the manufacturing yield, the combined NIR / SWIR and VIS light capabilities of the optoelectronic device 300 also eliminates the need for separate and discrete optoelectronic devices (e.g., VIS light optoelectronic devices) in image detection systems for low-light environments. In this way, the amount of resources (e.g., semiconductor manufacturing tools, labor, raw materials, and / or computing resources) required to support a market that consumes a large number of image detection systems with NIR / SWIR and VIS light detection capabilities is reduced.

[0120] As indicated above, Figure 3 Other examples may differ from those provided for Figure 3 The content described.

[0121] FIG. 4A to FIG. 4O To form Figure 3 FIG. 400 is a diagram of an exemplary embodiment of an optoelectronic device. As part of embodiment 400, in combination Figure 1 One or more of the described semiconductor processing tools 102 - 116 and / or wafer / die transport tool 118 may perform a series of operations to form optoelectronic device 300 .

[0122] like Figure 4A As shown in FIG. 1 , a semiconductor material layer 304a is formed above and / or on the substrate 302. The deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 The semiconductor material layer 304a is deposited in another type of deposition operation as described and / or in another suitable deposition operation. In some embodiments, after the deposition tool 102 deposits the semiconductor material layer 304a, the planarization tool 110 planarizes the semiconductor material.

[0123] like Figure 4B As shown in FIG. 3 , a gate structure 306a may be formed in the semiconductor material layer 304a. For example, the deposition tool 102, the exposure tool 104, the development tool 106, the etching tool 108 and / or the ion implantation tool 114 may perform a combination of deposition, lithography, etching and / or implantation operations to form the gate structure 306a.

[0124] like Figure 4C As shown in FIG. 1 , dielectric region 308a is formed on and / or over semiconductor material layer 304a. As part of forming dielectric region 308a and by way of example, deposition tool 102 may use CVD operation, PVD operation, ALD operation, a combination of the above, Figure 1 Another deposition operation as described and / or another suitable deposition operation is used to deposit one or more dielectric layers of dielectric region 308a. In some embodiments, after deposition tool 102 deposits the dielectric layers, planarization tool 110 planarizes one or more of the dielectric layers.

[0125] Additionally or alternatively and as part of forming the dielectric region 308a, the deposition tool 102, exposure tool 104, development tool 106, etching tool 108 and / or ion implantation tool 114 may perform a combination of deposition, lithography, etching and / or implantation operations to form source / drain regions 314a within the dielectric region 308a.

[0126] Additionally or alternatively and as part of forming dielectric region 308a, deposition tool 102, exposure tool 104, development tool 106, and / or etching tool 108 may perform a combination of deposition, lithography, and / or etching operations to form one or more metallization layers 312a. To form one or more of metallization layers 312a, deposition tool 102 and / or plating tool 112 may perform a CVD operation, a PVD operation, an ALD operation, a plating operation, a combination of the above, or a combination of the above. Figure 1 One or more of the metallization layers 312a are deposited in another deposition operation as described and / or another suitable deposition operation. In some implementations, the planarization tool 110 planarizes one or more of the metallization layers 312a after deposition.

[0127] Additionally or alternatively, as part of forming the dielectric region 308a, the deposition tool 102, exposure tool 104, development tool 106, and / or etching tool 108 may perform a combination of deposition, lithography, and / or etching operations to form the interconnect structure 310a.

[0128] Steering Figure 4D , forming a conductive material layer 218 on and / or above the dielectric region 308a. The deposition tool 102 and / or the electroplating tool 112 may be a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination thereof. Figure 1 The conductive material layer 218 is deposited in another deposition operation as described and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the conductive material layer 218 is deposited on the seed layer. In some embodiments, after the conductive material layer 218 is deposited by the deposition tool 102 and / or the electroplating tool 112, the planarization tool 110 planarizes the conductive material layer 218.

[0129] like Figure 4E As shown in FIG. 1 , a quantum dot material layer 214 is formed on and / or over a conductive material layer 218. Deposition tool 102 may be used in a spin coating operation, an ALD operation, a combination of Figure 1The quantum dot material layer 214 is deposited in another type of deposition operation and / or another suitable deposition operation as described. In some embodiments, after the quantum dot material layer 214 is deposited by the deposition tool 102 , the planarization tool 110 planarizes the quantum dot material layer 214 .

[0130] In some embodiments, the deposition tool 102 may deposit the quantum dot material layer 214 such that the thickness D1 of the quantum dot material layer 214 is included in the range of about 180 nanometers to about 220 nanometers. If the thickness D1 is less than about 180 nanometers, the resistivity property of the quantum dot material layer 214 may not meet the threshold value. If the thickness is greater than about 220 nanometers, the transmittance property of the quantum dot material layer 214 does not meet the threshold value. However, other values ​​and ranges of thickness D1 are also within the scope of the present disclosure.

[0131] like Figure 4F As shown in FIG. 2 , a conductive material layer 216 is formed on and / or over the quantum dot material layer 214. The deposition tool 102 and / or the electroplating tool 112 may be used in a CVD operation, a PVD operation, an ALD operation, an electroplating operation, or a combination of the above. Figure 1 The conductive material layer 216 is deposited in another deposition operation as described and / or another suitable deposition operation. In some embodiments, the seed layer is deposited first, and the conductive material layer 216 is deposited on the seed layer. In some embodiments, after the conductive material layer 216 is deposited by the deposition tool 102 and / or the electroplating tool 112, the planarization tool 110 planarizes the conductive material layer 216.

[0132] Steering Figure 4G , a portion of the SoC device 208 (e.g., a partially formed portion of the SoC device 208, including the dielectric region 308b, the semiconductor material layer 304b, and the photodiode 212 and formed via a series of separate operations) may be connected to the conductive material layer 216. As an example, connecting the portion of the SoC device 208 may include a bonding tool 116 performing a eutectic bonding operation that connects the dielectric region 308a and the conductive material layer 216 of the SoC device 208. Connecting the dielectric region 308a and the conductive material layer 216 may provide electrical connectivity between one or more of the metallization layers 312b of the SoC device 208 to form the photodiode 220 from a multi-layer stack that includes the conductive material layer 218, the quantum dot material layer 214, and the conductive material layer 216.

[0133] like Figure 4HAs shown in and as part of embodiment 400, etching tool 108 can form cavity 402 (e.g., cavity for DTI structure 322) and cavity 404 (e.g., cavity for HA region 324). In some embodiments, the pattern in the photoresist layer is used to etch semiconductor material layer 304b to form cavities 402 and 404. In these embodiments, deposition tool 102 forms a photoresist layer on semiconductor material layer 304b. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops portions of the photoresist layer and removes these portions to expose the pattern. Etching tool 108 etches semiconductor material layer 304b based on the pattern to form cavities 402 and 404 in semiconductor material layer 304b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes remaining portions of the photoresist layer (eg, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of the semiconductor material layer 304b.

[0134] like Fig. 4I As shown in FIG. 1 , an oxide layer 320 is formed above and / or on the semiconductor material layer 304 b. The deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 The oxide layer 320 is deposited in another type of deposition operation and / or another suitable deposition operation as described. In some embodiments, after the deposition tool 102 deposits the oxide layer 320, the planarization tool 110 planarizes the oxide layer 320. As part of forming the oxide layer 320, the cavities 402 and 404 can be filled with oxide to form the DTI structure 322 and the HA region 324. In some embodiments, the deposition tool 102 deposits an anti-reflective (ARC) layer before depositing the oxide layer 320.

[0135] like Figure 4J As shown in FIG. 1 , a BSI oxide layer 326 is formed over and / or on the oxide layer 320. The deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 BSI oxide layer 326 is deposited in another type of deposition operation and / or another suitable deposition operation as described. In some embodiments, after deposition tool 102 deposits BSI oxide layer 326 , planarization tool 110 planarizes BSI oxide layer 326 .

[0136] Steering Figure 4KAnd as part of embodiment 400, cavity 406 is formed to reach STI region 318 through BSI oxide layer 326, oxide layer 320, and semiconductor material layer 304b. In some embodiments, the pattern in the photoresist layer is used to etch BSI oxide layer 326, oxide layer 320, and semiconductor material layer 304b to form cavity 406. In these embodiments, deposition tool 102 forms a photoresist layer on semiconductor material layer 304b. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops portions of the photoresist layer and removes these portions to expose the pattern. Etching tool 108 etches cavity 406 based on the pattern to form cavity 406 in BSI oxide layer 326, oxide layer 320, and semiconductor material layer 304b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes remaining portions of the photoresist layer (eg, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of BSI oxide layer 326, oxide layer 320, and semiconductor material layer 304b.

[0137] like Figure 4L As shown in FIG. 1 , a buffer oxide layer 328 is formed over and / or on the BSI oxide layer 326. The deposition tool 102 may be used in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 Buffer oxide layer 328 is deposited in another type of deposition operation and / or another suitable deposition operation as described. In some embodiments, after deposition tool 102 deposits buffer oxide layer 328 , planarization tool 110 planarizes buffer oxide layer 328 .

[0138] like Figure 4M, cavity 408 is formed through buffer oxide layer 328, through STI region 318, and into dielectric region 308b. In some embodiments, the pattern in the photoresist layer is used to etch buffer oxide layer 328, STI region 318, and dielectric region 308b to form cavity 408. In these embodiments, deposition tool 102 forms a photoresist layer on buffer oxide layer 328. Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops portions of the photoresist layer and removes these portions to expose the pattern. Etching tool 108 etches buffer oxide layer 328, STI region 318, and dielectric region 308b based on the pattern to form cavity 408 through buffer oxide layer 328, through STI region 318, and into dielectric region 308b. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (eg, using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of buffer oxide layer 328, STI regions 318, and dielectric regions 308b.

[0139] As part of embodiment 400 and as Figure 4N As shown in FIG. 4 , a bonding pad 330 is formed in the cavity 408 . As an example, the deposition tool 102 , the exposure tool 104 , the development tool 106 , and / or the etching tool 108 may perform a combination of deposition, lithography, and / or etching operations to form the bonding pad 330 .

[0140] Steering Fig.4O , the filter layer 210 and the microlens layer 332 are formed above and / or on the buffer oxide layer 328. As an example, the deposition tool 102, the exposure tool 104, the development tool 106 and / or the etching tool 108 may perform a combination of deposition, lithography and / or etching operations to form the filter layer 210 and the microlens layer 332.

[0141] As indicated above, FIG. 4A to FIG. 4O Other examples may differ from those provided for FIG. 4A to FIG. 4O The content described.

[0142] Figure 5is a diagram of an exemplary optoelectronic device 500 described herein. Optoelectronic device 500 may be an optoelectronic device for detecting electromagnetic waves having wavelengths corresponding to NIR and / or SWIR light waves. Optoelectronic device 500 may be included in an image sensor such as a complementary metal-oxide semiconductor (CMOS) image sensor, a backside illumination (BSI) CMOS image sensor, or another type of image sensor. Optoelectronic device 500 includes a photodiode 220a for detecting NIR light waves and an adjacent photodiode 220b for detecting SWIR light waves.

[0143] like Figure 5 As shown in FIG, optoelectronic device 500 includes substrate layer 502. Substrate layer 502 is formed of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or another type of semiconductor material.

[0144] The optoelectronic device 500 further includes a DTI structure 504 penetrating into the substrate layer 502. The DTI structure 504, which can reduce the crosstalk between the photodiodes 220a and 220b, can include an oxide material and other exemplary embodiments. The optoelectronic device further includes an antireflective coating (ARC) layer 506 to reduce the reflection of incident light in the optoelectronic device 500. The ARC layer 506 can include a nitrogen-containing material and other exemplary embodiments.

[0145] The oxide layer 508 may be located on and / or above the ARC layer 506. The oxide layer 508 may serve as a dielectric buffer layer between the underlying structure of the optoelectronic device 500 and the photodiodes 220a / 220b. The oxide layer 508 may include an oxide material such as silicon oxide (SiO x ) (such as silicon dioxide (SiO2)), silicon nitride (SiN x ), Silicon Carbide (SiC x ), titanium nitride (TiN x ), Tantalum Nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ) or aluminum oxide (AlO x ) and / or another dielectric material capable of providing optical isolation within an optoelectronic device.

[0146] The pillar structure array 510 may be located on and / or above the oxide layer 508. The pillar structure array 510 may include a metal material such as tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), nickel (Ni), titanium (Ti), tantalum (Ta), another conductive material, and / or an alloy including one or more of the foregoing materials. Additionally or alternatively, the pillar structure array 510 may include a non-conductive reflective material. Figure 5 As further shown in FIG. 5 , optoelectronic device 500 includes a ground node 512 .

[0147] exist Figure 5 , the photodiodes 220a and 220b are located on and / or above the outline of the pillar structure array 510. The pillar structure array 510 may reflect incident light within the photodiodes 220a and / or 220b to increase the intensity of light absorbed within the photodiodes 220a and / or 220b.

[0148] Photodiode 220a includes quantum dot material layer 214a, and photodiode 220b includes quantum dot material layer 214b. Quantum dot material layers 214a and 214b may include quantum dots to form a pn junction region between conductive material layer 216 and conductive material layer 218. Figure 5 As shown in FIG. 5 , the conductive material layer 218 is located below the quantum dot material layers 214 a and 214 b , while the conductive material layer 216 is located above the quantum dot material layers 214 a and 214 b . The conductive material layer 218 is connected to the ground node 512 .

[0149] To detect NIR light waves (e.g., electromagnetic waves having a wavelength included in the range of about 800 nanometers to about 900 nanometers), and by way of example, the quantum dot material layer 214a (e.g., the photodiode 220a) may include a lead sulfide (PbS) quantum dot mixture. The PbS quantum dot mixture in the quantum dot material layer 214a may have a diameter included in the range of about 4 nanometers to about 6 nanometers. However, other materials and diameters of the quantum dot mixture in the quantum dot material layer 214a are within the scope of the present disclosure.

[0150] To detect SWIR light waves (e.g., electromagnetic waves having a wavelength included in the range of about 1000 nanometers to about 2500 nanometers), and by way of example, the quantum dot material layer 214b (e.g., the photodiode 220b) may include a PbS quantum dot mixture. In contrast to the PbS quantum dot mixture in the quantum dot material layer 214a and due to the longer wavelength of the SWIR light waves, the PbS quantum dot mixture in the quantum dot material layer 214b may have a diameter included in the range of about 5 nanometers to about 12 nanometers. However, other materials and diameters of the quantum dot mixture in the quantum dot material layer 214b are within the scope of the present disclosure.

[0151] like Figure 5 As shown in and in some embodiments, a device (e.g., optoelectronic device 300) includes a pillar structure array (e.g., pillar structure array 510). The device includes a photodiode (e.g., photodiode 220a and / or 220b) located above the contour of the pillar structure array. The photodiode includes a first conductive material layer (e.g., conductive material layer 218) conforming to the contour of the pillar structure array, a quantum dot material layer (e.g., quantum dot material layer 214a and / or quantum dot material layer 214b) located on the first conductive material layer, and a second conductive material layer (e.g., conductive material layer 216) located on the quantum dot material.

[0152] As indicated above, Figure 5 Other examples may differ from those provided for Figure 5 The content described.

[0153] Figure 6 is a diagram of an exemplary optoelectronic device 600 described herein. Optoelectronic device 600 may be an optoelectronic device for detecting electromagnetic waves having wavelengths corresponding to NIR light waves, SWIR light waves, and / or visible (VIS) light waves. Optoelectronic device 600 may be included in an image sensor such as a complementary metal-oxide semiconductor (CMOS) image sensor, a backside illumination (BSI) CMOS image sensor, or another type of image sensor.

[0154] The optoelectronic device 600 includes a photodiode 220a for detecting NIR light waves (eg, a photodiode 220a including a quantum dot material layer 214a), and further includes a photodiode 220b for detecting SWIR light waves (eg, a photodiode 220b including a quantum dot material layer 214b).

[0155] like Figure 6 As shown in FIG. 1 , the optoelectronic device includes a photodiode 220 c for detecting blue VIS light waves. To detect blue VIS light waves (e.g., electromagnetic waves having a wavelength included in the range of about 450 nanometers to about 490 nanometers), and as an example, the quantum dot material layer 214 c (e.g., the photodiode 220 c) may include a lead sulfide (PbS) quantum dot mixture. The PbS quantum dot mixture in the quantum dot material layer 214 c may have a diameter included in the range of about 3 nanometers to about 4 nanometers. However, other materials and diameters of the quantum dot mixture in the quantum dot material layer 214 c are within the scope of the present disclosure.

[0156] like Figure 6As shown in FIG. 1 , the optoelectronic device includes a photodiode 220 d for detecting green VIS light waves. To detect green VIS light waves (e.g., electromagnetic waves having a wavelength included in the range of about 495 nanometers to about 570 nanometers), and as an example, the quantum dot material layer 214 d (e.g., the photodiode 220 d) may include a lead sulfide (PbS) quantum dot mixture. The PbS quantum dot mixture in the quantum dot material layer 214 d may have a diameter included in the range of about 4 nanometers to about 5 nanometers. However, other materials and diameters of the quantum dot mixture in the quantum dot material layer 214 d are within the scope of the present disclosure.

[0157] In addition, the optoelectronic device includes a photodiode 212 for detecting electromagnetic waves corresponding to red VIS light waves (eg, electromagnetic waves having a wavelength within a range of about 620 nanometers to about 750 nanometers). Figure 6 As shown in FIG. 6 , a photodiode 212 (eg, an organic photodiode formed in substrate layer 502 via a doping operation) is located below photodiode 220 a. Photodiode 212 may be located below photodiode 220 a to save space in optoelectronic device 600 .

[0158] like Figure 6 As shown in , the filter layer 210 is located above the photodiodes 220a-220d and the photodiode 212. The filter layer 210 may include a region located above the photodiodes 212 and 220a, which is transparent to the NIR light wave and the red VIS light wave. Additionally or alternatively, the filter layer 210 may include a region located above the photodiode 220b, which is transparent to the SWIR light wave. Additionally or alternatively, the filter layer 210 may include a region located above the photodiode 220c, which is transparent to the blue VIS light wave. Additionally or alternatively, the filter layer 210 may include a region located above the photodiode 220d, which is transparent to the green VIS light wave.

[0159] The performance of optoelectronic device 600 (e.g., CIS device) including photodiodes 220a and 220b is improved relative to another optoelectronic device that does not include photodiodes 220a and 220b. Improving the performance of optoelectronic device 600 improves the manufacturing yield of optoelectronic device 600 to a certain performance threshold. In addition to improving manufacturing yield, the combined NIR / SWIR and VIS light capabilities of optoelectronic device 600 also eliminates the need for separate and discrete optoelectronic devices (e.g., VIS light optoelectronic devices) in image detection systems for low-light environments. In this way, the amount of resources (e.g., semiconductor manufacturing tools, labor, raw materials, and / or computing resources) required to support a market that consumes a large number of image detection systems with NIR / SWIR and VIS light detection capabilities is reduced.

[0160] Figure 6 The number and configuration of the devices shown in the figure are provided as one or more examples. In practice, there may be more than Figure 6 The photodiodes shown in FIG. 5 may include more photodiodes, fewer photodiodes, different photodiodes, or photodiodes configured differently.

[0161] 7A to 7I FIG. 700 is a diagram of an exemplary embodiment 700 described herein. As part of the embodiment 700, in conjunction with Figure 1 One or more of the described semiconductor processing tools 102-116 and / or wafer / die transport tool 118 may perform a series of operations to form optoelectronic device 500 including photodiodes 220a and 220b.

[0162] like Fig. 7A As shown in , an exemplary process for forming an optoelectronic device may be performed in conjunction with substrate layer 502. Fig. 7A In the embodiment, substrate layer 502 may include a semiconductor die substrate, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate that may form optoelectronic device 500. For example, substrate layer 502 may be formed of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon on insulator (SOI), or another type of semiconductor material. Fig. 7A As further shown in FIG. 5 , a DTI structure 504 can be included in substrate layer 502. The DTI structure 504 can be coated or lined with an ARC layer 506.

[0163] exist Fig. 7A In the embodiment, an oxide layer 508 is formed on and / or above the substrate layer 502. To form the oxide layer 508, the deposition tool 102 may perform a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a combination of Figure 1 The oxide layer 508 is deposited in another type of deposition operation as described and / or in another suitable deposition operation. In some embodiments, after the oxide layer 508 is deposited by the deposition tool 102 , the planarization tool 110 planarizes the oxide layer 508 .

[0164] like Fig. 7A As further shown in FIG. 5 , a pillar structure array 510 can be formed above the oxide layer 508. For example, the deposition tool 102 can deposit a layer of metal material above the front side surface of the substrate layer 502 and / or on the front side surface (e.g., deposited above the oxide layer 320). In some embodiments, the deposition tool 102 can use a CVD operation, a PVD operation, an ALD operation, an electroplating operation, a combination of Figure 1The metal material may be deposited by another type of deposition operation described and / or another suitable deposition operation. Thus, the deposition tool 102 may form a photoresist layer over and / or over the metal material layer, the exposure tool 104 may expose the photoresist layer to a radiation source to form a pattern on the photoresist layer, and the development tool 106 may develop portions of the photoresist layer and remove these portions to expose the pattern. Thus, the etching tool 108 may etch portions of the metal material layer to form the pillar structure array 510. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch portions of the metal material layer to form the pillar structure array 510. After the etching tool 108 etches the metal layer to form the metal structure, the photoresist removal tool may remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, a plasma ashing agent, and / or another technique). In addition to the pillar structure array 510, a ground node 512 may be formed. For example, the ground node 512 may be formed simultaneously with the metal structure.

[0165] like Figure 7B As shown in FIG. 1 , a conductive material layer 218 (e.g., a bottom electrode layer) is formed. For example, the deposition tool 102 can form the conductive material layer 218 on and / or on the front side surface of the substrate layer 502 and / or along the contour of the pillar structure array 510. In some embodiments, the deposition tool 102 can use a CVD operation, a PVD operation, an ALD operation, an electroplating operation, a combination of Figure 1 Another type of deposition operation and / or another suitable deposition operation is described to deposit the conductive material layer 218 .

[0166] like Figure 7C As shown in FIG. 1 , a quantum dot material layer 214a is formed on and / or over the conductive material layer 218. For example, the deposition tool 102 may use a spin coating operation, an ALD operation, a combination of Figure 1 Another type of deposition operation and / or another suitable deposition operation is described to deposit the quantum dot material layer 214a.

[0167] like Fig.7D As shown in , one or more masking layers (e.g., photoresist layer 702 in exemplary embodiment 700) may be formed over conductive material layer 218. For example, deposition tool 102 may form photoresist layer 702 over the front side surface of substrate layer 502 and / or over the front side surface (e.g., over conductive material layer 218). In some embodiments, deposition tool 102 may use spin coating, combined with Figure 1The photoresist layer 702 may be deposited by another type of deposition operation described and / or another suitable deposition operation. In some embodiments, the photoresist layer 702 may be formed over the entire conductive material layer 218. Thus, the exposure tool 104 may expose the photoresist layer 702 to a radiation source to form a pattern on the photoresist layer 702, and the development tool 106 may develop portions of the photoresist layer 702 and remove these portions to expose the pattern. Fig.7D As shown in , the pattern may be such that the photoresist layer 702 is located over a portion of the quantum dot material layer 214a.

[0168] like Fig. 7E , portions of the quantum dot material layer 214a are removed. Thus, the etching tool 108 may etch portions of the quantum dot material layer 214a that are not protected by the pattern of the photoresist layer 702. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch portions of the quantum dot material layer 214a. After the etching tool 108 etches portions of the quantum dot material layer 214a, the photoresist removal tool may remove the remaining portions of the photoresist layer 702 (e.g., using a chemical stripper, a plasma ashing agent, and / or another technique).

[0169] like Figure 7F As shown in FIG. 5 , a quantum dot material layer 214 b is formed over the pillar structure array 510. For example, the deposition tool 102 may form the quantum dot material layer 214 b over and / or along the contour of the conductive material layer 218. Additionally or alternatively, the deposition tool 102 may form the quantum dot material layer 214 b over and / or along the contour of the conductive material layer 218. For example, the deposition tool 102 may use a spin coating operation, an ALD operation, a combination of Figure 1 Another type of deposition operation and / or another suitable deposition operation is described to deposit the quantum dot material layer 214b.

[0170] like Figure 7G As shown in , one or more masking layers (e.g., photoresist layer 704 in exemplary embodiment 700) may be formed over quantum dot material layer 214b. For example, deposition tool 102 may form photoresist layer 704 over and / or on quantum dot material layer 214b. In some embodiments, deposition tool 102 may use a spin coating operation, a combination of Figure 1The photoresist layer 704 may be deposited by another type of deposition operation described and / or another suitable deposition operation. In some embodiments, the photoresist layer 704 may be formed over the entire quantum dot material layer 214b. Thus, the exposure tool 104 may expose the photoresist layer 704 to a radiation source to form a pattern on the photoresist layer 704, and the development tool 106 may develop portions of the photoresist layer 704 and remove these portions to expose the pattern. Figure 7G As shown in , the pattern may be such that the photoresist layer 704 is located over a portion of the quantum dot material layer 214b.

[0171] like Figure 7H , etching a portion of the quantum dot material layer 214b located above the conductive material layer 218. Thus, the etching tool 108 may etch a portion of the quantum dot material layer 214b that is not protected by the pattern of the photoresist layer 704. For example, the etching tool 108 may use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch the portion of the quantum dot material layer 214b. After the etching tool 108 etches the portion of the quantum dot material layer 214a, the photoresist removal tool may remove the remaining portion of the photoresist layer 704 (e.g., using a chemical stripper, a plasma ashing agent, and / or another technique).

[0172] like Fig.7I As shown in FIG. 1 , a conductive material layer 216 (e.g., a top electrode layer) is formed. For example, deposition tool 102 may form conductive material layer 216 above quantum dot material layer 214a and / or quantum dot material layer 214b and / or on quantum dot material layer 214a and / or quantum dot material layer 214b. In some embodiments, deposition tool 102 may use CVD operation, PVD operation, ALD operation, electroplating operation, combination of Figure 1 Another type of deposition operation and / or another suitable deposition operation is described to deposit the conductive material layer 218 .

[0173] As indicated above, 7A to 7I Other examples may differ from those provided for 7A to 7I The content described.

[0174] Figure 8 FIG. 8 is a diagram of exemplary elements of the apparatus 800 described herein. Figure 8 As shown in , the device 800 may include a bus 810 , a processor 820 , a memory 830 , an input component 840 , an output component 850 and / or a communication component 860 .

[0175] The bus 810 may include one or more components that enable wired and / or wireless communications between components of the device 800. The bus 810 may connect the components of the device 800 to each other, such as by operative coupling, communicative coupling, electronic coupling, and / or electrical coupling. Figure 8 Two or more elements of a computer programmable logic device are coupled together. For example, bus 810 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 820 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit, and / or another type of processing element. Processor 820 may be implemented using hardware, firmware, or a combination of hardware and software. In some embodiments, processor 820 may include one or more processors that can be programmed to perform one or more operations or processes described elsewhere herein.

[0176] The memory 830 may include volatile and / or non-volatile memory. For example, the memory 830 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). The memory 830 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). The memory 830 may be a non-transitory computer-readable medium. The memory 830 may store information related to the operation of the device 800, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, the memory 830 may include one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 820), such as via the bus 810. The communicative coupling between the processor 820 and the memory 830 may enable the processor 820 to read and / or process information stored in the memory 830 and / or store information in the memory 830 .

[0177] Input element 840 can enable device 800 to receive input, such as user input and / or sensed input. For example, input element 840 can include touch screen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope and / or actuator. Output element 850 can enable device 800 to provide output such as via display, speaker and / or light emitting diode. Communication element 860 can enable device 800 to communicate with other devices via wired connection and / or wireless connection. For example, communication element 860 can include receiver, transmitter, transceiver, modem, network interface card and / or antenna.

[0178] The device 800 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 830) may store an instruction set (e.g., one or more instructions or program codes) for execution by the processor 820. The processor 820 may execute the instruction set to perform one or more operations or processes described herein. In some embodiments, the execution of the instruction set by one or more processors 820 causes one or more processors 820 and / or the device 800 to perform one or more operations or processes described herein. In some embodiments, a hardware circuit system may be used in place of an instruction or may be used in conjunction with an instruction to perform one or more operations or processes described herein. Additionally or alternatively, the processor 820 may be used to perform one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuit systems and software.

[0179] Figure 8 The number and configuration of the elements shown in are provided as examples. The device 800 may include Figure 8 More elements, fewer elements, different elements, or elements configured differently than the elements shown in . Additionally or alternatively, one or more functions described as being performed by another group of elements of device 800 can be performed by one or more elements of device 800.

[0180] Fig. 9 FIG. 9 is a flow chart of an exemplary process 900 associated with forming an optoelectronic device having a photodiode including quantum dot material. In some embodiments, Fig. 9 One or more process blocks of are performed by one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-116). Additionally or alternatively, Fig. 9 One or more process blocks may be performed by one or more components of the apparatus 800 (such as a processor 820, a memory 830, an input component 840, an output component 850, and / or a communication component 860).

[0181] like Fig. 9 As shown in , process 900 may include forming a first conductive material layer on a surface (block 910). For example, as described herein, one or more of semiconductor processing tools 102-116 may form a first conductive material layer (e.g., conductive material layer 218) on a surface (e.g., on a surface of dielectric region 308a or on a surface corresponding to a contour of pillar structure array 510).

[0182] like Fig. 9As further shown in FIG. 9 , process 900 may include forming a quantum dot material layer on the first conductive material layer (block 920). For example, as described herein, one or more of semiconductor processing tools 102-116 may form a quantum dot material layer (e.g., quantum material layer 214, 214a, or 214b) on the first conductive material layer.

[0183] like Fig. 9 As further shown in FIG. 9 , process 900 may include forming a second conductive material layer on the quantum dot material layer (block 930). For example, as described herein, one or more of semiconductor processing tools 102-116 may form a second conductive material layer (e.g., conductive material layer 216) on the quantum dot material layer. In some embodiments, the second conductive material is transparent to near infrared light or short-wave infrared light.

[0184] Process 900 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or described in conjunction with one or more other processes described elsewhere herein.

[0185] In a first embodiment, forming the quantum dot material layer includes forming the quantum dot material layer using an atomic layer deposition process or forming the quantum dot material layer using a spin coating process.

[0186] In a second embodiment, either alone or in combination with the first embodiment, forming a first conductive material layer on a surface includes forming the first conductive material layer along a contour of a metal pillar (e.g., in a metal pillar array 510) located above a deep trench isolation structure (e.g., DTI structure 504) included in an optoelectronic device (e.g., optoelectronic device 500).

[0187] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming a quantum dot material layer on a first conductive material layer includes forming a first layer of a first quantum dot material (e.g., quantum dot material layer 214a), and further includes removing a portion of the first layer of the first quantum dot material to expose a portion of the first conductive material layer; and forming a second layer of a second quantum dot material (e.g., quantum dot material layer 214b) on a portion of the first conductive material layer.

[0188] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, forming the first conductive material layer on the surface includes forming the first conductive material layer on the top surface of an application specific integrated circuit device (eg, ASIC 206).

[0189] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, process 900 includes connecting a special application integrated circuit device to a portion of another integrated circuit device (e.g., a portion of SoC 208) using a eutectic bonding process, wherein the eutectic bonding process connects a second conductive material layer to a bottom surface of a portion of the other integrated circuit device.

[0190] although Fig. 9 Example blocks of process 900 are shown, but in some embodiments, process 900 includes more Fig. 9 More blocks, fewer blocks, different blocks, or blocks configured differently than those depicted in the process 900. Additionally or alternatively, two or more of the blocks of process 900 may be performed in parallel.

[0191] Some embodiments described herein include a CIS device for an image detection system used in a low-light environment. The CIS device includes a photodiode for detecting NIR and / or SWIR light waves. The photodiode includes a quantum dot material layer and a transparent electrode located above the quantum dot material layer. In addition to the photodiode having an improved QE relative to silicon-based photodiodes, the photodiode can also be integrated into a filter array structure to eliminate the need for a separate visible light (VIS) CIS device in the image detection system.

[0192] In this way, the performance (e.g., NIR / SWIR QE) of a CIS device including a photodiode is improved relative to another CIS device that does not include a photodiode. Improving the performance of the CIS device improves the manufacturing yield of the CIS device to a certain performance threshold. By improving the manufacturing yield and eliminating the need for a separate VIS device space and / or image detection system space, the amount of resources (e.g., semiconductor manufacturing tools, labor, raw materials, and / or computing resources) required to support a market that consumes a large number of image detection systems with NIR / SWIR and VIS light detection capabilities is reduced.

[0193] As described in more detail above, some embodiments described herein provide an optoelectronic device. The optoelectronic device includes a first photodiode, which includes: a semiconductor material layer and a p-type dopant or an n-type dopant located within the semiconductor material layer. The device includes a second photodiode, which includes: a quantum dot material layer; a first conductive material layer located above and in contact with the quantum dot material layer; and a second conductive material layer located below and in contact with the quantum dot material layer. In some embodiments, the second photodiode is located below the layer of semiconductor material. In some embodiments, the layer of the first conductive material includes a conductive material that is transparent to a plurality of near-infrared light waves. In some embodiments, the layer of the first conductive material includes a conductive material that is transparent to a plurality of short-wave infrared light waves. In some embodiments, the layer of the first conductive material includes tin oxide containing a tin dopant, tin oxide containing an antimony dopant, or tin oxide containing a fluorine dopant. In some embodiments, the thickness of the layer of quantum dot material is in a range of 180 nanometers to 220 nanometers. In some embodiments, the first photodiode is included as part of a system chip integrated circuit device, and the second photodiode is included as part of an interface structure between the system chip integrated circuit device and a special application integrated circuit device.

[0194] As described in more detail above, some embodiments described herein provide an optoelectronic device. The optoelectronic device includes an array of metal pillar structures. The device includes a photodiode located above the outline of the array of metal pillar structures. The photodiode includes a first conductive material layer that conforms to the outline of the array of metal pillar structures; a quantum dot material layer located on the first conductive material layer; and a second conductive material layer located on the quantum dot material. In some embodiments, the layer of quantum dot material is a first layer of quantum dot material that includes a plurality of quantum dots of a first size above a plurality of outlines of a first pair of metal pillar structures in the plurality of metal pillar structures, and the optoelectronic device further includes a second layer of quantum dot material that includes a plurality of quantum dots of a second size above a plurality of outlines of a second pair of metal pillar structures in the metal pillar structure, wherein the second size is different from the first size. In some embodiments, the layer of the first conductive material includes a layer of an oxide material. In some embodiments, the layer of the second conductive material includes a material that is permeable to a plurality of near-infrared light waves or a plurality of short-wave infrared light waves. In some embodiments, the layer of quantum dot material includes a plurality of quantum dots including a lead sulfide core. In some embodiments, the photodiode is a first photodiode, and the optoelectronic device further includes a second photodiode located below the first photodiode. In some embodiments, the second photodiode includes an organic photodiode for detecting visible light.

[0195] As described in more detail above, some embodiments described herein provide a method for making an optoelectronic device. The method includes forming a first conductive material layer on a surface. The method includes forming a quantum dot material layer on the first conductive material layer. The method includes forming a second conductive material layer on the quantum dot material layer, wherein the second conductive material is permeable to near infrared light or short-wave infrared light. In some embodiments, forming a layer of quantum dot material includes forming a layer of quantum dot material using an atomic layer deposition process, or forming a layer of quantum dot material using a spin coating process. In some embodiments, forming a layer of the first conductive material on the surface includes forming a layer of the first conductive material along the contour of a metal pillar located above a deep trench isolation structure included in the optoelectronic device. In some embodiments, forming a layer of quantum dot material on the layer of the first conductive material includes the step of forming a first layer of the first quantum dot material on the layer of the first conductive material, and the method further includes removing multiple portions of the first layer of the first quantum dot material to expose multiple portions of the layer of the first conductive material; and forming a second layer of the second quantum dot material on the multiple portions of the layer of the first conductive material. In some embodiments, forming a layer of the first conductive material on the surface includes forming a layer of the first conductive material on the top surface of a special application integrated circuit device. In some embodiments, the method further includes connecting the application specific integrated circuit device to a portion of another integrated circuit device using a eutectic bonding process, wherein the eutectic bonding process connects the layer of second conductive material to a bottom surface of the portion of the other integrated circuit device.

[0196] As described in more detail above, some embodiments described herein further provide an optoelectronic device, including a photodiode. The photodiode includes a layer of a first conductive material disposed along a contour of a metal pillar located above a deep trench isolation structure included in the optoelectronic device, a layer of a quantum dot material located on the layer of the first conductive material, and a layer of a second conductive material located on the layer of the quantum dot material, wherein the second conductive material is transparent to near infrared light or short-wave infrared light.

[0197] As used herein, "satisfying a threshold value" may refer to a value greater than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than or equal to a threshold value, equal to a threshold value, not equal to a threshold value, or the like, depending on the context.

[0198] As used herein, the term "and / or" when used in conjunction with multiple items is intended to cover each of the multiple items individually and to cover any and all combinations of the multiple items. For example, "A and / or B" covers "A and B", "A and not B", and "B and not A".

[0199] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A photoelectric device, characterized in that: include: A first photodiode, comprising: a layer of semiconductor material; and a p-type dopant or an n-type dopant located in the layer of the semiconductor material; and a second photodiode comprising: a layer of a quantum dot material; a layer of a first conductive material located above and in contact with the layer of quantum dot material; and A layer of a second conductive material is located below the layer of quantum dot material and contacts the layer of quantum dot material.

2. The photovoltaic device according to claim 1, wherein: Wherein the second photodiode is located below the layer of semiconductor material.

3. The photovoltaic device according to claim 1, wherein: The layer of the first conductive material is disposed along a contour of a metal pillar located above a deep trench isolation structure included in the optoelectronic device.

4. The photovoltaic device according to claim 1, wherein: The thickness of the layer of the quantum dot material is in a range of 180 nanometers to 220 nanometers.

5. The photovoltaic device according to claim 1, wherein: wherein the first photodiode is included as part of a system-on-chip integrated circuit device, and The second photodiode is included as a part of an interface structure between the system chip integrated circuit device and an application integrated circuit device.

6. A photoelectric device, characterized in that: include: an array of a plurality of metal pillar structures; and a photodiode located above the plurality of contours of the array of plurality of metal pillar structures and comprising: a layer of a first conductive material conforming to the contours of the plurality of metal pillar structures of the array; a layer of quantum dot material on the layer of first conductive material; and A layer of a second conductive material is located on the layer of quantum dot material.

7. The photovoltaic device according to claim 6, wherein: wherein the layer of the quantum dot material is a first layer of the quantum dot material comprising a plurality of quantum dots of a first size over a plurality of contours of a first pair of metal pillar structures in the plurality of metal pillar structures, and wherein the optoelectronic device further comprises: a second layer of a quantum dot material including a plurality of quantum dots of a second size over a plurality of contours of a second pair of metal pillar structures in the plurality of metal pillar structures, The second size is different from the first size.

8. The photovoltaic device according to claim 6, wherein: The photodiode is a first photodiode and further comprises: A second photodiode is located below the first photodiode.

9. The photovoltaic device according to claim 8, wherein: The second photodiode comprises: An organic photodiode is configured to detect visible light.

10. A photoelectric device, characterized in that: include: A photodiode comprising: a layer of a first conductive material disposed along a contour of a metal pillar located above a deep trench isolation structure included in the optoelectronic device; a layer of quantum dot material on the layer of first conductive material; and A layer of a second conductive material is located on the layer of the quantum dot material, wherein the second conductive material is transparent to near infrared light or short-wave infrared light.

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