Power transistors and electronic devices

Abstract

The utility model relates to a power transistor, characterized in that it comprises a substrate; an epitaxial layer, which is arranged on the substrate; an insulating dielectric layer, which is arranged above the epitaxial layer; a metal electrode layer, which is arranged above the insulating dielectric layer; a plurality of first body regions and a plurality of second body regions, which are arranged in the epitaxial layer; a third body region, which is arranged above the plurality of first body regions and the plurality of second body regions, wherein the upper surface of the third body region is flush with the upper surface of the epitaxial layer; a plurality of trench gates, which are arranged in the third body region and extend downward from the upper surface of the third body region to the first body region, the second body region and the epitaxial layer; a plurality of heavily doped regions, which are arranged in the third body region; one side of the heavily doped region is in direct interface contact with the trench gate, and the other side of the heavily doped region is in direct contact with a conductive through hole, and the conductive through hole penetrates the insulating dielectric layer and extends into the third body region.

Description

Technical Field

[0001] The utility model belongs to the field of semiconductor power devices, and particularly relates to a power transistor and electronic equipment. Background Art

[0002] In order to improve the withstand voltage of traditional power devices, it is necessary to continuously reduce the doping concentration of the drift region and increase the thickness of the drift region, which makes the on-resistance of the device increase sharply, thereby increasing the power consumption of the system. Super junction power devices use an alternating arrangement of N-type and P-type regions in the drift region of the device to achieve a charge balance structure, which greatly improves the relationship between the on-resistance and breakdown voltage of the device and is gaining more and more attention.

[0003] At the same time, when the super junction power device is turned off, as the drain voltage increases, the N-type and P-type regions of the device will be quickly exhausted in a very short time, and the capacitance at both ends of the gate and drain and the capacitance at both ends of the drain and source will also drop rapidly, causing a drastic change in dv / dt on the drain end of the device, that is, the voltage on the drain end rises rapidly in a short time. Because of these characteristics, compared with traditional planar power devices, the advantage of super junction power devices in switching applications is that the operating frequency can be higher, but the disadvantage is that a large amount of voltage and current noise will be generated. Utility Model Content

[0004] In response to the above-mentioned problems regarding super junction power devices, an embodiment of the present utility model provides a power transistor, characterized in that it includes a substrate; an epitaxial layer, arranged on the substrate; an insulating dielectric layer, arranged above the epitaxial layer; a metal electrode layer, arranged above the insulating dielectric layer; a plurality of first body regions and a plurality of second body regions, arranged in the epitaxial layer; a third body region, arranged above the plurality of first body regions and the plurality of second body regions, wherein the upper surface of the third body region is flush with the upper surface of the epitaxial layer; a plurality of trench gates, arranged in the third body region, and extending downward from the upper surface of the third body region to the first body region, the second body region and the epitaxial layer; a plurality of heavily doped regions, arranged in the third body region; one side of the heavily doped region is in direct interface contact with the trench gate, and the other side of the heavily doped region is in direct contact with a conductive via, the conductive via penetrates the insulating dielectric layer and extends into the third body region, wherein one side of the trench gate is in direct interface contact with the heavily doped region, and no heavily doped region is arranged on the other side of the trench gate.

[0005] It is characterized in that the multiple trench gates penetrate the third body region downward from the third body region and extend to the interface between the first body region and the epitaxial layer, or extend to the interface between the second body region and the epitaxial layer.

[0006] It is characterized in that the first body region and the second body region are in the epitaxial layer and are arranged alternately with the epitaxial layer.

[0007] The invention is characterized in that the widths of the first body region and the second body region are the same.

[0008] The invention is characterized in that the widths of the first body region and the second body region are different.

[0009] It is characterized in that the second body region 5 is formed as a whole above a plurality of the first body regions and a plurality of second body regions.

[0010] It is characterized in that the substrate, the epitaxial layer and the heavily doped region all have a first conductivity type.

[0011] It is characterized in that the first body region, the second body region and the third body region all have a second conductivity type.

[0012] It is characterized in that the doping concentration of the third body region is greater than the doping concentrations of the first body region and the second body region.

[0013] Yet another embodiment of the present invention includes an electronic device, characterized in that it includes an integrated circuit at least partially formed by the power transistor as described above.

[0014] This summary is provided to introduce some concepts in a simplified form, which will be further described in the following detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The technical solution of the present application is described in detail below with reference to the accompanying drawings, wherein:

[0016] Figure 1 A schematic top view of a power transistor according to an embodiment of the utility model is shown;

[0017] Figure 2 A schematic diagram of the device structure of a part of a cell region of a power transistor according to an embodiment of the utility model is shown;

[0018] Figure 3 A schematic diagram showing the device structure of a partial cell region of a power transistor according to another embodiment of the utility model is shown;

[0019] In the drawings, the same descriptions in the various drawings indicate the same elements or parts. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0021] The accompanying drawings show various structural schematic diagrams according to embodiments of the utility model. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0022] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "under" the other layer / element when the orientation is reversed.

[0023] The present invention may be embodied in various forms, some examples of which will be described below.

[0024] According to an embodiment of the utility model, a power transistor (for example, a power transistor with a super junction structure) can be formed on a semiconductor substrate, and the semiconductor substrate can be divided into a cell region, a transition region and a terminal structure region in a lateral direction (a direction parallel to the surface of the substrate). The cell region is located in the central region of the semiconductor substrate, and a MOS structure is formed in the cell region. The terminal structure region is located in the peripheral region of the semiconductor substrate and surrounds the cell region. The transition region is formed between the cell region and the terminal structure region. Figure 1 As shown, the dotted box marks the range of the cell area, the cell area is located in the center of the device, and the surface is covered with a metal electrode 10' and a polysilicon gate 8'. A transition area and a terminal structure area are formed on the periphery of the cell area. A plurality of polysilicon strips 8a arranged at intervals are formed in the terminal structure area, and the polysilicon strips 8a are formed in a ring shape, surrounding the cell area.

[0025] Specifically, Figure 2 FIG. 1 shows a schematic diagram of a device structure of a partial cell region of a power transistor according to an embodiment of the present utility model. Figure 2As shown, the power transistor according to the embodiment of the utility model comprises: a back electrode layer 1; a substrate 2, the substrate 2 is of a first conductivity type; an epitaxial layer 3 of the first conductivity type located above the substrate, the first conductivity type is, for example, N-type. A plurality of first body regions 4a, a plurality of second body regions 4b and a third body region 5 are formed in the epitaxial layer 3, the plurality of first body regions 4a and the plurality of second body regions 4b are arranged alternately with the epitaxial layer 3, the plurality of first body regions 4a and the plurality of second body regions 4b are of the second conductivity type, the second conductivity type is, for example, P-type. The first body region 4a and the second body region 4b have the same doping concentration, and the first body region 4a and the second body region 4b have the same injection window, that is, the width of the first body region 4a and the second body region 4b is the same. A third body region 5 is formed above the plurality of first body regions 4a and the plurality of second body regions 4b, the conductivity type of the third body region 5 is the same as the conductivity type of the first body region 4a, both of which are of the second conductivity type, the second conductivity type is, for example, P-type. Moreover, the doping concentration of the third body region 5 is higher than the doping concentration of the first body region 4a and the second body region 4b. like Figure 2 As shown, the third body region 5 is formed as a single body region that entirely covers the first body region 4a and the second body region 4b.

[0026] An insulating dielectric layer 10 is formed above the epitaxial layer 3, and a metal electrode layer 12 is formed above the insulating dielectric layer 10; a plurality of trench gates 6 are arranged in the epitaxial layer 3, and the trench gates 6 include a gate oxide layer 7 and a polysilicon gate 8, and the trench gates 6 extend downward from the upper surface of the epitaxial layer (i.e., the upper surface of the third body region 5) and extend downward to the first body region, the second body region and the epitaxial layer. Specifically, one of the plurality of trench gates 6 extends to the interface between the first body region 4a and the epitaxial layer 3, and another of the plurality of trench gates 6 extends to the interface between the second body region 4b and the epitaxial layer 3.

[0027] like Figure 2 As shown, a heavily doped region 9 is provided on one side of the trench gate 6, and no heavily doped region is provided on the other side of the trench gate 6. In the third body region 5 between the first body region 4a and the second body region 4b, one side of the heavily doped region 9 is in direct interface contact with the gate oxide layer 7 of the trench gate, and the other side of the heavily doped region 9 is in direct contact with a conductive via, which penetrates the insulating dielectric layer and extends into the third body region 5. The heavily doped region 9 has a first conductivity type, and the first conductivity type is, for example, N-type. The heavily doped region 9 is heavily doped, and the doping concentration is much higher than the doping concentration of the epitaxial layer 3 and the third body region 5. As a result, the heavily doped region 9 forms an electrical contact with the conductive via, forming a conductive path. The conductive via 9 penetrates the insulating dielectric layer 10 and is in electrical contact with the metal electrode layer 12.

[0028] like Figure 2As shown, two heavily doped regions 9 and a conductive through hole 11 are provided in two adjacent trench gates, and the two adjacent trench gates are electrically connected to the conductive through hole through the heavily doped regions on the corresponding sides, and then realize the conductive path with the metal electrode layer. It can be understood that the size of the heavily doped region 9 (such as the depth and width of the heavily doped region 9) and the size of the conductive through hole 11 (such as the depth and width of the conductive through hole 11 entering the third body region 5) can be adjusted as needed.

[0029] According to the embodiment of the utility model, when the power transistor is used, that is, when the power transistor is powered on, a potential is applied to the third body region 5, the first body region 4a, and the second body region 4b through the metal electrode layer, the conductive through hole, and the middle doped region. Since a heavily doped region 9 is provided on one side of the trench gate 6 to form a channel region, and no heavily doped region is provided on the other side, the capacitance between the gate drain and the gate source of the device is increased, and the current path width of the device when the channel is turned on is increased, which can reduce the conduction loss during operation and reduce the noise and EMI problems generated when the switch is working.

[0030] Easy to understand, though Figure 2 Only two first body regions 4a and one second body region 4b therebetween are shown, but those skilled in the art should be able to understand that Figure 2 It is only a schematic diagram of the structure of a part of the cell area. In the entire cell area, multiple first body areas 4a and multiple second body areas 4b are alternately arranged. Accordingly, multiple conductive vias extend upward from the third body area 5, penetrate the insulating dielectric layer, and reach the metal electrode layer.

[0031] Figure 3 FIG. 1 is a schematic diagram showing a device structure of a partial cell region of a power transistor according to another embodiment of the present utility model. A person skilled in the art should be able to understand that Figure 3 Another embodiment shown is Figure 2 The basic structure and inventive concept of the embodiment shown are the same, the difference is only in accordance with Figure 3 In another embodiment shown, an additional trench gate is provided in the fifth body region between two adjacent trench gates, and heavily doped regions are provided on both sides of the additional trench gate, one side of the two heavily doped regions is in direct interface electrical contact with the additional trench gate, and the other sides are respectively in electrical contact with different conductive vias. When the power transistor is applied, that is, when the power transistor is powered on, the additional trench gate can realize an additional channel region, thereby further increasing the current path width of the device when the channel is turned on while ensuring the capacitance between the gate-drain and gate-source ends of the device.

[0032] like Figure 3As shown, a conductive through hole is formed on both sides of the additional trench gate, one side of the conductive through hole is electrically connected to the additional trench gate through the heavily doped region, and the other side is connected to the trench gate through the heavily doped region.

[0033] As mentioned earlier, Figure 3 The size of the heavily doped region (eg, the depth and width of the heavily doped region) and the size of the conductive via (eg, the depth and width of the conductive via entering the third body region 5) within the partial cell region shown in the figure can be adjusted as needed.

[0034] It can be seen that the power transistor of the utility model is a super junction transistor structure realized by a deep trench filling process, which is characterized in that one side of the trench gate structure is above the second conductivity type and has no heavily doped region, and the other side of the trench structure is above the epitaxial layer and is provided with a heavily doped region to form a channel region. The utility model increases the capacitance between the gate drain and the gate source of the device and increases the current path width of the device when the channel is turned on, which can reduce the conduction loss during operation and reduce the noise and EMI problems generated when the switch is working. The structure preparation method of the utility model does not need to increase additional production costs and is easy to implement.

[0035] The power transistor with a super junction structure according to the embodiment of the utility model can be applied to various electronic devices. For example, by integrating a plurality of such power transistors and other devices (for example, other forms of transistors, etc.), an integrated circuit (IC) can be formed, and an electronic device can be constructed thereby. Therefore, the utility model also provides an electronic device including the above-mentioned power transistor. The electronic device may also include a display screen that cooperates with the integrated circuit and components such as a wireless transceiver that cooperates with the integrated circuit. Such electronic devices include smart phones, computers, tablet computers (PCs), artificial intelligence, wearable devices, mobile power supplies, etc.

[0036] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0037] The embodiments of the present invention are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A power transistor, characterized in that: include: substrate; an epitaxial layer, disposed on the substrate; An insulating dielectric layer, disposed above the epitaxial layer; A metal electrode layer, disposed above the insulating dielectric layer; a plurality of first body regions and a plurality of second body regions, disposed in the epitaxial layer; A third body region is disposed above the plurality of first body regions and the plurality of second body regions, wherein an upper surface of the third body region is flush with an upper surface of the epitaxial layer; A plurality of trench gates are disposed in the third body region and extend downward from the upper surface of the third body region into the first body region, the second body region and the epitaxial layer; A plurality of heavily doped regions are disposed in the third body region; one side of the heavily doped region is in direct interface contact with the trench gate, and the other side of the heavily doped region is in direct contact with a conductive through hole, and the conductive through hole penetrates the insulating dielectric layer and extends into the third body region, Wherein, one side of the trench gate is in direct interface contact with the heavily doped region, and the other side of the trench gate is not provided with a heavily doped region.

2. The power transistor according to claim 1, characterized in that The plurality of trench gates penetrate the third body region downward from the third body region and extend to an interface between the first body region and the epitaxial layer, or extend to an interface between the second body region and the epitaxial layer.

3. The power transistor according to claim 1, characterized in that The first body regions and the second body regions are within the epitaxial layer and are arranged alternately with the epitaxial layer.

4. The power transistor according to claim 1, characterized in that The first body region and the second body region have the same width.

5. The power transistor according to claim 1, characterized in that The first body region and the second body region have different widths.

6. The power transistor according to claim 1, characterized in that The second body region 5 is integrally formed above the plurality of first body regions and the plurality of second body regions.

7. The power transistor according to claim 1, characterized in that The substrate, the epitaxial layer and the heavily doped region all have a first conductivity type.

8. The power transistor according to claim 1, wherein: The first body region, the second body region, and the third body region all have a second conductivity type.

9. The power transistor according to claim 8, characterized in that The doping concentration of the third body region is greater than the doping concentration of the first body region and the second body region.

10. An electronic device comprising an integrated circuit formed at least in part from a power transistor as claimed in any one of claims 1 to 9.

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