SiC MOSFET device capable of reducing parasitic capacitance

Abstract

The utility model discloses a SiC MOSFET device capable of reducing stray capacitance, and relates to the technical field of semiconductors. In the SiC MOSFET device, the oxide dielectric layer for isolating the grid electrode and the source electrode in the device is uniquely arranged, so that the thickness of the oxide dielectric layer is increased, the parasitic capacitance between the grid electrode and the source electrode is reduced and the switching characteristic of the SiC MOSFET device is improved on the premise of not influencing the performance and normal use of the device.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a SiC MOSFET device for reducing parasitic capacitance. Background Art

[0002] Voltage-controlled MOSFET devices are widely used due to their fast switching speed. However, due to the performance limitations of Si materials, traditional Si MOSFET devices are difficult to achieve high voltage capabilities on small-sized chips. Therefore, Si IGBTs are usually used as switching devices in the high-voltage field. However, the structure of IGBT devices results in low switching frequencies. SiC can achieve high voltages on small-sized chips due to its superior physical properties, and SiC materials can directly grow gate oxide layers by thermal oxidation, so it is very suitable for preparing MOSFET devices. Compared with Si MOSFET and SiIGBT, SiC MOSFET devices can achieve high switching frequencies, low conduction losses, and high withstand voltage capabilities on small chip sizes, so they are gradually being used on a large scale in commercial applications.

[0003] The parasitic capacitance of SiC MOSFET devices is composed of gate-source capacitance Cgs, gate-drain capacitance Cgd and drain-source capacitance Cds. Among them, gate-source parasitic capacitance Cgs refers to the capacitance between the gate and source of the device. During the switching process of the device, the existence of gate-source capacitance will cause the switching speed to slow down, thereby reducing the switching efficiency of the device. Secondly, the existence of gate-source capacitance will also cause current leakage, increase power consumption and reduce the working efficiency of the device. In addition, gate-source capacitance will also affect the frequency response of MOSFET devices and reduce the operating frequency of the device. Therefore, reducing the gate-source parasitic capacitance in SiC MOSFET devices can further improve the working efficiency of the device. The current methods to reduce gate-source parasitic capacitance are: (1) by optimizing the structure and process parameters of the device; (2) using special design and layout techniques; (3) introducing some compensation circuits to offset the influence of gate-source capacitance. Utility Model Content

[0004] In view of the above problems, the utility model provides a SiC MOSFET device with reduced parasitic capacitance, which reduces the parasitic capacitance between the gate and the source and improves the switching characteristics of the SiC MOSFET device without affecting the performance and normal use of the device.

[0005] The technical solution of the utility model is:

[0006] A SiC MOSFET device with reduced parasitic capacitance includes a back electrode metal layer, a back ohmic contact alloy layer, a Sub layer, a Drift layer, a front ohmic contact alloy layer and a front electrode metal layer arranged in sequence from bottom to top;

[0007] The top of the Drift layer features:

[0008] An N-region extending downward from the top surface of the Drift layer;

[0009] A P-body region extending downward from the top surface of the N-region;

[0010] A PP region extending downward from a top surface of a middle portion of the N-region;

[0011] An NP region extends downward from the top surface of the N-region and is connected to the PP region; the bottom surfaces of the PP region and the NP region are spaced apart from the bottom surface of the N-region respectively;

[0012] The bottom surface of the front ohmic contact alloy layer is connected to the PP region and the NP region respectively;

[0013] The side of the front ohmic contact alloy layer is provided with a gate oxide layer, a Poly layer and an isolation dielectric layer connected in sequence from bottom to top; the bottom surface of the gate oxide layer is connected to the N-region, the P-body region and the NP region respectively;

[0014] The isolation dielectric layer extends downward from the side of the Poly layer;

[0015] When the middle part of the NP region is a PP region, the downward extension area of ​​the isolation dielectric layer is connected to the NP region;

[0016] When the middle part of the NP region is a P-body region, the downward extension region of the isolation dielectric layer is connected to the NP region and the P-body region respectively;

[0017] The bottom surface of the front electrode metal layer is respectively connected to the isolation dielectric layer and the front ohmic contact alloy layer.

[0018] Specifically, the isolation dielectric layer has two thicknesses in the Y direction;

[0019] When the middle of the NP region is the PP region, the thickness of the downward extending region of the isolation dielectric layer (9) is assumed to be t1;

[0020] When the middle of the NP region is the P-body region, the thickness of the downward extending region of the isolation dielectric layer (9) is assumed to be t2;

[0021] Its t2>t1.

[0022] Specifically, the depth of the P-body region is 0.8-1 um.

[0023] Specifically, the depth of the NP region is 0.4-0.5 um.

[0024] Specifically, the depth of the PP region is 0.6-0.7 um.

[0025] Specifically, the gate oxide layer has a thickness of 45 nm-50 nm.

[0026] In the SiC MOSFET device, the utility model adopts a unique layout of the oxide dielectric layer isolating the gate and the source in the device, and the thickness of the oxide dielectric layer is thickened without affecting the performance and normal use of the device, thereby reducing the parasitic capacitance between the gate and the source, and improving the switching characteristics of the SiC MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a top view of the utility model;

[0028] Figure 2 yes Figure 1 The structural diagram of the AA section in the X direction;

[0029] Figure 3 yes Figure 1 The structural diagram of the BB section in the X direction;

[0030] Figure 4 It is a structural schematic diagram of step S100 of the utility model;

[0031] Figure 5 It is a structural schematic diagram of step S200 of the utility model;

[0032] Figure 6 It is a structural schematic diagram of step S300 of the utility model;

[0033] Figure 7 It is a structural schematic diagram of step S400 of the utility model;

[0034] Figure 8 It is a schematic diagram of the structure of step S500 of the utility model;

[0035] Fig. 9 It is a structural schematic diagram of step S600 of the utility model;

[0036] Fig.10 It is a structural schematic diagram of step S700 of the utility model;

[0037] Fig.11 It is a structural schematic diagram of step S800 of the utility model;

[0038] Fig.12 It is a structural schematic diagram of step S900 of the utility model;

[0039] Fig.13 It is a structural schematic diagram of step S1000 of the utility model;

[0040] Fig.14 It is a structural schematic diagram of step S1100 of the utility model;

[0041] Fig.15 It is a structural schematic diagram of step S1100 of the utility model;

[0042] In the figure, 1 is the Sub layer, 2 is the Drift layer, 3 is the N-region, 4 is the P-body region, 5 is the NP region, 6 is the PP region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the isolation dielectric layer, 10 is the front ohmic contact alloy layer, 11 is the front electrode metal layer, 12 is the back ohmic contact alloy layer, and 13 is the back electrode metal layer. DETAILED DESCRIPTION

[0043] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0044] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0045] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] A method for preparing a SiC MOSFET device for reducing parasitic capacitance comprises the following steps:

[0047] S100, refer to Figure 4 As shown, an epitaxial Drift layer 2 is epitaxially grown on the Sub layer 1;

[0048] In step S100 , the conductivity types of the Sub layer 1 and the Epi layer 2 are both N-type.

[0049] S200, refer to Figure 5 As shown, an N-region 3 is initially formed on the upper surface of the Drift layer 2 by ion implantation;

[0050] The ions implanted into the N-region 3 in step S200 are N ions, with an implantation energy range of 20-300 keV and an implantation dose range of 3.6E11-1E15 cm -2 , the injection temperature is room temperature.

[0051] S300, refer to Figure 6 As shown, a P-body region 4 is initially formed on the upper surface of the Drift layer 2 by ion implantation;

[0052] The ions implanted into the P-body region 4 in step S300 are Al ions, the implantation energy range is 30-500keV, and the implantation dose range is 1E12-1E16cm -2 , the injection temperature is 400℃-600℃.

[0053] The depth of the P-body region 4 is 0.8-1 um.

[0054] S400, refer to Figure 7 As shown, a NP region 5 is initially formed on the upper surface of the Drift layer 2 by ion implantation;

[0055] The ions implanted into the NP region 5 in step S400 are N ions, the implantation energy range is 20-300 keV, and the implantation dose range is 3.6E11-1E15 cm -2 , the injection temperature is room temperature.

[0056] The depth of the NP region 5 is 0.4-0.5 um.

[0057] S500, refer to Figure 8 As shown, a PP region 6 is initially formed on the upper surface of the Drift layer 2 by ion implantation, and then the implantation region is completely formed by high temperature activation annealing;

[0058] The ions implanted into the PP region 6 in step S500 are Al ions, the implantation energy range is 30-500keV, and the implantation dose range is 1E12-1E16cm -2 The implantation temperature is between 400℃ and 600℃, and the high temperature activation annealing temperature is between 1600℃ and 1900℃.

[0059] The depth of the PP region 6 is 0.6-0.7 um.

[0060] S600, refer to Fig. 9 As shown, a gate oxide layer 7 is grown on the top surface of the Drift layer 2 by dry oxygen oxidation;

[0061] S700, reference Fig.10 As shown, a Poly layer 8 is formed on the top surface of the gate oxide layer 7 by polysilicon deposition, serving as the gate electrode of the SiC MOSFET device;

[0062] The thickness of the gate oxide layer 7 is 45nm-50nm.

[0063] S800, reference Fig.11 As shown, an isolation dielectric layer 9 is formed on the top surface of the Drift layer 2 and the Poly layer 8 by oxide deposition, serving as a dielectric for isolating the gate electrode and the source electrode of the SiC MOSFET device;

[0064] The isolation dielectric layer 9 in step S800 has two thicknesses in the Y direction, namely t1 and t2, t2>t1, wherein the thickness of t1 is designed to achieve good ohmic contact between the front Ni metal and the NP region 5 and PP region 6 on the surface of the Drfit layer, and the thickness of t2 is designed to reduce the gate-source parasitic capacitance of the device.

[0065] S900, refer to Fig.12 As shown, a metal layer is formed on the top surface of the Drift layer 2 by metal sputtering, and then a front ohmic contact alloy layer 10 is formed by rapid thermal annealing;

[0066] The sputtered metal in step S900 is Ni metal, and the sputtered thickness is 100 nm.

[0067] S1000, refer to Fig.13 As shown, a front electrode metal layer 11 is formed on the top surface of the isolation dielectric layer 9 and the surface ohmic contact alloy layer 10 by metal sputtering, serving as the source electrode of the SiC MOSFET device;

[0068] The sputtered metal in step S1000 is Ti / AlCu metal, and the sputtered thickness is 100nm / 5000nm.

[0069] S1100, reference Fig.14 As shown, a metal layer is formed on the bottom surface of the Sub layer 1 by metal sputtering, and then a back ohmic contact alloy layer 12 is formed by laser annealing;

[0070] The sputtered metal in step S1100 is Ni metal, and the sputtered thickness is 100 nm.

[0071] S1200, refer to Fig.15 As shown, a back electrode metal layer 13 is formed on the bottom surface of the back contact ohmic alloy layer 12 by metal evaporation to serve as the drain electrode of the SiC MOSFET device;

[0072] The evaporated metal in step S1200 is Ti / Ni / Ag metal, and the metal thickness is 30nm / 300nm / 1200nm.

[0073] A SiC MOSFET for adjusting gate-source parasitic capacitance, comprising a back electrode metal layer 13, a back ohmic contact alloy layer 12, a Sub layer 1, a Drift layer 2, a front ohmic contact alloy layer 10 and a front electrode metal layer 11 arranged in sequence from bottom to top;

[0074] The top of the Drift layer 2 features:

[0075] N-region 3, extending downward from the top surface of the Drift layer 2;

[0076] A P-body region 4 extending downward from a top surface of the N-region 3;

[0077] A PP region 6 extending downward from a top surface of a middle portion of the N-region 3;

[0078] The NP region 5 extends downward from the top surface of the N-region 3 and is connected to the PP region 6; the bottom surfaces of the PP region 6 and the NP region 5 are respectively spaced apart from the bottom surface of the N-region 3; the spacing is 0.2um to improve the reverse withstand voltage performance of the device during the blocking process.

[0079] The bottom surface of the front ohmic contact alloy layer 10 is connected to the PP region 6 and the NP region 5 respectively;

[0080] The side of the front ohmic contact alloy layer 10 is provided with a gate oxide layer 7, a Poly layer 8 and an isolation dielectric layer 9 connected in sequence from bottom to top; the bottom surface of the gate oxide layer 7 is connected to the N-region 3, the P-body region 4 and the NP region 5 respectively;

[0081] The isolation dielectric layer 9 extends downward from the side of the Poly layer 8;

[0082] When the middle of the NP region 5 is the PP region 6, the isolation dielectric layer 9 extends downward to connect with the NP region 5;

[0083] When the middle of the NP region 5 is the P-body region 4, the downward extending region of the isolation dielectric layer 9 is respectively connected to the NP region 5 and the P-body region 4;

[0084] The bottom surface of the front electrode metal layer 11 is connected to the isolation dielectric layer 9 and the front ohmic contact alloy layer 10 respectively.

[0085] When the middle of the NP region 5 is the PP region 6, the downward extending region of the isolation dielectric layer 9 is set as the first extending region, and the thickness value is set as t1;

[0086] When the middle of the NP region 5 is the P-body region 4, the downward extending region of the isolation dielectric layer 9 is set as the second extending region, and the thickness value is set as t2;

[0087] The t1<t2.

[0088] Beneficial effects of the utility model:

[0089] Reduce the gate-source parasitic capacitance of the device and improve the switching characteristics: SiC MOSFET has internal gate-source parasitic capacitance, which causes the gate-source capacitance to affect the switching performance of the device. In application, the switching rate and frequency response of the device are reduced, and the switching loss of the device is increased. The formula is used for calculation, where d is the distance between the gate and the source. Therefore, the utility model adopts a unique layout for the oxide dielectric layer isolating the gate and the source in the SiC MOSFET device, thereby thickening the oxide dielectric layer without affecting the performance and normal use of the device, that is, increasing the distance d between the gate and the source, thereby reducing the parasitic capacitance between the gate and the source, and improving the switching characteristics of the SiC MOSFET device.

Claims

1. A SiC MOSFET device with reduced parasitic capacitance, characterized in that: It comprises a back electrode metal layer (13), a back ohmic contact alloy layer (12), a Sub layer (1), a Drift layer (2), a front ohmic contact alloy layer (10) and a front electrode metal layer (11) which are arranged in sequence from bottom to top; The top of the Drift layer (2) features: An N-region (3) extending downward from the top surface of the Drift layer (2); A P-body region (4) extending downward from the top surface of the N-region (3); A PP region (6) extending downward from a top surface of a middle portion of the N-region (3); An NP region (5) extends downward from the top surface of the N-region (3) and is connected to the PP region (6); the bottom surfaces of the PP region (6) and the NP region (5) are respectively spaced apart from the bottom surface of the N-region (3); The bottom surface of the front ohmic contact alloy layer (10) is connected to the PP region (6) and the NP region (5) respectively; The side of the front ohmic contact alloy layer (10) is provided with a gate oxide layer (7), a Poly layer (8) and an isolation dielectric layer (9) which are connected in sequence from bottom to top; the bottom surface of the gate oxide layer (7) is respectively connected to the N-region (3), the P-body region (4) and the NP region (5); The isolation dielectric layer (9) extends downward from the side of the Poly layer (8); When the middle portion of the NP region (5) is the PP region (6), the isolation dielectric layer (9) extends downward and is connected to the NP region (5); When the middle portion of the NP region (5) is the P-body region (4), the downward extension region of the isolation dielectric layer (9) is respectively connected to the NP region (5) and the P-body region (4); The bottom surface of the front electrode metal layer (11) is respectively connected to the isolation dielectric layer (9) and the front ohmic contact alloy layer (10).

2. The SiC MOSFET device with reduced parasitic capacitance according to claim 1, characterized in that: The isolation dielectric layer (9) has two thicknesses in the Y direction; When the middle of the NP region (5) is the PP region (6), the thickness of the downward extending region of the isolation dielectric layer (9) is assumed to be t1; When the middle of the NP region (5) is the P-body region (4), the thickness of the downward extending region of the isolation dielectric layer (9) is assumed to be t2; Its t2>t1.

3. The SiC MOSFET device with reduced parasitic capacitance according to claim 1, characterized in that: The depth of the P-body region (4) is 0.8-1 um.

4. The SiC MOSFET device with reduced parasitic capacitance according to claim 1, characterized in that: The depth of the NP region (5) is 0.4-0.5 um.

5. The SiC MOSFET device with reduced parasitic capacitance according to claim 1, characterized in that: The depth of the PP region (6) is 0.6-0.7 um.

6. The SiC MOSFET device with reduced parasitic capacitance according to claim 1, characterized in that: The gate oxide layer (7) has a thickness of 45 nm to 50 nm.

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