SiC UMOSFET capable of reducing follow current loss

Abstract

The utility model discloses a SiC UMOSFET capable of reducing follow current loss, and relates to the technical field of semiconductors. The heterojunction diode is formed between the P-type polycrystalline silicon and the SiC drift layer, so that the on-resistance between the P-type polycrystalline silicon and the SiC drift layer is reduced. In the follow current process of the SiC UMOSFET device, due to the fact that on-resistance is smaller, the heterojunction diode is conducted in advance, follow current loss of the SiC UMOSFET device is reduced, the bipolar degradation effect of the SiC UMOSFET caused by follow current of a PN junction body diode can be avoided, and performance deterioration of the device is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC UMOSFET with reduced freewheeling loss. Background Art

[0002] As the main product of the third-generation wide bandgap semiconductor power devices, SiC MOSFET has begun to be widely used in harsh working conditions such as high voltage, high temperature, high frequency, and high radiation due to its excellent physical properties. At present, the SiC MOSFET structure is divided into planar MOSFET (DMOSFET) and trench MOSFET (UMOSFET). Compared with DMOSEFT, under the same current capacity, UMOSFET has a smaller chip size and higher power density. However, the long-term reliability of UMOSFET devices is more challenging than DMOSEFT. Due to the curvature effect of the bottom corner of the trench gate oxide, it is very easy to cause electric field concentration. In addition, the dielectric constants of SiC and SiO2 materials and the SiC / SiO2 interface state density, UMOSFET devices are prone to premature breakdown failure at the gate oxide. However, UMOSFET is still considered by the industry to be the future product development trend due to its lower device cost.

[0003] SiC MOSFET usually integrates PN junction body diodes to protect the device as a leakage path during the freewheeling process. SiIGBT devices usually use an additional freewheeling diode in the bypass to achieve protection. Therefore, in comparison, the structure of the integrated body diode inside the SiC MOSFET not only reduces the number of devices used, but also reduces the cost. However, the design of the internal integrated PN junction body diode also has obvious disadvantages. During the freewheeling process of the device, the P-region holes in the PN junction body diode will easily enter the SiC drift layer, causing the P-region holes to recombine with the SiC drift layer electrons to cause the lattice defects to spread and the bipolar degradation effect to occur. The significant disadvantage is that the performance of the device is deteriorated, especially when the device is used in parallel. The occurrence of this phenomenon will accelerate the breakdown failure of the device, thereby affecting the entire system. Therefore, it is very necessary to avoid the bipolar degradation effect of SiC MOSFET for the long-term stable use of the device. Utility Model Content

[0004] In view of the above problems, the utility model provides a SiC UMOSFET device which not only reduces the freewheeling loss of the SiC UMOSFET device, but also avoids the bipolar degradation effect caused by the freewheeling of the PN junction body diode of the SiCUMOSFET, thereby avoiding the deterioration of the device performance.

[0005] The technical solution of the utility model is:

[0006] A SiC UMOSFET with reduced freewheeling loss, including a SiC Sub layer, a SiC Drift layer, and a front electrode metal layer arranged in sequence from bottom to top;

[0007] Between the SiC Drift layer and the front electrode metal layer there is:

[0008] A P-body region extending downward from the top surface of the SiC Drift layer; an N+ region and a first P+ region extending downward from the top surface are provided in the P-body region, and the first P+ region is connected to the N+ region;

[0009] A groove region extends downward from the top surface of the N+ region through the P-body region; a second P+ region extending downward is provided at the bottom of the groove region; a gate oxide layer connected to the second P+ region is provided on the inner sidewall of the groove region, and the gate oxide layer is filled with a polysilicon Poly layer; the second P+ region is located below the P-body region;

[0010] An isolation dielectric layer, located on the top of the trench region, extending toward the middle of the SiC Drift layer, and connected to the N+ region;

[0011] A source-level Poly layer, located in the middle of the top surface of the SiC Drift layer;

[0012] An ohmic contact alloy layer, located on the top surfaces of the N+ region and the first P+ region, and connected to the isolation dielectric layer;

[0013] The oxide dielectric layer is located between the source-level Poly layer and the ohmic contact alloy layer, and its bottom surface is connected to the SiCDrift layer.

[0014] Specifically, the front electrode metal layer covers the isolation dielectric layer, the ohmic contact alloy layer, the oxide dielectric layer and the source level Poly layer.

[0015] The thickness of the gate oxide layer (6) is between 60nm and 70nm.

[0016] The bottom of the ohmic contact alloy layer (10) contacts the N+ region (4) and the P+ region (5) in the SiCDrift layer (2) to form an ohmic contact.

[0017] The bottom of the front electrode metal layer (12) is connected to the source-level Poly layer (9) and the ohmic contact alloy layer (10) to serve as a device source electrode.

[0018] The utility model forms a heterojunction diode by utilizing P-type polysilicon and SiC drift layer in the SiCUMOSFET device. Since the barrier height of the heterojunction diode can be adjusted by the doping concentration and interface charge of the material, the on-resistance can be made smaller, so that the PN junction body diode originally used as the freewheeling path can be transferred to the heterojunction diode. In the freewheeling process, the heterojunction diode is turned on first, which not only reduces the freewheeling loss of the UMOSFET device, but also avoids the holes in the P region of the PN junction body diode from entering the drift layer to cause the recombination of holes and electrons, thereby preventing the bipolar degradation effect from occurring, thereby avoiding the deterioration of device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of step S100 of the utility model;

[0020] Figure 2 It is a structural schematic diagram of step S200 of the utility model;

[0021] Figure 3 It is a structural schematic diagram of step S300 of the utility model;

[0022] Figure 4 It is a structural schematic diagram of step S400 of the utility model;

[0023] Figure 5 It is a schematic diagram of the structure of step S500 of the utility model;

[0024] Figure 6 It is a structural schematic diagram of step S600 of the utility model;

[0025] Figure 7 It is a structural schematic diagram of step S700 of the utility model;

[0026] Figure 8 It is a structural schematic diagram of step S800 of the utility model;

[0027] Fig. 9 It is a structural schematic diagram of step S900 of the utility model;

[0028] Fig.10 It is a structural schematic diagram of step S1000 of the utility model;

[0029] Fig.11 It is a structural schematic diagram of step S1100 of the utility model;

[0030] Fig.12 It is a structural schematic diagram of step S1200 of the present utility model.

[0031] In the figure, 1 is the SiCSub layer, 2 is the SiCDrift layer, 3 is the P-body region, 4 is the N+ region, 5 is the P+ region, 6 is the gate oxide layer, 7 is the Poly layer, 8 is the isolation dielectric layer, 9 is the source level Poly layer, 10 is the ohmic contact alloy layer, 11 is the oxide dielectric layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0032] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0033] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0034] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] A method for preparing a SiCU MOSFET with an integrated heterojunction diode comprises the following steps:

[0036] S100, refer to Figure 1 As shown, a SiC Drift layer 2 is epitaxially grown on the SiC Sub layer 1;

[0037] In step S100 , the conductivity types of the SiCSub layer 1 and the SiC Drift layer 2 are both N-type.

[0038] S200, refer to Figure 2 As shown, a P-body region 3 is formed on the upper surface of the SiC Drift layer 2 by Al ion implantation;

[0039] The P-body region 3 in step S200 is lightly doped with a doping concentration of 1E17 cm -2 -1E18cm-2 .

[0040] S300, refer to Figure 3 As shown, an N+ region 4 is formed on the upper surface of the P-body region 3 by N ion implantation;

[0041] The N+ region 4 in step S300 is heavily doped, with a doping concentration of 1E18 cm -2 -1E19cm -2 .

[0042] S400, refer to Figure 4 As shown, a groove region is formed by etching from top to bottom on the upper surface of the SiC Drift layer 2;

[0043] S500, refer to Figure 5 As shown, P+ region 5 is formed on the upper surface of P-body region 3 and the bottom of trench region by Al ion implantation, and then high temperature activation annealing is adopted to complete the formation of all implanted regions;

[0044] The P+ region 5 in step S500 is heavily doped, with a doping concentration of 1E18 cm -2 -1E19cm -2 , the high temperature activation annealing temperature is between 1600℃-1900℃.

[0045] S600, refer to Figure 6 As shown, a gate oxide layer 6 is formed on the inner wall of the trench region by introducing oxygen for dry oxygen oxidation growth;

[0046] The thickness of the gate oxide layer 6 in step S600 is 60 nm-70 nm to further improve the robustness of the gate oxide layer.

[0047] S700, reference Figure 7 As shown, a Poly layer 7 is formed inside the gate oxide layer 6 by polysilicon deposition to serve as the gate electrode of the device;

[0048] S800, reference Figure 8 As shown, an isolation dielectric layer (8) is formed on the top of the trench region and the top of the N+ region 4 by oxide deposition to isolate the gate electrode and the source electrode of the device to prevent the two from being short-circuited;

[0049] S900, refer to Fig. 9 As shown, a source-level Poly layer 9 is formed on the top of the SiC Drift layer 2 by a P-type polysilicon deposition method to serve as a heterojunction diode of the device;

[0050] The bottom of the source-level Poly layer 9 in step S900 is only in contact with the SiC Drift layer 2 , serving as a heterojunction diode of the device.

[0051] S1000, refer to Fig.10 As shown, a Ni metal layer is formed on the N+ region 4 and the P+ region 5 of the SiC Drift layer 2 by Ni metal sputtering, and then an ohmic contact alloy layer 10 is formed by alloying annealing;

[0052] In step S1000 , the bottom of the ohmic contact alloy layer 10 contacts the N+ region 4 and the P+ region 5 in the SiCDrift layer 2 to form an ohmic contact.

[0053] S1100, reference Fig.11 As shown, on the top surface of the SiC Drift layer 2, an oxide dielectric layer 11 is formed upward between the source-level Poly layer 9 and the ohmic contact alloy layer 10 by oxide deposition, isolating the source-level Poly layer 9 and the ohmic contact alloy layer 10 to prevent the two from contacting each other;

[0054] In step S1100, the oxide dielectric layer 11 overlaps on both sides of the source level Poly layer 9 and the ohmic contact alloy layer 10 to avoid incomplete deposition of the oxide dielectric layer 11 and formation of holes between the source level Poly layer 9 and the ohmic contact alloy layer 10. The overlapping distance is not set and is adjusted according to actual process conditions.

[0055] S1200, a front electrode metal layer 12 is formed again on the device by Ti / AlCu metal sputtering.

[0056] The bottom of the front electrode metal layer 12 in step S1200 is connected to the source-level Poly layer 9 and the ohmic contact alloy layer 10 to serve as the device source electrode.

[0057] A SiC UMS OFET with an integrated heterojunction diode, comprising a SiC Sub layer 1, a SiC Drift layer 2 and a front electrode metal layer 12 arranged in sequence from bottom to top;

[0058] Between the SiC Drift layer 2 and the front electrode metal layer 12 there is:

[0059] A P-body region 3 extends downward from the top surface of the SiC Drift layer 2; an N+ region 4 and a first P+ region extending downward from the top surface are provided in the P-body region 3, and the first P+ region is connected to the N+ region 4;

[0060] A trench region extends downward from the top surface of the N+ region 4 through the P-body region 3; a second P+ region extending downward is provided at the bottom of the trench region; a gate oxide layer 6 connected to the second P+ region is provided on the inner sidewall of the trench region, and the gate oxide layer 6 is filled with a polysilicon Poly layer 7;

[0061] An isolation dielectric layer 8, located at the top of the trench region, extending toward the middle of the SiC Drift layer 2, and connected to the N+ region 4;

[0062] A source-level Poly layer 9, located in the middle of the top surface of the SiCDrift layer 2;

[0063] An ohmic contact alloy layer 10, located on the top surfaces of the N+ region 4 and the first P+ region, and connected to the isolation dielectric layer 8;

[0064] The oxide dielectric layer 11 is located between the source-level Poly layer 9 and the ohmic contact alloy layer 10 , and its bottom surface is connected to the SiCDrift layer 2 .

[0065] The front electrode metal layer 12 covers the isolation dielectric layer 8 , the ohmic contact alloy layer 10 , the oxide dielectric layer 11 and the source level Poly layer 9 .

[0066] Beneficial effects of the utility model:

[0067] Reduce device freewheeling losses and avoid bipolar degradation effects:

[0068] Conventional SiC MOSFET devices have an anti-parallel PN junction body diode integrated inside, so during the freewheeling process, the PN junction body diode will be turned on as a leakage path to protect the MOSFET device. However, during the freewheeling process, the P-region holes in the PN junction will also easily enter the SiC drift layer, causing the P-region holes to recombine with the drift layer electrons, causing the lattice defects in the drift layer to spread and deteriorate the device performance.

[0069] The utility model forms a heterojunction diode by using P-type polysilicon and SiC drift layer in SiC UMOSFET device. Since the barrier height of the heterojunction can be adjusted by the doping concentration and interface charge of the material, the on-resistance can be made smaller, and the on-voltage drop is lower than that of the PN junction body diode. In the freewheeling process, the heterojunction diode will be turned on first, which not only reduces the freewheeling loss of the SiC UMOSFET device, but also avoids the occurrence of bipolar degradation effect. In addition, compared with SiC DMOSFET devices with the same integrated heterojunction diode, the chip size of the UMOSFET device will be smaller and the power density will be higher at the same current capacity. At the same threshold voltage, since the channel electron mobility of the UMOSFET device is higher, the thickness of the trench gate oxide layer can be made thicker and the robustness is better.

Claims

1. A SiC UMOSFET with reduced freewheeling loss, characterized in that: It includes a SiC Sub layer (1), a SiC Drift layer (2) and a front electrode metal layer (12) which are arranged in sequence from bottom to top; Between the SiC Drift layer (2) and the front electrode metal layer (12) there is provided: A P-body region (3) extending downward from the top surface of the SiC Drift layer (2); an N+ region (4) and a first P+ region extending downward from the top surface are provided in the P-body region (3), and the first P+ region is connected to the N+ region (4); A trench region extending downward from the top surface of the N+ region (4) through the P-body region (3); a second P+ region extending downward is provided at the bottom of the trench region; a gate oxide layer (6) connected to the second P+ region is provided on the inner sidewall of the trench region, and the gate oxide layer (6) is filled with a polysilicon Poly layer (7); the second P+ region is located below the P-body region (3); An isolation dielectric layer (8), located at the top of the trench region, extending toward the middle of the SiC Drift layer (2), and connected to the N+ region (4); A source-level Poly layer (9), located in the middle of the top surface of the SiC Drift layer (2); An ohmic contact alloy layer (10), located on the top surfaces of the N+ region (4) and the first P+ region, and connected to the isolation dielectric layer (8); The oxide dielectric layer (11) is located between the source-level Poly layer (9) and the ohmic contact alloy layer (10), and its bottom surface is connected to the SiC Drift layer (2).

2. The SiC UMOSFET with reduced freewheeling loss according to claim 1, characterized in that: The front electrode metal layer (12) covers the isolation dielectric layer (8), the ohmic contact alloy layer (10), the oxide dielectric layer (11) and the source-level Poly layer (9).

3. The SiC UMOSFET with reduced freewheeling loss according to claim 1, characterized in that: The thickness of the gate oxide layer (6) is between 60nm and 70nm.

4. The SiC UMOSFET with reduced freewheeling loss according to claim 1, characterized in that: The bottom of the ohmic contact alloy layer (10) contacts the N+ region (4) and the P+ region (5) in the SiCDrift layer (2) to form an ohmic contact.

5. The SiC UMOSFET with reduced freewheeling loss according to claim 1, characterized in that: The bottom of the front electrode metal layer (12) is connected to the source-level Poly layer (9) and the ohmic contact alloy layer (10) to serve as a device source electrode.

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