Inverter circuit and semiconductor circuit

Abstract

The utility model provides an inverter circuit and a semiconductor circuit. The inverter circuit includes a gate electrode, a gate dielectric layer, a second conductive type semiconductor layer, a first source electrode, a second source electrode, and a shared drain electrode. The gate electrode is formed on the interlayer dielectric layer. The gate dielectric layer is formed on the gate electrode. The first conductive type semiconductor layer is formed on the gate dielectric layer. The second conductive type semiconductor layer is formed on the gate dielectric layer and is laterally offset relative to the first conductive type semiconductor layer. And a first source electrode formed in contact with the first conductive type semiconductor layer. The second source electrode is formed in contact with the second conductive type semiconductor layer. The shared drain electrode is formed in contact with the first conductive type semiconductor layer and the second conductive type semiconductor layer.

Description

Technical Field

[0001] The utility model relates to an integrated circuit, and in particular to an inverter circuit and a semiconductor circuit. Background Art

[0002] The semiconductor industry has grown due to the continued improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, inductors, capacitors, etc.). In large part, these improvements in integration density come from repeated reductions in minimum feature size, which enables more components to be integrated into a given area. In this regard, individual transistors, interconnects, and related structures have become smaller and smaller, and there is a continuing need to develop new materials, processes, and designs for semiconductor devices and interconnects to enable further advances.

[0003] Transistors made of oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration because they can be processed at low temperatures and thus may not damage previously fabricated devices. For example, fabrication conditions and techniques may not damage previously fabricated front-end-of-line (FEOL) and middle-end-of-line (MEOL) devices. Circuits based on oxide semiconductor-based transistor devices may also include other components that may be fabricated in BEOL processes, such as capacitors, inductors, resistors, and integrated passive devices. Utility Model Content

[0004] The utility model provides an inverter circuit, comprising: a gate electrode, a gate dielectric layer, a first conductive semiconductor layer, a second conductive semiconductor layer, a first source electrode, a second source electrode and a shared drain electrode. The gate electrode is formed on an interlayer dielectric layer. The gate dielectric layer is formed on the gate electrode. The first conductive semiconductor layer is formed on the gate dielectric layer. The second conductive semiconductor layer is formed on the gate dielectric layer, and is laterally offset relative to the first conductive semiconductor layer and isolated from the first conductive semiconductor layer. The first source electrode is formed to contact the first conductive semiconductor layer. The second source electrode is formed to contact the second conductive semiconductor layer. The shared drain electrode is formed to contact the first conductive semiconductor layer and the second conductive semiconductor layer. .

[0005] A semiconductor circuit of the utility model comprises a gate electrode, a p-type metal oxide semiconductor layer, an n-type metal oxide semiconductor layer, a first source electrode, a second source electrode and a shared drain electrode. The gate electrode is formed on an interlayer dielectric layer so that the gate electrode is parallel to the horizontal interface of the interlayer dielectric layer. The p-type metal oxide semiconductor layer is formed on the gate electrode so that the p-type metal oxide semiconductor layer is close to the horizontal surface of the gate electrode. The n-type metal oxide semiconductor layer is formed on the gate electrode so that the n-type metal oxide semiconductor layer is close to the horizontal surface of the gate electrode and is laterally offset relative to the p-type metal oxide semiconductor layer and isolated from the p-type metal oxide semiconductor layer. The first source electrode is formed to contact the p-type metal oxide semiconductor layer. The second source electrode is formed to contact the n-type metal oxide semiconductor layer. The shared drain electrode electrically connects the p-type metal oxide semiconductor layer with the n-type metal oxide semiconductor layer.

[0006] In order to make the above features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a vertical cross-sectional view of a first structure after forming a complementary metal oxide semiconductor (CMOS) transistor, forming a first metal interconnect structure and an isolation dielectric layer in a lower level dielectric material layer according to various embodiments.

[0009] Figure 2A is a three-dimensional perspective view of a semiconductor circuit that can be formed in a BEOL process according to various embodiments.

[0010] Figure 2B According to various embodiments Figure 2A Schematic equivalent circuit of the semiconductor circuit shown.

[0011] Figure 2C According to various embodiments Figure 2A Another three-dimensional perspective view of a semiconductor circuit is shown, illustrating various sizes of components of the semiconductor circuit.

[0012] Figure 3A is a top view of an intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0013] Figure 3B According to various embodiments Figure 3A A vertical cross-sectional view of the intermediate structure shown.

[0014] Figure 4A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0015] Figure 4B According to various embodiments Figure 4A A vertical cross-sectional view of the intermediate structure shown.

[0016] Figure 5A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0017] Figure 5B According to various embodiments Figure 5A A vertical cross-sectional view of the intermediate structure shown.

[0018] Fig. 6A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0019] Figure 6B According to various embodiments Fig. 6A A vertical cross-sectional view of the intermediate structure shown.

[0020] Fig. 7A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0021] Figure 7B According to various embodiments Fig. 7A A vertical cross-sectional view of the intermediate structure shown.

[0022] Fig. 8A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0023] Figure 8B According to various embodiments Fig. 8A A vertical cross-sectional view of the intermediate structure shown.

[0024] Fig. 9A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0025] Fig. 9B According to various embodiments Fig. 9A A vertical cross-sectional view of the intermediate structure shown.

[0026] Fig. 10A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0027] Fig. 10B According to various embodiments Fig. 10A A vertical cross-sectional view of the intermediate structure shown.

[0028] Fig.11A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0029] Fig. 11B According to various embodiments Fig.11A A first vertical cross-sectional view of the intermediate structure is shown.

[0030] Fig. 11C According to various embodiments Fig.11A A second vertical cross-sectional view of the intermediate structure is shown.

[0031] Fig. 12A is a top view of yet another intermediate structure that may be used to form a semiconductor circuit according to various embodiments.

[0032] Fig. 12B According to various embodiments Fig. 12A A first vertical cross-sectional view of the intermediate structure is shown.

[0033] Fig. 12C According to various embodiments Fig. 12A A second vertical cross-sectional view of the intermediate structure is shown.

[0034] Fig.13A According to various embodiments, by referring to FIG. 3A to FIG. 13C A top view of a semiconductor circuit formed by the described process.

[0035] Fig. 13B According to various embodiments Fig.13A A first vertical cross-sectional view of a semiconductor circuit is shown.

[0036] Fig. 13C According to various embodiments Fig.13A A second vertical cross-sectional view of the semiconductor circuit is shown.

[0037] Fig.14A is a top view of a semiconductor circuit according to another embodiment of various embodiments, which can be connected with the semiconductor circuit shown in FIG. FIG. 3A to FIG. 13C The process described is similar to the process used to form.

[0038] Fig. 14B According to various embodiments Fig.14A A first vertical cross-sectional view of a semiconductor circuit is shown.

[0039] Fig. 14C According to various embodiments Fig.14AA second vertical cross-sectional view of the semiconductor circuit is shown.

[0040] Fig.14D According to various embodiments Fig.14A A three-dimensional perspective view of the semiconductor circuit shown.

[0041] Fig.15A is a top view of a semiconductor circuit according to another embodiment of various embodiments, which can be viewed from above with reference to FIG. 3A to FIG. 13C The process described is similar to the process used to form.

[0042] Fig. 15B According to various embodiments Fig.15A A first vertical cross-sectional view of a semiconductor circuit is shown.

[0043] Fig. 15C According to various embodiments Fig.15A A second vertical cross-sectional view of the semiconductor circuit is shown.

[0044] Fig.15D According to various embodiments Fig.15A A three-dimensional perspective view of the semiconductor circuit shown.

[0045] Fig.16 is a flowchart illustrating the operations of a method of forming a semiconductor circuit according to various embodiments. DETAILED DESCRIPTION

[0046] The following disclosure provides many different embodiments or examples to implement different features of the provided target. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0047] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Unless expressly stated otherwise, each component having the same reference number is assumed to have the same material composition and have a thickness within the same thickness range.

[0048] Various embodiments of the present disclosure provide semiconductor circuits and methods that may have advantages in terms of manufacturing flexibility, size reduction, and reduction in short channel effect. In this regard, an embodiment semiconductor circuit (e.g., a complementary metal oxide semiconductor (CMOS) inverter) is provided, which can be formed in a BEOL process and can be combined with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. As such, the disclosed semiconductor circuit may include materials that can be processed at low temperatures. Therefore, the fabrication of such a semiconductor circuit may not damage previously fabricated devices (e.g., FEOL devices and MEOL devices). In addition, various embodiment semiconductor circuits may include a dual conductive channel (e.g., a p-type channel and an n-type channel separated by an isolation oxide in a first horizontal direction) formed above a back gate electrode. The semiconductor circuit may have a reduced size relative to an alternative structure that does not include such a dual channel / back gate configuration. The embodiment semiconductor circuit may allow for a longer channel length without increasing the device size, which may mitigate the short channel effect.

[0049] An inverter circuit of an embodiment may include: a gate electrode formed on an interlayer dielectric layer; a gate dielectric layer formed on the gate electrode; a first conductive type semiconductor layer formed on the gate dielectric layer; a second conductive type semiconductor layer formed on the gate dielectric layer and laterally offset relative to the first conductive type semiconductor layer; a first source electrode formed to contact the first conductive type semiconductor layer; a second source electrode formed to contact the second conductive type semiconductor layer; and a shared drain electrode formed to contact the first conductive type semiconductor layer and the second conductive type semiconductor layer. At least one of the first conductive type semiconductor layer and the second conductive type semiconductor layer may include a metal oxide semiconductor and / or a multilayer structure formed in a BEOL process, and the metal oxide semiconductor and / or the multilayer structure may be combined with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices.

[0050] In yet another embodiment, a semiconductor circuit may include: a gate electrode formed on an interlayer dielectric layer so that the gate electrode is parallel to a horizontal interface of the interlayer dielectric layer; a p-type metal oxide semiconductor layer formed on the gate electrode so that the p-type metal oxide semiconductor layer is adjacent to a horizontal surface of the gate electrode; an n-type metal oxide semiconductor layer formed on the gate electrode so that the n-type metal oxide semiconductor layer is adjacent to the horizontal surface of the gate electrode and is laterally offset relative to the p-type metal oxide semiconductor layer; a first source electrode formed to contact the p-type metal oxide semiconductor layer; a second source electrode formed to contact the n-type metal oxide semiconductor layer; and a shared drain electrode electrically connecting the p-type metal oxide semiconductor layer and the n-type metal oxide semiconductor layer.

[0051] An embodiment method for forming a semiconductor circuit may include: forming a gate electrode on an interlayer dielectric layer; forming a gate dielectric layer on the gate electrode; forming a first conductive semiconductor layer on the gate dielectric layer; forming a second conductive semiconductor layer on the gate dielectric layer so that the second conductive semiconductor layer is laterally offset relative to the first conductive semiconductor layer; forming a first source electrode in contact with the first conductive semiconductor layer; forming a second source electrode in contact with the second conductive semiconductor layer; and forming a shared drain electrode in contact with the first conductive semiconductor layer and the second conductive semiconductor layer.

[0052] Figure 1 A semiconductor structure 100 according to various embodiments is shown. The semiconductor structure 100 includes a substrate 102, which may be a semiconductor substrate (e.g., a commercially available silicon substrate). The substrate 102 may include, or at least include at an upper portion thereof, a semiconductor material layer 104. The semiconductor material layer 104 may be a surface portion of a bulk semiconductor substrate, or may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In an embodiment, the semiconductor material layer 104 includes a single crystalline semiconductor material (e.g., single crystalline silicon). In an embodiment, the substrate 102 may include a single crystalline silicon substrate including a single crystalline silicon material.

[0053] A shallow trench isolation structure 106 including a dielectric material such as silicon oxide may be formed in an upper portion of the semiconductor material layer 104. A suitable doped semiconductor well such as a p-type well and an n-type well may be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 106. Field effect transistors 108 may be formed over a top surface of the semiconductor material layer 104. For example, each of the field effect transistors 108 may include a source electrode 110, a drain electrode 112, a semiconductor channel 114 including a surface portion of the substrate 102 extending between the source electrode 110 and the drain electrode 112, and a gate structure 116. The semiconductor channel 114 may include a single crystalline semiconductor material.

[0054] Each gate structure 116 may include a gate dielectric layer 118, a gate electrode 120, a gate cap dielectric 122, and a dielectric gate spacer 124. A source-side metal semiconductor alloy region 126 may be formed on each source electrode 110, and a drain-side metal semiconductor alloy region 128 may be formed on each drain electrode 112. The devices formed on the top surface of the semiconductor material layer 104 may include complementary metal oxide semiconductor (CMOS) transistors and optional additional semiconductor devices such as resistors, diodes, capacitors, etc., and are collectively referred to as CMOS circuitry 134.

[0055] Figure 1 The semiconductor structure 100 may include a memory array region 130 in which an array of memory cells may be subsequently formed. The first exemplary structure may also include a peripheral region 132 in which metal wiring for the array of memory devices is provided. Generally speaking, the field effect transistors 108 in the CMOS circuit system 134 may be electrically connected to electrodes of corresponding memory cells through corresponding sets of metal interconnect structures.

[0056] The devices in the peripheral region 132 (e.g., field effect transistors 108) may provide functions for operating an array of memory cells to be formed later. Specifically, the devices in the peripheral region may be configured to control programming operations, erasing operations, and sensing (reading) operations of the array of memory cells. For example, the devices in the peripheral region 132 may include sensing circuitry and / or programming circuitry.

[0057] One or more of the field effect transistors 108 in the CMOS circuit system 134 may include a semiconductor channel 114 that includes a portion of a semiconductor material layer 104 in the substrate 102. In an embodiment in which the semiconductor material layer 104 includes a single crystalline semiconductor material (e.g., single crystalline silicon), the semiconductor channel 114 of each of the field effect transistors 108 in the CMOS circuit system 134 may include a single crystalline semiconductor channel (e.g., a single crystalline silicon channel). In an embodiment, a plurality of field effect transistors 108 in the CMOS circuit system 134 may include a corresponding node that is subsequently electrically connected to a node of a corresponding memory cell to be subsequently formed. For example, a plurality of field effect transistors 108 in the CMOS circuit system 134 may include a corresponding source electrode 110 or a corresponding drain electrode 112 that is subsequently electrically connected to a node of a corresponding memory cell to be subsequently formed.

[0058] In an embodiment, the CMOS circuit system 134 may include a programming control circuit configured to control the gate voltage of a group of field effect transistors 108 (the gate voltage may be used to program the corresponding memory cells (e.g., ferroelectric memory cells)) and control the gate voltage of transistors (e.g., thin film transistors) to be formed subsequently. In this embodiment, the programming control circuit may be configured to provide a first programming pulse, the first programming pulse programs the corresponding ferroelectric dielectric material layer in the selected ferroelectric memory cell to a first polarization state, in which the electrical polarization in the ferroelectric dielectric material layer is directed toward the first electrode of the selected ferroelectric memory cell, and the programming control circuit may be configured to provide a second programming pulse, the second programming pulse programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell to a second polarization state, in which the electrical polarization in the ferroelectric dielectric material layer is directed toward the second electrode of the selected ferroelectric memory cell.

[0059] In an embodiment, the substrate 102 may include a single crystal silicon substrate, and the field effect transistor 108 may include a corresponding portion of the single crystal silicon substrate as a semiconducting channel. As used herein, a "semiconducting" device refers to a device having a conductivity of 1.0×10 -6 Siemens / cm (S / cm) to 1.0×10 5 Siemens / cm range. As used herein, "semiconductor material" refers to a material in which the electrical conductivity in the absence of electrical dopants is in the range of 1.0×10 -6 Siemens / cm to 1.0×10 5 Siemens / cm range and can produce conductivity in the range of 1.0 Siemens / cm to 1.0×10 5 Doped materials in the Siemens / cm range.

[0060] According to an embodiment, the field effect transistor 108 may then be electrically connected to a drain electrode and a gate electrode of an access transistor including a semiconductive metal oxide plate to be formed above the field effect transistor 108. In an embodiment, a subset of the field effect transistors 108 may then be electrically connected to at least one of the drain electrode and the gate electrode. For example, the field effect transistor 108 may include a first word line driver configured to apply a first gate voltage to a first word line through a first subset of a lower level metal interconnect structure to be formed later, and a second word line driver configured to apply a second gate voltage to a second word line through a second subset of a lower level metal interconnect structure to be formed later. In addition, the field effect transistor 108 may include a bit line driver configured to apply a bit line bias voltage to a bit line to be formed later, and a sense amplifier configured to detect a current flowing through the bit line during a read operation.

[0061] Various metal interconnect structures formed in the dielectric material layer may subsequently be formed over the substrate 102 and the semiconductor devices thereon, such as the field effect transistor 108. In an illustrative example, the dielectric material layer may include, for example, a first dielectric material layer 136 (sometimes referred to as a contact level dielectric material layer), which may be a layer surrounding contact structures connected to the source and drain, a first interconnect level dielectric material layer 138, and a second interconnect level dielectric material layer 140. The metal interconnect structures may include a device contact via structure 142 formed in the first dielectric material layer 136 and contacting respective components of the CMOS circuitry 134, a first metal line structure 144 formed in the first interconnect level dielectric material layer 138, a first metal via structure 146 formed in a lower portion of the second interconnect level dielectric material layer 140, and a second metal line structure 148 formed in an upper portion of the second interconnect level dielectric material layer 140.

[0062] Each of the dielectric material layers (136, 138, 140) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (142, 144, 146, 148) may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and / or combinations thereof.

[0063] Other suitable metal liner and metal filling materials within the scope of the present disclosure may also be used. In an embodiment, the first metal via structure 146 and the second metal line structure 148 may be formed as an integrated line and via structure by a dual damascene process. The dielectric material layers (136, 138, 140) are referred to herein as lower level dielectric material layers. The metal interconnect structures (142, 144, 146, 148) formed in the lower level dielectric material layers are referred to herein as lower level metal interconnect structures.

[0064] Although the present disclosure is described using embodiments in which an array of memory cells may be formed above the second line and via level dielectric material layer 140, embodiments in which an array of memory cells may be formed at a different metal interconnect level are expressly contemplated herein.

[0065] An array of thin film transistors and an array of ferroelectric memory cells (or other types of memory cells) may then be deposited on the dielectric material layers (136, 138, 140) in which the metal interconnect structures (142, 144, 146, 148) are formed. A set of all dielectric material layers formed before forming the array of thin film transistors or the array of ferroelectric memory cells is collectively referred to as lower-level dielectric material layers (136, 138, 140). A set of all metal interconnect structures formed within the lower-level dielectric material layers (136, 138, 140) is referred to herein as first metal interconnect structures (142, 144, 146, 148). In general, the first metal interconnect structures (142, 144, 146, 148) formed within at least one lower-level dielectric material layer (136, 138, 140) may be formed on the semiconductor material layer 104 located in the substrate 102.

[0066] According to an embodiment, a thin film transistor may then be formed in the metal interconnect level, the thin film transistor being overlying the metal interconnect level including the lower level dielectric material layer (136, 138, 140) and the first metal interconnect structure (142, 144, 146, 148). In an embodiment, a planar dielectric material layer having a uniform thickness may be formed over the lower level dielectric material layer (136, 138, 140). The planar dielectric material layer is referred to herein as an insulating matrix layer 150. The insulating matrix layer 150 may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating matrix layer 150 may range from 20 nanometers (i.e., 200 angstroms) to 300 nanometers (i.e., 3000 angstroms), although lesser and greater thicknesses may also be employed.

[0067] Generally, an interconnect level dielectric layer (e.g., lower level dielectric material layer (136, 138, 140)) containing metal interconnect structures (e.g., first metal interconnect structures (142, 144, 146, 148)) may be formed over the semiconductor device. An insulating matrix layer 150 may be formed over the interconnect level dielectric layer. Other passive devices may be formed in the BEOL process. For example, various capacitors, inductors, resistors, and integrated passive devices may be used with other BEOL devices.

[0068] Figure 2A is a three-dimensional perspective view of a semiconductor circuit 200 that can be formed in a BEOL process, and Figure 2B According to various embodiments Figure 2A Schematic equivalent circuit 200b of semiconductor circuit 200 is shown. Figure 2A As shown, the semiconductor circuit 200 may include a gate electrode 116 formed on an interlayer dielectric layer (not shown). For example, the semiconductor circuit 200 may be formed on an insulating matrix layer 150 (eg, see Figure 1 ) or on one or more additional interconnect layers formed on the insulating matrix layer 150. The semiconductor circuit 200 may further include: a gate dielectric layer 118 formed on the gate electrode 116; a first conductivity type semiconductor layer (e.g., a p-type semiconductor layer 206a) formed on the gate dielectric layer 118; and a second conductivity type semiconductor layer (e.g., an n-type semiconductor layer 206b) formed on the gate dielectric layer 118 and laterally offset relative to the first conductivity type semiconductor layer 206a.

[0069] The semiconductor circuit 200 may further include a first source electrode 110a formed in contact with the first conductive type semiconductor layer 206a and a second source electrode 110b formed in contact with the second conductive type semiconductor layer 206b. The semiconductor circuit 200 may further include a shared drain electrode 112 in contact with the first conductive type semiconductor layer 206a and the second conductive type semiconductor layer 206b. The semiconductor circuit 200 may be formed on an interlayer dielectric layer having a horizontal interface (e.g., see Figure 1 The insulating matrix layer 150 is shown above.

[0070] like Figure 2A As shown, the gate electrode 116 may include a surface 117 that is adjacent to an interlayer dielectric layer 150 (eg, see Figure 1) is parallel to the horizontal interface of the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b. The first conductive semiconductor layer 206a may include a first channel layer 119a formed in a horizontal direction (for example, parallel to the surface 117 of the gate electrode 116) near the surface 117 of the gate electrode 116. Similarly, the second conductive semiconductor layer 206b may include a second channel layer 119b formed in a horizontal direction adjacent to the surface 117 of the gate electrode 116. In this way, the semiconductor circuit 200 may include a dual conductive channel (119a, 119b) and a back gate electrode 116, and the back gate electrode 116 may be used to form an inverter circuit 200b, as described below with reference to Figure 2B A more detailed description is shown below.

[0071] like Figure 2A As shown, the semiconductor circuit 200 may include another interlayer dielectric layer (eg, 7A to 15C The fourth interlayer dielectric layer 304d is formed so that the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b are electrically insulated from each other by another interlayer dielectric layer 304d. Since the fourth interlayer dielectric layer 304d isolates the first conductive semiconductor layer 206a from the second conductive semiconductor layer 206b, the fourth interlayer dielectric layer 304d can also be referred to as an isolation oxide or an isolation dielectric. Figure 2A As shown, the first source electrode 110a can be electrically connected to the voltage supply 208 (e.g., can be maintained at the source voltage VDD), and the second source electrode 110b can be connected to the ground voltage terminal 210 (e.g., can be maintained at the ground (GND) voltage). The gate electrode 116 can be connected to the input signal (Vin) terminal 212, and the shared drain electrode 112 can be electrically connected to the output signal (Vout) terminal 214. In this way, the semiconductor circuit 200 can be configured as an inverter circuit 200b, such as Figure 2B shown.

[0072] Figure 2B According to various embodiments Figure 2ASchematic equivalent circuit 200b of semiconductor circuit 200 is shown. In this regard, p-type semiconductor layer 206a can be configured to include a horizontal p-channel layer 119a of a p-channel metal oxide semiconductor field effect transistor (MOSFET) (i.e., pFET 216), and n-type semiconductor layer 206 can be configured to include a horizontal n-channel layer 119b of an n-channel MOSFET transistor (i.e., nFET 218). Therefore, pFET 216 can include p-type semiconductor layer 206a, a first source electrode 110a, a shared drain electrode 112, a gate dielectric layer 118, and a gate electrode 116. Similarly, nFET 218 can include n-type semiconductor layer 206b, a second source electrode 110b, a shared drain electrode 112, a gate dielectric layer 118, and a gate electrode 116.

[0073] Reference Figure 2B , a low voltage applied to the input signal terminal 212 turns on the pFET 216 and turns off the nFET 218. Since the source of the pFET 216 (i.e., the first source electrode 110a) is connected to the voltage supply 208 having the high voltage VDD, the output voltage Vout (i.e., the voltage at the shared drain electrode 112) will have a high voltage. Similarly, a high voltage placed on the input signal terminal 212 turns on the nFET 218 and turns off the pFET 216. Since the source of the nFET 218 (i.e., the second source electrode 110b) is connected to the ground voltage terminal 210, the output voltage Vout (i.e., the voltage at the shared drain electrode 112) will have a low voltage GND. In this way, a high input signal applied at Vin is converted into a low output signal Vout, and a low input signal applied at Vin is converted into a high output signal Vout. As such, the semiconductor circuit 200 may be configured as an inverter circuit 200 b and operate as the inverter circuit 200 b .

[0074] An interlayer dielectric layer (eg, see Figure 1 The lower level dielectric material layer (136, 138, 140) in the embodiment of the present invention may include one or more electrical interconnect structures (e.g., see Figure 1 The first metal interconnect structure (142, 144, 146, 148) in the embodiment of the present invention is a first metal interconnect structure (142, 144, 146, 148), wherein the one or more electrical interconnect structures can be electrically connected to Figure 2A and Figure 2BThe semiconductor circuit 200 is shown. In this aspect, one or more of the first source electrode 110a, the second source electrode 110b, the shared drain electrode 112, and the gate electrode 116 can be electrically connected to the one or more electrical interconnect structures (142, 144, 146, 148) formed in one or more dielectric material layers (136, 138, 140) below the semiconductor circuit 200. In other embodiments, one or more of the first source electrode 110a, the second source electrode 110b, the shared drain electrode 112, and the gate electrode 116 can be electrically connected to one or more electrical interconnect structures that will be subsequently formed above the semiconductor circuit 200.

[0075] In one or more embodiments, one or both of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b may include a metal oxide semiconductor. For example, the p-type semiconductor layer 206a may include one or more of NiO, SnO, Cu2O, etc., and the n-type semiconductor layer 206b may include amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and one or more of their alloys. In some embodiments, the n-type semiconductor layer 206b may have a x Ga y Zn z The composition given by MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce and Sn. In other embodiments, the n-type semiconductor layer 206b may include an alloy of oxygen, a group III element and a group V element. In other embodiments, one or more of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b may be formed of a metal oxide semiconductor having a multi-layer structure.

[0076] In some embodiments, one or more of the gate dielectric layers 118 may include a high-k dielectric material and may include one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, hafnium dioxide-aluminum oxide, etc. As described in more detail below, one or more of the first source electrode 110a, the second source electrode 110b, and the shared drain electrode 112 may include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, Al, etc. Other suitable conductor materials may be within the scope of the present disclosure. For example, in some embodiments, one or more of the first source electrode 110a, the second source electrode 110b and the shared drain electrode 112 may further include one or more alloys of one or more of W, Mo, Co, Pd, Ti and mixtures thereof with N and / or O or without N and / or O, the alloys being deposited by chemical vapor deposition or by atomic layer deposition.

[0077] As described above, the p-type semiconductor layer 206a may be configured to include a pFET 216 device (see, e.g., Figure 2B ) of the p-channel layer 119a (see, for example, Figure 2A ), and the n-type semiconductor layer 206b may be configured to include an nFET 218 device (eg, see Figure 2B ) of the n-channel layer 119b (see, for example, Figure 2A Thus, in the example where the corresponding device (pFET 216, nFET 218) is enabled, the current may be as follows: Figure 2A In this regard, when the pFET 216 is enabled (e.g., by applying a low bias or zero bias to the gate electrode 116), positive charge carriers (i.e., "holes") may flow from the first source electrode 110a to the shared drain electrode 112 (e.g., see Figure 2A ), thereby generating a first current 220a. Similarly, when the nFET 218 is enabled (e.g., by applying a high bias voltage to the gate electrode 116), negative charge carriers (i.e., electrons) may flow from the shared drain electrode 112 to the second source electrode 110b, but since the current carried by the negative charges is opposite to their movement, the movement of charges in the nFET 218 generates a second current 220b in the same direction as the first current 220a flowing in the pFET 216.

[0078] Figure 2C is a diagram showing various embodiments Figure 2AAnother three-dimensional stereogram of various sizes of components of the semiconductor circuit 200 is shown. Each of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b may have a corresponding channel length 222 and a corresponding channel width (224a, 224b). For example, the p-type semiconductor layer 206a may have a first channel width 224a, and the n-type semiconductor layer 206b may have a second channel width 224b. In various embodiments, the channel length 222 may have a value greater than 10 nanometers. An increased value of the channel length 222 may mitigate short channel effects. However, increasing the channel length 222 may reduce the drive current and make the size of the semiconductor circuit 200 larger. Therefore, the channel length 222 may be optimized to determine a sufficiently large value to avoid the short channel effect while also keeping the size of the semiconductor circuit 200 as small as possible.

[0079] According to various embodiments, the corresponding channel widths (224a, 224b) may each have a value greater than 10 nanometers. In some embodiments, the first channel width 224a may be approximately equal to the second channel width 224b. In other embodiments, the first channel width 224a and the second channel width 224b may have different values. For example, in some embodiments, selecting different values ​​of the first channel width 224a and the second channel width 224b may have advantages in the following aspects: fine-tuning the electrical properties of the corresponding first channel layer 119a and the second channel layer 119b, for example to compensate for different carrier mobilities and / or adjust the corresponding current values.

[0080] Each of the first source electrode 110a and the second source electrode 110b may have a respective source width (224a, 224b) that is approximately equal to the respective channel width (224a, 224b), such as Figure 2C As shown. Each of the source / drain electrodes (110a, 110b, 112) may also have a source / drain length 226 and a source / drain thickness 228, which may each have a value greater than 5 nanometers (e.g., 5 nanometers to 50 nanometers). Another interlayer dielectric layer 304d may have a thickness 230 greater than 5 nanometers (e.g., greater than 5 nanometers and less than 100 nanometers) and a width 231 that may be comparable to the source width (224a, 224b). The gate electrode 116 may have a gate length 232 and a gate width 233 that may each be greater than 10 nanometers and less than 500 nanometers. The gate electrode 116 may have a gate thickness 236 that may have a value greater than 5 nanometers and less than 50 nanometers. The gate dielectric layer 118 may have a gate dielectric thickness 238 greater than 2 nanometers and less than 20 nanometers. The p-type semiconductor layer 206a may have a p-type thickness 240a, and the n-type semiconductor layer 206b may have an n-type thickness 240b, each of which may be greater than 2 nanometers and less than 50 nanometers.

[0081] Figure 3A is a top view of an intermediate structure 300 that can be used to form the semiconductor circuit 200, and Figure 3B According to various embodiments Figure 3A A vertical cross-sectional view of the intermediate structure 300 is shown. Figure 3B The vertical plane of view in is given by Figure 3A The cross section B–B' in the figure is represented by Figure 3A and Figure 3B As shown, the intermediate structure 300 may include a substrate 302, a first interlayer dielectric layer 304a, an etch stop layer 306L, a second interlayer dielectric layer 304b, and a patterned photoresist 308. The substrate 302 may be formed in a BEOL process, and thus may be formed on an interlayer dielectric layer (e.g., Figure 1 The substrate 302 may be formed by depositing an interlayer dielectric layer or insulating matrix layer 150 of the substrate 302. For example, the substrate 302 may include undoped silicate glass, doped silicate glass (e.g., deposited by decomposing tetraethylorthosilicate (TEOS)), organosilicate glass, silicon oxynitride, or silicon carbide nitride. Other suitable dielectric materials are also within the scope of the present disclosure. The dielectric material of the substrate 302 may be deposited by a conformal deposition process (e.g., a chemical vapor deposition process) or a self-planarizing deposition process (e.g., spin coating). The thickness of the substrate 302 may each be in the range of about 15 nanometers to about 60 nanometers (e.g., about 20 nanometers to about 40 nanometers), although lesser and greater thicknesses may also be used.

[0082] The first interlayer dielectric layer 304a may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide, or various other insulating structures (e.g., a multilayer stack structure including alternating insulating layers). The first interlayer dielectric layer 304a may be deposited by a conformal deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), etc.) or by a self-planarization deposition process (e.g., spin coating). In this example, the first interlayer dielectric layer 304a may be formed as a flat blanket (i.e., unpatterned) layer having a flat top surface and a flat bottom surface. Excess portions of the first interlayer dielectric layer 304a may be removed by a planarization process, such as by chemical mechanical planarization (CMP). The thickness of the first interlayer dielectric layer 304a may be in a range from about 5 nanometers to about 50 nanometers (eg, about 20 nanometers to about 40 nanometers), although other embodiments may include lesser and greater thicknesses.

[0083] The etch stop layer 306L may include an etch stop material such as silicon nitride, silicon carbide, silicon carbide nitride, or a dielectric metal oxide (e.g., aluminum oxide, titanium oxide, tantalum oxide, etc.). The etch stop layer 306L may be deposited by a conformal deposition process or a non-conformal deposition process. In an embodiment, the etch stop layer 306L may be deposited by CVD, ALD, or PVD. The thickness of the etch stop layer 306L may be in a range of about 2 nanometers to about 20 nanometers (e.g., about 3 nanometers to about 12 nanometers), although lesser and greater thicknesses may also be used.

[0084] The second interlayer dielectric layer 304b may be formed on the first oxide semiconductor layer 206La using materials and processes similar to those described above with reference to the first interlayer dielectric layer 304a. In this regard, the second interlayer dielectric layer 304b may be the same material as the first interlayer dielectric layer 304a. Alternatively, the first interlayer dielectric layer 304a and the second interlayer dielectric layer 304b may be different materials. The second interlayer dielectric layer 304b may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide, or various other insulating structures (e.g., a multilayer stack structure including alternating insulating layers). The second interlayer dielectric layer 304b may be deposited by a conformal deposition process (e.g., CVD, ALD, PVD, PECVD, etc.) or by a self-planarization deposition process (e.g., spin coating). Excess portions of the second interlayer dielectric layer 304 b may be removed by a planarization process (eg, by CMP).

[0085] The patterned photoresist 308 may be formed by depositing a uniform photoresist layer (not shown) and then patterning the uniform photoresist layer using photolithography. According to some embodiments, the patterned photoresist 308 may be formed into a periodic rectangular array on the second interlayer dielectric layer 304b. For example, Figure 3A and Figure 3B The view may correspond to a repeating unit of the array of periodic rectangular shapes. The patterned photoresist 308 may then be used as a mask to pattern the second interlayer dielectric layer 304b, as described below with reference to Figure 4A and Figure 4B A more detailed description is shown below.

[0086] Figure 4A is a top view of yet another intermediate structure 400 that can be used to form the semiconductor circuit 200, and Figure 4B According to various embodiments Figure 4A A vertical cross-sectional view of the intermediate structure 400 is shown. Figure 4B The vertical plane of view in is given by Figure 4AThe intermediate structure 400 can be formed by Figure 3A and Figure 3B The intermediate structure 300 is formed by patterning the second interlayer dielectric layer 304b using a patterned photoresist 308 and an etching process to form a gate opening (not shown) in the second interlayer dielectric layer 304b, depositing a conductive material into the gate opening to form a gate electrode 116, and planarizing the resulting structure.

[0087] The conductive material may include a metal liner material and a metal filler material. The metal liner material may include a conductive metal nitride or a conductive metal carbide, such as Ti, Al, TiN, TiN / W, Ti / Al / Ti, TaN, W, Cu, WN, WCN, PdCo, ​​TiC, TaC, and / or WC. The thickness of the metal liner material may be in the range of about 1 nanometer to about 10 nanometers (e.g., about 3 nanometers to about 8 nanometers), but smaller and larger thicknesses may also be used. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal filler materials within the scope of the present disclosure may also be used. The thickness of the metal filler material may be in the range of about 5 nanometers to about 500 nanometers (e.g., about 20 nanometers to about 40 nanometers), but smaller and larger thicknesses may also be used. The metal liner material and the metal filling material may be formed by a suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are within the scope of the present disclosure.

[0088] Then, the excess portion of the conductive material may be removed from above the horizontal plane including the top surface of the second interlayer dielectric layer 304b by a planarization process such as CMP, but other suitable planarization processes may be used. The remaining portion of the conductive material forms the gate electrode 116. In some embodiments, the gate electrode 116 may be formed by depositing one or more alloys of one or more of W, Mo, Co, Pd, Ti, and mixtures thereof with or without N and / or O, the one or more alloys being deposited by chemical vapor deposition or by atomic layer deposition.

[0089] Figure 5A is a top view of yet another intermediate structure 500 that can be used to form the semiconductor circuit 200, and Figure 5B According to various embodiments Figure 5A A vertical cross-sectional view of the intermediate structure 500 is shown. Figure 5B The vertical plane of view in is given by Figure 5A The intermediate structure 500 can be formed by Figure 4Aand Figure 4B The intermediate structure 400 shown is formed: Figure 4A and Figure 4B A gate dielectric layer 118 , a first oxide semiconductor layer 206La, a third interlayer dielectric layer 304 c and a patterned photoresist 308 are formed on the intermediate structure 400 .

[0090] The gate dielectric layer 118 may include, but is not limited to, silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, tantalum oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide, or various other insulating structures (e.g., a multilayer stack structure including alternating insulating layers). Other suitable dielectric materials are also within the scope of the present disclosure. In other embodiments, the gate dielectric layer 118 may include an alternating multilayer structure (not shown) including silicon oxide and silicon nitride. In other embodiments, the gate dielectric layer 118 may include a ferroelectric material.

[0091] The gate dielectric layer 118 may be formed by any suitable technique (e.g., ALD, CVD, PECVD, PVD, etc.). The thickness of the gate dielectric layer 118 may be in a range of about 2 nanometers to about 20 nanometers (e.g., about 5 nanometers to about 12 nanometers), but other embodiments may include lesser and greater thicknesses. After depositing the gate dielectric layer 118, the intermediate structure 500 may optionally be annealed. The optional annealing process may be performed using a rapid thermal annealing or furnace annealing process at a temperature in a range of 200 degrees Celsius to 400 degrees Celsius. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof.

[0092] The first oxide semiconductor layer 206La may be a first conductivity type semiconductor layer (e.g., a p-type semiconducting material including but not limited to NiO, SnO, Cu2O, etc.), which may be formed by any suitable method (e.g., ALD, CVD, PECVD, PVD, etc.). The thickness of the first oxide semiconductor layer 206La may be in a range of about 2 nanometers to about 50 nanometers (e.g., about 5 nanometers to about 15 nanometers), but other embodiments may include smaller and larger thicknesses. After depositing the first oxide semiconductor layer 206La, the intermediate structure 500 may be optionally annealed. The optional annealing process may be performed at a temperature in a range of 200 degrees Celsius to 400 degrees Celsius using a rapid thermal annealing or furnace annealing process. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof. In other embodiments, the first oxide semiconductor layer 206La may be an n-type semiconducting layer.

[0093] The third interlayer dielectric layer 304c may be formed using the materials and processes described above with reference to forming the first interlayer dielectric layer 304a and the second interlayer dielectric layer 304b. In this regard, the third interlayer dielectric layer 304c may be formed by depositing an interlayer dielectric layer and then performing a planarization process (e.g., CMP) to remove a portion of the interlayer dielectric located above the top surface of the third interlayer dielectric layer 304c.

[0094] The patterned photoresist 308 may also be formed using the above process. In this regard, a uniform photoresist layer (not shown) may be deposited over the top surface of the third interlayer dielectric layer 304c. The uniform photoresist layer may then be patterned using photolithography techniques to form the patterned photoresist 308. The patterned photoresist 308 may then be used as a mask to pattern the third interlayer dielectric layer 304c and the first oxide semiconductor layer 206La, as described below with reference to Fig. 6A and Figure 6B A more detailed description is shown below.

[0095] Fig. 6A is a top view of yet another intermediate structure 600 that can be used to form the semiconductor circuit 200, and Figure 6B According to various embodiments Fig. 6A A vertical cross-sectional view of the intermediate structure 600 is shown. Figure 6B The vertical plane of view in is given by Fig. 6A The intermediate structure 600 can be formed by Figure 5A and Figure 5B The intermediate structure 500 is formed by performing an anisotropic etching process to remove the third interlayer dielectric layer 304c and the first oxide semiconductor layer 206La that are not shielded by the patterned photoresist 308. The resulting intermediate structure 600 includes the above-mentioned Figure 2A and Figure 2C The patterned first conductivity type semiconductor layer 206a and the remaining portion of the third interlayer dielectric layer 304c are illustrated. The patterned photoresist 308 may then be removed by ashing or by dissolving with a solvent.

[0096] Fig. 7A is a top view of yet another intermediate structure 700 that can be used to form the semiconductor circuit 200, and Figure 7B According to various embodiments Fig. 7A A vertical cross-sectional view of the intermediate structure 700 is shown. Figure 7B The vertical plane of view in is given by Fig. 7A The intermediate structure 700 can be formed by Fig. 6A and Figure 6BThe intermediate structure 600 is shown formed by removing the patterned photoresist 308 and depositing a fourth interlayer dielectric layer 304 d over the intermediate structure 600 after removing the patterned photoresist 308 .

[0097] The fourth interlayer dielectric layer 304d may be formed using the materials and processes described above with reference to forming the first interlayer dielectric layer 304a, the second interlayer dielectric layer 304b, and the third interlayer dielectric layer 304c. As shown, the fourth interlayer dielectric layer 304d may partially or completely surround the first conductive type semiconductor layer 206a. In this regard, Fig. 7A and Figure 7B In the processing stage, the fourth interlayer dielectric layer 304d surrounds (encapsulates) the first conductive semiconductor layer 206a. However, in the planarization process (hereinafter referred to as Fig. 10A and Fig. 10B 1. After the fourth interlayer dielectric layer 304d is formed, the fourth interlayer dielectric layer 304d may only partially surround the first conductive type semiconductor layer 206a. The fourth interlayer dielectric layer 304d may be used to protect the first conductive type semiconductor layer 206a during further processing operations, as described below with reference to Fig. 8A and Figure 8B A more detailed description is shown below.

[0098] Fig. 8A is a top view of yet another intermediate structure 800 that may be used to form the semiconductor circuit 200, and Figure 8B According to various embodiments Fig. 8A A vertical cross-sectional view of the intermediate structure 800 is shown. Definition Figure 8B The vertical plane of view in is given by Fig. 8A The intermediate structure 800 can be formed by Fig. 7A and Figure 7B The intermediate structure 700 is formed by forming a patterned photoresist 308 on the intermediate structure 600 and performing an anisotropic etching process to etch the portion of the intermediate structure 700 that is not shielded by the patterned photoresist 308. As shown, the anisotropic etching process can produce a through hole opening 702. The patterned photoresist 308 can then be removed (e.g., by ashing or by dissolving with a solvent). Then, a second oxide semiconductor layer 206Lb can be deposited on the resulting structure to fill the through hole opening 702, as described below with reference to Fig. 9A and Fig. 9B A more detailed description is shown below.

[0099] Fig. 9A is a top view of yet another intermediate structure 900 that can be used to form the semiconductor circuit 200, and Fig. 9B According to various embodiments Fig. 9A A vertical cross-sectional view of the intermediate structure 900 is shown. Fig. 9B The vertical plane of view in is given by Fig. 9A The intermediate structure 900 can be formed by Fig. 8A and Figure 8B The intermediate structure 800 is formed as shown: a second oxide semiconductor layer 206Lb is formed on the intermediate structure 800, thereby filling the through hole opening 702. The second oxide semiconductor layer 206Lb can be a second conductivity type semiconductor layer, such as but not limited to amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and its alloys. Other suitable semiconductive materials are also within the scope of the present disclosure. For example, in various embodiments, the second oxide semiconductor layer 206Lb may include In x Ga y Zn z MO is a composition given by 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce, and Sn. The second oxide semiconductor layer 206Lb may be formed by any suitable method (eg, ALD, CVD, PECVD, PVD, etc.).

[0100] The thickness of the second oxide semiconductor layer 206Lb may be in a range of about 2 nanometers to about 50 nanometers (e.g., about 5 nanometers to about 15 nanometers), but other embodiments may include lesser and greater thicknesses. After depositing the second oxide semiconductor layer 206Lb, the intermediate structure 900 may be optionally annealed. The optional annealing process may be performed using a rapid thermal annealing or furnace annealing process at a temperature in a range of 200 degrees Celsius to 400 degrees Celsius. The annealing may be performed in an environment of nitrogen, oxygen, or a mixture thereof.

[0101] Fig. 10A is a top view of yet another intermediate structure 1000 that can be used to form the semiconductor circuit 200, and Fig. 10B According to various embodiments Fig. 10A A vertical cross-sectional view of intermediate structure 1000 is shown. Definition Fig. 10B The vertical plane of view in is given by Fig. 10A The intermediate structure 1000 can be formed by Fig. 9A and Fig. 9BThe intermediate structure 900 is formed by performing a planarization process (e.g., CMP) to remove the top portion of the second oxide semiconductor layer 206Lb and a portion of the fourth interlayer dielectric layer 304d, thereby exposing the top surface of each of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b. In some embodiments, before performing the planarization process, an additional interlayer dielectric layer (not shown) may be formed on the intermediate structure 900.

[0102] Fig.11A is a top view of yet another intermediate structure 1100 that can be used to form the semiconductor circuit 200, and Fig. 11B According to various embodiments Fig.11A A vertical cross-sectional view of the intermediate structure 1100 is shown. Fig. 11B and Fig. 11C The vertical planes of the view in Fig.11A The intermediate structure 1100 can be formed by the following method: Fig. 10A and Fig. 10B The intermediate structure 1000 shown is formed: Fig. 10A and Fig. 10B Additional interlayer dielectric material is deposited over the intermediate structure 1000 to increase the thickness of the fourth interlayer dielectric layer 304d.

[0103] The fourth interlayer dielectric layer 304d may partially or completely surround the first conductive type semiconductor layer 206a and the second conductive type semiconductor layer 206b. FIG. 11A to FIG. 11C In the processing stage of FIG. 1 , the fourth interlayer dielectric layer 304d completely surrounds the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b. The fourth interlayer dielectric layer 304d can be used to protect the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b during further processing operations, as described below with reference to FIG. FIG. 12A to FIG. 13C A more detailed description is shown below.

[0104] Fig. 12A is a top view of yet another intermediate structure 1200 that can be used to form the semiconductor circuit 200, Fig. 12B yes Fig. 12A A first vertical cross-sectional view of the intermediate structure 1200 is shown, and Fig. 12C According to various embodiments Fig. 12A A second vertical cross-sectional view of intermediate structure 1200 is shown. Fig. 12B and Fig. 12C The vertical planes of the view in Fig. 12A The intermediate structure 1200 can be formed by the following method: FIG. 11A to FIG. 11CThe intermediate structure 1100 is formed by forming a patterned photoresist 308 on the intermediate structure 1100, and performing an anisotropic etching process to etch the portion of the intermediate structure 1100 that is not shielded by the patterned photoresist 308. As shown in the figure, the anisotropic etching process can produce a through hole opening 703. A conductive material can then be deposited in the through hole opening 703 to form a first source electrode 110a, a second source electrode 110b, and a shared drain electrode 112, as described below with reference to FIG. 13A to FIG. 13C A more detailed description is shown below.

[0105] Fig.13A By reference FIG. 3A to FIG. 12C A top view of a semiconductor circuit 200 formed by the process described, Fig. 13B yes Fig.13A A first vertical cross-sectional view of the semiconductor circuit 200 is shown, and Fig. 13C According to various embodiments Fig.13A A second vertical cross-sectional view of the semiconductor circuit 200 is shown. Fig. 13B and Fig. 13C The vertical planes of the view in Fig.13A The semiconductor circuit 200 can be self-assembled by the following method: FIG. 12A to FIG. 12C The intermediate structure 1200 is formed by depositing a conductive material in the through-hole opening 703, removing the patterned photoresist 308 (e.g., by ashing or by dissolving with a solvent), and removing excess portions of the conductive material and removing a portion of the fourth interlayer dielectric layer 304d by performing a planarization process (e.g., CMP). The remaining portions of the conductive material form the first source electrode 110a, the second source electrode 110b, and the shared drain electrode 112, as shown in FIG. FIG. 13A to FIG. 13C shown.

[0106] The conductive material may include a metal liner material and a metal filler material. The metal liner material may include a conductive metal nitride or a conductive metal carbide, such as Ti, Al, TiN, TiN / W, Ti / Al / Ti, TaN, W, Cu, WN, WCN, PdCo, ​​TiC, TaC, and / or WC. The thickness of the metal liner material may be in the range of about 1 nanometer to about 10 nanometers (e.g., about 3 nanometers to about 8 nanometers), but smaller and larger thicknesses may also be used. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, TiN, alloys thereof, and / or combinations thereof. Other suitable metal liner materials and metal filler materials within the scope of the present disclosure may also be used. The thickness of the metal filler material may be in the range of about 5 nanometers to about 500 nanometers (e.g., about 20 nanometers to about 40 nanometers), but smaller and larger thicknesses may also be used. The metal liner material and the metal filling material may be formed by a suitable deposition process, which may include one or more of a CVD process, a PVD process, an ALD process, an electroplating process, etc. Other suitable deposition processes are within the scope of the present disclosure.

[0107] As described above, the excess portion of the conductive material may be removed from above the horizontal plane including the top surface of the fourth interlayer dielectric layer 304d by a planarization process such as CMP, but other suitable planarization processes may be used. The remaining portion of the conductive material forms the second source electrode 110b. In some embodiments, the second source electrode 110b may be formed by depositing one or more alloys of one or more of W, Mo, Co, Pd, Ti, and mixtures thereof with or without N and / or O, the one or more alloys being deposited by chemical vapor deposition or by atomic layer deposition.

[0108] Various other embodiments may include pFETs 216 and nFETs 218 having additional numbers of parallel conductive channels (119a, 119b). For example, some embodiments may include: pFETs 216 having a number P=1, 2, 3, etc. of parallel p-type channel layers 119a; and nFETs 218 having a number N=1, 2, 3, etc. of parallel n-type channel layers 119b. Embodiments such as semiconductor circuits 200d and 200e having multiple channel layers may allow for additional circuit design flexibility in various circumstances. For example, by forming semiconductor circuits having corresponding numbers (P, N) of p-type channel layers 119a and n-type channel layers 119b, the effective on-resistance of pFETs 216 and / or nFETs 218 may be adjusted to compensate for different material properties (e.g., different carrier mobilities of p-type semiconductor layers 206a and n-type semiconductor layers 206b).

[0109] Fig.14A 1 is a top view of another embodiment of a semiconductor circuit 200d having an additional number of parallel conductive channels 119a1, 119a2, 119b, which can be connected by the same method as described above. FIG. 3A to FIG. 13C The process described is similar to the process to form, Fig. 14B yes Fig.14A A first vertical cross-sectional view of a semiconductor circuit 200d is shown, Fig. 14C yes Fig.14A A second vertical cross-sectional view of the semiconductor circuit 200d is shown, Fig.14D is a three-dimensional perspective view of a semiconductor circuit 200d that can be formed in a BEOL process according to various embodiments. Fig. 14B and Fig. 14C The vertical planes of the view in Fig.14A In the embodiment semiconductor circuit 200d, two adjacent p-type semiconductor layers (eg, see Fig. 14B and Fig. 14C 206a1 and 206a2) in the embodiment may share a shared first source electrode 110a and a shared drain electrode 112, and a single n-type semiconductor layer 206b may be electrically connected to a second source electrode 110b and the shared drain electrode 112.

[0110] Reference FIG. 14A to FIG. 14D In the embodiment semiconductor circuit 200d, two adjacent p-type semiconductor layers (for example, see 206a1 and 206a2) can share a shared first source electrode 110a and a shared drain electrode 112, and a single n-type semiconductor layer 206b can be electrically connected to a second source electrode 110b and a shared drain electrode 112. In this way, FIG. 14A to FIG. 14D The semiconductor circuit 200d shown may include: a pFET 216 (see, for example, Figure 2B ), comprising two parallel p-type channel layers provided by the two adjacent p-type semiconductor layers (206a1, 206a2) (see Fig.14D , 119a1, 119a2); and nFET 218 may include a single n-type channel layer 119b provided by a single n-type semiconductor layer 206b.

[0111] Fig.15A 2 is a top view of a semiconductor circuit 200e according to another embodiment. The semiconductor circuit 200e according to the embodiment can be viewed from above. FIG. 3A to FIG. 13C The process described is similar to the process formation, Fig. 15B yes Fig.15A A first vertical cross-sectional view of a semiconductor circuit 200e is shown, Fig. 15C yes Fig.15A A second vertical cross-sectional view of the semiconductor circuit 200e is shown, Fig.15D is a three-dimensional diagram of a semiconductor circuit 200e that can be formed in a BEOL process according to various embodiments. Fig. 15B and Fig. 15C The vertical planes of the view in Fig.15A In the embodiment semiconductor circuit 200e, a single p-type semiconductor layer 206a can be electrically connected to the first source electrode 110a and the shared drain electrode 112, while two adjacent n-type semiconductor layers (eg, see Fig. 15B and Fig. 15C 206b1 and 206b2) can share a shared second source electrode 110b and a shared drain electrode 112.

[0112] Fig.15D 2 is a three-dimensional diagram of another semiconductor circuit 200d that can be formed in a BEOL process according to various embodiments. In the embodiment semiconductor circuit 200e, a single p-type semiconductor layer 206a can be electrically connected to a first source electrode 110a and a shared drain electrode 112, and two adjacent n-type semiconductor layers (206b1 and 206b2) can share a shared second source electrode 110b and a shared drain electrode 112. In this way, FIG. 15A to FIG. 15D The semiconductor circuit 200e may include: a pFET 216 (eg, see Figure 2B ), including a single p-type channel layer 119a provided by a single p-type semiconductor layer 206a; and nFET 218, which may include two parallel n-type channel layers (119b1, 119b2) provided by the two adjacent n-type semiconductor layers (206b1, 206b2).

[0113] As shown in the figure, FIG. 14A to FIG. 14D The semiconductor circuit 200d may include: a pFET 216 (eg, see Figure 2B ), including two parallel p-type channel layers (119a1, 119a2) provided by the two adjacent p-type semiconductor layers (206a1, 206a2); and nFET 218, may include a single n-type channel layer 119b provided by a single n-type semiconductor layer 206b. Alternatively, FIG. 15A to FIG. 15D The semiconductor circuit 200e may include: a pFET 216 (eg, see Figure 2B ), including a single p-type channel layer 119a provided by a single p-type semiconductor layer 206a; and nFET 218, which may include two parallel n-type channel layers (119b1, 119b2) provided by the two adjacent n-type semiconductor layers (206b1, 206b2).

[0114] Various other embodiments may include pFETs 216 and nFETs 218 having additional numbers of parallel conductive channels (119a, 119b). For example, some embodiments may include: pFETs 216 having a number P=1, 2, 3, etc. of parallel p-type channel layers 119a; and nFETs 218 having a number N=1, 2, 3, etc. of parallel n-type channel layers 119b. In some embodiments, the number of p-type channel layers 119a may be equal to the number of n-type channel layers 119b (i.e., P=N). In other embodiments, the number of p-type channel layers 119a may be different from the number of n-type channel layers 119b (i.e., P≠N). Embodiments such as semiconductor circuits 200d and 200e having multiple channel layers may allow for additional circuit design flexibility in various circumstances. For example, by forming a semiconductor circuit having a corresponding number (P, N) of p-type channel layers 119a and n-type channel layers 119b, the effective on-resistance of pFET 216 and / or nFET 218 can be adjusted to compensate for different material properties (e.g., different carrier mobilities of p-type semiconductor layer 206a and n-type semiconductor layer 206b).

[0115] Fig.16 1 is a flow chart illustrating operations of a method 1600 of forming a semiconductor circuit (200, 200b, 200d, 200e) according to various embodiments. In operation 1602, the method 1600 may include forming a gate electrode 116 over an interlayer dielectric layer (136, 138, 140, 150, 302, 304a to 304d). In operation 1604, the method 1600 may include forming a gate dielectric layer 118 over the gate electrode 116. In operation 1606, the method 1600 may include forming a first conductivity type semiconductor layer (e.g., a p-type semiconductor layer 206a) over the gate dielectric layer 118. In operation 1608, the method 1600 may include forming a second conductivity type semiconductor layer (e.g., an n-type semiconductor layer 206b) over the gate dielectric layer 118 such that the second conductivity type semiconductor layer 206b is laterally offset relative to and isolated from the first conductivity type semiconductor layer 206a. In operation 1610, the method 1600 may include forming a first source electrode 110a in contact with the first conductive type semiconductor layer 206a. In operation 1612, the method 1600 may include forming a second source electrode 110b in contact with the second conductive type semiconductor layer 206b. In operation 1614, the method 1600 may include forming a shared drain electrode 112 in contact with the first conductive type semiconductor layer 206a and the second conductive type semiconductor layer 206b.

[0116] The method 1600 may further include configuring the semiconductor circuit (200, 200b, 200d, 200e) as an inverter circuit 200b by performing the following operations: the operations include electrically connecting the first source electrode 110a to the voltage supply 208 (e.g., maintained at a high voltage VDD), and electrically connecting the second source electrode 110b to the ground voltage terminal 210 (e.g., maintained at GND). The method 1600 may further include electrically connecting the gate electrode 116 to the input signal terminal 212 (having a signal voltage Vin) and electrically connecting the shared drain electrode 112 to the output signal terminal 214 (having a voltage Vout).

[0117] The method 1600 may further include: forming one of the first conductive type semiconductor layer 206a and the second conductive type semiconductor layer 206b to include an n-type semiconductor layer 206b, wherein the n-type semiconductor layer 206b includes amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and at least one of its alloys; and forming the other of the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b to include a p-type semiconductor layer 206a, wherein the p-type semiconductor layer 206a includes at least one of NiO, SnO, and Cu2O. The method 1600 may also include: forming the gate dielectric layer 118 to include at least one of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-aluminum oxide; forming one or more of the first source electrode 110a, the second source electrode 110b, and the shared drain electrode 112 to include TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, T i and one or more of Al; and forming another interlayer dielectric layer (136, 138, 140, 150, 302, 304a to 304d) that partially surrounds the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b, so that the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b are electrically insulated from each other by the another interlayer dielectric layer (136, 138, 140, 150, 302, 304a to 304d).

[0118] With reference to all the drawings and according to various embodiments of the present disclosure, an inverter circuit (200, 200b, 200d, 200e) is provided. The inverter circuit (200, 200b, 200d, 200e) may include: a gate electrode 116 formed on an interlayer dielectric layer (136, 138, 140, 150, 302); a gate dielectric layer 118 formed on the gate electrode 116; a first conductive semiconductor layer 206a formed on the gate dielectric layer 118; and a second conductive semiconductor layer 206b formed on the gate dielectric layer 118 and laterally offset relative to the first conductive semiconductor layer 206a. The inverter circuit (200, 200b, 200d, 200e) may also include: a first source electrode 110a, formed to contact the first conductive semiconductor layer 206a; a second source electrode 110b, formed to contact the second conductive semiconductor layer 206b; and a shared drain electrode 112, formed to contact the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b.

[0119] In some embodiments, the interlayer dielectric layer (136, 138, 140, 150, 302) may include a horizontal interface (eg, see Figure 1 ), the gate electrode 116 may include a surface 117 parallel to the horizontal interface of the interlayer dielectric layer (136, 138, 140, 150, 302) and close to the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b, the first conductive semiconductor layer 206a may include a first channel layer 119a formed in a horizontal direction close to the surface 117 of the gate electrode 116, and the second conductive semiconductor layer 206b may include a second channel layer 119b formed in a horizontal direction close to the surface 117 of the gate electrode 116.

[0120] In other embodiments, the first conductive semiconductor layer 206a may be a p-type semiconductor layer 206a, and the second conductive semiconductor layer 206b may be an n-type semiconductor layer 206b. The first source electrode 110a may be electrically connected to the voltage supplier 208, the second source electrode 110b may be electrically connected to the ground voltage terminal 210, the gate electrode 116 may be electrically connected to the input signal terminal 212, and the shared drain electrode 112 may be electrically connected to the output signal terminal 214. In some embodiments, at least one of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b may include a metal oxide semiconductor. In addition, at least one of the p-type semiconductor layer 206a and the n-type semiconductor layer 206b may include a metal oxide semiconductor including a multi-layer structure.

[0121] In some embodiments, the n-type semiconductor layer 206b may include an alloy including oxygen, a group III element, and a group V element, or the n-type semiconductor layer 206b may include amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and one or more of their alloys. In other embodiments, the n-type semiconductor layer 206b may include In x Ga y Zn z The composition given by MO, wherein 0<x<1; 0≤y≤1; 0≤z≤1; and M is one of Ti, Al, Ag, Ce and Sn. In various embodiments, the p-type semiconductor layer 206a may include one or more of NiO, SnO and Cu2O or other p-type metal oxide semiconductor layers 206a.

[0122] A semiconductor circuit (200, 200b, 200d, 200e) may be formed on the interlayer dielectric layer (136, 138, 140, 150, 302), and the interlayer dielectric layer may also include one or more electrical interconnect structures (for example, see Figure 1 The gate dielectric layer 118 may include a first metal interconnect structure (142, 144, 146, 148) in the common drain electrode 112, and one or more of the first source electrode 110a, the shared drain electrode 112, the second source electrode 110b, and the gate electrode 116 may be electrically connected to the one or more electrical interconnect structures (142, 144, 146, 148). In various embodiments, the gate dielectric layer 118 may include one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-aluminum oxide.

[0123] In some embodiments, the inverter circuit (200, 200b, 200d, 200e) may further include: another interlayer dielectric layer 304d, which surrounds the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b in the lateral direction and isolates the first conductive semiconductor layer 206a from the second conductive semiconductor layer 206b, so that the first conductive semiconductor layer 206a and the second conductive semiconductor layer 206b are electrically insulated from each other by the further interlayer dielectric layer 304d. In some embodiments, one or more of the first source electrode 110a, the shared drain electrode 112, and the second source electrode 110b include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, and Al. One or more of the first source electrode 110a, the shared drain electrode and the second source electrode 110b may further include one or more alloys of one or more of W, Mo, Co, Pd, Ti and mixtures thereof with N and / or O or without N and / or O, wherein the one or more alloys are deposited by chemical vapor deposition or by atomic layer deposition.

[0124] In other embodiments, a semiconductor circuit (200, 200b, 200d, 200e) may be provided. The semiconductor circuit (200, 200b, 200d, 200e) may include: a gate electrode 116 formed on an interlayer dielectric layer (136, 138, 140, 150, 302) such that the gate electrode 116 may be parallel to a horizontal interface of the interlayer dielectric layer (136, 138, 140, 150, 302); a p-type metal oxide semiconductor layer 206a formed on the gate electrode 116 such that the p-type metal oxide semiconductor layer 206a may be close to a horizontal surface 117 of the gate electrode 116; and an n-type metal oxide semiconductor layer 206b formed on the gate electrode 116 such that the n-type metal oxide semiconductor layer 206b may be close to a horizontal surface of the gate electrode 116 and may be laterally offset relative to the p-type metal oxide semiconductor layer 206a. The semiconductor circuit (200, 200b, 200d, 200e) may also include: a first source electrode 110a formed to contact the p-type metal oxide semiconductor layer 206a; a second source electrode 110b formed to contact the n-type metal oxide semiconductor layer 206b; and a shared drain electrode 112 electrically connecting the p-type metal oxide semiconductor layer 206a with the n-type metal oxide semiconductor layer 206b.

[0125] The semiconductor circuit (200, 200b, 200d, 200e) may further include: a further interlayer dielectric layer 304d, which surrounds the p-type metal oxide semiconductor layer 206a and the n-type metal oxide semiconductor layer 206b in the lateral direction; and a gate dielectric layer 118, which is disposed between the gate electrode 116 and the p-type metal oxide semiconductor layer 206a and between the gate electrode 116 and the n-type metal oxide semiconductor layer 206b. In some embodiments, the gate dielectric layer 118 may include one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium dioxide-aluminum oxide.

[0126] In other embodiments, the n-type metal oxide semiconductor layer 206b may include amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and one or more of their alloys; the p-type metal oxide semiconductor layer 206a may include one or more of NiO, SnO and Cu2O; and one or more of the first source electrode 110a, the second source electrode 110b and the shared drain electrode 112 may include one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, Al and one or more of W, Mo, Co, Pd, Ti and mixtures thereof, alloys with N and / or O or without N and / or O.

[0127] Various embodiments of the present disclosure provide semiconductor circuits (200, 200b, 200d, 200e) and methods 1600 that may have advantages in terms of manufacturing flexibility, size reduction, and reduction in short channel effect. In this regard, an embodiment semiconductor circuit (200, 200b, 200d, 200e) (e.g., CMOS inverter 200b) may be provided, which may be formed in a BEOL process and may be combined with other BEOL circuit components such as capacitors, inductors, resistors, and integrated passive devices. As such, the embodiment semiconductor circuit (200, 200b, 200d, 200e) may include materials that may be processed at low temperatures. Therefore, the fabrication of such a semiconductor circuit (200, 200b, 200d, 200e) may not damage previously fabricated devices (e.g., FEOL devices and MEOL devices). In addition, various embodiment semiconductor circuits (200, 200b, 200d, 200e) may include a dual conductive channel (e.g., p-type channel layer 119a and n-type channel layer 119b) formed above the back gate electrode 116. The semiconductor circuits (200, 200b, 200d, 200e) may have reduced size relative to alternative structures that do not include such a dual channel / back gate configuration. Embodiment semiconductor circuits (200, 200b, 200d, 200e) may allow for longer channel lengths without increasing device size, which may mitigate short channel effects.

[0128] According to an embodiment of the utility model, an inverter circuit includes: a gate electrode, a gate dielectric layer, a first conductive semiconductor layer, a second conductive semiconductor layer, a first source electrode, a second source electrode, and a shared drain electrode. The gate electrode is formed on an interlayer dielectric layer. The gate dielectric layer is formed on the gate electrode. The first conductive semiconductor layer is formed on the gate dielectric layer. The second conductive semiconductor layer is formed on the gate dielectric layer, and is laterally offset relative to the first conductive semiconductor layer and isolated from the first conductive semiconductor layer. The first source electrode is formed to contact the first conductive semiconductor layer. The second source electrode is formed to contact the second conductive semiconductor layer. The shared drain electrode is formed to contact the first conductive semiconductor layer and the second conductive semiconductor layer.

[0129] In an embodiment of the present invention, the interlayer dielectric layer includes a horizontal interface. The gate electrode includes a surface parallel to the horizontal interface of the interlayer dielectric layer and close to the first conductive semiconductor layer and the second conductive semiconductor layer. The first conductive semiconductor layer includes a first channel layer close to the surface of the gate electrode. The second conductive semiconductor layer includes a second channel layer close to the surface of the gate electrode. In an embodiment of the present invention, the first conductive semiconductor layer is a p-type semiconductor layer, and the second conductive semiconductor layer is an n-type semiconductor layer. The first source electrode is electrically connected to a voltage supplier, and the second source electrode is electrically connected to a ground voltage terminal. The gate electrode is electrically connected to an input signal terminal. The shared drain electrode is electrically connected to an output signal terminal. In an embodiment of the present invention, at least one of the p-type semiconductor layer and the n-type semiconductor layer includes a metal oxide semiconductor. In an embodiment of the present invention, at least one of the p-type semiconductor layer and the n-type semiconductor layer includes a metal oxide semiconductor, and the metal oxide semiconductor includes a multilayer structure. In an embodiment of the present invention, the n-type semiconductor layer includes an alloy including oxygen, a group III element, and a group V element. In an embodiment of the present invention, the n-type semiconductor layer includes amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x In an embodiment of the present invention, the n-type semiconductor layer comprises In x Ga y Zn zA composition given by MO, where 0 < x < 1, 0 ≤ y ≤ 1, 0 ≤ z ≤ 1, and M is one of Ti, Al, Ag, Ce, and Sn. In an embodiment of the present invention, the p-type semiconductor layer comprises one or more of NiO, SnO, and Cu2O. In an embodiment of the present invention, the interlayer dielectric layer further includes one or more electrical interconnect structures, and one or more of the first source electrode, the second source electrode, the shared drain electrode, and the gate electrode are electrically connected to the one or more electrical interconnect structures. In an embodiment of the present invention, the gate dielectric layer comprises one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide, and hafnium-aluminum dioxide. In an embodiment of the present invention, the inverter circuit further includes another interlayer dielectric layer that laterally surrounds the first conductive-type semiconductor layer and the second conductive-type semiconductor layer, such that the first conductive-type semiconductor layer and the second conductive-type semiconductor layer are electrically insulated from each other through the another interlayer dielectric layer. In an embodiment of the present invention, one or more of the first source electrode, the second source electrode, and the shared drain electrode comprise one or more of TiN, W, WN, WCN, Co, PdCo, Mo, Cu, TaN, Ti, and Al. In an embodiment of the present invention, one or more of the first source electrode, the second source electrode, and the shared drain electrode further comprise one or more alloys of W, Mo, Co, Pd, Ti, and their mixtures, with one or more of N and / or O or without N and / or O, and the one or more alloys are deposited by chemical vapor deposition or by atomic layer deposition.

[0130] According to an embodiment of the present invention, a semiconductor circuit includes a gate electrode, a p-type metal oxide semiconductor layer, an n-type metal oxide semiconductor layer, a first source electrode, a second source electrode, and a shared drain electrode. The gate electrode is formed on the interlayer dielectric layer such that a horizontal interface between the gate electrode and the interlayer dielectric layer is parallel. The p-type metal oxide semiconductor layer is formed on the gate electrode such that a horizontal surface of the p-type metal oxide semiconductor layer is close to the gate electrode. The n-type metal oxide semiconductor layer is formed on the gate electrode such that a horizontal surface of the n-type metal oxide semiconductor layer is close to the gate electrode and is laterally offset from and isolated from the p-type metal oxide semiconductor layer. The first source electrode is formed to contact the p-type metal oxide semiconductor layer. The second source electrode is formed to contact the n-type metal oxide semiconductor layer. The shared drain electrode electrically connects the p-type metal oxide semiconductor layer and the n-type metal oxide semiconductor layer.

[0131] In an embodiment of the present invention, the semiconductor circuit further includes another interlayer dielectric layer, which surrounds the p-type metal oxide semiconductor layer, the n-type metal oxide semiconductor layer and the gate dielectric layer in the lateral direction, and is disposed between the gate electrode and the p-type metal oxide semiconductor layer and between the gate electrode and the n-type metal oxide semiconductor layer, wherein the gate dielectric layer comprises one or more of silicon oxide, aluminum oxide, hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, tantalum oxide and hafnium dioxide-aluminum oxide. In an embodiment of the present invention, the n-type metal oxide semiconductor layer comprises amorphous silicon, ZnO doped with Al2O5Zn2, InGaZnO, InGaO, InWO, InZnO, InSnO, Ga2O3, ZnO, GaO, InO, In2O3, InZnO, ZnO, TiO x and one or more of their alloys, wherein the p-type metal oxide semiconductor layer comprises one or more of NiO, SnO and Cu2O, and wherein the first source electrode, the second source electrode and one or more of the shared drain electrode comprise one or more of TiN, W, WN, WCN, Co, PdCo, ​​Mo, Cu, TaN, Ti, Al and one or more of W, Mo, Co, Pd, Ti and mixtures thereof, alloys with N and / or O or without N and / or O.

[0132] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. An inverter circuit, characterized in that: include: A gate electrode formed on the interlayer dielectric layer; a gate dielectric layer formed on the gate electrode; A first conductive semiconductor layer formed on the gate dielectric layer; A second conductive semiconductor layer is formed on the gate dielectric layer, is laterally offset relative to the first conductive semiconductor layer and is isolated from the first conductive semiconductor layer; a first source electrode formed to contact the first conductive type semiconductor layer; a second source electrode formed to contact the second conductive type semiconductor layer; as well as The shared drain electrode is formed to be in contact with the first conductive type semiconductor layer and the second conductive type semiconductor layer.

2. The inverter circuit according to claim 1, characterized in that: in: The interlayer dielectric layer includes a horizontal interface.

3. The inverter circuit according to claim 2, characterized in that: in: The gate electrode includes a surface parallel to the horizontal interface of the interlayer dielectric layer and close to the first conductive type semiconductor layer and the second conductive type semiconductor layer.

4. The inverter circuit according to claim 3, characterized in that: in: The first conductive type semiconductor layer includes a first channel layer close to the surface of the gate electrode.

5. The inverter circuit according to claim 4, characterized in that: in: The second conductive type semiconductor layer includes a second channel layer close to the surface of the gate electrode.

6. The inverter circuit according to claim 1, characterized in that: in: The first conductive type semiconductor layer is a p-type semiconductor layer, and the second conductive type semiconductor layer is an n-type semiconductor layer; The first source electrode is electrically connected to a voltage supplier, and the second source electrode is electrically connected to a ground voltage terminal; The gate electrode is electrically connected to an input signal terminal; and The common drain electrode is electrically connected to the output signal terminal.

7. The inverter circuit according to claim 1, characterized in that: The interlayer dielectric layer further comprises one or more electrical interconnect structures, and One or more of the first source electrode, the second source electrode, the shared drain electrode and the gate electrode are electrically connected to the one or more electrical interconnect structures.

8. The inverter circuit according to claim 1, characterized in that: The invention also includes another interlayer dielectric layer surrounding the first conductive semiconductor layer and the second conductive semiconductor layer in a lateral direction, so that the first conductive semiconductor layer and the second conductive semiconductor layer are electrically insulated from each other by the another interlayer dielectric layer.

9. A semiconductor circuit, characterized in that: include: A gate electrode is formed on the interlayer dielectric layer so that the gate electrode is parallel to a horizontal interface of the interlayer dielectric layer; A p-type metal oxide semiconductor layer is formed on the gate electrode so that the p-type metal oxide semiconductor layer is close to a horizontal surface of the gate electrode; an n-type metal oxide semiconductor layer formed on the gate electrode such that the n-type metal oxide semiconductor layer is adjacent to the horizontal surface of the gate electrode and is laterally offset from and isolated from the p-type metal oxide semiconductor layer; a first source electrode formed to contact the p-type metal oxide semiconductor layer; a second source electrode formed to contact the n-type metal oxide semiconductor layer; as well as A shared drain electrode electrically connects the p-type metal oxide semiconductor layer and the n-type metal oxide semiconductor layer.

10. The semiconductor circuit according to claim 9, characterized in that Also includes: an interlayer dielectric layer laterally surrounding the p-type metal oxide semiconductor layer and the n-type metal oxide semiconductor layer; as well as The gate dielectric layer is disposed between the gate electrode and the p-type metal oxide semiconductor layer and between the gate electrode and the n-type metal oxide semiconductor layer.

Images