Image sensor substrate and semiconductor chip

Abstract

The utility model provides an image sensor substrate, including: a semiconductor substrate, provided with a plurality of cutting paths; a plurality of image sensing units, which are formed between two adjacent cutting paths, each of which includes a plurality of pixel areas; a plurality of active areas, one of which is arranged at the periphery of a pixel area, and a plurality of active areas respectively surround the corresponding pixel areas; a plurality of deep trench isolation structures, one of which is arranged at the periphery of an active area, and a plurality of deep trench isolation structures respectively surround the corresponding active areas; wherein a shallow trench isolation structure is formed on the pixel area, and the shallow trench isolation structure extends from the active area to the pixel area. The image sensor substrate and semiconductor chip disclosed by the utility model can improve the detection efficiency of the image sensor.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor chips, and in particular to an image sensor substrate and a semiconductor chip. Background Art

[0002] With the continuous development of semiconductor technology, image sensors have been widely used in our daily lives. The photoelectric conversion efficiency of existing image sensors is affected by the health of the pixel area inside the image sensor after the process. Therefore, the image sensor needs to be tested after the process to confirm whether the pixel area inside the image sensor is damaged.

[0003] However, the existing detection methods are often performed by directly detecting the pixel area in the image sensor, which easily causes irreversible damage and destruction to the pixel area, thereby reducing the detection efficiency of the image sensor. Therefore, there is room for improvement. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an image sensor substrate and a semiconductor chip to improve the problem of low detection efficiency of the image sensor.

[0005] In order to solve the above technical problems, the utility model is realized by the following technical solutions:

[0006] The utility model provides an image sensor substrate, comprising:

[0007] A semiconductor substrate is provided with a plurality of cutting lanes;

[0008] A plurality of image sensing units are formed between two adjacent cutting lanes, and each of the image sensing units includes a plurality of pixel areas;

[0009] A plurality of active regions, one of the active regions is disposed on the periphery of one of the pixel regions, and the plurality of active regions respectively surround the corresponding pixel regions;

[0010] A plurality of deep trench isolation structures, one of the deep trench isolation structures is disposed on the periphery of one of the active regions, and the plurality of the deep trench isolation structures respectively surround the corresponding active regions;

[0011] Wherein, a shallow trench isolation structure is formed on the pixel area, and the shallow trench isolation structure extends from the active area to the pixel area.

[0012] In an embodiment of the present invention, on the surface facing the semiconductor substrate, the shallow trench isolation structure is arranged in a grid shape, and the deep trench isolation structure is arranged in a closed ring shape.

[0013] In an embodiment of the present invention, the upper surface of the shallow trench isolation structure, the upper surface of the deep trench isolation structure, and the surface of the active region are flush with each other.

[0014] In an embodiment of the present invention, the cross-sectional shape of the shallow trench isolation structure and the cross-sectional shape of the deep trench isolation structure are inverted trapezoids.

[0015] In an embodiment of the present invention, the depth of the shallow trench isolation structure is greater than or equal to 1.4 microns and less than or equal to 1.6 microns.

[0016] In an embodiment of the present invention, the upper aperture width of the shallow trench isolation structure is less than or equal to 0.069 micrometers, and the lower aperture width of the shallow trench isolation structure is smaller than the upper aperture width of the shallow trench isolation structure.

[0017] In an embodiment of the present invention, the widths of all sides of the active region are equal, and the width of the side of the active region is greater than or equal to 0.97 microns and less than or equal to 1.03 microns.

[0018] In an embodiment of the present invention, the depth of the deep trench isolation structure is greater than or equal to 2.9 microns and less than or equal to 3.3 microns.

[0019] In one embodiment of the utility model, the upper aperture width of the deep trench isolation structure is greater than or equal to the upper aperture width of the shallow trench isolation structure, and the inclination angle between the side of the deep trench isolation structure and the horizontal plane where its upper aperture is located is greater than or equal to 88° and less than 90°.

[0020] The utility model also provides a semiconductor chip, comprising the above-mentioned image sensor substrate.

[0021] As described above, the utility model provides an image sensor substrate and a semiconductor chip, and the unexpected technical effect is: the utility model can simulate the setting of the same isolation structure as that in the pixel area on the cutting road, so as to directly detect the cutting road after the process, so as to achieve indirect monitoring of the health of the pixel area after the process, thereby improving the detection efficiency of the image sensor and further improving the manufacturing efficiency of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for describing the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 Shown is a schematic diagram of a semiconductor chip of the present utility model;

[0024] Figure 2 Shown is a structural schematic diagram of an image sensor substrate of the utility model;

[0025] Figure 3 Display as Figure 2 A magnified view of the local structure;

[0026] Figure 4 Display as Figure 3 A partial cross-sectional view of .

[0027] Component number description:

[0028] 100, image sensor substrate; 110, semiconductor substrate; 111, cutting path;

[0029] 120. Image sensing unit; 121. Pixel area;

[0030] 130. Shallow trench isolation structure; 140. Active region; 150. Deep trench isolation structure;

[0031] 200. Semiconductor chips. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0033] See also Figures 1 to 4 The utility model provides an image sensor substrate, which can be applied to the health monitoring of the pixel area of ​​the image sensor during the manufacturing process, so as to improve the detection efficiency of the image sensor, and further improve the manufacturing efficiency of the image sensor. The image sensor substrate 100 may include but is not limited to a semiconductor substrate 110, an image sensing unit 120, a shallow trench isolation structure 130, an active area 140, and a deep trench isolation structure 150. Among them, the image sensing unit 120, the shallow trench isolation structure 130, the active area 140, and the deep trench isolation structure 150 can all be formed on the semiconductor substrate 110.

[0034] See also Figure 1 and Figure 2, a plurality of cutting lanes 111 may be formed on the semiconductor substrate 110, so as to facilitate cutting and separating the image sensing units 120 on the semiconductor substrate 110, thereby forming a plurality of image sensors. Each image sensing unit 120 may be formed between two adjacent cutting lanes 111, and a plurality of pixel regions 121 may be formed on each image sensing unit 120. A plurality of image sensing units 120 may be provided, and each image sensing unit 120 is surrounded by a plurality of cutting lanes 111.

[0035] See also Figure 3 and Figure 4 A shallow trench isolation structure 130 may be formed on the pixel region 121, so as to monitor the health of the pixel region 121 by monitoring the shallow trench isolation structure 130. Specifically, the shallow trench isolation structure 130 on the pixel region 121 may be arranged in a grid shape. In addition, the cross-sectional shape of the shallow trench isolation structure 130 may be an inverted trapezoid or other shapes.

[0036] See also Figure 3 and Figure 4 , further, the depth of the shallow trench isolation structure 130 may be greater than or equal to 1.4 microns and less than or equal to 1.6 microns. For example, the depth of the shallow trench isolation structure 130 may be 1.4 microns or 1.6 microns, but not limited thereto, the depth of the shallow trench isolation structure 130 may also be 1.5 microns. The upper aperture width of the shallow trench isolation structure 130 may be less than or equal to 0.069 microns, and the lower aperture width of the shallow trench isolation structure 130 may be less than the upper aperture width of the shallow trench isolation structure 130. However, not limited thereto, the depth of the shallow trench isolation structure 130 and its upper aperture width and lower aperture width may also be other range values. For example, the upper aperture width of the shallow trench isolation structure 130 may be 0.069 microns, and the lower aperture width of the shallow trench isolation structure 130 is 0.06 microns. However, the present invention is not limited thereto. The upper diameter width of the shallow trench isolation structure 130 may also be 0.065 micrometers, and the lower diameter width of the shallow trench isolation structure 130 may be 0.06 micrometers.

[0037] See also Figure 3 and Figure 4 Furthermore, the shallow trench isolation structure 130 can also be used to isolate the multiple pixel areas 121 in the image sensor unit 120 to prevent charge transfer and cross communication between them, thereby further improving the performance and stability of the image sensor. However, it is not limited to this. The shallow trench isolation structure 130 can also increase the fill factor in the image sensor unit 120 to improve the resolution and sensitivity of the image sensor unit 120.

[0038] See also Figure 3 and Figure 4, multiple active areas 140 can be provided, and one active area 140 can be provided on the peripheral side of a pixel area 121, and multiple active areas 140 can respectively surround the corresponding pixel areas 121. In addition, the shallow trench isolation structure 130 formed on the pixel area 121 surrounded by the active area 140 can extend from the active area 140 to the pixel area 121. That is, each active area 140 can correspond to surrounding a shallow trench isolation structure 130, so as to realize the monitoring of the health of the pixel area 121 by detecting the active area 140. On the surface facing the semiconductor substrate 110, the active area 140 can be arranged in a rectangular shape or in other shapes. In addition, the surface of the active area 140 can be flush with the upper surface of the shallow trench isolation structure 130.

[0039] See also Figure 3 and Figure 4 , further, all side widths of the active area 140 may be equal, and the side width of the active area 140 is greater than or equal to 0.97 microns and less than or equal to 1.03 microns. For example, on the surface facing the semiconductor substrate 110, the active area 140 may be in a square shape, and the side width of the active area 140 may be 0.97 microns or 1.03 microns. However, it is not limited thereto, and the side width of the active area 140 may also be 1 micron. In addition, the active area 140 may also function as a signal amplification, by amplifying the signal voltage and reducing the noise, thereby enhancing the signal-to-noise ratio of the image obtained by the image sensing unit 120.

[0040] See also Figure 3 and Figure 4 , multiple deep trench isolation structures 150 are provided, one deep trench isolation structure 150 can be provided at the periphery of an active area 140, and multiple deep trench isolation structures 150 can respectively surround the corresponding active area 140 to simulate the structure inside the pixel area 121. By sequentially providing the shallow trench isolation structure 130, the active area 140 and the deep trench isolation structure 150, the health of the pixel area 121 can be monitored by detecting the cutting road 111, avoiding irreversible damage to the pixel area 121 when the pixel area 121 is directly detected.

[0041] See also Figure 3 and Figure 4, further, the cross-sectional shape of the deep trench isolation structure 150 may be an inverted trapezoid or other shapes. Specifically, on the surface facing the semiconductor substrate 110, the deep trench isolation structure 150 may be arranged in a closed ring shape, and the upper surface of the deep trench isolation structure 150 may be flush with the surface of the active area 140. In addition, the depth of the deep trench isolation structure 150 may be greater than or equal to 2.9 microns and less than or equal to 3.3 microns. For example, the depth of the deep trench isolation structure 150 may be 2.9 microns or 3.3 microns. However, it is not limited thereto, and the depth of the deep trench isolation structure 150 may also be 3 microns. The upper aperture width of the deep trench isolation structure 150 may be greater than or equal to the upper aperture width of the shallow trench isolation structure 130, the lower aperture width of the deep trench isolation structure 150 may be less than the upper aperture width, and the inclined angle between the side of the deep trench isolation structure 150 and the horizontal plane where its upper aperture is located is greater than or equal to 88° and less than 90°. For example, the upper aperture width of the deep trench isolation structure 150 is 0.069 micrometers, and the inclined angle between the side of the deep trench isolation structure 150 and the horizontal plane where the upper aperture is located is 88°.

[0042] See also Figure 3 and Figure 4 Furthermore, by setting a deep trench isolation structure 150 on the cutting road 111, pixel isolation on the pixel area 121 within the image sensing unit 120 adjacent to each other on both sides of the cutting road 111 can be achieved, thereby reducing the charge transfer and cross-communication between adjacent pixel areas 121, thereby improving the performance and stability of the image sensing unit 120 adjacent to each other on both sides of the cutting road 111.

[0043] See also Figures 1 to 4The utility model also provides a semiconductor chip 200, and the semiconductor chip 200 may include the above-mentioned image sensor substrate 100. The image sensor substrate 100 may be provided with at least one to form an image sensor. Specifically, an image sensing unit 120 may be provided in the image sensor substrate 100, and 20 pixel areas 121 may be formed in the image sensing unit 120, and the 20 pixel areas 121 may be arranged in 4 rows and 5 columns. Furthermore, a cutting road 111 may be formed between two adjacent pixel areas 121 to cut and separate the adjacent pixel areas 121. A plurality of shallow trench isolation structures 130, a plurality of active areas 140, and a plurality of deep trench isolation structures 150 may be provided on the image sensor substrate 100. Each shallow trench isolation structure 130 is formed in the pixel area 121 and extends from the active area 140 to the pixel area 121. The depth of the shallow trench isolation structure 130 can be set to 1.4 microns, or 1.6 microns, but is not limited thereto. The depth of the shallow trench isolation structure 130 can also be set to 1.5 microns. The upper aperture width of the shallow trench isolation structure 130 can be set to 0.069 microns, and the lower aperture width of the shallow trench isolation structure 130 is set to 0.06 microns. However, it is not limited thereto. The upper aperture width of the shallow trench isolation structure 130 can also be set to 0.065 microns, and the lower aperture width of the shallow trench isolation structure 130 is set to 0.06 microns.

[0044] Further, a plurality of active regions 140 may be provided, and the active regions 140 may be provided at the periphery of the pixel region 121, and the plurality of active regions 140 may respectively surround the corresponding pixel regions 121. The surface of the active region 140 may be flush with the upper surface of the shallow trench isolation structure 130. In addition, the side width of the active region 140 may be set to 0.97 microns or 1.03 microns. However, it is not limited thereto, and the side width of the active region 140 may also be set to 1 micron.

[0045] Furthermore, the deep trench isolation structure 150 can be arranged on the periphery of the active area 140. Each deep trench isolation structure 150 can surround a corresponding active area 140 to simulate the structure inside the pixel area 121. The cross-sectional shape of the deep trench isolation structure 150 can be an inverted trapezoid or other shapes. The depth of the deep trench isolation structure 150 can be set to 2.9 microns or 3.3 microns. However, it is not limited to this, and the depth of the deep trench isolation structure 150 can also be set to 3 microns. Specifically, the upper aperture width of the deep trench isolation structure 150 is set to 0.069 microns, and the inclination angle between the side of the deep trench isolation structure 150 and the horizontal plane where its upper aperture is located can be set to 88°. After the process of the image sensor substrate 100 is completed, due to the shallow trench isolation structure 130 in the pixel area 121, the active area 140 on the cutting road 111 and the deep trench isolation structure 150 are the same as the structure in the pixel area 121. Therefore, the pixel area 121 can be indirectly monitored by directly detecting the cutting street 111 and detecting the changes in the depth and width of the shallow trench isolation structure 130, the active area 140 and the deep trench isolation structure 150. For example, the health of the pixel area 121 after the process can be indirectly monitored by measuring the key dimensions, defect detection and defect detection using an optical microscope on the cutting street 111.

[0046] In summary, the utility model provides an image sensor substrate and a semiconductor chip, which relate to the field of semiconductor technology. The unexpected technical effect of the utility model is that the same structure as that in the pixel area can be simulated on the cutting road, so as to directly detect the cutting road after the process, so as to indirectly monitor the health of the pixel area after the process, thereby improving the detection efficiency of the image sensor, and then improving the manufacturing efficiency of the image sensor. Therefore, the utility model has a high industrial utilization value because it effectively overcomes various shortcomings in the prior art.

[0047] In the description of this specification, the description with reference to the terms "this embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0048] The embodiments of the utility model disclosed above are only used to help illustrate the utility model. The embodiments do not describe all the details in detail, nor do they limit the utility model to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the utility model, so that technicians in the relevant technical field can well understand and use the utility model. The utility model is limited only by the claims and their full scope and equivalents.

Claims

1. An image sensor substrate, characterized in that: include: A semiconductor substrate is provided with a plurality of cutting lanes; A plurality of image sensing units are formed between two adjacent cutting lanes, and each of the image sensing units includes a plurality of pixel areas; A plurality of active regions, one of the active regions is disposed on the periphery of one of the pixel regions, and the plurality of active regions respectively surround the corresponding pixel regions; A plurality of deep trench isolation structures, one of the deep trench isolation structures is disposed on the periphery of one of the active regions, and the plurality of the deep trench isolation structures respectively surround the corresponding active regions; Wherein, a shallow trench isolation structure is formed on the pixel area, and the shallow trench isolation structure extends from the active area to the pixel area.

2. The image sensor substrate according to claim 1, wherein: On the surface facing the semiconductor substrate, the shallow trench isolation structure is arranged in a grid shape, and the deep trench isolation structure is arranged in a closed ring shape.

3. The image sensor substrate according to claim 1, wherein: An upper surface of the shallow trench isolation structure, an upper surface of the deep trench isolation structure, and a surface of the active region are flush with each other.

4. The image sensor substrate according to claim 1, wherein: The cross-sectional shape of the shallow trench isolation structure and the cross-sectional shape of the deep trench isolation structure are inverted trapezoids.

5. The image sensor substrate according to claim 4, characterized in that: The depth of the shallow trench isolation structure is greater than or equal to 1.4 microns and less than or equal to 1.6 microns.

6. The image sensor substrate according to claim 4, characterized in that: The upper aperture width of the shallow trench isolation structure is less than or equal to 0.069 micrometers, and the lower aperture width of the shallow trench isolation structure is smaller than the upper aperture width of the shallow trench isolation structure.

7. The image sensor substrate according to claim 1, wherein: The widths of all sides of the active region are equal, and the width of the side of the active region is greater than or equal to 0.97 microns and less than or equal to 1.03 microns.

8. The image sensor substrate according to claim 4, characterized in that: The depth of the deep trench isolation structure is greater than or equal to 2.9 microns and less than or equal to 3.3 microns.

9. The image sensor substrate according to claim 4, characterized in that: The upper aperture width of the deep trench isolation structure is greater than or equal to the upper aperture width of the shallow trench isolation structure, and the inclined angle between the side of the deep trench isolation structure and the horizontal plane where its upper aperture is located is greater than or equal to 88° and less than 90°.

10. A semiconductor chip, characterized in that: The invention comprises the image sensor substrate as claimed in any one of claims 1 to 9.

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