A solar cell and its component

Abstract

The utility model discloses a solar cell and its components, which are used to reduce the influence of electrode preparation on other film layer structures and performances. The solar cell comprises a substrate, a first electrode layer and a second electrode layer, wherein the substrate has a first doping region and a second doping region arranged in a staggered manner on the first surface, and an isolation region separating the first doping region and the second doping region, wherein the first doping region and the first doping region have different doping types; the first doping region comprises a first tunneling layer, a first doped polysilicon layer and a second tunneling layer sequentially arranged along the direction from the second surface to the first surface, the second tunneling layer covers the surface of the first doped polysilicon layer, the first electrode layer is arranged on the second tunneling layer, and the projection area of ​​the first electrode layer on the substrate accounts for 90% to 100% of the projection area of ​​the first doping region on the substrate; the second electrode layer is arranged on the second doping region, and its projection area on the substrate accounts for 90% to 100% of the projection area of ​​the second doping region on the substrate; the isolation region comprises a tunneling layer arranged on the first surface.

Description

Technical Field

[0001] The utility model relates to the technical field of photovoltaics, in particular to a solar cell and a component thereof. Background Art

[0002] Back contact (BC) solar cells refer to cells with emitter and metal contact both on the back of the cell, and no metal electrode blocking the front. Compared with cells with blocked front, back contact cells have higher short-circuit current and photoelectric conversion efficiency. The passivation contact structure composed of tunnel oxide layer and doped polysilicon layer in tunnel oxide passivated contact (TOPCon) cells can effectively reduce the recombination rate between silicon wafer surface and metal contact. The efficiency of BC cells with superimposed TOPCon and IBC technologies is relatively high, and it has gradually become a research hotspot. In BC cells with superimposed TOPCon and IBC technologies, a stack of aluminum oxide and silicon nitride is often used as a passivation anti-reflection layer on the doped polysilicon layer on the back. By sintering or laser etching, the electrode material deposited on the passivation anti-reflection layer can contact the doped polysilicon layer.

[0003] However, the process of preparing the above-mentioned passivation anti-reflection layer is relatively cumbersome, and for the back of the battery, it receives less sunlight, so the necessity of setting the anti-reflection layer is not very high. In addition, when preparing a metal electrode on the passivation anti-reflection layer, if the electrode material is a material that is easy to corrode the passivation anti-reflection layer, such as silver, then the silver paste can be directly printed on the passivation anti-reflection layer, and then the silver paste is made to penetrate the passivation anti-reflection layer and contact the doped polysilicon layer by high-temperature sintering. However, when the electrode paste contacts the doped polysilicon layer, the electrode paste is easy to react with the doped polysilicon layer to produce an alloy, destroy the structure of the doped polysilicon layer or introduce impurities, thereby degrading the performance of the doped polysilicon layer; if the electrode material is a material that is not easy to corrode the passivation anti-reflection layer, such as aluminum, copper, etc., it is necessary to laser etch the passivation anti-reflection layer before preparing the electrode material, leak out the doped polysilicon layer, and then prepare the electrode by screen printing, but during laser etching, it is not easy to control the laser etching depth, and it is easy to damage the doped polysilicon layer. Utility Model Content

[0004] The utility model aims to provide a solar cell and a component thereof, so as to reduce the influence of electrode preparation on other film structures and performances.

[0005] In a first aspect, the utility model provides a solar cell, comprising a substrate, a first electrode layer and a second electrode layer, wherein the substrate has a first surface and a second surface opposite to each other, the first surface has first doping regions and second doping regions arranged alternately, and an isolation region for spacing the first doping regions and the second doping regions, and the first doping regions and the second doping regions have different doping types;

[0006] The first doped region includes a first tunneling layer, a first doped polysilicon layer, and a second tunneling layer sequentially arranged from the second surface to the first surface, the first tunneling layer is in contact with the first surface, the second tunneling layer covers the surface of the first doped polysilicon layer, the first electrode layer is disposed on the second tunneling layer, and a projection area of ​​the first electrode layer on the substrate accounts for 90% to 100% of a projection area of ​​the first doped region on the substrate;

[0007] The second electrode layer is disposed in the second doping region, and a projection area of ​​the second electrode layer on the substrate accounts for 90% to 100% of a projection area of ​​the second doping region on the substrate;

[0008] The isolation region includes a tunneling layer disposed on the first surface.

[0009] In the case of adopting the above technical solution, compared with the structure in the prior art in which the doped region is composed of a tunneling oxide layer, a doped polysilicon layer and a passivation anti-reflection layer, the first doped region of the solar cell in the present application includes a first tunneling layer, a first doped polysilicon layer and a second tunneling layer, that is, the second tunneling layer replaces the original passivation anti-reflection layer. When the first electrode layer is made on the second tunneling layer, since the second tunneling layer has a unidirectional carrier transmission capability, the first electrode layer can achieve contact with the first doped polysilicon layer through the second tunneling layer, and the first electrode layer and the second electrode layer with a projected area of ​​90%-100% of the doped region prepared by low-temperature processes such as physical vapor deposition, that is, the electrode with a wider width prepared by the low-temperature process, the wide electrode can reduce the series resistance Rs, reduce the resistivity, increase the projected area of ​​the electrode layer on the substrate, increase the contact area between the electrode layer and the second tunneling layer, and improve the bonding force between the electrode and the second tunneling layer. And the thickness of the electrode layer can be reduced while meeting the conductivity requirements, effectively preventing the electrode from tipping over or deforming. At the same time, the electrode layer is arranged on the back of the battery, and the wide back electrode or back contact electrode formed will not block the light absorption of the light-receiving surface of the battery, and the thickness of the wide electrode can be thinned, which can reduce the electrode preparation time and improve the electrode preparation efficiency. The first electrode layer prepared by the low-temperature process avoids the reduction of the passivation effect caused by the escape of H atoms in the first doped polysilicon layer and at the interface with the first tunneling layer under high temperature conditions, and there will be no electrode slurry contacting the first doped polysilicon layer due to high-temperature sintering, resulting in the electrode slurry and the first doped polysilicon layer reacting to produce alloys, destroying the structure of the first doped polysilicon layer or introducing impurities. The present application will not destroy the interface between the first doped polysilicon layer and the first tunneling layer, protecting the battery structure. In addition, the present application adopts a low-temperature preparation process to prepare the first electrode layer on the second tunneling layer, and there is no need to perform laser etching and grooving on the second tunneling layer, so as to avoid accidental damage to the first doped polysilicon layer caused by laser etching.

[0010] In some possible implementations, the thickness of the first electrode layer and / or the second electrode layer at any position is 0.5 μm-31 μm.

[0011] In some possible implementations, the second doped region includes the first tunneling layer, the second doped polysilicon layer, and the second tunneling layer sequentially arranged along a direction from the second surface to the first surface, the first tunneling layer contacts the first surface, the second tunneling layer covers a surface of the second doped polysilicon layer, and the second electrode layer is disposed on the second tunneling layer; the tunneling layer is a stack of the first tunneling layer and the second tunneling layer;

[0012] The first doped polysilicon layer and the second doped polysilicon layer have different doping types.

[0013] In some possible implementations, the thickness of the first tunneling layer is less than or equal to 2 nm;

[0014] And / or, the thickness of the second tunneling layer is less than or equal to 5 nm.

[0015] In some possible implementations, the thickness of the second tunneling layer is less than or equal to 2.5 nm.

[0016] In some possible implementations, the thickness of the second tunneling layer is less than or equal to 2 nm.

[0017] In some possible implementations, the thickness of the second tunneling layer is less than or equal to 1.5 nm.

[0018] In some possible implementations, the first tunneling layer is one or more stacks of a silicon oxide layer, a hydrogenated silicon oxide layer, a silicon nitride layer, a hydrogenated silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer, a hydrogenated silicon oxynitride layer, a silicon carbide layer, a molybdenum oxide layer, a chromium oxide layer, and a thallium oxide layer;

[0019] And / or, the second tunneling layer is one or more layers selected from the group consisting of a silicon oxide layer, a hydrogenated silicon oxide layer, a silicon nitride layer, a hydrogenated silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer, a hydrogenated silicon oxynitride layer, a silicon carbide layer, a molybdenum oxide layer, a chromium oxide layer, and a thallium oxide layer.

[0020] In some possible implementations, the first electrode layer is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, and Cd, or a corresponding number of stacked electrodes composed of multiple stacks;

[0021] And / or, the second electrode layer is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, and Cd, or a corresponding number of stacked electrodes composed of multiple stacked layers.

[0022] In some possible implementations, the first electrode layer is a laminated electrode composed of Ti, Al and Ni layers or a laminated electrode composed of Al and Ni layers;

[0023] And / or, the second electrode layer is a laminated electrode consisting of Ti, Al and Ni laminated layers or a laminated electrode consisting of Al and Ni laminated layers.

[0024] In some possible implementations, the solar cell further includes a passivation layer and an anti-reflection layer sequentially arranged on the second surface along a direction from the first surface to the second surface.

[0025] In some possible implementations, the anti-reflection layer is a single-layer anti-reflection structure composed of one of silicon nitride, silicon oxynitride, silicon oxide, and a transparent conductive layer, or a corresponding number of stacked anti-reflection structures composed of multiple stacked layers.

[0026] In some possible implementations, the passivation layer is a single-layer passivation structure composed of one of intrinsic amorphous silicon, aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide, or a corresponding number of stacked passivation structures composed of multiple stacked layers.

[0027] In a second aspect, the utility model further provides a solar cell assembly, comprising a solar cell as described in any one of the above items.

[0028] The solar cell assembly has the same beneficial effects as the solar cell of the first aspect, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0030] Figure 1 A schematic structural diagram of a solar cell provided in an embodiment of the utility model.

[0031] Reference numerals:

[0032] 10-substrate, 101-first doping region,

[0033] 102 - second doping region, 103 - isolation region,

[0034] 11-first tunneling layer, 12-first doped polysilicon layer,

[0035] 13- second tunneling layer, 14- first electrode layer,

[0036] 15- second electrode layer, 16- passivation layer,

[0037] 17 - anti-reflection layer, 18 - second doped polysilicon layer. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0040] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0041] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0042] In the description of the present utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0043] In the current BC cells that superimpose TOPCon and IBC technologies, a stack of aluminum oxide and silicon nitride is often used as a passivation anti-reflection layer on the doped polysilicon layer on the back. By sintering or laser etching, the electrode material deposited on the passivation anti-reflection layer can contact the doped polysilicon layer.

[0044] However, when preparing a metal electrode on the passivation anti-reflection layer, if the electrode material is a material that easily corrodes the passivation anti-reflection layer, such as silver, silver paste can be directly printed on the passivation anti-reflection layer, and then the silver paste can be made to penetrate the passivation anti-reflection layer and contact the doped polysilicon layer by high-temperature sintering. However, when the electrode paste contacts the doped polysilicon layer, the electrode paste easily reacts with the doped polysilicon layer to produce an alloy, destroying the structure of the doped polysilicon layer or introducing impurities, thereby degrading the performance of the doped polysilicon layer. If the electrode material is a material that is not easy to corrode the passivation anti-reflection layer, such as aluminum, copper, etc., it is necessary to laser etch the passivation anti-reflection layer before preparing the electrode material to leak out the doped polysilicon layer, and then prepare the electrode by screen printing. However, during laser etching, it is not easy to control the laser etching depth, and the doped polysilicon layer is easily damaged.

[0045] In view of this, refer to Figure 1 The present invention provides a solar cell, comprising a substrate 10, a first electrode layer 14 and a second electrode layer 15; wherein the substrate 10 has a first surface and a second surface opposite to each other, and for the solar cell, the first surface is a backlight surface, and the second surface is a light-facing surface, and the first surface has staggered first doping regions 101 and second doping regions 102, and an isolation region 103 for spacing the first doping regions 101 and the second doping regions 102, and the first doping regions 101 and the second doping regions 102 have different doping types;

[0046] The first doped region 101 includes a first tunneling layer 11, a first doped polysilicon layer 12, and a second tunneling layer 13 arranged in sequence along the direction from the second surface to the first surface (i.e., from the inside to the outside); the first tunneling layer 11 contacts the first surface, and the first tunneling layer 11 and the first doped polysilicon layer 12 form a tunnel passivation contact structure; the second tunneling layer 13 covers the surface of the first doped polysilicon layer 12, that is, the second tunneling layer 13 covers a surface of the first doped polysilicon layer 12 away from the substrate 10 and the side surface of the first doped polysilicon layer 12; the first electrode layer 14 is arranged on the second tunneling layer 13, and the projection area of ​​the first electrode layer 14 on the substrate 10 accounts for 90% to 100% of the projection area of ​​the first doped region 101 on the substrate 10. The second electrode layer 15 is arranged in the second doped region 102, and the projection area of ​​the second electrode layer 15 on the substrate 10 accounts for 90% to 100% of the projection area of ​​the second doped region 102 on the substrate 10. The isolation region 103 includes a tunneling layer disposed on the first surface.

[0047] Compared with the structure of the doped region composed of the tunnel oxide layer, the doped polysilicon layer and the passivation anti-reflection layer in the prior art, the first doped region 101 of the solar cell in the present application includes the first tunnel layer 11, the first doped polysilicon layer 12 and the second tunnel layer 13, that is, the second tunnel layer 13 replaces the original passivation anti-reflection layer. When the first electrode layer 14 is made on the second tunnel layer 13, since the second tunnel layer 13 has the unidirectional carrier transmission capability, the first electrode layer 14 can achieve contact with the first doped polysilicon layer 12 through the second tunnel layer 13. The first electrode layer 14 and the second electrode layer 15, whose projected area accounts for 90%-100% of the doped region, are prepared by low-temperature processes such as physical vapor deposition, that is, electrodes with a wider width and a thinner thickness prepared by low-temperature processes. The wide electrode can reduce the series resistance Rs and the resistivity. By increasing the projected area of ​​the electrode layer on the substrate 10, the contact area between the electrode layer and the second tunnel layer 13 is increased, and the bonding force between the electrode and the second tunnel layer 13 is improved. And under the condition of meeting the conductivity requirements, the thickness of the electrode layer can be reduced, the electrode can be effectively prevented from tipping or deforming, and the electrode preparation time can be reduced, and the electrode preparation efficiency can be improved. At the same time, the electrode layer is arranged on the back of the battery, and the wide back electrode or back contact electrode formed will not block the light absorption of the light-receiving surface of the battery. The first electrode layer 14 prepared by the low-temperature process avoids the reduction of the passivation effect caused by the escape of H atoms in the first doped polysilicon layer 12 and at the interface with the first tunneling layer 11 under high temperature conditions, and there will be no electrode slurry due to high-temperature sintering and contact with the first doped polysilicon layer 12, resulting in the electrode slurry and the first doped polysilicon layer 12 reacting to produce alloys, destroying the structure of the first doped polysilicon layer 12 or introducing impurities. The present application will not destroy the interface between the first doped polysilicon layer 12 and the first tunneling layer 11, and protect the battery structure. In addition, the present application adopts a low-temperature preparation process to prepare the first electrode layer 14 on the second tunneling layer 13, and there is no need to perform laser etching and grooving on the second tunneling layer 13, so as to avoid accidental damage to the first doped polysilicon layer 12 caused by laser etching.

[0048] In summary, it can be seen that the structure of the first doping region 101 of the solar cell can reduce the impact of electrode preparation on other film structures and performances. In addition, the second tunneling layer 13 and the first electrode layer 14 can be prepared using the same low-temperature process, which can reduce process steps and preparation procedures.

[0049] In practical applications, the substrate 10 is a semiconductor substrate. The material of the substrate 10 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the substrate 10 can be an intrinsic conductive substrate, an N-type conductive substrate or a P-type conductive substrate. Preferably, the substrate 10 is a P-type conductive substrate or an N-type conductive substrate. Compared with an intrinsic conductive substrate, a P-type conductive substrate or an N-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the back contact cell.

[0050] The material of the first doped polysilicon layer 12 can be silicon (Si), germanium (Ge), silicon carbide (SiC x ) or gallium arsenide (GaAs), etc. In terms of conductivity type, the first doped polysilicon layer 12 may be a P-type doped polysilicon layer or an N-type doped polysilicon layer.

[0051] In some examples, when the substrate 10 is an N-type conductive substrate, the first doped region 101 can be a P-type doped region, the second doped region 102 can be an N-type doped region, and the corresponding first doped polysilicon layer 12 can be a P-type polysilicon doped layer; or, the first doped region 101 can be an N-type doped region, the second doped region 102 can be a P-type doped region, and the corresponding first doped polysilicon layer 12 can be an N-type polysilicon doped layer.

[0052] In some possible implementations, the thickness of any position of the first electrode layer 14 and / or the second electrode layer 15 is 0.5 μm-31 μm, specifically, the thickness of any position of the first electrode layer 14 and / or the second electrode layer 15 may be 0.5 μm, 1 μm, 2 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 31 μm, etc. In the case where the first electrode layer 14 and the second electrode layer 15 meet the conductivity requirements, when the electrode width is wide, the thickness of the electrode layer can be reduced, effectively preventing the electrode from tipping over or deforming, and reducing the electrode preparation time and improving the electrode preparation efficiency.

[0053] like Figure 1As shown, when the solar cell is a TBC (Topcon+BC, back contact tunneling passivation) cell, the first doped region 101 includes a first tunneling layer 11, a first doped polysilicon layer 12 and a second tunneling layer 13 arranged in sequence from the second surface to the first surface, which is the same as the description of the above embodiment and will not be repeated. The second doping region 102 of the TBC battery specifically includes a first tunneling layer 11, a second doped polysilicon layer 18 and a second tunneling layer 13 arranged in sequence from the second surface to the first surface, the first tunneling layer 11 is in contact with the first surface, and the first tunneling layer 11 and the second doped polysilicon layer 18 of the second doping region 102 form a tunneling passivation contact structure; the second tunneling layer 13 of the second doping region 102 covers the surface of the second doped polysilicon layer 18, that is, the second tunneling layer 13 covers a surface of the second doped polysilicon layer 18 away from the substrate 10 and the side surface of the second doped polysilicon layer 18; the second electrode layer 15 is arranged on the second tunneling layer 13 corresponding to the second doping region 102; the tunneling layer on the isolation region 103 is a stack of the first tunneling layer 11 and the second tunneling layer 13, and the first tunneling layer 11 of the isolation region 103 is in contact with the first surface of the substrate 10; wherein the doping types of the first doped polysilicon layer 12 and the second doped polysilicon layer 18 are different.

[0054] When preparing the first doping region 101, the second doping region 102 and the isolation region 103 of the TBC battery, a first tunneling layer 11 is formed on the entire first surface of the substrate 10; then, a first doped polysilicon layer 12 is formed on the first tunneling layer 11 at a position corresponding to the first doping region 101; a second doped polysilicon layer 18 is formed on the first tunneling layer 11 at a position corresponding to the second doping region 102; next, a second tunneling layer 13 is formed on the surface of the first doped polysilicon layer 12, the surface of the second doped polysilicon layer 18 and on the first tunneling layer 11 at a position corresponding to the isolation region 103, that is, the second tunneling layer 13 of the first doping region 101, the second tunneling layer 13 of the second doping region 102 and the second tunneling layer 13 on the isolation region 103 are the same layer and are formed in the same step, and the tunneling layer of the isolation region 103 is formed by stacking the first tunneling layer 11 and the second tunneling layer 13.

[0055] Compared with the structure composed of a tunneling oxide layer, a doped polysilicon layer and a passivation anti-reflection layer in the prior art, the second doped region 102 of the solar cell in the present application includes a first tunneling layer 11, a second doped polysilicon layer 18 and a second tunneling layer 13, that is, the second tunneling layer 13 replaces the original passivation anti-reflection layer. When the second electrode layer 15 is made on the second tunneling layer 13, since the second tunneling layer 13 has a unidirectional carrier transmission capability, the second electrode layer 15 can achieve contact with the second doped polysilicon layer 18 through the second tunneling layer 13. The second electrode layer 15 with a projected area of ​​90%-100% of the doped region prepared by a low-temperature process such as physical vapor deposition, that is, an electrode with a wider width and a thinner thickness prepared by a low-temperature process, the wide electrode can reduce the series resistance Rs and the resistivity. By increasing the projected area of ​​the electrode layer on the substrate, the contact area between the electrode layer and the second tunneling layer 13 is increased, and the bonding force between the electrode and the second tunneling layer 13 is improved. And under the condition of meeting the conductivity requirements, the thickness of the electrode layer can be reduced, the electrode can be effectively prevented from tipping or deforming, and the electrode preparation time can be reduced, and the electrode preparation efficiency can be improved. At the same time, the electrode layer is arranged on the back of the battery, and the wide back electrode or back contact electrode formed will not block the light absorption of the light-receiving surface of the battery. The second electrode layer 15 prepared by the low-temperature process avoids the reduction of the passivation effect caused by the escape of H atoms in the second doped polysilicon layer 18 and at the interface with the first tunneling layer 11 under high temperature conditions, and there will be no electrode slurry due to high-temperature sintering. Contact with the second doped polysilicon layer 18, resulting in the electrode slurry and the second doped polysilicon layer 18 react to produce alloys, destroy the structure of the second doped polysilicon layer 18 or introduce impurities. The present application will not destroy the interface between the second doped polysilicon layer 18 and the first tunneling layer 11, and protect the battery structure. In addition, the present application adopts a low-temperature preparation process to prepare the second electrode layer 15 on the second tunneling layer 13, and there is no need to perform laser etching and grooving on the second tunneling layer 13, so as to avoid accidental damage to the second doped polysilicon layer 18 caused by laser etching. By replacing the passivation anti-reflection layers on the first doped polysilicon layer 12 and the second doped polysilicon layer 18 with the second tunneling layer 13, the structure and performance of other film layers of the battery can be further protected from being affected when preparing the first electrode layer 14 and the second electrode layer 15.

[0056] For example, the substrate 10 of the TBC cell can be a P-type silicon substrate or an N-type silicon substrate. When the substrate 10 is a P-type silicon substrate, the first doped region 101 is an N-type doped region, the second doped region 102 is a P-type doped region, the first doped polysilicon layer 12 in the N-type doped region is an N-type doped polysilicon layer, and the second doped polysilicon layer 18 in the P-type doped region is a P-type doped polysilicon layer. When the substrate 10 is an N-type silicon substrate, the first doped region 101 is a P-type doped region, the second doped region 102 is an N-type doped region, the first doped polysilicon layer 12 in the P-type doped region is a P-type doped polysilicon layer, and the second doped polysilicon layer 18 in the N-type doped region is an N-type doped polysilicon layer. The first electrode layer 14 and the second electrode layer 15 can be metal gate lines, and the metal gate lines can include a main gate and a fine gate, or only a fine gate.

[0057] In some possible implementations, the thickness of the first tunneling layer 11 is less than or equal to 2 nm, and the first tunneling layer 11 forms a tunneling passivation contact structure with the doped polysilicon layer. The thinner first tunneling layer 11 allows majority carriers to tunnel into the doped polysilicon layer while blocking minority carriers from passing through, and then majority carriers are transported laterally in the doped polysilicon layer and collected by the electrode, reducing the recombination of carriers and improving the open circuit voltage and short circuit current of the back contact battery. The tunneling passivation contact structure can achieve excellent interface passivation and selective collection of carriers, improving the photoelectric conversion efficiency of the back contact battery.

[0058] In some possible implementations, the thickness of the second tunnel layer 13 is less than or equal to 5 nm. Specifically, the thickness of the second tunnel layer 13 is less than or equal to 2.5 nm. Further, the thickness of the second tunnel layer 13 is less than or equal to 2 nm. Further, the thickness of the second tunnel layer 13 is less than or equal to 1.5 nm. The thickness of the second tunnel layer 13 is very thin. A second tunneling layer 13 is arranged between the first doped polysilicon layer 12 and the first electrode layer 14 and between the second doped polysilicon layer 18 and the second electrode layer 15. Since the thickness of the second tunneling layer 13 is very thin, selective transmission of carriers can be achieved through the tunneling principle, that is, one carrier can pass through the second tunneling layer 13, while the other carrier is difficult to tunnel through the second tunneling layer 13 due to the existence of potential barriers and field effects in the doped region, thereby reducing interface recombination. Moreover, since the thickness of the second tunneling layer 13 is very thin, contact between the doped polysilicon layer and the electrode layer can also be achieved, that is, not only can the interface recombination be significantly reduced, but also the contact between the doped polysilicon layer and the electrode layer can be ensured, so that the solar cell has a higher open circuit voltage and short circuit current, thereby increasing the photoelectric conversion efficiency.

[0059] In some embodiments, the materials of the first tunneling layer 11 and the second tunneling layer 13 may be the same or different, wherein the first tunneling layer 11 may be a layer or a plurality of stacked layers selected from a silicon oxide layer, a hydrogenated silicon oxide layer, a silicon nitride layer, a hydrogenated silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer, a hydrogenated silicon oxynitride layer, a silicon carbide layer, a molybdenum oxide layer, a chromium oxide layer, and a thallium oxide layer. It should be noted that the stacked structure is composed of a plurality of physical stacked layers of film layers of different materials, each film layer is made of a single material, and there is no mixing or chemical reaction combination between adjacent film layers. Of course, the first tunneling layer 11 may also be formed as a layer by mixing a plurality of materials.

[0060] Similarly, the structure of the second tunnel layer 13 refers to the structure of the first tunnel layer 11 , and will not be described in detail here.

[0061] For example, when the first tunneling layer 11 or the second tunneling layer 13 is a stack of multiple materials, the first tunneling layer 11 or the second tunneling layer 13 includes an Al2O3 layer and a SiO2 layer stacked in a direction from the second surface to the first surface. Compared with a single-layer Al2O3 layer or SiO2 layer, the stacked tunneling layer can provide sufficiently good passivation performance. Of course, the first tunneling layer 11 and the second tunneling layer 13 can also be other materials and structural forms, and are not limited to the forms described in this embodiment.

[0062] In practical applications, the first tunneling layer 11 and the second tunneling layer 13 can be prepared by techniques such as atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition. In one example, the second tunneling layer 13 can be generated by physical vapor deposition (such as evaporation or sputtering) under low temperature conditions, and after the second tunneling layer 13 is prepared in the same process, metal can be deposited to form a metal electrode, namely the first electrode layer 14 and the second electrode layer 15. This can reduce the process steps and the preparation process. Moreover, since the first electrode layer 14 and the second electrode layer 15 are prepared by the low-temperature preparation process, the escape of H atoms at the interface between the doped polysilicon layer and the first tunneling layer 11 under high temperature conditions to reduce the passivation effect during the high-temperature sintering process is avoided. Furthermore, since the low-temperature process is adopted, the electrode slurry of the metal (such as Ag) and the doped polysilicon layer are avoided to react during the high-temperature sintering process to produce an alloy, destroy the structure of the doped polysilicon layer or introduce impurities, and destroy the interface between the doped polysilicon layer and the first tunneling layer 11, thereby protecting the battery structure.

[0063] In some embodiments, the first electrode layer 14 is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, Cd, and Ti, or a corresponding number of stacked electrodes composed of multiple stacked layers. It should be noted that the stacked electrode is composed of a physical stack of multiple electrode film layers of different materials, and the material of each electrode film layer is a single material, and there is no mixing and chemical reaction combination between adjacent electrode film layers. Of course, the first electrode layer 14 can also be an alloy composed of multiple materials.

[0064] Similarly, the structure of the second electrode layer 15 refers to the structure of the first electrode layer 14, which will not be described in detail. In addition, the second electrode layer 15 and the first electrode layer 14 can be made of the same or different materials. When the materials are the same, they can be prepared in the same process to simplify the process.

[0065] For example, when the first electrode layer 14 and the second electrode layer 15 are a stacked electrode, the first electrode layer 14 can be a stacked electrode composed of Ti, Al and Ni stacked in sequence, the Ti layer in the first electrode layer 14 is in contact with the second tunneling layer 13, the thickness of the Ti layer can be 0nm-50nm, the thickness of the Al layer can be 0.5μm-30μm, and the thickness of the Ni layer can be 20nm-500nm.

[0066] Alternatively, the first electrode layer 14 is a stacked electrode formed by sequentially stacking Al and Ni, and the Al layer in the first electrode layer 14 is in contact with the second tunneling layer 13 .

[0067] Similarly, the second electrode layer 15 may be a laminated electrode composed of Ti, Al and Ni or a laminated electrode composed of Al and Ni. The same may be said for the first electrode layer 14 and will not be described in detail.

[0068] The first electrode layer 14 and the second electrode layer 15 adopt a multi-layer metal stack, which expands the selection range of the electrode, and can select a metal with good conductive contact with the second tunneling layer 13 as the first layer of the electrode, select a metal with low cost as the main material of the electrode, and select a metal with good welding performance as the outermost layer of the electrode. The conductive efficiency of the electrode is improved by stacking multiple metal layers.

[0069] In practical applications, the first electrode layer 14 and / or the second electrode layer 15 can be prepared by screen printing, physical vapor deposition, electroplating, etc., and the present application does not make specific limitations. A low-temperature process can be used to prepare them directly on the second tunneling layer 13. The second tunneling layer 13 can be used to achieve contact between the first electrode layer 14 and the first doped polysilicon layer 12, and between the second electrode layer 15 and the second doped polysilicon layer 18. There is no need to burn through the second tunneling layer 13 at high temperature or to etch grooves on the second tunneling layer 13. The same process as the second tunneling layer 13 can be used to prepare them, which simplifies the process and protects the membrane structure and performance of the battery.

[0070] like Figure 1 As shown, the solar cell also includes a passivation layer 16 and an anti-reflection layer 17 sequentially arranged on the second surface along the direction from the first surface to the second surface. For example, the second surface of the TBC cell, that is, the light-facing surface, is sequentially provided with a passivation layer 16 and an anti-reflection layer 17. By providing the anti-reflection layer 17, the reflection of the light incident on the second surface is reduced, the refraction of the light is improved, and the utilization rate of the light incident on the second surface is increased, thereby improving the photoelectric conversion efficiency of the solar cell. By providing the passivation layer 16, the surface of the second surface can be passivated to improve the photoelectric conversion efficiency.

[0071] Exemplarily, the anti-reflection layer 17 can be a single-layer anti-reflection structure composed of one of silicon nitride, silicon oxynitride, silicon oxide, and a transparent conductive layer, or a corresponding number of stacked anti-reflection structures composed of multiple stacked layers. It should be noted that the material of each layer of the stacked anti-reflection structure is a single material, and the adjacent layer structures are only physically stacked, and there is no mixing or chemical reaction combination. Of course, the anti-reflection layer 17 can also be a layer of anti-reflection structure mixed with multiple materials. The process for forming the anti-reflection layer 17 can be a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process, a physical vapor deposition (PVD) process, a low pressure chemical vapor deposition (LPCVD) process or a catalytic chemical vapor deposition process, etc., which is not limited here.

[0072] For example, the passivation layer 16 can be a single-layer passivation structure composed of one of intrinsic amorphous silicon, aluminum oxide, silicon nitride, silicon oxynitride, and silicon oxide, or a corresponding number of stacked passivation structures composed of multiple stacked layers. It should be noted that the material of each layer of the stacked passivation structure is a single material, and the adjacent layer structures are only physically stacked, and there is no mixing or chemical reaction combination. Of course, the passivation layer 16 can also be a layer of passivation structure mixed with multiple materials. The process for forming the passivation layer 16 can be a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process, a physical vapor deposition (PVD) process, a low pressure chemical vapor deposition (LPCVD) process, or a catalytic chemical vapor deposition process, etc., which is not limited here.

[0073] Based on the solar cell described in any one of the above embodiments, an embodiment of the utility model further provides a solar cell assembly, comprising the solar cell described in any one of the above embodiments.

[0074] The solar cell assembly has the same beneficial effects as the solar cell described in any of the above embodiments, which will not be described in detail here.

[0075] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0076] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: The invention comprises a substrate, a first electrode layer and a second electrode layer, wherein the substrate has a first surface and a second surface opposite to each other, the first surface has first doping regions and second doping regions arranged alternately, and an isolation region for spacing the first doping regions and the second doping regions, and the first doping regions and the second doping regions have different doping types; The first doped region includes a first tunneling layer, a first doped polysilicon layer, and a second tunneling layer sequentially arranged from the second surface to the first surface, the first tunneling layer is in contact with the first surface, the second tunneling layer covers the surface of the first doped polysilicon layer, the first electrode layer is disposed on the second tunneling layer, and a projection area of ​​the first electrode layer on the substrate accounts for 90% to 100% of a projection area of ​​the first doped region on the substrate; The second electrode layer is disposed in the second doping region, and a projection area of ​​the second electrode layer on the substrate accounts for 90% to 100% of a projection area of ​​the second doping region on the substrate; The isolation region includes a tunneling layer disposed on the first surface.

2. The solar cell according to claim 1, characterized in that The thickness of the first electrode layer and / or the second electrode layer at any position is 0.5 μm-31 μm.

3. The solar cell according to claim 1, characterized in that The second doped region includes the first tunneling layer, the second doped polysilicon layer and the second tunneling layer sequentially arranged from the second surface to the first surface, the first tunneling layer is in contact with the first surface, the second tunneling layer covers the surface of the second doped polysilicon layer, and the second electrode layer is arranged on the second tunneling layer; the tunneling layer is a stack of the first tunneling layer and the second tunneling layer; The first doped polysilicon layer and the second doped polysilicon layer have different doping types.

4. The solar cell according to any one of claims 1 to 3, characterized in that: The thickness of the first tunneling layer is less than or equal to 2 nm; And / or, the thickness of the second tunneling layer is less than or equal to 5 nm.

5. The solar cell according to claim 4, characterized in that: The thickness of the second tunneling layer is less than or equal to 2.5 nm.

6. The solar cell according to claim 5, characterized in that: The thickness of the second tunneling layer is less than or equal to 2 nm.

7. The solar cell according to claim 6, characterized in that: The thickness of the second tunneling layer is less than or equal to 1.5 nm.

8. The solar cell according to any one of claims 1 to 3, characterized in that: The first tunneling layer is one or more layers selected from the group consisting of a silicon oxide layer, a hydrogenated silicon oxide layer, a silicon nitride layer, a hydrogenated silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer, a hydrogenated silicon oxynitride layer, a silicon carbide layer, a molybdenum oxide layer, a chromium oxide layer, and a thallium oxide layer; And / or, the second tunneling layer is one or more layers selected from the group consisting of a silicon oxide layer, a hydrogenated silicon oxide layer, a silicon nitride layer, a hydrogenated silicon nitride layer, an aluminum oxide layer, a silicon oxynitride layer, a hydrogenated silicon oxynitride layer, a silicon carbide layer, a molybdenum oxide layer, a chromium oxide layer, and a thallium oxide layer.

9. The solar cell according to any one of claims 1 to 3, characterized in that: The first electrode layer is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, Cd, and Ti, or a corresponding number of stacked electrodes composed of multiple stacked layers; And / or, the second electrode layer is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, Cd, and Ti, or a corresponding number of stacked electrodes composed of multiple stacked layers.

10. The solar cell according to claim 3, characterized in that: The first electrode layer is a laminated electrode composed of Ti, Al and Ni layers or a laminated electrode composed of Al and Ni layers; And / or, the second electrode layer is a laminated electrode consisting of Ti, Al and Ni laminated layers or a laminated electrode consisting of Al and Ni laminated layers.

11. The solar cell according to any one of claims 1 to 3, characterized in that: The solar cell further includes a passivation layer and an anti-reflection layer which are sequentially arranged on the second surface along a direction from the first surface to the second surface.

12. A solar cell module, characterized in that: Comprising the solar cell according to any one of claims 1 to 11.

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