A solar cell and its component

Abstract

The utility model discloses a solar cell and a component thereof. The solar cell comprises: a substrate, a first surface of which is provided with a first doping region, a second doping region and an isolation region; a first passivation layer, arranged on the first surface; a first doped amorphous silicon layer, arranged on the first passivation layer corresponding to the first doping region; a second doped amorphous silicon layer, arranged on the first passivation layer corresponding to the second doping region, and the first doped amorphous silicon layer and the second doped amorphous silicon layer have different doping types; a tunneling layer, at least covering the first doped amorphous silicon layer and the second doped amorphous silicon layer; a first electrode layer, arranged on the tunneling layer corresponding to the first doping region, and the projection area of ​​the first electrode layer on the substrate accounts for 90% to 100% of the projection area of ​​the first doping region; and a second electrode layer, arranged on the tunneling layer corresponding to the second doping region, and the projection area of ​​the second electrode layer on the substrate accounts for 90% to 100% of the projection area of ​​the second doping region.

Description

Technical Field

[0001] The utility model relates to the technical field of photovoltaics, in particular to a solar cell and a component thereof. Background Art

[0002] Back contact (BC) solar cells refer to cells with emitter and metal contact on the back of the cell, and no metal electrode blocking the front. Compared with cells with blocked front, back contact cells have higher short-circuit current and photoelectric conversion efficiency. Heterojunction back contact (HBC) solar cells have the advantages of both heterojunction (Heterojunction Technology) and back contact (BC) cells, and can obtain high open circuit voltage and large short circuit current. Its development potential has been proven, and it is one of the future development directions of high-efficiency solar cells. The back of the HBC cell usually includes a passivation layer, a doped amorphous silicon layer, a transparent conductive film layer (Transparent Conductive Oxide, TCO layer) and a metal electrode layer stacked on a crystalline silicon substrate.

[0003] Although the TCO layer has an extremely low resistivity and the technology is quite mature, the work function of the TCO layer is low (the work function is 4.5-4.8eV), and the work function of the TCO layer is quite different from that of the doped amorphous silicon layer (work function>5eV). If the TCO layer is in direct contact with the doped amorphous silicon layer, an interface barrier will be generated, which is not conducive to the transmission and extraction of electrons and holes, and affects the improvement of battery conversion efficiency. Utility Model Content

[0004] The utility model aims to provide a solar cell to improve the cell conversion efficiency.

[0005] In a first aspect, the utility model provides a solar cell, comprising:

[0006] A substrate, wherein the substrate has a first surface and a second surface opposite to each other, wherein the first surface has first doping regions and second doping regions arranged alternately, and an isolation region for spacing the first doping regions and the second doping regions;

[0007] A first passivation layer, disposed on the first surface;

[0008] A first doped amorphous silicon layer is disposed in a region of the first passivation layer corresponding to the first doped region;

[0009] A second doped amorphous silicon layer is disposed in a region of the first passivation layer corresponding to the second doped region, and the first doped amorphous silicon layer and the second doped amorphous silicon layer have different doping types;

[0010] A tunneling layer at least covering the first doped amorphous silicon layer and the second doped amorphous silicon layer;

[0011] A first electrode layer is disposed in a region of the tunneling layer corresponding to the first doping region, wherein a projection area of ​​the first electrode layer on the substrate accounts for 90% to 100% of a projection area of ​​the first doping region on the substrate;

[0012] The second electrode layer is arranged in a region of the tunneling layer corresponding to the second doping region, and a projection area of ​​the second electrode layer on the substrate accounts for 90% to 100% of a projection area of ​​the second doping region on the substrate.

[0013] In the case of adopting the above technical solution, compared with the back of the HBC battery in the prior art, which usually includes a passivation layer, a doped amorphous silicon layer, a TCO layer and a metal electrode layer stacked on a crystalline silicon substrate, a tunneling layer is arranged between the first doped amorphous silicon layer and the first electrode layer on the back of the HBC battery in the present application, and a tunneling layer is arranged between the second doped amorphous silicon layer and the second electrode layer, that is, the existing TCO layer is replaced by the tunneling layer. Since the tunneling layer has a unidirectional carrier transmission capability, the first electrode layer can be in contact with the first doped amorphous silicon layer through the tunneling layer, and the second electrode layer can be in contact with the second doped amorphous silicon layer through the tunneling layer, ensuring good conductivity. In addition, due to the presence of the tunneling layer, the electrode layer can be prevented from diffusing into the doped amorphous silicon layer, causing serious recombination. At the same time, the difference in work function between the tunneling layer and the doped amorphous silicon layer is smaller than the difference in work function between the TCO layer and the doped amorphous silicon layer. When the tunneling layer contacts the doped amorphous silicon layer, the interface barrier height can be reduced, so that electrons can easily pass through the barrier, thereby improving the conversion efficiency. In addition, the tunneling layer replaces the TCO layer to contact the doped amorphous silicon layer, avoiding damage to the doped amorphous silicon layer caused by high temperature conditions and crystallization of the TCO layer when preparing the TCO layer. And by increasing the projected area of ​​the first electrode layer and the second electrode layer on the substrate, that is, the back of the solar cell can be provided with a wider electrode, reducing the series resistance Rs, reducing the resistivity, thereby increasing the filling factor FF, further improving the photoelectric conversion efficiency, and increasing the contact area between the electrode layer and the tunneling layer, and improving the bonding force between the electrode and the tunneling layer. And the thickness of the electrode layer can be reduced while meeting the conductivity requirements, effectively preventing the electrode from tipping over or deforming. And thinner electrodes can shorten the preparation time and improve the efficiency of electrode preparation.

[0014] In some possible implementations, the thickness of the first electrode layer and / or the second electrode layer at any position is 0.5 μm-31 μm.

[0015] In some possible implementations, the tunneling layer covers the first doped amorphous silicon layer, the second doped amorphous silicon layer, and a region of the first passivation layer corresponding to the isolation region.

[0016] In some possible implementations, the solar cell further includes a first conductive layer and a second conductive layer; the first conductive layer is disposed in an area of ​​the tunneling layer corresponding to the first doping region, and the first electrode layer is disposed in the first conductive layer; the second conductive layer is disposed in an area of ​​the tunneling layer corresponding to the second doping region, and the second electrode layer is disposed in the second conductive layer.

[0017] In some possible implementations, the first conductive layer is a transparent conductive oxide layer or a metal conductive layer;

[0018] And / or, the second conductive layer is a transparent conductive oxide layer or a metal conductive layer.

[0019] In some possible implementations, the transparent conductive oxide layer is a stack of one or more layers selected from the group consisting of an ITO layer, a FTO layer, an AZO layer, an ICO layer, an IWO layer, and a TiO2 layer.

[0020] And / or, the metal conductive layer is a laminate of one or more of an aluminum metal film, a nickel metal film, a chromium metal film, and a titanium alloy metal film.

[0021] In some possible implementations, the thickness of the first conductive layer is 5 nm to 200 nm;

[0022] And / or, the thickness of the second conductive layer is 5 nm to 200 nm.

[0023] In some possible implementations, the thickness of the tunneling layer is less than or equal to 5 nm;

[0024] In some possible implementations, the thickness of the tunneling layer is less than or equal to 2.5 nm.

[0025] In some possible implementations, the tunneling layer is a single-layer film composed of one of silicon oxide, hydrogenated silicon oxide, silicon nitride, hydrogenated silicon nitride, aluminum oxide, silicon oxynitride, hydrogenated silicon oxynitride, silicon carbide, molybdenum oxide, chromium oxide, and thallium oxide, or a corresponding number of stacked films composed of multiple types;

[0026] In some possible implementations, the first electrode layer is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, Cd, and Ti, or a corresponding number of stacked electrodes composed of multiple stacks;

[0027] And / or, the second electrode layer is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, Cd, and Ti, or a corresponding number of stacked electrodes composed of multiple stacked layers.

[0028] In some possible implementations, the solar cell further includes:

[0029] A second passivation layer, disposed on the second surface;

[0030] The third doped amorphous silicon layer is disposed on the second passivation layer, and the third doped amorphous silicon layer has the same doping type as the first doped amorphous silicon layer.

[0031] In some possible implementations, the solar cell further includes an anti-reflection layer disposed on the third doped amorphous silicon layer.

[0032] In some possible implementations, the first passivation layer is a first intrinsic amorphous silicon layer or a first tunneling layer;

[0033] And / or, the second passivation layer is a second intrinsic amorphous silicon layer or a second tunneling layer.

[0034] In a second aspect, the utility model further provides a solar cell assembly, comprising a solar cell as described in any one of the above items.

[0035] The solar cell assembly has the same beneficial effects as the solar cell of the first aspect, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation on the present invention. In the drawings:

[0037] Figure 1 A schematic diagram of the structure of a solar cell provided by an embodiment of the utility model;

[0038] Figure 2 A schematic diagram of the structure of another solar cell provided by an embodiment of the utility model;

[0039] Figure 3 A schematic diagram of the structure of a third solar cell provided by an embodiment of the utility model;

[0040] Figure 4 This is a schematic structural diagram of a fourth solar cell provided in an embodiment of the utility model.

[0041] Reference numerals:

[0042] 10-substrate, 101-first doping region,

[0043] 102 - second doping region, 103 - isolation region,

[0044] 11-a first passivation layer, 12-a first doped amorphous silicon layer,

[0045] 13- tunneling layer, 14- first electrode layer,

[0046] 15-a second passivation layer, 16-a third doped amorphous silicon layer,

[0047] 17-anti-reflection layer, 18-second doped amorphous silicon layer,

[0048] 19- second electrode layer, 20- first conductive layer,

[0049] 21-Second conductive layer. DETAILED DESCRIPTION

[0050] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0051] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0053] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0054] In the description of the present utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0055] Currently, the back side of an HBC battery generally includes a passivation layer, a doped amorphous silicon layer, a transparent conductive film layer (Transparent Conductive Oxide, TCO layer) and a metal electrode layer stacked on a crystalline silicon substrate.

[0056] Although the TCO layer has an extremely low resistivity and the technology is quite mature, the work function of the TCO layer is low (the work function is 4.5-4.8eV), and the work function of the TCO layer is quite different from that of the doped amorphous silicon layer (work function>5eV). If the TCO layer is in direct contact with the doped amorphous silicon layer, an interface barrier will be generated, which is not conducive to the transmission and extraction of electrons and holes, and affects the improvement of battery conversion efficiency.

[0057] In view of this, if Figure 1As shown, the utility model provides a solar cell, including a substrate 10, a first passivation layer 11, a first doped amorphous silicon layer 12, a second doped amorphous silicon layer 18, a tunneling layer 13, a first electrode layer 14 and a second electrode layer 19; wherein the substrate 10 has a first surface and a second surface opposite to each other, and for the solar cell, the first surface is a backlight surface, and the second surface is a light-facing surface, and the first surface has staggered first doping regions 101 and second doping regions 102, and an isolation region 103 for spacing the first doping regions 101 and the second doping regions 102. The first passivation layer 11 is disposed on the first surface of the substrate 10, i.e., the backlight surface, and the first passivation layer 11 covers the first doped region 101, the second doped region 102, and the isolation region 103; the first doped amorphous silicon layer 12 is disposed in the region of the first passivation layer 11 corresponding to the first doped region 101; the second doped amorphous silicon layer 18 is disposed in the region of the first passivation layer 11 corresponding to the second doped region 102, and the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18 have different doping types; the tunneling layer 13 at least covers the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18; The silicon layer 12 and the second doped amorphous silicon layer 18; the first electrode layer 14 is arranged in the area of ​​the tunneling layer 13 corresponding to the first doping region 101, and the projection area of ​​the first electrode layer 14 on the substrate 10 accounts for 90% to 100% of the projection area of ​​the first doping region 101 on the substrate 10; the second electrode layer 19 is arranged in the area of ​​the tunneling layer 13 corresponding to the second doping region 102, and the projection area of ​​the second electrode layer 19 on the substrate 10 accounts for 90% to 100% of the projection area of ​​the second doping region 102 on the substrate 10.

[0058] When the above technical solution is adopted, compared with the HBC battery in the prior art, which usually includes a passivation layer, a doped amorphous silicon layer, a TCO layer and a metal electrode layer stacked on a crystalline silicon substrate, a tunneling layer 13 is arranged between the first doped amorphous silicon layer 12 and the first electrode layer 14 on the back of the HBC battery in the present application, and a tunneling layer 13 is arranged between the second doped amorphous silicon layer 18 and the second electrode layer 19, that is, the existing TCO layer is replaced by the tunneling layer 13. Since the tunneling layer 13 has a unidirectional carrier transmission capability, the first electrode layer 14 can achieve contact with the first doped amorphous silicon layer 12 through the tunneling layer 13, and the second electrode layer 19 can achieve contact with the second doped amorphous silicon layer 18 through the tunneling layer 13, thereby ensuring good conductivity. In addition, due to the presence of the tunneling layer 13, the electrode layer can be prevented from diffusing into the doped amorphous silicon layer, thereby reducing carrier recombination. At the same time, the difference in work function between the tunneling layer 13 and the doped amorphous silicon layer is smaller than the difference in work function between the TCO layer and the doped amorphous silicon layer. When the tunneling layer 13 contacts the doped amorphous silicon layer, the interface barrier height can be reduced, making it easy for electrons to pass through the barrier, thereby improving the conversion efficiency. In addition, the tunneling layer 13 replaces the TCO layer to contact the doped amorphous silicon layer. In addition, the tunneling layer 13 can be formed on the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18 under low-temperature process conditions. Since the preparation temperature is low, the doped amorphous silicon layer will not be damaged. Compared with preparing the TCO layer on the doped amorphous silicon layer, the damage to the doped amorphous silicon layer caused by the high temperature conditions and the crystallization of the TCO layer when preparing the TCO layer is avoided. In addition, the projection area of ​​the first electrode layer 14 accounts for 90% to 100% of the projection area of ​​the first doping region 101, and the projection area of ​​the second electrode layer 19 accounts for 90% to 100% of the projection area of ​​the second doping region 102, that is, a wider and thinner metal grid line can be set on the back of the solar cell, reducing the series resistance Rs, reducing the resistivity, thereby improving the filling factor FF, and further improving the photoelectric conversion efficiency. By increasing the projection area of ​​the first electrode layer 14 and the second electrode layer 19 on the substrate 10, the contact area between the electrode layer and the tunneling layer is increased, and the bonding force between the electrode and the tunneling layer is improved. And the thickness of the electrode layer can be reduced while meeting the conductivity requirements, effectively preventing the electrode from tipping over or deforming. And thinner electrodes can shorten the preparation time and improve the efficiency of electrode preparation.

[0059] In some possible implementations, the thickness of any position of the first electrode layer 14 and / or the second electrode layer 19 is 0.5 μm-31 μm, specifically, the thickness of any position of the first electrode layer 14 and / or the second electrode layer 19 may be 0.5 μm, 1 μm, 2 μm, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 31 μm, etc. In the case where the first electrode layer 14 and the second electrode layer 19 meet the conductivity requirements, when the electrode width is wide, the thickness of the electrode layer can be reduced, effectively preventing the electrode from tipping over or deforming, and reducing the electrode preparation time and improving the electrode preparation efficiency.

[0060] In some embodiments, a second passivation layer 15 and a third doped amorphous silicon layer 16 are sequentially arranged from the inside to the outside on the second surface of the substrate 10, that is, the light-facing surface, that is, the second passivation layer 15 is arranged on the second surface, and the third doped amorphous silicon layer 16 is arranged on the second passivation layer 15. The third doped amorphous silicon layer 16 has the same doping type as the first doped amorphous silicon layer 12. By arranging the second passivation layer 15 and the third doped amorphous silicon layer 16 on the second surface, the photoelectric conversion efficiency of the second surface is further improved.

[0061] In practical applications, the substrate 10 is a semiconductor substrate. The material of the substrate 10 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the substrate 10 can be an intrinsic conductive substrate, an N-type conductive substrate or a P-type conductive substrate. Preferably, the substrate 10 is a P-type conductive substrate or an N-type conductive substrate. Compared with the intrinsic conductive substrate, the P-type conductive substrate or the N-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0062] The materials of the first doped amorphous silicon layer 12, the second doped amorphous silicon layer 18 and the third doped amorphous silicon layer 16 can be silicon (Si), germanium (Ge), silicon carbide (SiC x ) or gallium arsenide (GaAs), etc. In terms of conductivity type, the third doped amorphous silicon layer 16 and the first doped amorphous silicon layer 12 have the same doping type, which can be one of a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer, and the second doped amorphous silicon layer 18 has a doping type different from that of the third doped amorphous silicon layer 16 and the first doped amorphous silicon layer 12, which can be the other of an N-type doped amorphous silicon layer and a P-type doped amorphous silicon layer.

[0063] In some examples, when the substrate 10 is an N-type conductive substrate, the third doped amorphous silicon layer 16 is a P-type doped amorphous silicon layer, the first doped region 101 can be a P-type doped region, and the corresponding first doped amorphous silicon layer 12 is a P-type doped amorphous silicon layer, the second doped region 102 is an N-type doped region, and the corresponding second doped amorphous silicon layer 18 is an N-type doped amorphous silicon layer; or, the first doped region 101 can be an N-type doped region, and the corresponding first doped amorphous silicon layer 12 is an N-type doped amorphous silicon layer, the second doped region 102 is a P-type doped region, and the corresponding second doped amorphous silicon layer 18 is a P-type doped amorphous silicon layer.

[0064] like Figure 2 As shown, further, in some embodiments, the tunneling layer 13 covers the first doped amorphous silicon layer 12, the second doped amorphous silicon layer 18, and the region of the first passivation layer 11 corresponding to the isolation region 103. That is, the tunneling layer 13 is a whole layer and can be prepared and formed in the same process, so that the insulation between the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18 can be better guaranteed.

[0065] like Figure 3 and 4 As shown, this embodiment provides another solar cell. Figure 1 and Figure 2 Based on the structure shown, the solar cell further includes a first conductive layer 20 and a second conductive layer 21; the first conductive layer 20 is disposed in a region of the tunneling layer 13 corresponding to the first doping region 101, and the first electrode layer 14 is disposed in the first conductive layer 20; the second conductive layer 21 is disposed in a region of the tunneling layer 13 corresponding to the second doping region 102, and the second electrode layer 19 is disposed in the second conductive layer 21. The conductive properties of the doped amorphous silicon layer and the first electrode layer 14 and the second electrode layer 19 can be further improved by the first conductive layer 20 and the second conductive layer 21 having lower resistivity.

[0066] Exemplarily, the first conductive layer 20 is a transparent conductive oxide layer or a metal conductive layer; and / or, the second conductive layer 21 is a transparent conductive oxide layer or a metal conductive layer. The materials of the first conductive layer 20 and the second conductive layer 21 may be the same or different. When the materials of the first conductive layer 20 and the second conductive layer 21 are the same, they may be formed in the same process.

[0067] As an example, the transparent conductive oxide layer can be one or more stacks of an ITO layer, a FTO layer, an AZO layer, an ICO layer, an IWO layer, and a TiO2 layer. It should be noted that the multiple stacks are only physically stacked, and there is no chemical reaction. When the first conductive layer 20 and the second conductive layer 21 are both transparent conductive oxide layers, since the work function of the transparent conductive oxide layer is relatively low, for example, the work function of the ITO layer is 4.5 to 4.8 eV, the work function of the transparent conductive oxide layer is quite different from that of the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18 (work function>5 eV). If the transparent conductive oxide layer is in direct contact with the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18, an interface barrier will be generated, which is not conducive to the transmission and extraction of electrons and holes, and affects the improvement of the battery conversion efficiency. Therefore, the present application is in the transparent conductive oxide layer. A tunneling layer 13 is disposed between the transparent conductive oxide layer and the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18. Since the work function of the tunneling layer 13 is between that of the first doped amorphous silicon layer 12 and the transparent conductive oxide layer and between that of the second doped amorphous silicon layer 18 and the transparent conductive oxide layer, that is, the work function difference between the tunneling layer 13 and the transparent conductive oxide layer is small, and the work function difference between the tunneling layer 13 and the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18 is also small, the interface barrier height can be reduced, and electrons can easily pass through the barrier, thereby improving the conversion efficiency. In addition, the refractive index of the tunneling layer 13 is less than 2.0, preferably 1 to 1.5, and more preferably 1.0, because, from the perspective of light management, long-wave light passing through the substrate 10 enters the first conductive layer 20 and the second conductive layer 21 (refractive index 1.6 to 2.0) from the doped amorphous silicon layer (refractive index 3.0 to 4.0), and total reflection occurs when the incident angle reaches a certain angle. Inserting a tunneling layer 13 with a low refractive index (such as SiOx refractive index 1.18 to 1.44) in the doped amorphous silicon layer and the conductive layer is conducive to suppressing the transmission of light, increasing the total reflection probability of light on the back and the effective optical path of light on the substrate, and improving the short-circuit current of the battery. In addition, in the case of providing the tunneling layer 13, when the first conductive layer 20 and the second conductive layer 21 are subsequently prepared, the tunneling layer 13 can protect the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18.

[0068] As another example, the metal conductive layer can be one or more stacks of aluminum metal film, nickel metal film, chromium metal film, titanium alloy metal film. It should be noted that the multiple stacked metal conductive layers are only physical stacks and there is no chemical reaction between the layers.

[0069] In this embodiment, the thickness of the first conductive layer 20 and the second conductive layer 21 may be the same or different, and the thickness may be 5nm to 200nm, specifically 5nm, 10nm, 20nm, 50nm, 100nm, 130nm, 150nm, 180nm, 200nm, etc.

[0070] like Figure 1-Figure 4 As shown, in some possible implementations, the thickness of the tunneling layer 13 is less than or equal to 5 nm, specifically, the thickness of the tunneling layer 13 is less than or equal to 2.5 nm, further, the thickness of the tunneling layer 13 is less than or equal to 2 nm, and further, the thickness of the tunneling layer 13 is less than or equal to 1.5 nm. The thickness of the tunneling layer 13 is extremely thin. A tunneling layer 13 is arranged between the first doped amorphous silicon layer 12 and the first electrode layer 14 and between the second doped amorphous silicon layer 18 and the second electrode layer 19. Since the thickness of the tunneling layer 13 is extremely thin, selective transmission of carriers can be achieved through the tunneling principle, that is, one carrier can pass through the tunneling layer 13, while the other carrier is difficult to tunnel through the tunneling layer 13 due to the existence of potential barriers and field effects in the doped area, thereby reducing interface recombination. Moreover, since the thickness of the tunneling layer 13 is very thin, contact between the doped amorphous silicon layer and the electrode layer can also be achieved, that is, not only can the interface recombination be significantly reduced, but also the contact between the doped amorphous silicon layer and the electrode layer can be ensured, so that the solar cell has a higher open circuit voltage and short circuit current, thereby increasing the photoelectric conversion efficiency. In the case of setting the first conductive layer 20 and the second conductive layer 21, the extremely thin tunneling layer 13 can protect the first doped amorphous silicon layer 12 and the second doped amorphous silicon layer 18 when preparing the first conductive layer 20 and the second conductive layer 21. In addition, since the work function of the tunneling layer 13 is between the doped amorphous silicon layer and the conductive layer, the interface barrier is reduced, which is beneficial to the transition of electron holes, and thus the conversion efficiency can be improved. Furthermore, the tunneling layer has a low refractive index, which is beneficial to suppressing the transmission of light, increasing the probability of total reflection of light on the back side and the effective optical path of light in the substrate, and improving the short-circuit current of the battery.

[0071] In some embodiments, the tunneling layer 13 may be a single-layer film composed of one of silicon oxide, hydrogenated silicon oxide, silicon nitride, hydrogenated silicon nitride, aluminum oxide, silicon oxynitride, hydrogenated silicon oxynitride, silicon carbide, molybdenum oxide, chromium oxide, and thallium oxide, or a corresponding number of stacked films composed of multiple materials. It should be noted that the stacked film is composed of a physical stack of film layers of multiple different materials, and the material of each film layer is a single material, and there is no mixing and chemical reaction combination between adjacent film layers. Of course, the tunneling layer 13 can also be formed by mixing multiple materials into one layer.

[0072] For example, when the tunneling layer 13 is a laminated film composed of multiple materials, the tunneling layer 13 includes an Al2O3 layer and a SiO2 layer stacked in a direction from the second surface to the first surface. Compared with a single-layer Al2O3 layer or SiO2 layer, the laminated tunneling layer can provide sufficiently good passivation performance. Of course, the tunneling layer 13 can also be made of other materials and structural forms, and is not limited to the form described in this embodiment.

[0073] In practical applications, the tunneling layer 13 can be prepared by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition, etc. In one example, the tunneling layer 13 can be formed by physical vapor deposition (such as evaporation or sputtering) under low temperature conditions, and after the tunneling layer 13 is prepared in the same process, metal can be deposited to form a metal electrode, that is, the first electrode layer 14 and the second electrode layer 19, so that the process steps and preparation flow can be reduced.

[0074] In some embodiments, the first electrode layer 14 is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, Cd, and Ti, or a corresponding number of stacked electrodes composed of multiple stacked layers. It should be noted that the stacked electrode is composed of a physical stack of electrode film layers of multiple different materials, and the material of each electrode film layer is a single material, and there is no mixing and chemical reaction combination between adjacent electrode film layers. Of course, the first electrode layer 14 can also be an alloy composed of multiple materials. The first electrode layer 14 can be a metal grid line, and the metal grid line can include a main grid and a fine grid, or only a fine grid.

[0075] Similarly, the structure of the second electrode layer 19 refers to the structure of the first electrode layer 14, which will not be described in detail. In addition, the second electrode layer 19 and the first electrode layer 14 can be made of the same or different materials. When the materials are the same, they can be prepared in the same process to simplify the process.

[0076] For example, when the first electrode layer 14 and the second electrode layer 19 are a stacked electrode, the first electrode layer 14 can be a stacked electrode composed of Ti, Al and Ni stacked in sequence, and the Ti layer in the first electrode layer 14 is in contact with the tunneling layer 13. When a transparent conductive oxide layer is provided, the Ti layer is in contact with the transparent conductive oxide layer. The thickness of the Ti layer can be 0nm-50nm, the thickness of the Al layer can be 0.5μm-30μm, and the thickness of the Ni layer can be 20nm-500nm.

[0077] Alternatively, the first electrode layer 14 is a laminated electrode composed of Al and Ni laminated in sequence, the Al layer in the first electrode layer 14 contacts the tunneling layer 13, and when a transparent conductive oxide layer is provided, the Al layer contacts the transparent conductive oxide layer.

[0078] Similarly, the second electrode layer 19 may be a laminated electrode composed of Ti, Al and Ni or a laminated electrode composed of Al and Ni. The same may be said for the first electrode layer 14 and will not be described in detail.

[0079] The first electrode layer 14 and the second electrode layer 19 adopt a multi-layer metal stack, which expands the selection range of the electrode, and can select a metal with good conductive contact with the tunneling layer 13 or the transparent conductive oxide layer as the first layer of the electrode, select a metal with low cost as the main material of the electrode, select a metal with good welding performance as the outermost layer of the electrode, and improve the conductive efficiency of the electrode by stacking multiple metal layers.

[0080] In practical applications, the first electrode layer 14 and / or the second electrode layer 19 can be prepared by screen printing, physical vapor deposition, electroplating, etc., and the present application does not make specific limitations. A low-temperature process can be used to prepare them directly on the tunneling layer 13. The first electrode layer 14 and the first doped amorphous silicon layer 12 and the second electrode layer 19 and the second doped amorphous silicon layer 18 can be contacted through the tunneling layer 13. The same process as the tunneling layer 13 can be used to prepare them, which simplifies the process.

[0081] like Figure 1-Figure 4 As shown, in some possible implementations, based on the cell structure described in any of the above embodiments, the solar cell further includes an anti-reflection layer 17, and the anti-reflection layer 17 is disposed on the third doped amorphous silicon layer 16. The anti-reflection layer 17 is disposed to reduce reflection of light incident on the second surface, improve refraction of light, increase utilization of light incident on the second surface, and thus improve the photoelectric conversion efficiency of the solar cell.

[0082] Exemplarily, the anti-reflection layer 17 can be a single-layer anti-reflection structure composed of one of silicon nitride, silicon oxynitride, silicon oxide, and a transparent conductive layer, or a corresponding number of stacked anti-reflection structures composed of multiple stacked layers. It should be noted that the material of each layer of the stacked anti-reflection structure is a single material, and the adjacent layer structures are only physically stacked, and there is no mixing or chemical reaction combination. Of course, the anti-reflection layer 17 can also be a layer of anti-reflection structure mixed with multiple materials. The process for forming the anti-reflection layer 17 can be a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process, a physical vapor deposition (PVD) process, a low pressure chemical vapor deposition (LPCVD) process or a catalytic chemical vapor deposition process, etc., which is not limited here.

[0083] In some possible implementations, the first passivation layer 11 is a first intrinsic amorphous silicon layer or a first tunneling layer; and / or, the second passivation layer 15 is a second intrinsic amorphous silicon layer or a second tunneling layer, and the materials of the second passivation layer 15 and the first passivation layer 11 may be the same or different, and this application does not make specific limitations. The process for forming the second passivation layer 15 and the first passivation layer 11 may be a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process, a physical vapor deposition (PVD) process, a low pressure chemical vapor deposition (LPCVD) process, or a catalytic chemical vapor deposition process, etc., and is not limited here.

[0084] Based on the solar cell described in any one of the above embodiments, an embodiment of the utility model further provides a solar cell assembly, comprising the solar cell described in any one of the above embodiments.

[0085] The solar cell assembly has the same beneficial effects as the solar cell described in any of the above embodiments, which will not be described in detail here.

[0086] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0087] The above is only a specific implementation of the utility model, but the protection scope of the utility model is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the utility model, which should be included in the protection scope of the utility model. Therefore, the protection scope of the utility model should be based on the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A substrate, wherein the substrate has a first surface and a second surface opposite to each other, wherein the first surface has first doping regions and second doping regions arranged alternately, and an isolation region for spacing the first doping regions and the second doping regions; A first passivation layer, disposed on the first surface; A first doped amorphous silicon layer is disposed in a region of the first passivation layer corresponding to the first doped region; A second doped amorphous silicon layer is disposed in a region of the first passivation layer corresponding to the second doped region, and the first doped amorphous silicon layer and the second doped amorphous silicon layer have different doping types; A tunneling layer at least covering the first doped amorphous silicon layer and the second doped amorphous silicon layer; A first electrode layer is disposed in a region of the tunneling layer corresponding to the first doping region, wherein a projection area of ​​the first electrode layer on the substrate accounts for 90% to 100% of a projection area of ​​the first doping region on the substrate; The second electrode layer is arranged in a region of the tunneling layer corresponding to the second doping region, and a projection area of ​​the second electrode layer on the substrate accounts for 90% to 100% of a projection area of ​​the second doping region on the substrate.

2. The solar cell according to claim 1, characterized in that The thickness of the first electrode layer and / or the second electrode layer at any position is 0.5 μm-31 μm.

3. The solar cell according to claim 1, characterized in that The tunneling layer covers the first doped amorphous silicon layer, the second doped amorphous silicon layer, and a region of the first passivation layer corresponding to the isolation region.

4. The solar cell according to claim 1, characterized in that It also includes a first conductive layer and a second conductive layer; the first conductive layer is arranged in an area of ​​the tunneling layer corresponding to the first doping region, and the first electrode layer is arranged in the first conductive layer; the second conductive layer is arranged in an area of ​​the tunneling layer corresponding to the second doping region, and the second electrode layer is arranged in the second conductive layer.

5. The solar cell according to claim 4, characterized in that: The first conductive layer is a transparent conductive oxide layer or a metal conductive layer; And / or, the second conductive layer is a transparent conductive oxide layer or a metal conductive layer.

6. The solar cell according to claim 5, characterized in that: The transparent conductive oxide layer is one or more stacked layers of an ITO layer, a FTO layer, an AZO layer, an ICO layer, an IWO layer, and a TiO2 layer; And / or, the metal conductive layer is a laminate of one or more of an aluminum metal film, a nickel metal film, a chromium metal film, and a titanium alloy metal film.

7. The solar cell according to claim 4, characterized in that: The thickness of the first conductive layer is 5 nm to 200 nm; And / or, the thickness of the second conductive layer is 5 nm to 200 nm.

8. The solar cell according to any one of claims 1 to 7, characterized in that: The thickness of the tunneling layer is less than or equal to 5 nm.

9. The solar cell according to claim 8, characterized in that The thickness of the tunneling layer is less than or equal to 2.5 nm.

10. The solar cell according to any one of claims 1 to 7, characterized in that: The tunneling layer is a single layer film composed of one of silicon oxide, hydrogenated silicon oxide, silicon nitride, hydrogenated silicon nitride, aluminum oxide, silicon oxynitride, hydrogenated silicon oxynitride, silicon carbide, molybdenum oxide, chromium oxide, and thallium oxide, or a corresponding number of stacked films composed of multiple materials.

11. The solar cell according to any one of claims 1 to 7, characterized in that: The first electrode layer is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, Cd, and Ti, or a corresponding number of stacked electrodes composed of multiple stacked layers; And / or, the second electrode layer is a single-layer electrode composed of one of Al, Ni, Cu, Ag, Au, Cr, Pb, Sn, In, Bi, Zn, Co, Cd, and Ti, or a corresponding number of stacked electrodes composed of multiple stacked layers.

12. The solar cell according to any one of claims 1 to 7, characterized in that: Also includes: A second passivation layer, disposed on the second surface; The third doped amorphous silicon layer is disposed on the second passivation layer, and the third doped amorphous silicon layer has the same doping type as the first doped amorphous silicon layer.

13. The solar cell according to claim 12, characterized in that: It also includes an anti-reflection layer, which is arranged on the third doped amorphous silicon layer.

14. The solar cell according to claim 12, characterized in that: The first passivation layer is a first intrinsic amorphous silicon layer or a first tunneling layer; And / or, the second passivation layer is a second intrinsic amorphous silicon layer or a second tunneling layer.

15. A solar cell module, characterized in that: Comprising the solar cell according to any one of claims 1 to 14.

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