Solar cells and photovoltaic modules

Abstract

A solar cell includes a silicon substrate and a plurality of grid lines. The silicon substrate includes a first surface and a second surface relative to each other. A plurality of grid lines are arranged on at least one of the first surface and the second surface. The plurality of grid lines extend along a first direction and are arranged at intervals along a second direction, and the first direction intersects the second direction. Each grid line has a height along the thickness direction of the silicon substrate. Along the second direction, the silicon substrate includes two side regions that are relative and spaced apart, the height of at least one grid line located in at least one side region is greater than the height of at least one grid line located in the region between the two side regions, and the silicon substrate has a width W along the second direction, and the width of the side region is W / 6. The present application also provides a photovoltaic module including the solar cell. The present application improves the performance of the solar cell by specially designing the height and / or width of the grid lines.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and more specifically, to a solar cell and a photovoltaic module including the solar cell. Background Art

[0002] A solar cell includes a silicon substrate, a functional layer formed on the surface of the silicon substrate, and a gate electrode located on the functional layer. The gate electrode is used to collect photogenerated carriers generated on the surface of the solar cell. The shape of the gate electrode will affect the degree of light shielding and light reflection of the gate electrode. The cross-sectional area of ​​the gate electrode will also affect the resistance of the gate electrode and thus affect the current collection. Different positions of the cell have different requirements for current collection and the degree of light shielding of the gate electrode. Differentiated settings according to different requirements of different positions can effectively improve the performance of the solar cell. Utility Model Content

[0003] In view of this, the present application provides a solar cell, comprising:

[0004] A silicon substrate including a first surface and a second surface opposite to each other;

[0005] a plurality of gate lines, arranged on at least one of the first surface and the second surface, the plurality of gate lines extending along a first direction and arranged at intervals along a second direction, the first direction intersecting the second direction, the gate lines having a height along a thickness direction of the silicon substrate,

[0006] Along the second direction, the silicon substrate includes two opposite and spaced side regions, the height of at least one gate line located in at least one of the side regions is greater than the height of at least one gate line located in the area between the two side regions, and the silicon substrate has a width W along the second direction, and the width of the side region is W / 6.

[0007] The present application specially designs the height and / or width of the gate lines in the side areas and the middle area of ​​the silicon substrate. The gate lines in the side areas are high in height, which improves the carrier collection and transmission capabilities of the side areas, and improves the light reflection capability of the gate lines, so that more light can be reflected to the center area of ​​the cell; the gate lines in the middle area are low in height, which avoids shading in the middle area, improves light absorption in the middle area, and improves the photoelectric conversion efficiency in the middle area, thereby improving the overall performance of the solar cell.

[0008] In some embodiments, an average height of the gate lines located in at least one of the side regions is greater than an average height of the gate lines located in a region between two of the side regions.

[0009] In some embodiments, the height of any gate line located in at least one of the side regions is greater than the height of any gate line located in a region between two of the side regions.

[0010] In some embodiments, the height of at least one gate line in the two side regions is greater than the height of at least one gate line in the region between the two side regions.

[0011] In some embodiments, the gate lines have a width along the second direction, the widths of the same collinear region of the plurality of gate lines extending along the second direction are substantially consistent, and the difference between any two widths does not exceed 1 μm.

[0012] In some embodiments, the height of the same gate line along the thickness direction of the silicon substrate remains substantially consistent, and the height difference between any two points on the same gate line does not exceed 1.5 μm.

[0013] In some embodiments, the gate line has a width along the second direction, the width of the same gate line along the second direction remains substantially consistent, and the difference in width between any two points on the same gate line does not exceed 2 μm.

[0014] In some embodiments, along the first direction, a ratio of the height to the width of the gate lines located in the side region is greater than a ratio of the height to the width of the gate lines in the region between the two side regions.

[0015] In some embodiments, the ratio of the height to the width of the gate line is greater than 45%, or the ratio of the height to the width of the gate line is greater than 50%.

[0016] In some embodiments, along the first direction, the width of the middle region of the gate line is greater than the width of other regions of the gate line, the gate line has a length L along the first direction, the middle region of the gate line refers to a region extending L / 18 from the center point of the gate line along the first direction toward the upper edge and the lower edge of the silicon substrate respectively, and the upper edge and the lower edge of the silicon substrate are relatively spaced along the first direction.

[0017] In some embodiments, the gate line has a width ranging from 19.5 μm to 25 μm.

[0018] In some embodiments, the height of the gate line is in the range of 9-13 μm.

[0019] In some embodiments, the gate line includes a plurality of sub-gate line segments arranged along a first direction.

[0020] In some embodiments, a plurality of the sub-gate line segments arranged in the same row along the first direction have intervals between adjacent sub-gate line segments.

[0021] In some embodiments, the solar cell further includes a plurality of busbar lines extending along the second direction, the plurality of busbar lines are arranged at intervals along the first direction, and the plurality of busbar lines intersect at least a portion of the sub-grid line segments.

[0022] In some embodiments, a plurality of solder joints are arranged in a row along the first direction and spaced apart from each other. At least one solder joint is arranged on one gate line, and each solder joint is electrically connected to at least a portion of the sub-gate line segments.

[0023] In some embodiments, the sub-gate line segment has a width along the second direction, and in the same gate line, the widths of the middle sections of adjacent sub-gate line segments along the second direction are substantially consistent, and the difference in widths between any two points of adjacent sub-gate line segments does not exceed 1 μm. The length of the sub-gate line segment along the first direction is d, and the middle section of the sub-gate line segment is a portion extending from the center point of the sub-gate line segment in the first direction to both ends of the first direction by a length of d / 6.

[0024] The present application also provides a photovoltaic assembly, comprising at least one solar cell as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 FIG. 1 is a schematic top view of a solar cell according to an embodiment of the present application.

[0026] Figure 2 It is a schematic diagram of a test grid line of a solar cell according to an embodiment of the present application.

[0027] Figure 3 is a schematic cross-sectional view of a solar cell according to an embodiment of the present application.

[0028] Description of main component symbols:

[0029] Solar cell 100

[0030] Silicon substrate 10

[0031] Grid line 20

[0032] First surface 11

[0033] Width W

[0034] Length L DETAILED DESCRIPTION

[0035] like Figure 1As shown, the present application provides a solar cell 100, including a silicon substrate 10 and a plurality of grid lines 20 formed on the silicon substrate 10. The silicon substrate 10 is in the shape of a thin plate, including a first surface 11 and a second surface (not shown) relative to each other. The first surface and the second surface are the front and back of the silicon substrate. A plurality of grid lines 20 are formed on at least one of the first surface and the second surface. Each grid line 20 extends in a long strip along a first direction. A plurality of grid lines 20 are arranged at intervals along a second direction. The second direction is different from the first direction, and the two intersect. In some embodiments, the second direction is perpendicular to the first direction. Each grid line 20 has a length extending along the first direction, a width extending along the second direction, and a height extending along the thickness direction of the silicon substrate 10.

[0036] The present application improves the performance of solar cells by designing the height and / or width of the grid lines at different positions of the cell. The embodiments of the present application are mainly for solar cells with double-sided electrodes, and the grid line electrodes are arranged on the first surface and the second surface, and the height and / or width of the front grid line are designed for layout, but it is not limited to this, and can also be applied to other solar cells with single-sided electrodes (such as back contact cells) or back grid lines of double-sided electrodes. In some embodiments, the first surface is the front side and the second surface is the back side. It can be understood that the grid lines are not directly formed on the surface of the silicon substrate, and the surface of the silicon substrate is formed with at least one functional layer, such as a passivation layer and / or an anti-reflection layer.

[0037] In this embodiment, the gate line is formed by printing and sintering the slurry. The sintering process is to make the printed gate line form a good contact with the silicon wafer under the action of high temperature, thereby improving the open circuit voltage and fill factor of the solar cell. At the same time, the high temperature in the sintering furnace can promote the H generated during the coating process to diffuse into the battery, which has a good passivation effect on the solar cell and improves the conversion efficiency of the solar cell.

[0038] The paste composition used in the gate line of the present application includes metal particles, inorganic phase and organic phase. Metal particles are the conductive functional phase in the paste, and their sintering quality directly affects the product performance. The inorganic phase is mainly glass powder, which not only has a high-temperature bonding effect, but also serves as a solvent for the sintering of metal particles such as silver powder to form a silver-silicon ohmic contact. The organic phase mainly includes a volatile solvent and a non-volatile phase of resin (mainly phenolic resin and epoxy resin). The organic phase mainly plays a dispersing and wrapping role, and the metal particles, such as silver powder particles, are evenly wrapped, so that the conductive paste is not easy to precipitate.

[0039] The present application also uses reverse current secondary firing (RCSF) technology for auxiliary sintering. After the slurry is printed, it is sintered and then RCSF treatment is performed for auxiliary sintering. Reverse current secondary sintering is a technology that uses high current to pass through small contact points to generate high heat to complete secondary sintering, which is used to optimize the contact between metal electrodes and silicon wafers in solar cells. In the RCSF process, laser irradiation of the grid line area is used to generate photogenerated carriers, and the role of the reverse voltage is to complete the fixed flow direction of electrons in the battery to achieve a larger reverse current. Under this technology, the laser can use the higher heat generated by the current flow to accurately heat the grid line part, while only destroying the passivation layer at the top of the pyramid on the front surface, so that the metal can directly form contact with the silicon, without damaging the silicon substrate, causing the metal slurry to locally melt and diffuse into the surface of the silicon substrate to form a tiny metal silicon alloy junction, which has a very low contact resistance and a very high transmission efficiency for electrons.

[0040] In some embodiments, the slurry used in the RCSF process is silver slurry. By controlling the erosion of the slurry and combining it with the laser post-processing process, the two key steps of passivation layer erosion and contact formation in the silver electrode sintering process are successfully separated, while maintaining the open circuit voltage as high as possible, while reducing the contact resistance. At the same time, the slurry has better printability and ink permeability, which can effectively reduce the line width of the grid line during screen printing, reduce the shading area and increase the current.

[0041] In other embodiments, the gate lines of the present application may also be formed by screen printing, electroplating, and the like.

[0042] In other embodiments, the paste that can be used in the present application can be silver paste, silver aluminum paste, copper paste, silver-coated copper paste, silver-coated aluminum paste, etc.

[0043] like Figure 1As shown, along the second direction, the silicon substrate 10 includes two side regions that are opposite and spaced apart, and the height of at least one gate line 20 located in at least one side region is greater than the height of at least one gate line 20 located in the region between the two side regions. The silicon substrate 10 has a width W along the second direction, and the width of the side region is W / 6. In the present application, the height of the gate line is obtained by measuring the height of the gate line protruding relative to the outermost functional layer (such as the anti-reflection layer) of the silicon substrate using an optical profilometer microscope. The side region of the present application refers to a region extending W / 6 from the first edge of the silicon substrate 10 along the second direction toward the center of the silicon substrate 10, and a region extending W / 6 from the second edge of the silicon substrate 10 along the second direction toward the center of the silicon substrate 10, wherein the first edge and the second edge of the silicon substrate 10 are relatively spaced apart along the second direction. When the number of gate lines 20 in the side region is n, the height of at least one, or two, or three, or four ... or n gate lines 20 located in at least one side region is greater than the height of at least one gate line 20 located in the region between the two side regions. In the present application, the area between the two side areas is usually selected from the grid lines 20 near the center of the battery cell, and the number of the grid lines 20 selected near the center is usually equal to the number of the grid lines 20 selected from the side areas.

[0044] In actual application, the more the number of the gate lines 20 in the side regions whose height is greater than the height of the gate lines 20 located in the region between the two side regions, the better the effect of improving the battery efficiency. In some embodiments, the height of the gate lines 20 located in at least one side region is greater than the height of the gate lines 20 located in the region between the two side regions. In some embodiments, the height of the gate lines 20 located in the two side regions is greater than the height of the gate lines 20 located in the region between the two side regions.

[0045] The average height of the grid lines 20 in the side regions is higher than the average height of the grid lines 20 in the region between the two side regions, which can also improve the carrier collection and transmission capabilities of the side regions and improve the photoelectric conversion efficiency of the middle region, thereby improving the performance of the solar cell as a whole. In some embodiments, the average height of the grid lines 20 located in at least one side region is greater than the average height of the grid lines 20 located in the region between the two side regions. In some embodiments, the average height of the grid lines 20 located in the two side regions is greater than the average height of the grid lines 20 located in the region between the two side regions.

[0046] Usually, in the side region, the distance between the gate line closest to the edge of the silicon substrate and the edge of the silicon substrate is greater than half of the distance between two adjacent gate lines, and the edge of the silicon substrate refers to the edge portion of the silicon substrate extending along the first direction. The gate line located in the side region occupies a larger area for absorbing photons, so increasing the height of the gate line in the side region can make it more effective in collecting and transmitting current.

[0047] Will Figure 1 The silicon substrate 10 shown is divided into nine regions along the second direction. A gate line 20 is selected at the middle position of each region. A total of nine gate lines 20 are selected. Figure 2 As shown. Figure 2 As shown, nine test points spaced apart along the first direction are selected for each gate line 20 to measure the height and width, and the nine test points include the two end points of the gate line 20 along the first direction. Usually, the nine test points are selected with equal spacing along the first direction, and when there is a bus electrode or a solder joint, the connection position between the gate line and the bus electrode or the solder joint is avoided, and the test points can be adjusted according to actual needs.

[0048] Table 1 shows the height results measured at each test point of the nine gate lines 20, and the unit of each parameter is micrometer. According to Table 1, it can be seen that the heights of the gate lines numbered 1, 2, 8, and 9 located in the side regions of the silicon substrate 10 are obviously higher than the heights of the gate lines 20 numbered 3, 4, 5, and 6 located between the two side regions.

[0049] Table 1

[0050]

[0051]

[0052] Figure 3 Schematic diagram of the cross section of the gate line 20 on the surface of the silicon substrate 10. The cross section of each gate line 20 is tower-shaped, and the gate line 20 gradually becomes thinner in the direction away from the silicon substrate 10, that is, the width of the gate line 20 becomes narrower.

[0053] In some embodiments, the widths of the same collinear region of the plurality of gate lines 20 along the second direction are substantially consistent. In the present application, substantially consistent widths means that the difference between the two widths does not exceed 1 μm. Figure 1 The position of each dotted line extending along the second direction in the figure represents the same collinear region of the plurality of grid lines 20 along the second direction. In this way, the line widths of the corresponding regions of the grid lines 20 along the second direction are consistent, indicating that the uniformity of the line types of the plurality of grid lines 20 is better, which reduces the use of silver paste and saves manufacturing costs on the one hand, and the resistance distribution of the plurality of grid lines 20 is basically consistent on the other hand, which is beneficial to carrier transmission and comprehensively improves the conversion efficiency of the solar cell.

[0054] The width of the gate line 20 has a structural design of being narrow at both ends and wide in the middle. Along the first direction, the width of the middle region of the gate line 20 is greater than the width of other regions of the gate line 20. Figure 1Each gate line 20 has a length L along the first direction, and the middle area of ​​the gate line 20 refers to an area extending L / 18 from the center point of the gate line 20 along the first direction toward the upper edge and the lower edge of the silicon substrate 10, respectively, and the upper edge and the lower edge of the silicon substrate 10 are relatively spaced along the first direction. Figure 1 The position of the middle dotted line box represents the middle area of ​​the gate line 20. The two ends of the gate line 20 are close to the edge of the silicon substrate 10 and can be designed to be narrower than the middle part, which can save slurry and save costs.

[0055] Table 2 shows the width results measured at each test point of the nine gate lines 20, and the unit of each parameter is micrometer. According to Table 2, it can be seen that the width of the test point 5 at the middle position of each gate line 20 is significantly greater than the width of the test points in other areas, and the widths of the same collinear area of ​​the nine gate lines 20 tested along the second direction are basically consistent.

[0056] Table 2

[0057] Grid line number 1 2 3 4 5 6 7 8 9 Test point 1 20.7 20.9 20.6 20.4 20.9 20.9 21.3 20.6 21.1 Test point 2 21.2 21.5 21.1 20.9 21.4 21.4 21.8 21.1 21.6 Test point 3 20.2 20.4 20.1 19.9 20.4 20.4 20.8 20.1 20.6 Test point 4 21.2 21.5 21.1 20.9 21.4 21.4 21.8 21.1 21.6 Test point 5 22.3 22.5 22.2 21.9 22.4 22.4 22.8 22.2 22.6 Test point 6 21.5 21.7 21.4 21.1 21.7 21.7 22.1 21.4 21.9 Test point 7 21 21.2 20.9 20.7 21.2 21.2 21.6 20.9 21.4 Test point 8 21.2 21.5 21.1 20.9 21.4 21.4 21.8 21.1 21.6 Test point 9 21.2 21.4 21 20.7 21.2 21.2 21.6 21 21.4

[0058] In some embodiments, the height of the same gate line 20 along the thickness direction of the silicon substrate 10 is basically the same, and the height difference between any two points of the same gate line 20 does not exceed 1.5 μm. The uniformity of the line type of the same gate line 20 is better, which reduces the use of silver paste and saves manufacturing costs. On the other hand, the resistance distribution of a single gate line is basically consistent, which is beneficial to carrier transmission, and the light shielding distribution of a single gate line is basically consistent, which comprehensively improves the conversion efficiency of the solar cell.

[0059] In some embodiments, the width of the same gate line 20 along the second direction is basically the same, and the difference in width corresponding to any two points of the same gate line 20 does not exceed 2μm. The uniformity of the line type of the same gate line 20 is better. On the one hand, the use of silver paste is reduced, saving manufacturing costs. On the other hand, the resistance distribution of a single gate line is basically the same, which is conducive to carrier transmission, and the shading distribution of a single gate line is basically the same, which comprehensively improves the conversion efficiency of the solar cell. Since the height of the gate line in the side area is greater than the height of the gate line in the area between the two side areas, and the width of the gate line in the side area is basically the same as the width of the gate line in the area between the two side areas, the height-to-width ratio of the gate line located in the side area is greater than the height-to-width ratio of the gate line located in the area between the two side areas. When the gate line widths are equal, the higher the height, the larger the cross-sectional area of ​​the gate line along the thickness direction of the silicon wafer.

[0060] In some embodiments, the ratio of the height to the width of the gate line 20 is 45% or more, for example, the ratio of the height to the width of the gate line 20 may be 45%, 46%, 47%, 48%, 49%, 50%, 51%, 52%, 53%, 54%, 55%, 56%, 57%, 58%, etc. Further, in some embodiments, the ratio of the height to the width of the gate line 20 is 50% or more.

[0061] In some embodiments, the width of the gate line 20 ranges from 19.5 to 25 μm. For example, the width of the gate line 20 may be 19.5 μm, 20 μm, 20.5 μm, 21 μm, 21.5 μm, 22 μm, 22.5 μm, 23 μm, 23.5 μm, 24 μm, 24.5 μm, or 25 μm. Further, in some embodiments, the width of the gate line 20 ranges from 19.5 to 23 μm.

[0062] In some embodiments, the height of the gate line 20 ranges from 9 to 13 μm, for example, the height of the gate line 20 may be 9 μm, 9.5 μm, 10 μm, 10.5 μm, 11 μm, 11.5 μm, 12 μm, 12.5 μm, 13 μm. Further, in some embodiments, the height of the gate line 20 ranges from 10 to 12 μm.

[0063] It can be understood that, although not shown in the figure, at least part of the gate lines include a plurality of sub-gate line segments arranged along the first direction.

[0064] In some embodiments, a plurality of sub-grid segments arranged in the same row along the first direction have a gap between adjacent sub-grid segments. The gap between adjacent sub-grid segments can be the gap required for setting heterogeneous grid lines in a back contact battery, or can be the space for accommodating busbars or welding strips.

[0065] It is understandable that, although not shown in the figure, in some embodiments, the solar cell further includes a plurality of bus grid lines, and the bus grid lines extend along the second direction. The plurality of bus grid lines are arranged at intervals along the first direction. The plurality of bus grid lines intersect with the plurality of grid lines, and the plurality of bus grid lines are cross-connected with at least part of the sub-grid line segments, and the bus grid lines are arranged at the sub-grid line segment interval positions. In the presence of bus grid lines, the width of the grid lines involved in this application refers to the width of the sub-grid line segments along the second direction at the cross-connection position between the non-bus grid lines and the sub-grid line segments. Because the width of the intersection position of the grid lines and the bus grid lines is uncertain and not representative, it should not be used as a measurement point.

[0066] It is understandable that, although not shown in the figure, in some embodiments, the solar cell further comprises a plurality of solder joints. Each solder joint is electrically connected to at least part of the sub-grid segment, and the solder joint is arranged at the sub-grid segment interval position. The width of the grid line 20 involved in the present application refers to the width of the sub-grid segment along the second direction at the non-solder joint and the sub-grid segment connection position. Because the width of the intersection position of the grid line and the solder joint is uncertain and unrepresentative, it should not be used as a measurement point.

[0067] In some embodiments, when the solar cell includes both a plurality of bus bars and a plurality of solder joints, a portion of the bus bars are collinear with a portion of the solder joints along the second direction.

[0068] It can be understood that, although not shown in the figure, the present application scheme can be applicable to battery cells without main grid, or battery cells with main grid, or battery cells without main grid with welding points, or battery cells with main grid with welding points design, wherein the main grid is the bus electrode.

[0069] It can be understood that, although not shown in the figure, the present application scheme can be applied to double-sided batteries or back-contact batteries.

[0070] Each sub-grid line has a width along the second direction. In the same grid line, the widths of the middle sections of adjacent sub-grid line segments along the second direction are basically consistent, and the difference in widths between any two points of adjacent sub-grid lines does not exceed 1μm. The length of the sub-grid line segment is d, and the middle section of the sub-grid line segment is the portion extending from the center point of the sub-grid line segment in the first direction to both ends of the first direction by a length of d / 6. The uniformity of the line type of adjacent sub-grid lines is better, that is, the uniformity of a single grid line is better, and the conversion efficiency of the solar cell is improved. For example, when the battery cell does not include a bus grid line and a soldering point, the adjacent sub-grid lines can be set so that the difference in widths between any two points does not exceed 1μm; when the battery cell includes a bus grid line and / or a soldering point, the adjacent sub-grid lines can be set so that the difference in widths between any two points does not exceed 1μm except near the connection parts with the bus grid line and / or the soldering point.

[0071] The present application also provides a photovoltaic module (not shown) comprising at least one of the above-mentioned solar cells, for example, may comprise at least two of the above-mentioned solar cells spliced ​​to each other.

[0072] The present application improves the performance of solar cells by specially designing the height and / or width of the grid lines. Screen printing or electroplating can also be used. As long as the grid lines at different positions of the cell are arranged as described in the present application, the performance of the solar cell can be improved.

[0073] The above implementation modes are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred implementation modes, a person skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A solar cell, characterized in that: include: A silicon substrate including a first surface and a second surface opposite to each other; A plurality of gate lines are arranged on at least one of the first surface and the second surface, the plurality of gate lines extend along a first direction and are arranged at intervals along a second direction, the first direction intersects with the second direction, the gate lines have a height along the thickness direction of the silicon substrate, along the second direction, the silicon substrate includes two opposite and spaced side regions, the height of at least one gate line located in at least one of the side regions is greater than the height of at least one gate line located in the region between the two side regions, the silicon substrate has a width W along the second direction, and the width of the side region is W / 6.

2. The solar cell according to claim 1, characterized in that The average height of the grid lines located in at least one of the side regions is greater than the average height of the grid lines located in the region between the two side regions; and / or, The height of any gate line located in at least one of the side regions is greater than the height of any gate line located in a region between two of the side regions.

3. The solar cell according to claim 1 or 2, characterized in that: The height of at least one gate line in the two side regions is greater than the height of at least one gate line in the region between the two side regions.

4. The solar cell according to claim 1, characterized in that The gate lines have a width along the second direction, and the widths of the same collinear region of the plurality of gate lines extending along the second direction are substantially consistent, and the difference between any two widths does not exceed 1 μm.

5. The solar cell according to claim 1, characterized in that: The height of the same gate line along the thickness direction of the silicon substrate is substantially consistent, and the height difference between any two points of the same gate line does not exceed 1.5 μm; and / or, The gate line has a width along the second direction, the width of the same gate line along the second direction is substantially consistent, and the difference in width between any two points of the same gate line does not exceed 2 μm.

6. The solar cell according to claim 1, characterized in that The ratio of the height to the width of the gate lines located in the side area is greater than the ratio of the height to the width of the gate lines in the area between the two side areas.

7. The solar cell according to claim 1, characterized in that The ratio of the height to the width of the gate line is greater than 45%, or the ratio of the height to the width of the gate line is greater than 50%.

8. The solar cell according to claim 1, characterized in that Along the first direction, the width of the middle area of ​​the gate line is greater than the width of other areas of the gate line, and the gate line has a length L along the first direction. The middle area of ​​the gate line refers to an area extending L / 18 from the center point of the gate line along the first direction toward the upper edge and the lower edge of the silicon substrate respectively, and the upper edge and the lower edge of the silicon substrate are relatively spaced along the first direction.

9. The solar cell according to claim 1, characterized in that: The width of the gate line is in the range of 19.5-25 μm; and / or the height of the gate line is in the range of 9-13 μm.

10. The solar cell according to claim 1, characterized in that: The gate line comprises a plurality of sub-gate line segments arranged along a first direction; A plurality of the sub-grid line segments are arranged in the same row along the first direction, and there is a gap between adjacent sub-grid line segments; and / or, The solar cell further comprises a plurality of busbar lines extending along the second direction, the plurality of busbar lines are arranged at intervals along the first direction, the plurality of busbar lines intersect at least a portion of the sub-grid line segments, and / or, A plurality of welding spots are arranged at intervals in the same row along the first direction, at least one welding spot is arranged on one gate line, and each welding spot is electrically connected to at least part of the sub-gate line segments.

11. The solar cell according to claim 10, characterized in that The sub-gate line segment has a width along the second direction. In the same gate line, the widths of the middle sections of adjacent sub-gate line segments along the second direction are basically consistent, and the difference in corresponding widths between any two points of adjacent sub-gate lines does not exceed 1 μm; the length of the sub-gate line segment along the first direction is d, and the middle section of the sub-gate line segment is a portion extending from the center point of the sub-gate line segment in the first direction to both ends of the first direction by a length of d / 6.

12. A photovoltaic module, characterized in that: Comprising at least one solar cell according to any one of claims 1 to 11.

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