Surge protection device and power supply

Abstract

The utility model discloses a surge protection device and a power supply, the device comprises a fast surge sampling circuit, a surge identification circuit, an enabling circuit and a control circuit; the fast surge sampling circuit samples the output voltage, the surge identification circuit identifies whether there is a surge by sampling the voltage; when there is no surge, the output voltage is a normal output voltage, the surge identification circuit identifies that there is no surge, and continuously outputs the voltage through the enabling circuit and the control circuit; when there is a surge, the output voltage is greater than the normal output voltage, the surge identification circuit identifies that there is a surge, and disconnects the voltage output through the enabling circuit and the control circuit, and the output voltage begins to drop; when the output voltage drops to a certain level, the surge identification circuit identifies that there is no surge, and continuously outputs the voltage through the enabling circuit and the control circuit; and so on and so forth until the surge ends. The utility model can actively and real-timely protect against surges.

Description

Technical Field

[0001] The utility model belongs to the field of electronic technology, and in particular relates to a surge protection device and a power supply. Background Art

[0002] In order to meet the requirements of electromagnetic compatibility and power supply transient characteristics and adapt to complex environmental requirements, the power supply usually needs to be designed to protect against surge impact.

[0003] Most surge suppression devices use Zener diodes, varistors, thermistors, resettable fuses, air spark gap dischargers, transient voltage suppressors (TVS), electrostatic protection (ESD) diodes, etc. These are passive absorption or shunt devices. For large surges, the failure of the impact device may lead to the failure of the entire electrical system.

[0004] At present, the surge voltage under single fault conditions is 100V / 50ms, and the surge voltage under no fault conditions is 40V / 50ms. The pulse peak power of TVS allows only 1ms of operation time. If the duration is 10ms, the pulse peak power will be about 1 / 3; the typical surge duration of varistor is 8us and 20us, and the charge flow under 8us and 20us is very different; the surge duration of ESD is even lower. These surge suppression devices generally do not have the performance characteristics of surge duration of 50ms, and it is not guaranteed whether they can prevent 50ms large surges. Utility Model Content

[0005] In order to solve the technical problems existing in the prior art, the utility model provides a surge protection device and a power supply, which adopt an active surge identification circuit and a real-time control circuit to actively and real-time block surge impacts, which can not only suppress nanosecond level surge impacts but also millisecond level or even tens of millisecond level surge impacts.

[0006] The technical solutions adopted by the utility model to solve the above technical problems are as follows:

[0007] A surge protection device, comprising a fast surge sampling circuit, a surge identification circuit, an enabling circuit and a control circuit;

[0008] The fast surge impact sampling circuit includes a ninth resistor R9, a tenth resistor R10 and a sixth capacitor C6; the ninth resistor R9 and the tenth resistor R10 are connected in series to the positive and negative electrodes of the output end, and the sixth capacitor C6 is connected in parallel to the ninth resistor R9;

[0009] The surge impact identification circuit includes a sixth resistor R6, a seventh resistor R7 and an NMOS tube U1; the drain of the NMOS tube U1 is connected to the positive electrode of the output end through the sixth resistor R6, the gate thereof is connected to the connection point of the ninth resistor R9 and the tenth resistor R10 through the seventh resistor R7, and the source thereof is connected to the negative electrode of the output end;

[0010] The enabling circuit includes an enabling signal V3, a thirteenth resistor R13, a fourteenth resistor R14 and a transistor Q1; the emitter of the transistor Q1 is connected to the negative electrode of the output end, and the base thereof is connected to the drain of the NMOS tube U1 through the fourteenth resistor R14; the high level of the enabling signal V3 is connected to the drain of the NMOS tube U1 through the fourteenth resistor R14;

[0011] The control circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a voltage stabilizing diode D2 and a PMOS tube M2; the source of the PMOS tube M2 is connected to the positive electrode of the input end, the drain thereof is connected to the positive electrode of the output end, and the gate thereof is connected to the emitter of the transistor Q1 through the third resistor R3 and the second resistor R2 connected in series; the first resistor R1 is connected to the positive electrode of the input end and the connection point of the third resistor R3 and the second resistor R2, the voltage stabilizing diode D2 is connected in parallel with the first resistor R1, and the cathode of the voltage stabilizing diode D2 is connected to the positive electrode of the input end;

[0012] When there is no surge impact, the NMOS tube U1 is disconnected, the transistor Q1 is turned on, the PMOS tube M2 is turned on, and the output voltage is normal;

[0013] When there is a surge impact, the output voltage increases, the NMOS tube U1 is turned on, the transistor Q1 is turned off, and the PMOS tube M2 is turned off. At this time, the output voltage begins to drop; when the output voltage drops to a certain level, the NMOS tube U1 is turned off, the transistor Q1 is turned on, and the PMOS tube M2 is turned on, and the output voltage begins to rise; this cycle repeats until the surge ends.

[0014] Furthermore, the device also includes a filter circuit; the filter circuit includes a seventh capacitor C7, a diode D1, a twelfth resistor R12 and a fifth capacitor C5;

[0015] The seventh capacitor C7 is connected to the positive and negative electrodes of the output terminal, the positive electrode of the output terminal is connected to the twelfth resistor R12 and one end of the fifth capacitor C5 connected in parallel through the diode D1, and the other end of the twelfth resistor R12 and the fifth capacitor C5 connected in parallel is connected to the negative electrode of the output terminal;

[0016] Two ends of the twelfth resistor R12 and the fifth capacitor C5 connected in parallel serve as power output ends.

[0017] Furthermore, the surge impact identification circuit also includes a diode; the positive and negative electrodes of the diode are respectively connected to the source and drain of the NMOS tube U1.

[0018] Furthermore, the enabling circuit also includes a power supply; the power supply generates an enabling signal V3.

[0019] A power supply adopts any one of the above-mentioned surge protection devices to actively and in real time protect against surges.

[0020] Compared with the prior art, the utility model has the following advantages and beneficial effects:

[0021] 1. Initiative: Through the surge sampling circuit and surge fast identification circuit, the surge is sampled and the width and amplitude of the surge are quickly identified, and the surge is actively suppressed through the control circuit.

[0022] 2. Real-time: The surge sampling circuit samples the surge in real time, the surge identification circuit identifies the nature of the surge in real time, and the active surge control circuit suppresses the surge in real time, achieving the function of suppressing the surge in real time whether it is turned on or during operation.

[0023] 3. The surge impact suppression amplitude is high and the surge impact duration is long. The surge impact suppression amplitude is determined by the withstand voltage of the switch tube M2, and the surge impact suppression duration can reach tens of milliseconds. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a principle block diagram of the surge protection device of the utility model;

[0025] Figure 2 This is a circuit diagram of the utility model surge protection device;

[0026] Figure 3 This is a control waveform diagram of an active real-time surge protection device of the utility model;

[0027] Figure 4 Another active real-time surge protection device control waveform diagram of the utility model;

[0028] Figure 5 This is a block diagram of the circuit control of the utility model when there is no surge;

[0029] Figure 6 This is a block diagram of the circuit control of the utility model when there is a surge. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific implementation methods described herein are used to explain the utility model and are not used to limit the utility model. In addition, the technical features involved in each implementation method of the utility model described below can be combined with each other as long as they do not conflict with each other.

[0031] The utility model provides a surge impact protection device, which is used for active and real-time surge impact protection. The device includes a fast surge impact sampling circuit, a surge impact identification circuit, an enabling circuit and a control circuit; the fast surge impact sampling circuit samples the output terminal voltage, and the surge impact identification circuit identifies whether there is a surge impact through the sampled voltage; when there is no surge impact, the output terminal voltage is a normal output voltage, the surge impact identification circuit identifies that there is no surge impact, and then continuously outputs the voltage through the enabling circuit and the control circuit; when there is a surge impact, the output terminal voltage is greater than the normal output voltage, the surge impact identification circuit identifies that there is a surge impact, and then disconnects the voltage output through the enabling circuit and the control circuit, and the output terminal voltage begins to drop at this time; when the output terminal voltage drops to a certain level, the surge impact identification circuit identifies that there is no surge impact, and then continuously outputs the voltage through the enabling circuit and the control circuit; and so on and so forth until the surge ends.

[0032] like Figure 1 and Figure 2 As shown, an active real-time surge protection device includes: a fast surge sampling circuit, which is composed of resistors R9, R10 and C6, and the surge amplitude is sampled through the resistors R9 and R10, and the surge front is quickly sampled through C6; a surge identification circuit, which is composed of resistors R6, R7 and U1, and when there is a surge, the identification circuit determines to block the surge, and when there is no surge, the identification circuit determines to keep the power output normal; an enabling circuit, which is composed of an enabling signal V3, resistors R13, R14 and transistor Q 1, the enable signal is high level, Q1 is turned on and grounded, a saturated conduction gate-source control voltage is generated on M2, the power supply outputs a normal voltage to supply power to the load, the enable signal is low level, Q1 is disconnected, the M2 gate-source control voltage is zero, and M2 is disconnected; control circuit: composed of R1, R2, R3, D2 and M2. When there is no surge impact, the control circuit and the enable circuit ensure that the power supply output is normal. When there is a surge impact, the control circuit, the enable circuit and the surge impact identification circuit work together to block the surge impact and ensure the normal output of the power supply.

[0033] Specifically, Figure 2 As shown, the utility model is an active real-time surge protection device, the circuit mainly includes a fast surge sampling circuit N1, a surge identification circuit N2, an enabling circuit N3 and a control circuit N4. When there is no surge, the sampling circuit N1 samples the power supply output voltage, the voltage on the resistor R10 is less than the conduction threshold voltage of U1, and U1 is turned off. The enabling signal V3 and the pull-up resistor R6 and the resistor R13 work together, Q1 is turned on, and the gate-source voltage of M2 is U gs=Vin×R2 / (R1+R2), Vin is the power input voltage (DC 24V), by adjusting the size of R1 and R2, ensure that the gate-source voltage Ugs of M2 is greater than the saturation conduction gate-source voltage of M2, M2 is saturated and turned on, and the power output is normal; when there is a surge impact, the power output voltage Vout rises, the voltage on the resistor R10 rises to a value greater than the conduction threshold voltage of U1, U1 is turned on, the voltage of R14 is approximately zero, Q1 is turned off, there is no current on R1 and R2, the gate-source voltage Ugs of M2 = 0, M2 is turned off, the output voltage Vout of the power supply drops to a certain level, U1 is disconnected, Q1 resumes conduction, M2 resumes conduction, and the output voltage Vout of the power supply rises over time, and so on, until the surge ends. The control process is simplified as follows Figure 5 and Figure 6 shown.

[0034] When there is no surge, the circuit follows Figure 5 Mode stable control. Where Vin is the power input voltage, U R10 is the voltage across resistor R10, U R14 is the voltage across the resistor R14, Ugs is the gate-source voltage of the MOSFET adjustment tube M2, and Vout is the power supply output voltage.

[0035] When there is a surge, the circuit follows Figure 6 In the process of cyclic control, sampling circuit parameters are selected to ensure that the power output remains basically unchanged when there is a surge.

[0036] like Figure 3 and Figure 4 As shown, the utility model can not only suppress nanosecond level surge impact, but also millisecond level or even tens of millisecond level surge impact.

[0037] It should be noted that U1 can be set according to actual conditions, but it is necessary to ensure that U1 is less than or equal to the normal output voltage.

[0038] The utility model also provides a power supply, which adopts any one of the above-mentioned surge protection devices to actively and real-time protect against surges.

[0039] In summary, the utility model adopts an active surge impact identification circuit and a real-time control circuit to block surge impacts in real time. It can not only suppress nanosecond-level surge impacts with real-time blocking effect, but also has a blocking effect on surge impacts of tens of milliseconds, and the power supply output always remains basically stable.

[0040] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A surge protection device, characterized in that: The device includes a fast surge impact sampling circuit, a surge impact identification circuit, an enabling circuit and a control circuit; The fast surge impact sampling circuit includes a ninth resistor R9, a tenth resistor R10 and a sixth capacitor C6; the ninth resistor R9 and the tenth resistor R10 are connected in series to the positive and negative electrodes of the output end, and the sixth capacitor C6 is connected in parallel to the ninth resistor R9; The surge impact identification circuit includes a sixth resistor R6, a seventh resistor R7 and an NMOS tube U1; the drain of the NMOS tube U1 is connected to the positive electrode of the output end through the sixth resistor R6, the gate thereof is connected to the connection point of the ninth resistor R9 and the tenth resistor R10 through the seventh resistor R7, and the source thereof is connected to the negative electrode of the output end; The enabling circuit includes an enabling signal V3, a thirteenth resistor R13, a fourteenth resistor R14 and a transistor Q1; the emitter of the transistor Q1 is connected to the negative electrode of the output end, and the base thereof is connected to the drain of the NMOS tube U1 through the fourteenth resistor R14; the high level of the enabling signal V3 is connected to the drain of the NMOS tube U1 through the fourteenth resistor R14; The control circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a voltage stabilizing diode D2 and a PMOS tube M2; the source of the PMOS tube M2 is connected to the positive electrode of the input end, the drain thereof is connected to the positive electrode of the output end, and the gate thereof is connected to the emitter of the transistor Q1 through the third resistor R3 and the second resistor R2 connected in series; the first resistor R1 is connected to the positive electrode of the input end and the connection point of the third resistor R3 and the second resistor R2, the voltage stabilizing diode D2 is connected in parallel with the first resistor R1, and the cathode of the voltage stabilizing diode D2 is connected to the positive electrode of the input end; When there is no surge impact, the NMOS tube U1 is disconnected, the transistor Q1 is turned on, the PMOS tube M2 is turned on, and the output voltage is normal; When there is a surge impact, the output voltage increases, the NMOS tube U1 is turned on, the transistor Q1 is turned off, and the PMOS tube M2 is turned off. At this time, the output voltage begins to drop; when the output voltage drops to a certain level, the NMOS tube U1 is turned off, the transistor Q1 is turned on, and the PMOS tube M2 is turned on, and the output voltage begins to rise; this cycle repeats until the surge ends.

2. The surge protection device according to claim 1, characterized in that: The device also includes a filter circuit; the filter circuit includes a seventh capacitor C7, a diode D1, a twelfth resistor R12 and a fifth capacitor C5; The seventh capacitor C7 is connected to the positive and negative electrodes of the output terminal, the positive electrode of the output terminal is connected to the twelfth resistor R12 and one end of the fifth capacitor C5 connected in parallel through the diode D1, and the other end of the twelfth resistor R12 and the fifth capacitor C5 connected in parallel is connected to the negative electrode of the output terminal; Two ends of the twelfth resistor R12 and the fifth capacitor C5 connected in parallel serve as power output ends.

3. The surge protection device according to claim 1, characterized in that: The surge impact identification circuit also includes a diode; the positive and negative electrodes of the diode are respectively connected to the source and drain of the NMOS tube U1.

4. The surge protection device according to claim 1, characterized in that: The enabling circuit also includes a power supply; the power supply generates an enabling signal V3.

5. A power supply, characterized in that: The power supply adopts the surge protection device described in any one of claims 1 to 4 to actively and real-timely protect against surges.

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