Nitride semiconductor device

Abstract

The utility model relates to a nitride semiconductor device. The passivation layer is arranged among the source electrode, the drain electrode and the grid electrode, that is, the plasma is injected into the ion injection region, so that the plasma and impurities in the cap layer in the ion injection region form a complex, the doping state and the electrical property of the cap layer are changed, the conductivity and the carrier concentration of the cap layer are influenced, and passivation of the cap layer is achieved. Through the arrangement, the problem of an interface state caused by a traditional etching technology can be reduced, and the quality and the stability of the material are improved. In addition, grid leakage circuits can be reduced, grid breakdown voltage is increased, and the performance and reliability of the device are improved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a nitride semiconductor device. Background Art

[0002] High electron mobility transistor (HEMT) is a heterojunction field effect transistor. High-mobility two-dimensional electron gas (2DEG) exists in the heterojunction, which makes HEMT devices have superior performance such as high frequency, high power, high temperature resistance, and strong radiation resistance. Gallium nitride (GaN) material is widely used in power semiconductor devices due to its wide band gap and high thermal conductivity.

[0003] The conductive channel of GaN HEMT is naturally formed by piezoelectric effect and polarization effect. Therefore, under normal conditions, the device works in the on state, so it is called a normally-on (D-mode) device. In order to meet the needs of safe operation and simplify the drive, the D-mode device needs to be processed to become a normally-off (E-mode) device that can only be turned on under the action of gate voltage (VG). Among them, the methods of realizing E-mode GaN HEMT include gate recess, p-GaN layer depletion (p-GaN) and fluorine ion implantation.

[0004] p-GaN HEMT is the most attractive device type. Among them, p-GaN enhanced HEMT devices can reduce system power consumption and complexity and improve safety. Therefore, they have broad application prospects in high-temperature and radio frequency integrated circuits, high-speed switches and microwave monolithic integrated circuits.

[0005] At present, the mainstream technology for realizing p-GaN enhanced HEMT devices is to grow another p-GaN layer on the traditional ALGaN / GaN epitaxy. During the preparation process, the p-GaN layer except the p-GaN layer under the gate can be partially or completely removed, thereby retaining the inherent 2DEG conductive channel. The p-GaN retained by the gate interacts with the ALGaN layer, which will deplete the 2DEG below, and in the absence of gate voltage, it is in the off state, thereby realizing the normally off (E-mode) function.

[0006] In the prior art, the p-GaN layer between the source, drain and gate is generally removed by etching, but the etching process will damage the lattice, increase the interface difficulty between the p-GaN layer and other layers, and cause the dynamic characteristics to deteriorate. At the same time, the field strength is high when the side of the p-GaN gate close to the drain is under pressure. Long-term pressure causes device reliability problems and easily causes device breakdown. Summary of the invention

[0007] The present application provides a nitride semiconductor device that can solve the problems of poor performance and low stability of existing gallium nitride high electron mobility transistor devices. The technical solution is as follows:

[0008] A nitride semiconductor device comprises a substrate, a channel layer, a barrier layer and a semiconductor layer arranged in sequence from bottom to top;

[0009] The semiconductor layer comprises a gate region, an ion implantation region, a first electrode region and a second electrode region, wherein the gate region and the ion implantation region are located between the first electrode region and the second electrode region;

[0010] The gate region is provided with a cap layer, a first buffer layer and a gate layer from bottom to top;

[0011] The ion implantation region includes a passivation layer, and the passivation layer is formed by combining the impurities of the cap layer with the implanted plasma;

[0012] The first electrode region and the second electrode region are located at two ends of the upper surface of the barrier layer. A source electrode is disposed in the first electrode region, and a drain electrode is disposed in the second electrode region.

[0013] In one embodiment, the semiconductor layer includes two gate regions and three ion implantation regions, the gate regions are arranged at intervals, and the ion implantation regions are respectively located between the gate regions, between the first electrode region and the gate region, and between the second electrode region and the gate region.

[0014] In one embodiment, the material of the cap layer is gallium nitride doped with p-type impurities.

[0015] In one embodiment, the material of the first buffer layer is undoped gallium nitride.

[0016] In one of the embodiments, the first buffer layer includes a first sub-buffer layer and a second sub-buffer layer, wherein the first sub-buffer layer is disposed on the cap layer, and the second sub-buffer layer is disposed on the first sub-buffer layer.

[0017] In one embodiment, the material of the first sub-buffer layer is n-type doped gallium nitride, and the material of the second sub-buffer layer is n-type doped aluminum gallium nitride.

[0018] In one embodiment, the material of the first sub-buffer layer is p-type doped aluminum gallium nitride, and the material of the second sub-buffer layer is p-type doped gallium nitride; wherein,

[0019] The amount of p-type dopant added in the first sub-buffer layer is greater than that in the second sub-buffer layer.

[0020] In one embodiment, the plasma is hydrogen plasma, and the acceptor impurity magnesium ions of the cap layer are combined with the implanted hydrogen plasma to form the passivation layer containing a magnesium-hydrogen complex.

[0021] In one embodiment, the plasma uses nitrogen ions, and the impurities in the cap layer are combined with the implanted nitrogen ions to form the passivation layer.

[0022] In one embodiment, the plasma uses helium ions, and the impurities in the cap layer are combined with the implanted helium ions to form the passivation layer.

[0023] In one embodiment, the material of the substrate is selected from one of gallium nitride, silicon, silicon carbide and sapphire; and / or

[0024] The material of the channel layer is gallium nitride; and / or

[0025] The material of the barrier layer is aluminum gallium nitride.

[0026] In one of the embodiments, a two-dimensional electron gas layer is further included, which is formed on a side of the contact surface between the channel layer and the barrier layer that is biased toward the channel layer, and the source electrode and the drain electrode are electrically connected via the two-dimensional electron gas layer.

[0027] In one embodiment, a second buffer layer is further included, wherein the buffer layer is located between the substrate and the channel layer;

[0028] The material of the second buffer layer is carbon-doped gallium nitride.

[0029] In one embodiment, a nucleation layer is further included, and the nucleation layer is located between the substrate and the second buffer layer;

[0030] The material of the nucleation layer is aluminum nitride.

[0031] In one embodiment, it also includes a source metal interconnection layer, a drain metal interconnection layer and a gate metal interconnection layer;

[0032] The source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer are formed on the top of the source electrode, the drain electrode and the gate layer respectively;

[0033] It also includes a source metal pad, a drain metal pad and a gate metal pad, wherein the source metal pad, the drain metal pad and the gate metal pad are formed on the top of the source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer respectively.

[0034] The technical solution provided by the embodiments of the present application may include the following beneficial effects: It can be seen from the above embodiments that the present application forms a passivation layer between the source, drain and gate, that is, by injecting plasma into the ion injection area, so that the plasma and the impurities in the cap layer in the ion injection area form a complex to change the doping state and electrical properties of the cap layer, affect its conductivity and carrier concentration, so as to achieve passivation of the cap layer. This setting can not only reduce the interface state problems caused by traditional etching technology, but also improve the quality and stability of the material. It can also reduce the gate leakage circuit, increase the gate breakdown voltage effect, and improve the device performance and reliability.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0037] Figure 1 FIG. 1 is a schematic structural diagram of a nitride semiconductor device according to an embodiment of the present application.

[0038] Figure 2a-2e This is a schematic diagram of the structure of the preparation process of a nitride semiconductor device according to an embodiment of the present application.

[0039] Figure 3 FIG. 4 is another schematic diagram of the structure of a nitride semiconductor device according to an embodiment of the present application.

[0040] Description of reference numerals:

[0041] 10. Substrate; 20. Channel layer; 30. Barrier layer; 40. Semiconductor layer; 401. Cap layer; 402. First buffer layer; 403. Gate layer; 404. Passivation layer; 405. Source electrode; 406. Drain electrode; 4021. First sub-buffer layer; 4022. Second sub-buffer layer; 50. Two-dimensional electron device layer; 60. Second buffer layer; 70. Nucleation layer.

[0042] a, gate region; b, ion implantation region; e, first electrode region; f, second electrode region. DETAILED DESCRIPTION

[0043] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The methods described in the following exemplary embodiments do not represent all methods consistent with the present application. Instead, they are merely examples of devices consistent with some aspects of the present application as detailed in the appended claims.

[0044] Gallium nitride (GaN) is a third-generation wide bandgap semiconductor material with the characteristics of large bandgap width, high critical breakdown electric field, and large saturated electron drift velocity. It has obvious advantages in microwave high-power and radio frequency applications. With the development of epitaxial technology, the preparation technology and material quality of GaN have been gradually improved. GaN devices are increasingly used in wireless communications, radar, aerospace, and intelligent weapons, and continue to meet the requirements for high-frequency, high-bandwidth, high-efficiency, and high-power devices. It occupies an important position in the field of semiconductor devices. GaN-based power devices can be used to prepare a new generation of high-power switching devices. At present, they are mainly lateral heterojunction AlGaN / GaN HEMT (high electron mobility transistor) devices. The AlGaN / GaN structure has a high electron mobility and can achieve low on-resistance and high operating frequency. Transistors based on the AlGaN / GaN structure are depletion-type devices, but in order to ensure the safety and reliability of power electronic systems, enhancement-type transistors need to be introduced. Therefore, it is very important to realize enhancement-type HEMT devices with stable threshold voltage and large on-current.

[0045] At present, p-GaN / AlGaN / GaN epitaxial wafers can meet the needs of enhancement-mode devices. Among them, the presence of p-GaN can deplete the electrons in the AlGaN barrier layer, etch the p-GaN at the gate region, and only retain a very thin thickness (<10nm) in the gate region, which can deplete the holes in the p-GaN channel layer under zero gate voltage and realize a normally closed p-channel device.

[0046] A process for forming a partially p-GaN AlGaN / GaN HEMT device in the prior art generally comprises the following steps:

[0047] (1) Growth of epitaxial layers: GaN layer, AlGaN layer, and p-GaN are sequentially formed on the substrate.

[0048] (2) Photolithography and etching of the p-GaN layer. The p-GaN layer except for the gate region is removed by etching.

[0049] (3) Preparation of gate metal: After the gate metal is deposited, the gate metal is etched to retain the gate metal on the p-GaN.

[0050] (4) Prepare source and drain electrodes. Use metal deposition techniques such as electron beam evaporation or sputtering to make source and drain electrodes on the AlGaN layer.

[0051] As can be seen from the above, since the deposited p-GaN layer needs to be etched to form an independent gate structure, the etching of p-GaN will undoubtedly damage the lattice, and the hole mobility in the p-channel will also decrease. Moreover, the interface after etching also forms a high-density trap state due to factors such as the accumulation of etching byproducts and nitrogen vacancies, which seriously affects the performance of the device.

[0052] In view of this, the present application discloses a nitride semiconductor device, specifically a gallium nitride HEMT. After preparing the gate metal, plasma treatment technology is used to directly passivate the p-GaN into a high-resistance passivation layer 404, eliminating the process step of etching the p-GaN layer, avoiding the negative effects caused by etching damage, and improving the performance and reliability of the device.

[0053] like Figure 2e As shown, the nitride semiconductor device of the present application includes a substrate 10, a channel layer 20, a barrier layer 30 and a semiconductor layer 40 arranged in sequence from bottom to top. The semiconductor layer 40 includes a gate region a, an ion implantation region b, a first electrode region e and a second electrode region f, and the gate region a and the ion implantation region b are located between the first electrode region e and the second electrode region f. A cap layer 401, a first buffer layer 402 and a gate layer 403 are arranged from bottom to top in the gate region a. The ion implantation region b includes a passivation layer 404, which is formed by combining the impurities of the cap layer 401 with the injected plasma. The first electrode region e and the second electrode region f are located at both ends of the upper surface of the barrier layer 30, and a source electrode 405 is arranged in the first electrode region e, and a drain electrode 406 is arranged in the second electrode region f.

[0054] Specifically, the semiconductor layer 40 includes two gate regions a and three ion implantation regions b. The gate regions a are arranged at intervals. The ion implantation regions b are respectively located between the gate regions a, between the first electrode region e and the gate region a, and between the second electrode region f and the gate region a.

[0055] It can be understood that the nitride semiconductor device of the present application is set as a dual-gate structure. It includes a gate and a barrier gate. Among them, the gate is used to control the transmission of electrons, and the barrier gate is used to regulate the transmission of electrons in the barrier layer 30 and limit the leakage current. The dual-gate mechanism can provide better control and regulation performance, and is suitable for high-frequency, low-noise and high-power applications.

[0056] Reference Figure 2a-2e , is a process flow chart of preparing a nitride semiconductor device of the present application, comprising:

[0057] Step 1: Prepare epitaxial wafer.

[0058] Reference Figure 2a , the substrate 10 is provided with a substrate 10, a channel layer 20, a barrier layer 30, a cap layer 401 and a first buffer layer 402 from bottom to top. Among them, the material of the channel layer 20 of the channel layer 20 is selected from gallium nitride (GaN), which can be referred to as a GaN layer. The material of the barrier layer 30 is selected from aluminum gallium nitride (AlGaN), which can be referred to as an AlGaN layer. The material of the cap layer 401 is selected from gallium nitride doped with p-type impurities (p-GaN), which can be referred to as a p-GaN layer. The material of the first buffer layer 402 is selected from undoped gallium nitride (u-GaN). The material of the substrate 10 is selected from one of gallium nitride, silicon, silicon carbide and sapphire.

[0059] Specifically, silicon is selected as the material of the substrate 10. After cleaning a silicon wafer of a certain size, a GaN layer, an AlGaN layer, a p-GaN layer and a u-GaN layer are sequentially deposited by using a metal organic chemical vapor deposition (MOCVD) process or a molecular beam epitaxy (MBE) process.

[0060] When the p-GaN layer and the u-GaN layer form a p-GaN junction, the u-GaN can provide a low resistance path, which helps to share the gate leakage current, reduce the possibility of current flowing through the p-GaN junction, and effectively reduce the gate leakage current.

[0061] At the same time, due to the presence of u-GaN, its electrical properties can change the electric field distribution of the entire device, so that the electric field is more evenly distributed in the entire structure during breakdown, the voltage division of the pn junction will increase, thereby increasing the gate breakdown voltage.

[0062] Therefore, the present invention can simultaneously reduce the gate leakage current and increase the gate breakdown voltage by combining u-GaN and p-GaN to form a p-GaN junction, thereby improving the performance and reliability of the device.

[0063] In some embodiments, reference Figure 3 The first buffer layer 402 includes a first sub-buffer layer 4021 and a second sub-buffer layer 4022 , wherein the first sub-buffer layer 4021 is disposed on the cap layer 401 , and the second sub-buffer layer 4022 is disposed on the first sub-buffer layer 4021 .

[0064] Specifically, the material of the first sub-buffer layer 4021 is n-type doped gallium nitride (n-GaN), and the material of the second sub-buffer layer 4022 is n-type doped aluminum gallium nitride (n-ALGaN).

[0065] This setup has the following advantages:

[0066] Lattice matching: n-GaN layer can help reduce the defect density caused by lattice mismatch and improve crystal quality. n-AlGaN layer can provide better lattice matching performance, help reduce the stress caused by lattice mismatch and reduce lattice defects.

[0067] Electron transport: The n-GaN layer has good electron transport performance, which helps to improve the electron transport performance of the device. The n-AlGaN layer acts as an electron barrier layer, which can effectively prevent electrons from leaking upward and reduce gate leakage current.

[0068] Interface quality: The n-AlGaN layer can provide better interface quality, help reduce the interface state density, and improve the interface characteristics of the device.

[0069] Therefore, setting the first buffer layer 402 as a combination of an n-GaN layer and an n-AlGaN layer can effectively optimize the device structure and improve the working efficiency and reliability of the device.

[0070] In some embodiments, the material of the first sub-buffer layer 4021 is p-type doped aluminum gallium nitride (p-AlGaN), and the material of the second sub-buffer layer 4022 is p-type doped gallium nitride (p-GaN). The amount of p-type dopant added in the p-AlGaN layer is greater than that in the p-type dopant in the p-GaN layer.

[0071] When setting the p-AlGaN and weak p-GaN layers, the amount of p-type dopant added to them is set differently. The p-AlGaN layer is added with a higher p-type doping concentration to ensure its good electron barrier performance and lattice matching performance. The p-GaN layer is added with a lower p-type doping concentration to reduce the hole concentration and reduce the hole leakage current.

[0072] As part of the buffer layer, the p-AlGaN layer can provide better lattice matching performance, help reduce the stress caused by lattice mismatch, and improve crystal quality. In addition, the p-AlGaN layer can act as an electron barrier layer, which helps reduce gate leakage current.

[0073] The weak p-GaN layer can provide a lower hole concentration, which helps to reduce the hole concentration and hole leakage current. The weak p-GaN layer can also provide better electron transport performance, which helps to improve the electron transport performance of the device.

[0074] Therefore, combining the p-AlGaN and weak p-GaN layers as the first buffer layer 402 can improve the performances such as lattice matching, electron transmission and hole leakage, which is helpful to optimize the device structure and improve the working efficiency and reliability of the device.

[0075] Step 2: Etching the U-GaN layer.

[0076] Reference Figure 2b , the U-GaN layer outside the non-gate region a is removed by etching. That is, the U-GaN in the ion implantation region b, the first electrode region e and the second electrode region f is etched by etching. The etching stops on the cap layer 401, that is, the p-GaN layer.

[0077] The specific steps of photolithography include pretreatment, resist coating, pre-baking, exposure and development. The specific operations are all conventional operations and will not be described in detail here.

[0078] Step 3: Prepare gate metal.

[0079] Reference Figure 2c , a gate is prepared in the gate region a. The gate is made of at least one of metal materials such as Ni (Nickel), Pt (Platinum), Mo (Molybdenum), Cr (Chromium), Al (Aluminum), and Au (Gold).

[0080] The preparation process is a conventional cleaning, deposition, photolithography, top view, cleaning and annealing process, which will not be described in detail again.

[0081] Step 4: Prepare a passivation layer 404 .

[0082] Reference Figure 2d , using a diffusion process, an ion implanter is used to perform ion implantation in the ion implantation area b, wherein the ion implantation is based on not entering the barrier layer 30 (i.e., the AlGaN layer), so that the ions can react with the p-GaN to form a complex. Then, the passivation of the p-GaN layer in the ion implantation area b is achieved. That is, the p-GaN in the ion implantation area b is prepared into a high-resistance state, while the p-GaN in the gate area a, the first electrode area e, and the second electrode area f is not prepared into a high-resistance state.

[0083] In some embodiments, the plasma is hydrogen plasma. The acceptor impurity magnesium ions of the cap layer 401 are combined with the implanted hydrogen plasma to form a passivation layer 404 containing a magnesium-hydrogen complex.

[0084] Specifically, a diffusion process (300° C. to 1000° C.) is used to passivate Mg in p-GaN using H atoms in H2, making it impossible for Mg to separate, thereby reducing the hole concentration in p-GaN.

[0085] Compared with traditional P-type GaN gate devices, GaN-based HEMT devices prepared using H plasma can effectively solve the surface etching damage problem that is common in current P-type gate HEMT devices. H atoms can passivate shallow acceptor impurities in GaN materials, and the passivated material is converted into a high-resistance state. Under low-pressure conditions, the plasma energy and density can be adjusted by changing the ICP (Inductively Coupled Plasma) power. During the process, H plasma is injected into P-GaN to produce MgH complexes. On the other hand, in order to reduce surface damage during the etching process, the traditional P-type gate electrode technology reserves about 10nm of GaN, which reduces the concentration of two-dimensional electron gas. However, this application reduces the impact of surface traps on device performance by passivating the p-GaN layer and optimizing the internal electric field distribution, so that the output current of the device is significantly increased.

[0086] In some embodiments, the plasma uses nitrogen ions (N − ) or helium ions (He + ), and the impurities of the cap layer 401 are combined with the implanted nitrogen ions or helium ions to form the passivation layer 404 .

[0087] In the present application, the passivation layer 404 is provided to achieve the following effects.

[0088] Reduce surface state density. Passivation of p-GaN can reduce or eliminate defects and oxides on the surface of the material, thereby reducing the interface state density and improving the quality and stability of the material.

[0089] Improve interface properties. Passivating p-GaN can improve the interface properties between the material and other layers, reduce the impact of impurity diffusion and charge drift, and improve device performance and reliability.

[0090] Inhibit material surface reactions: Passivating p-GaN can reduce the reaction between the material surface and the external environment, prevent material oxidation, corrosion and other problems, and extend the life of the device.

[0091] Optimizing device performance: By passivating p-GaN, the electrical properties, carrier concentration and other parameters of the material can be adjusted to optimize device performance and improve device efficiency and stability.

[0092] Step 5: Prepare the source and drain.

[0093] Reference Figure 2e A source electrode 405 is prepared in the first electrode region e, and a drain electrode 406 is prepared in the second electrode region f. Ohmic metal is deposited by evaporation or sputtering, and the source electrode 405 and the drain electrode 406 are formed by a lift-off process, and an ohmic contact is formed by an annealing process.

[0094] The source electrode 405 and the drain electrode 406 are made of one of Pt (Platinum), Mo (Molybdenum), silver (Silver, Ag), aluminum (Aluminum, Al), and copper (Copper, Cu).

[0095] In some embodiments, reference Figure 1 The nitride semiconductor device further includes a two-dimensional electron gas layer 50 formed on a side of the contact surface between the channel layer 20 and the barrier layer 30 that is biased toward the channel layer 20 , and the source electrode 405 and the drain electrode 406 are electrically connected via the two-dimensional electron gas layer 50 .

[0096] In some embodiments, continue to refer to Figure 1 The nitride semiconductor device further includes a second buffer layer 60, which is located between the substrate 10 and the channel layer 20. The material of the second buffer layer 60 is carbon-doped gallium nitride.

[0097] The second buffer layer 60 can help reduce the influence of lattice mismatch on device performance, alleviate the lattice mismatch between the substrate and the channel layer 20, reduce lattice strain, thereby reducing lattice defect density and improving device performance and reliability.

[0098] In some embodiments, aluminum nitride (AlN) is selected as the material of the second buffer layer 60. The AlN buffer layer has a larger band gap and a smaller lattice constant, can provide better lattice matching performance, and further reduce the lattice defect density.

[0099] In some embodiments, continue to refer to Figure 1 The nitride semiconductor device further includes a nucleation layer 70 , which is located between the substrate 10 and the second buffer layer 60 ; wherein the material of the nucleation layer 70 is aluminum nitride.

[0100] First, the nucleation layer 70 can promote crystal growth, reduce lattice defects, and improve crystal quality. Secondly, the material selection of the nucleation layer 70 can affect the electrical, optical and other properties of the device. In practical applications, the performance of the device can be optimized by adjusting the properties of the nucleation layer 70. Finally, the nucleation layer 70 can alleviate the lattice mismatch between different crystals, reduce lattice strain, and reduce the generation of lattice defects.

[0101] In some embodiments, the material of the nucleation layer 70 may also be gallium nitride (GaN), indium nitride (InN), etc.

[0102] In some embodiments, a source metal interconnection layer, a drain metal interconnection layer and a gate metal interconnection layer are further included. The source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer are formed on the top of the source electrode 405, the drain electrode 406 and the gate layer 403 respectively.

[0103] It also includes a source metal pad, a drain metal pad and a gate metal pad, which are formed on the top of the source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer respectively.

[0104] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one" or "one" do not indicate a quantitative limit, but indicate that there is at least one, and if only "one" is referred to, it will be separately described. "Multiple" or "several" means two or more. Unless otherwise specified, similar words such as "front", "rear", "lower" and / or "upper" are only for the convenience of explanation, and are not limited to one position or one spatial orientation. Similar words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" cover the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. The singular forms "a", "said" and "the" used in this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0105] The specific embodiments described herein are merely examples of the spirit of the present application. A person skilled in the art of the present application may make various modifications, supplements, or replace the described specific embodiments with similar methods, but they will not deviate from the spirit of the present application or exceed the scope defined by the attached claims.

[0106] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A nitride semiconductor device, characterized in that: It includes a substrate, a channel layer, a barrier layer and a semiconductor layer arranged in sequence from bottom to top; The semiconductor layer comprises a gate region, an ion implantation region, a first electrode region and a second electrode region, wherein the gate region and the ion implantation region are located between the first electrode region and the second electrode region; The gate region is provided with a cap layer, a first buffer layer and a gate layer from bottom to top; The ion implantation region includes a passivation layer, and the passivation layer is formed by combining the impurities of the cap layer with the implanted hydrogen plasma; The first electrode region and the second electrode region are located at two ends of the upper surface of the barrier layer. A source electrode is disposed in the first electrode region, and a drain electrode is disposed in the second electrode region.

2. The nitride semiconductor device according to claim 1, wherein: The semiconductor layer includes two gate regions and three ion implantation regions. The gate regions are arranged at intervals. The ion implantation regions are respectively located between the gate regions, between the first electrode region and the gate region, and between the second electrode region and the gate region.

3. The nitride semiconductor device according to claim 2, wherein: The material of the cap layer is gallium nitride doped with p-type impurities.

4. The nitride semiconductor device according to claim 3, characterized in that The material of the first buffer layer is undoped gallium nitride.

5. The nitride semiconductor device according to claim 3, characterized in that: The first buffer layer includes a first sub-buffer layer and a second sub-buffer layer, wherein the first sub-buffer layer is disposed on the cap layer, and the second sub-buffer layer is disposed on the first sub-buffer layer.

6. The nitride semiconductor device according to claim 5, characterized in that The material of the first sub-buffer layer is n-type doped gallium nitride, and the material of the second sub-buffer layer is n-type doped aluminum gallium nitride.

7. The nitride semiconductor device according to claim 5, characterized in that: The material of the first sub-buffer layer is p-type doped aluminum gallium nitride, and the material of the second sub-buffer layer is p-type doped gallium nitride.

8. The nitride semiconductor device according to claim 1, wherein: The acceptor impurity magnesium ions of the cap layer are combined with the implanted hydrogen plasma to form the passivation layer containing a magnesium-hydrogen complex.

9. The nitride semiconductor device according to claim 1, wherein: The material of the substrate is selected from one of gallium nitride, silicon, silicon carbide and sapphire; and / or The material of the channel layer is gallium nitride; and / or The material of the barrier layer is aluminum gallium nitride.

10. The nitride semiconductor device according to claim 1, wherein: It also includes a two-dimensional electron gas layer, which is formed on a side of the contact surface between the channel layer and the barrier layer that is biased toward the channel layer, and the source electrode and the drain electrode are electrically connected via the two-dimensional electron gas layer.

11. The nitride semiconductor device according to claim 10, characterized in that: It also includes a second buffer layer, which is located between the substrate and the channel layer; wherein, The material of the second buffer layer is carbon-doped gallium nitride.

12. The nitride semiconductor device according to claim 11, characterized in that: It also includes a nucleation layer, which is located between the substrate and the second buffer layer; wherein, The material of the nucleation layer is aluminum nitride.

13. The nitride semiconductor device according to claim 1, wherein: Also includes a source metal interconnection layer, a drain metal interconnection layer and a gate metal interconnection layer; The source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer are formed on the top of the source electrode, the drain electrode and the gate layer respectively; It also includes a source metal pad, a drain metal pad and a gate metal pad, wherein the source metal pad, the drain metal pad and the gate metal pad are formed on the top of the source metal interconnection layer, the drain metal interconnection layer and the gate metal interconnection layer respectively.

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