Asymmetric trench gate silicon carbide VDMOS

Abstract

The utility model provides an asymmetric trench gate silicon carbide VDMOS. The asymmetric trench gate silicon carbide VDMOS is characterized in that the lower side surface of a freewheeling region is connected to the upper side surface of a drift layer, and the lower side surface of a well region is connected to the upper side surface of the freewheeling region; the lower side surface of the first P-type source region is connected to the upper side surface of the drift layer; the right side of the first P-type source region is connected with the left side of the freewheeling region and the left side of the well region; the lower side surface of the second P-type source region is connected to the upper side surface of the drift layer; the left side surface of the second P-type source region is connected to the right side surface of the freewheeling region; the lower side surface of the N-type source region is connected with the upper side surface of the well region and the second P-type source region; the lower side surface of the gate dielectric layer is connected to the second P-type source region; the side surface of the gate dielectric layer is respectively connected with the well region, the N-type source region and the second P-type source region; a groove is formed in the gate dielectric layer; the gate metal layer is arranged in the groove; the source metal layer is respectively connected to the first P-type source region, the second P-type source region and the N-type source region; under the condition of ensuring low on-resistance of the device, the large follow current capability and the on-resistance of the body diode can be realized at the same time.

Description

Technical Field

[0001] The utility model relates to an asymmetric trench gate silicon carbide VDMOS. Background Art

[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. In some new power topology applications, the device on-resistance is concerned while the device is required to have a large body diode freewheeling capability and small body diode loss; however, the body diode freewheeling capability of existing silicon carbide power devices does not meet the requirements, or when it meets the requirements, the body diode loss also increases. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide an asymmetric trench gate silicon carbide VDMOS, which can achieve both large body diode freewheeling capability and on-resistance under the condition of ensuring low on-resistance of the device.

[0004] The utility model is implemented as follows: an asymmetric trench gate silicon carbide VDMOS, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;

[0007] A freewheeling region, wherein the lower side of the freewheeling region is connected to the upper side of the drift layer,

[0008] A well region, wherein the lower side of the well region is connected to the upper side of the freewheeling region;

[0009] A first P-type source region and a lower side surface of the first P-type source region are connected to an upper side surface of the drift layer; a right side surface of the first P-type source region is respectively connected to a left side surface of the freewheeling region and a left side surface of the well region;

[0010] A second P-type source region, wherein a lower side surface of the second P-type source region is connected to an upper side surface of the drift layer, and a left side surface of the second P-type source region is connected to a right side surface of the freewheeling region;

[0011] An N-type source region, wherein the lower side of the N-type source region is respectively connected to the upper side of the well region and the second P-type source region;

[0012] A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the second P-type source region, and the side surfaces of the gate dielectric layer are respectively connected to the well region, the N-type source region and the second P-type source region; a groove is provided in the gate dielectric layer;

[0013] A gate metal layer, wherein the gate metal layer is disposed in the groove;

[0014] A source metal layer, the source metal layer being connected to the first P-type source region, the second P-type source region and the N-type source region respectively;

[0015] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0016] The advantages of the utility model are:

[0017] 1. The device adopts an asymmetric trench device structure. By designing the position of the P-type source region on one side, the gate reliability problem caused by the electric field concentration at the corner of the device gate can be effectively suppressed;

[0018] Second, the P-type source regions on both sides of the device are extended downward to reduce the on-resistance of the body diode introduced by the low doping concentration of the P-type well region, which can reduce the freewheeling loss of the device body diode;

[0019] 3. In the single-sided conduction structure of the device, a longitudinal N-type source region-P-type well region-N-type freewheeling region structure is constructed. The N-type source region forms an ohmic contact with the source metal to reduce the contact resistance. The P-type well region is used to control the on and off of the device by the gate. The N-type freewheeling region is used to suppress the expansion of the pn junction space charge region of the P-type source region to the conductive channel, thereby reducing the on-resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0021] Figure 1 The utility model is a schematic diagram of an asymmetric trench gate silicon carbide VDMOS.

[0022] Figure 2 The utility model is a flow chart of a method for preparing an asymmetric trench gate silicon carbide VDMOS.

[0023] Figure 3 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 1 .

[0024] Figure 4 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 2 .

[0025] Figure 5 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 3 .

[0026] Figure 6 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 4 .

[0027] Figure 7 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 5 .

[0028] Figure 8 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 6 .

[0029] Fig. 9 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 7 .

[0030] Fig.10 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 8 .

[0031] Fig.11 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 9 .

[0032] Fig.12 This is a cross-sectional view of the process of an asymmetric trench gate silicon carbide VDMOS of the utility model. Figure 10 . DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] like Figure 1 As shown, the embodiment of the present application provides an asymmetric trench gate silicon carbide VDMOS, including:

[0039] Silicon carbide substrate 101,

[0040] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101;

[0041] A freewheeling region 103, wherein the lower side of the freewheeling region 103 is connected to the upper side of the drift layer 102, and the thickness of the freewheeling region is 300 nm;

[0042] A well region 104, wherein the lower side of the well region 104 is connected to the upper side of the freewheeling region 103;

[0043] A first P-type source region 105, wherein the lower side of the first P-type source region 105 is connected to the upper side of the drift layer 102; the right side of the first P-type source region 105 is respectively connected to the left side of the freewheeling region 103 and the left side of the well region 104;

[0044] A second P-type source region 106 , wherein the lower side of the second P-type source region 106 is connected to the upper side of the drift layer 102 , and the left side of the second P-type source region 106 is connected to the right side of the freewheeling region 103 ;

[0045] An N-type source region 107, wherein the lower side of the N-type source region 107 is respectively connected to the upper side of the well region 104 and the second P-type source region 106;

[0046] A gate dielectric layer 108, wherein the lower side of the gate dielectric layer 108 is connected to the second P-type source region 106, and the side surfaces of the gate dielectric layer 108 are respectively connected to the well region 104, the N-type source region 107 and the second P-type source region 106; a groove 1081 is provided in the gate dielectric layer 108, and the lower side surface of the well region 104 and the lower side surface of the gate dielectric layer 108 are located in the same plane;

[0047] A gate metal layer 109, wherein the gate metal layer 109 is disposed in the groove 1081;

[0048] A source metal layer 110, wherein the source metal layer 110 is respectively connected to the first P-type source region 105, the second P-type source region 106 and the N-type source region 107;

[0049] and a drain metal layer 111 , wherein the drain metal layer 111 is connected to the lower side of the silicon carbide substrate 101 .

[0050] like Figures 2 to 12 As shown, the method for preparing the silicon carbide VDMOS comprises the following steps:

[0051] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 111; epitaxially growing a drift layer 102 on the upper side of the silicon carbide substrate 101;

[0052] Step 2: forming a barrier layer a on the upper part of the drift layer 102, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 102 to form a first P-type source region 105 and a second P-type source region 106, respectively, with an ion implantation energy of 100-400 keV;

[0053] Step 3, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, and performing ion implantation into the drift layer 102 to form a freewheeling region 103, with the ion implantation energy being 300-400kev;

[0054] Step 4: using ion implantation to form a P-type well region 104 in the drift layer 102, the ion implantation energy is 200-300kev;

[0055] Step 5: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, and use ion implantation to form an N-type source region 107 in the drift layer 102 and the second P-type source region 106, with an ion implantation energy of 100-200 keV;

[0056] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, etch the drift layer 102 and the second P-type source region 106 to form a groove 112, the etching depth is 900nm, and dry oxygen oxidize the groove 112 to form a gate dielectric layer 108;

[0057] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, depositing metal, and forming a gate metal layer 109;

[0058] Step 8: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a through hole, etch the drift layer 102 to a depth of 300 nm, deposit metal, and form a source metal layer 110.

[0059] The doping concentration of the silicon carbide substrate 101 is 2e18cm -3 The doping concentration of the drift layer 102 is 5e16cm -3 The doping concentration of the first P-type source region 105 and the second P-type source region 106 is 2e18cm -3 The doping concentration of the freewheeling region 103 is 8e18cm -3 The doping concentration of the well region 104 is 1e17 cm -3 The well region is N-type, and the doping concentration of the N-type source region 107 is 5e18cm -3, the lower side of the well region 104 and the lower side of the gate dielectric layer 108 are located in the same plane; the gate dielectric layer 108 is silicon dioxide, the gate, the source metal layer 110 and the drain metal layer 109 are all Al. The thickness of the N-type silicon carbide substrate 101 of the device is 600nm, the thickness of the N-type drift layer 102 is 10-20μm, the thickness of the first P-type source region 105 is 900nm, the thickness of the N-type source region 107 is 300nm, the thickness of the N-type freewheeling region 103 is 300nm, the thickness of the P-type well region 104 is 300nm, and the thickness of the source metal layer 110 is 300nm; the bottom thickness of the gate dielectric layer is 30nm, and the side wall thickness is 20nm; the gate metal layer thickness is 900nm, and the device withstand voltage is 800-1200V; N-type silicon carbide substrate The doping concentration of 101 is to form a low-resistance ohmic contact with the drain metal layer 111 to reduce the on-resistance of the device. Its thickness is based on the design conditions of the device epitaxial thickness (N-type drift layer 102) to ensure support and improve process stability. The thickness and doping concentration of the N-type drift layer 102 are a compromise between on-resistance and withstand voltage. The first P-type source region 105 and the second P-type source region 106 are designed to protect the device gate dielectric layer 108 to achieve body diode performance improvement. The N-type freewheeling region 103 is to reduce the on-resistance of the device. The gate design is to ensure the gate control capability of the device.

[0060] The second P-type source region 106 is designed to form a P-type doped region at the bottom of the device gate dielectric layer 108, thereby protecting the electric field concentration at the corner of the device gate and suppressing the damage to the gate dielectric caused by voltage and current overshoots at the device drain.

[0061] The first P-type source region 105 and the second P-type source region 106 are both extended downward to the same height as the bottom of the N-type freewheeling region 103, which can reduce the problem of large on-resistance of the P-type well region 104 due to low doping concentration during body diode freewheeling, thereby reducing the body diode freewheeling loss of the device;

[0062] In the single-sided conduction structure of the device, a longitudinal N-type source region 107-P-type well region 104-N-type freewheeling region 103 structure is constructed. The N-type source region 107 forms an ohmic contact with the source metal layer 110 to reduce the contact resistance. The P-type well region 104 is used to control the on and off of the device by the gate. The N-type freewheeling region 103 is used to suppress the expansion of the pn junction space charge region of the first P-type source region 105 to the conductive channel, thereby reducing the on-resistance of the device.

[0063] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. An asymmetric trench gate silicon carbide VDMOS, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; A freewheeling region, wherein the lower side of the freewheeling region is connected to the upper side of the drift layer, A well region, wherein the lower side of the well region is connected to the upper side of the freewheeling region; A first P-type source region and a lower side surface of the first P-type source region are connected to an upper side surface of the drift layer; a right side surface of the first P-type source region is respectively connected to a left side surface of the freewheeling region and a left side surface of the well region; A second P-type source region, wherein a lower side surface of the second P-type source region is connected to an upper side surface of the drift layer, and a left side surface of the second P-type source region is connected to a right side surface of the freewheeling region; An N-type source region, wherein the lower side of the N-type source region is respectively connected to the upper side of the well region and the second P-type source region; A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the second P-type source region, and the side surfaces of the gate dielectric layer are respectively connected to the well region, the N-type source region and the second P-type source region; and a groove is provided in the gate dielectric layer; A gate metal layer, wherein the gate metal layer is disposed in the groove; A source metal layer, the source metal layer being connected to the first P-type source region, the second P-type source region and the N-type source region respectively; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. The asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the freewheeling region is 300 nm.

3. The asymmetric trench gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side surface of the well region and the lower side surface of the gate dielectric layer are located in the same plane.

Images