Display panel and display terminal

Abstract

The utility model discloses a display panel and a display terminal. The display panel comprises a substrate and a thin film transistor arranged on one side of the substrate, the thin film transistor comprises an active part, a gate insulating layer and a grid electrode, and the active part comprises a main body part and edge parts arranged at the two ends of the main body part; the gate insulating layer is arranged on one side of the active part; the grid electrode is arranged on the surface of the side, away from the active part, of the grid insulating layer, the orthographic projection of the grid electrode on the active part overlaps with the active part, the grid electrode is provided with at least one opening, and the side wall of the opening is aligned with the edge part. The opening is formed in the position, corresponding to the edge part, of the gate, and no gate voltage exists at the opening, so that the transistor corresponding to the edge part corresponding to the opening is prevented from being opened, the hump effect is improved, and the charging capacity of the circuit is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] There is a hump effect in thin film transistors, that is, the main area and edge area of ​​the active layer of the thin film transistor have different threshold voltages. The threshold voltage of the active layer in the edge area is more negative than the threshold voltage of the active layer in the main area, which causes the current of the thin film transistor to decrease within the operating voltage range, affecting the charging capacity of the circuit.

[0003] Therefore, it is urgent to improve the above technical problems. Utility Model Content

[0004] The present application provides a display panel and a display terminal to improve the technical problem that the current of a thin film transistor decreases within an operating voltage range, thereby affecting the charging capacity of the thin film transistor.

[0005] To solve the above technical problems, the technical solutions provided by this application are as follows:

[0006] The present application provides a display panel, the display panel comprising a substrate and a thin film transistor disposed on one side of the substrate, the thin film transistor comprising:

[0007] The active part includes a main body and edge parts arranged at two ends of the main body;

[0008] A gate insulating layer, disposed on one side of the active portion;

[0009] The gate is arranged on the surface of the gate insulating layer away from the active part, the orthographic projection of the gate on the active part overlaps with the active part, and the gate is provided with at least one opening, and the side wall of the opening is arranged in alignment with the edge part.

[0010] In the display panel of the present application, the orthographic projection of the side wall of the opening on the substrate does not overlap with the main body.

[0011] In the display panel of the present application, the main body portion and the edge portion are arranged along a first direction, and in the first direction, the length of the opening is greater than or equal to the length of the edge portion;

[0012] The width of the opening is greater than or equal to half of the width of the gate and smaller than the width of the gate.

[0013] In the display panel of the present application, the edge portions at both ends are respectively a first edge portion and a second edge portion, and the opening includes a first sub-opening corresponding to the first edge portion and a second sub-opening corresponding to the second edge portion.

[0014] In the display panel of the present application, the shape of the first sub-opening is different from the shape of the second sub-opening.

[0015] In the display panel of the present application, the area of ​​the first sub-opening is the same as the area of ​​the second sub-opening.

[0016] In the display panel of the present application, the gate insulating layer includes a first sublayer and a second sublayer stacked together, and the second sublayer is arranged on a side of the first sublayer close to the gate electrode;

[0017] The second sub-layer is provided with a through hole corresponding to the opening, the opening is connected to the through hole, and the number of positive charges in the second sub-layer is greater than the number of positive charges in the first sub-layer.

[0018] In the display panel of the present application, the material of the first sub-layer is silicon oxide, and the material of the second sub-layer is silicon nitride.

[0019] In the display panel of the present application, the active portion includes a channel portion and doping portions disposed at both ends of the channel portion, and ions doped in the channel portion corresponding to the opening are the same as ions doped in the doping portions.

[0020] The present application also provides a display terminal, which includes the above-mentioned display panel.

[0021] Beneficial effects: The present application discloses a display panel and a display terminal. The display panel includes a substrate and a thin film transistor arranged on one side of the substrate, the thin film transistor includes an active part, a gate insulating layer and a gate, the active part includes a main body and edge parts arranged at both ends of the main body; the gate insulating layer is arranged on one side of the active part; the gate is arranged on the surface of the gate insulating layer away from the active part, the orthographic projection of the gate on the active part overlaps with the active part, the gate is provided with at least one opening, and the side wall of the opening is arranged in alignment with the edge part. The present application arranges an opening at the position of the edge part corresponding to the gate, and there is no gate voltage at the opening, thereby avoiding turning on the transistor corresponding to the edge part corresponding to the opening, thereby improving the hump effect and enhancing the charging capacity of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0023] Figure 1 A schematic diagram of a top view structure of a display panel provided in an embodiment of the present application;

[0024] Figure 2 for Figure 1 A schematic diagram of an amplified structure of a thin film transistor;

[0025] Figure 3 for Figure 2 A schematic diagram of a cross-sectional structure at AA;

[0026] Figure 4 for Figure 2 A schematic diagram of a cross-sectional structure at BB;

[0027] Figure 5 for Figure 1 A schematic diagram of an enlarged structure of another thin film transistor;

[0028] Figure 6 for Figure 1 A schematic diagram of an enlarged structure of another thin film transistor;

[0029] Figure 7 for Figure 2 A schematic diagram of a cross-sectional structure at AA;

[0030] Figure 8 for Figure 2 Another schematic diagram of the cross-sectional structure at BB

[0031] Fig. 9 A comparison diagram of the transfer characteristic curve of the embodiment of the present application and the transfer characteristic curve of the comparative example;

[0032] Fig.10 A schematic diagram of the structure of a display terminal provided in an embodiment of the present application.

[0033] Description of reference numerals:

[0034] Display panel 1, display area AA, non-display area NA, substrate 10, thin film transistor 20, active portion 21, source contact portion 211, drain contact portion 212, doped portion 213, channel portion 214, main body 21a, edge portion 21b, first side portion 2110, second side portion 2120, gate insulating layer 22, first sub-layer 221, second sub-layer 222, through hole 22a, gate 23, opening 23a, width W1 of opening 23a, width W2 of gate 23, first sub-opening 231a, second sub-opening 232a, source 24, drain 25, light shielding portion 30, pixel electrode 40, second direction D2, first direction D1, display terminal 2, terminal body 3. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0036] The present application provides a display panel 1, such as Figures 1 to 4 As shown, the display panel 1 includes a substrate 10 and a thin film transistor 20 arranged on one side of the substrate 10, the thin film transistor 20 includes an active portion 21, a gate insulating layer 22 and a gate 23, the active portion 21 includes a main body portion 21a and edge portions 21b arranged at both ends of the main body portion 21a; the gate insulating layer 22 is arranged on one side of the active portion 21; the gate 23 is arranged on the surface of the gate insulating layer 22 away from the active portion 21, the orthographic projection of the gate 23 on the active portion 21 overlaps with the active portion 21, and the gate 23 is provided with at least one opening 23a, and the side wall of the opening 23a is arranged in alignment with the edge portion 21b.

[0037] In this embodiment, the display panel 1 may be an LCD panel, an OLED panel, a Mini-LED panel, a Micro-LED panel, etc.

[0038] In this embodiment, the substrate 10 may be a rigid substrate or a flexible substrate. The material of the rigid substrate includes a glass substrate, a quartz substrate or a silicon wafer, etc., and the material of the flexible substrate includes one of colorless polyimide (PI), polycarbonate (PC), polynorbornene (PNB) and polyethylene terephthalate (PET), etc.

[0039] In this embodiment, if Figure 1 As shown, the display panel 1 includes a display area AA and a non-display area NA arranged on at least one side of the display area AA. The display area AA is provided with a plurality of sub-pixels (not shown in the figure), and the display area AA is used to display images. The non-display area NA is provided with a gate drive circuit, etc., and the gate drive circuit is used to drive the sub-pixels of the display area AA to display. The thin film transistor 20 can be located in the display area AA or the non-display area NA, and this application does not limit this.

[0040] In this embodiment, the thin film transistor 20 includes an active portion 21. The material of the active portion 21 can be single crystal silicon, low temperature polysilicon, oxide semiconductor, etc.

[0041] In this embodiment, if Figure 3 As shown, the active portion 21 may include a channel portion 214 and a source contact portion 211 and a drain contact portion 212 disposed at both ends of the channel portion 214, a doping portion 213 may be disposed between the source contact portion 211 and the channel portion 214, and a doping portion 213 may be disposed between the drain contact portion 212 and the channel portion 214. The doping portion 213 may be lightly doped with phosphorus ions (Lightly Doped Drain, LDD), but is not limited thereto.

[0042] The thin film transistor 20 includes a source 24 and a drain 25, a source contact 211 is electrically connected to the source 24, and a drain contact 212 is electrically connected to the drain 25. In order to make the source contact 211 form an ohmic contact with the source 24 and the drain contact 212 form an ohmic contact with the drain 25, the source contact 211 and the drain contact 212 may be heavily doped with phosphorus ions, but the present invention is not limited thereto.

[0043] In this embodiment, if Figure 2 and Figure 3 As shown, the main body 21a of the active part 21 extends in the direction from the source 24 to the drain 25, and the main body 21a is arranged in the middle area of ​​the active part 21. For the convenience of description, the arrangement direction of the edge part 21b and the main body 21a is referred to as the first direction D1, and the direction from the source 24 to the drain 25 is referred to as the second direction D2. The second direction D2 can be perpendicular to the first direction D1 or at an acute angle. The main body 21a extends along the second direction D2, and one end of the main body 21a is electrically connected to the source 24, and the other end is electrically connected to the drain 25. The second direction D2 is the channel length direction.

[0044] like Figure 2 As shown, the edge portion 21b is disposed at both ends of the main body 21a, and the edge portion 21b also extends along the second direction D2, and the edge portion 21b is located in the edge area of ​​the active part 21, and the edge area is disposed adjacent to the middle area. That is to say, the main body 21a and the edge portion 21b can be disposed in contact.

[0045] In this embodiment, the gate insulating layer 22 is disposed between the gate 23 and the active portion 21. The material of the gate insulating layer 22 can be a stack of one or more layers of silicon nitride, silicon oxide, silicon oxynitride, etc. The gate insulating layer 22 can be disposed as a whole layer or in a patterned manner. When the gate insulating layer 22 is disposed in a patterned manner, the gate insulating layer 22 at least covers the active portion 21.

[0046] In this embodiment, the gate 23 is disposed on the surface of the gate insulating layer 22 facing away from the substrate 10. The orthographic projection of the gate 23 on the substrate 10 overlaps with the orthographic projection of the channel portion 214 on the substrate 10. The orthographic projection of the gate 23 on the substrate 10 is disposed between the orthographic projections of the source contact portion 211 and the drain contact portion 212 on the substrate 10. That is to say, the orthographic projection of the gate 23 on the substrate 10 overlaps with the orthographic projection of the main portion 21a on the substrate 10, and the orthographic projection of the gate 23 on the substrate 10 overlaps with the orthographic projection of the edge portion 21b on the substrate 10.

[0047] In this embodiment, the gate 23 is provided with at least one opening 23a, and the sidewall of the opening 23a is arranged in alignment with the edge portion 21b. Since the thin film transistor 20 includes edge portions 21b located at both ends of the main body portion 21a, that is, the number of edge portions 21b is two. When the gate 23 is provided with one opening 23a, the opening 23a can be arranged corresponding to one of the two edge portions 21b. When the gate 23 is provided with two openings 23a, the two openings 23a can be respectively arranged corresponding to the same edge portion 21b or corresponding to different edge portions 21b, and the present application does not limit this.

[0048] In this embodiment, the shape of the opening 23a can be a regular pattern or an irregular pattern. When the shape of the opening 23a is a regular pattern, the difficulty of the patterning process can be reduced. Optionally, the shape of the opening 23a can match the shape of the edge portion 21b, so that the opening 23a exposes a larger area of ​​the edge portion 21b without affecting the function of the main body 21a. For example, the shape of the opening 23a can be rectangular, elliptical, trapezoidal, etc.

[0049] The sidewall of the opening 23a is aligned with the edge portion 21b, which means that the opening 23a at least exposes a portion of the edge portion 21b, that is, the orthographic projection of the opening 23a on the substrate 10 partially overlaps with the orthographic projection of the edge portion 21b on the substrate 10.

[0050] In this embodiment, the thin film transistor 20 may be a top-gate transistor or a bottom-gate transistor. The top-gate transistor is used as an example for description in this application, which should not be construed as a limitation to this application.

[0051] In this embodiment, the material of the gate 23 can be any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0052] Due to the influence of the patterning process, the side wall of the active portion 21 forms a taper angle with the supporting surface of the substrate 10. The patterning process includes coating photoresist, exposure and development, etching, etc. The patterning process causes the edge portion 21b to include an inclined surface, and the inclined surface forms an acute angle with the supporting surface of the substrate 10. The thickness of the edge portion 21b is less than or equal to the thickness of the main portion 21a, and the threshold voltage of the transistor corresponding to the edge portion 21b is less than the threshold voltage of the transistor corresponding to the main portion 21a, that is, the edge portion 21b is easier to turn on under the same gate voltage.

[0053] That is to say, the characteristics of the transistor corresponding to the edge portion 21b are different from those of the transistor corresponding to the main portion 21a, and the thin film transistor 20 can be regarded as a transistor corresponding to the edge portion 21b and a transistor corresponding to the main portion 21a connected in parallel, resulting in a hump effect. The hump effect reduces the current of the thin film transistor 20 in the working range and reduces the charging capacity of the circuit.

[0054] The bearing surface of the substrate 10 refers to a surface of the substrate 10 close to the thin film transistor 20 . The thickness refers to a dimension in a direction perpendicular to the bearing surface of the substrate 10 .

[0055] It should be understood that, in theory, the thickness of the edge portion 21b is less than the thickness of the main body 21a, that is, the cross-sectional shape of the edge portion 21b is a triangle. However, due to the influence of process accuracy, the cross-sectional shape of the edge portion 21b may be a right-angled trapezoid, in which case the thickness of the portion of the edge portion 21b close to the main body 21a is consistent with the thickness of the main body 21a.

[0056] In this embodiment, if Figure 3 As shown, the display panel 1 includes a pixel electrode 40, and the pixel electrode 40 is electrically connected to the drain electrode 25. The thin film transistor 20 provides a driving voltage for the pixel electrode 40.

[0057] In this embodiment, if Figure 2 and Figure 3 As shown, the display panel 1 includes a light shielding portion 30, which is disposed on a side of the active portion 21 close to the substrate 10, and the orthographic projection of the channel portion 214 on the substrate 10 is located within the orthographic projection of the light shielding portion 30 on the substrate 10. The light shielding portion 30 is used to shield light incident from one side of the substrate 10 to prevent the light from affecting the electrical properties of the thin film transistor 20.

[0058] In the display panel 1 of the present application, Figure 2 As shown, the orthographic projection of the side wall of the opening 23 a on the substrate 10 does not overlap with the main body 21 a , thereby preventing the setting of the opening 23 a from affecting the performance of the transistor corresponding to the main body 21 a .

[0059] Optionally, in this embodiment, the orthographic projection of a portion of the sidewall of the opening 23 a on the active portion 21 may not overlap with the active portion 21 , thereby increasing the size of the opening 23 a and reducing the difficulty of the process.

[0060] In the display panel 1 of the present application, the main body portion 21 a and the edge portion 21 b are arranged along the first direction D1 , and in the first direction D1 , the length of the opening 23 a is greater than or equal to the length of the edge portion 21 b .

[0061] In this embodiment, the first direction D1 is the length direction. Through the above configuration, the size of the opening 23a in the first direction D1 can be increased, so that the edge portion 21b with a larger area is not controlled by the voltage of the gate 23 and is turned on, thereby reducing the influence of the hump effect.

[0062] In the display panel 1 of the present application, Figure 2 As shown, the main body 21 a and the edge 21 b are arranged along the first direction D1 , the gate 23 extends along the first direction D1 , and the width W1 of the opening 23 a is greater than or equal to half of the width W2 of the gate 23 and less than the width W2 of the gate 23 .

[0063] In this embodiment, the gate 23 extends along a first direction D1 , and a direction perpendicular to the first direction D1 is a width W2 direction of the gate 23 .

[0064] By making the width W1 of the opening 23a greater than or equal to half the width W2 of the gate 23, that is, W1≥(W2) / 2, the size of the opening 23a in the second direction D2 can be increased, so that the edge portion 21b with a larger area is not controlled by the voltage of the gate 23 and is turned on, thereby reducing the impact of the hump effect.

[0065] In the display panel 1 of the present application, Figure 2 As shown, the edge portions 21b at both ends are respectively a first edge portion 2110 and a second edge portion 2120 , and the opening 23a includes a first sub-opening 231a corresponding to the first edge portion 2110 and a second sub-opening 232a corresponding to the second edge portion 2120 .

[0066] In this embodiment, the first sub-opening 231a is disposed corresponding to the first side portion 2110. The first sub-opening 231a is used to open the first side portion 2110 without being controlled by the voltage of the gate 23, thereby reducing the influence of the hump effect.

[0067] In this embodiment, the second sub-opening 232a is disposed corresponding to the second side portion 2120. The second sub-opening 232a is used to open the second side portion 2120 without being controlled by the voltage of the gate 23, thereby reducing the influence of the hump effect.

[0068] In the display panel 1 of the present application, Figure 5 and Figure 6As shown, the shape of the first sub-opening 231a is different from the shape of the second sub-opening 232a. The shapes of the first sub-opening 231a and the second sub-opening 232a can be set as needed. Figure 5 As shown, the first sub-opening 231a and the second sub-opening 232a may both be rectangular, and the rectangles have different lengths and widths. Figure 6 As shown, the first sub-opening 231a may be elliptical, and the second sub-opening 232a may be trapezoidal.

[0069] It should be noted that the maximum width of the first sub-opening 231 a and the second sub-opening 232 a is smaller than the width W2 of the gate 23 , so as to avoid disconnection of the gate 23 .

[0070] Optionally, in some embodiments, Figure 2 As shown, the shape of the first sub-opening 231a is the same as the shape of the second sub-opening 232a. The first sub-opening 231a and the second sub-opening 232a may be symmetrically arranged about the center line of the active part 21, but are not limited thereto.

[0071] Optionally, in some embodiments, Figure 2 As shown, the area of ​​the first sub-opening 231a is the same as the area of ​​the second sub-opening 232a. The first sub-opening 231a and the second sub-opening 232a may be symmetrically arranged about the center line of the active part 21, but are not limited thereto.

[0072] In the display panel 1 of the present application, Figure 7 and Figure 8 , which shows a cross-sectional structure of another display panel. The gate insulating layer 22 includes a stacked first sublayer 221 and a second sublayer 222, the second sublayer 222 is disposed on a side of the first sublayer 221 close to the gate 23; the second sublayer 222 is provided with a through hole 22a corresponding to the opening 23a, the opening 23a is connected to the through hole 22a, and the number of positive charges in the second sublayer 222 is greater than the number of positive charges in the first sublayer 221.

[0073] In this embodiment, the first sublayer 221 and the second sublayer 222 are at least disposed between the gate 23 and the active portion 21. The second sublayer 222 is provided with a through hole 22a communicating with the opening 23a, while the first sublayer 221 is not provided with the opening 23a.

[0074] In this embodiment, the shape of the opening 23 a may be the same as that of the through hole 22 a , so that the opening 23 a and the through hole 22 a are formed by using the same photomask, thereby simplifying the manufacturing process of the display panel 1 .

[0075] In this embodiment, since the number of positive charges in the second sublayer 222 is greater than the number of positive charges in the first sublayer 221, the positive charges in the second sublayer 222 can make the threshold voltage of the transistor corresponding to the main body 21a biased negative, and the edge portion 21b is provided with a through hole 22a, that is, the second sublayer 222 is not provided, which can reduce the degree of negative bias of the threshold voltage of the transistor corresponding to the edge portion 21b. Through the above arrangement, the threshold voltage of the transistor corresponding to the main body 21a can be close to that of the transistor corresponding to the edge portion 21b, thereby reducing the impact of the hump effect.

[0076] Optionally, in some embodiments, the shape of the opening 23a may be different from that of the through hole 22a. The width of the through hole 22a in the second direction D2 may be greater than the width W1 of the opening 23a, so that the through hole 22a exposes more edge portions 21b, further reducing the degree to which the threshold voltage of the transistor corresponding to the edge portion 21b is biased negative.

[0077] In the display panel 1 of the present application, the material of the first sub-layer 221 is silicon oxide, and the material of the second sub-layer 222 is silicon nitride.

[0078] In this embodiment, due to the influence of the process technology, the formed silicon nitride film layer will contain positive charges. The positive charges in the silicon nitride film layer will cause the threshold voltage of the thin film transistor 20 to be negative. By providing a silicon nitride film layer in the transistor corresponding to the main body 21a, the threshold voltage of the transistor corresponding to the main body 21a can be made negative. The threshold voltage of the transistor corresponding to the edge portion 21b will also be negative due to the hump effect. Through the above-mentioned arrangement, the threshold voltage of the transistor corresponding to the main body 21a can be close to that of the transistor corresponding to the edge portion 21b, thereby reducing the influence of the hump effect.

[0079] In the display panel 1 of the present application, the active portion 21 includes a channel portion 214 and doped portions 213 disposed at both ends of the channel portion 214 , and ions doped in the channel portion 214 corresponding to the opening 23 a are the same as ions doped in the doped portion 213 .

[0080] In this embodiment, ion doping is performed after the gate 23 is formed. After the active portion 21 is ion doped, a doped portion 213 is formed. The doped portion 213 can be lightly doped with phosphorus ions. Since the active portion 21 corresponding to the opening 23a is not blocked, the active portion 21 corresponding to the opening 23a is also lightly doped with phosphorus ions.

[0081] In this embodiment, the channel portion 214 covered by the gate 23 may be lightly doped with boron ions. That is, the ions doped in the channel portion 214 corresponding to the gate 23 and the ions doped in the channel portion 214 corresponding to the opening 23 a may be different.

[0082] In order to illustrate the effect of the embodiment of the present application, the inventor proposes a comparative example. The difference between the comparative example and the embodiment of the present application is that the gate 23 of the comparative example is not provided with an opening 23a.

[0083] Fig. 9 The figure is a comparison of the transfer characteristic curve of the thin film transistor 20 of the embodiment of the present application and the transfer characteristic curve of the thin film transistor 20 of the comparative example. The horizontal axis is the gate 23 voltage Vgs of the thin film transistor 20, in volts; the vertical axis is the logarithmic form of the source-drain current Ids of the thin film transistor 20, in amperes. Among them, curve S1, curve S2, and curve S3 are the transfer curves of the thin film transistor 20 when Vd is 0.1 volts, and curve S4, curve S5, and curve S6 are the transfer curves of the thin film transistor 20 when Vd is 10 volts. Curves S1 and curve S4 are the transfer curves of the comparative example, and curves S2 and curve S5 are Figure 4 The transfer curves of the embodiment, curve S3 and curve S6 are Figure 8 The transfer curve of the embodiment. Figure 4 Examples and Figure 8 The difference between the embodiments is only the arrangement of the gate insulating layer 22.

[0084] The working range of the thin film transistor 20 is Fig. 9 The range between the two dotted lines in FIG. 1 , that is, the operating voltage of the thin film transistor 20 is between 2V and 5V. Fig. 9 It can be seen that within the working range, the curves S1 and S4 of the comparative example are concave downward, that is, the current decreases, resulting in a decrease in charging capacity. However, within the working range, the concave degree of the curves S2, S3, S5 and S6 of the embodiment is improved, that is, the current increases, improving the charging capacity.

[0085] That is to say, compared with the curve S1 and curve S4 of the comparative example, the thin film transistor 20 of the embodiment of the present application has a larger current in the working interval, which improves the charging capacity of the circuit. In the embodiment, the current increase in the working interval of curve S3 and curve S6 is greater than that of another embodiment, which can further improve the charging capacity of the circuit. Curve S3 and curve S6 correspond to Fig. 9 The embodiment shows that the hump effect is better improved by setting the first sub-layer 221 and the second sub-layer 222.

[0086] like Fig.10 As shown, the present application also provides a display terminal 2, and the display terminal 2 includes the above-mentioned display panel 1.

[0087] In this embodiment, the display terminal 2 includes a display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one body.

[0088] In this embodiment, the display terminal 2 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0089] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0090] The display panel 1 and the display terminal provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a substrate and a thin film transistor arranged on one side of the substrate, wherein the thin film transistor comprises: The active part includes a main body and edge parts arranged at two ends of the main body; A gate insulating layer, disposed on one side of the active portion; The gate is arranged on the surface of the gate insulating layer away from the active part, the orthographic projection of the gate on the active part overlaps with the active part, and the gate is provided with at least one opening, and the side wall of the opening is arranged in alignment with the edge part.

2. The display panel according to claim 1, characterized in that: An orthographic projection of a side wall of the opening on the substrate does not overlap with the main body.

3. The display panel according to claim 2, characterized in that: The main body portion and the edge portion are arranged along a first direction, and in the first direction, the length of the opening is greater than or equal to the length of the edge portion; The width of the opening is greater than or equal to half of the width of the gate and smaller than the width of the gate.

4. The display panel according to claim 1, characterized in that: The edge portions at both ends are respectively a first side portion and a second side portion, and the opening comprises a first sub-opening corresponding to the first side portion and a second sub-opening corresponding to the second side portion.

5. The display panel according to claim 4, characterized in that: The shape of the first sub-port is different from the shape of the second sub-port.

6. The display panel according to claim 4, characterized in that: The area of ​​the first sub-port is the same as the area of ​​the second sub-port.

7. The display panel according to claim 1, characterized in that: The gate insulating layer comprises a first sublayer and a second sublayer stacked together, wherein the second sublayer is arranged on a side of the first sublayer close to the gate; The second sub-layer is provided with a through hole corresponding to the opening, the opening is connected to the through hole, and the number of positive charges in the second sub-layer is greater than the number of positive charges in the first sub-layer.

8. The display panel according to claim 7, characterized in that: The material of the first sub-layer is silicon oxide, and the material of the second sub-layer is silicon nitride.

9. The display panel according to any one of claims 1 to 8, characterized in that: The active portion includes a channel portion and doping portions disposed at two ends of the channel portion, and ions doped in the channel portion corresponding to the opening are the same as ions doped in the doping portions.

10. A display terminal, characterized in that: The display terminal comprises the display panel according to any one of claims 1 to 9.

Images