Self-aligned silicon carbide MOSFET device

Abstract

The utility model discloses a self-aligned silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device, which relates to the technical field of semiconductor power devices and comprises a drain electrode, a silicon carbide substrate arranged above the drain electrode, a gate electrode arranged between two conductive source areas, a gate oxide layer and a mask layer arranged in the gate electrode, the gate oxide layer is in contact with the mask layer, a conductive channel region is arranged between the gate electrode and the conductive base region, and triangular grooves are formed in the two ends of the conductive channel region. According to the self-aligned silicon carbide MOSFET device, the electric field intensity borne by a gate medium of the silicon carbide MOSFET device in a power-off state can be effectively reduced through double buffering of an electric field, the working stability and reliability of the silicon carbide MOSFET device are improved, a JFET region of the silicon carbide MOSFET device can be gradually widened along with increase of the depth, and the current conduction capacity of the device is enhanced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor power devices, in particular to a self-aligned silicon carbide MOSFET device. Background Art

[0002] MOSFET is a power semiconductor device that uses a new semiconductor material, silicon carbide. With its various electrical properties, it has extremely promising prospects in the application of high-voltage, high-temperature and high-power devices. Specifically, it has high withstand voltage, wide bandgap, high temperature resistance and high electron mobility, etc. Therefore, as one of the most cutting-edge power devices, corresponding research on MOSFET power devices is urgently needed and also has great scientific research significance.

[0003] Patent No. CN201910879295.7 discloses a method for preparing a silicon carbide MOSFET device with a p+ region self-alignment process. The utility model forms an n+ ion implantation region, ion implantation forms a source contact n+ region, and after the source contact n+ region is formed, a third ion implantation mask layer of the source contact p+ region is deposited. Without photolithography, the etching mask is directly back-etched to form a p+ ion implantation region, and ion implantation forms a source contact p+ region. This not only realizes the self-alignment process of the channel region, but also realizes the self-alignment process of the P+ region, reduces one photolithography, simplifies the process, saves manufacturing costs, and at the same time improves the uniformity and long-term reliability of the on-resistance of the silicon carbide MOSFET device.

[0004] At present, silicon carbide MOSFET is an important component of all-silicon carbide power modules, and its efficiency and reliability are crucial. Reducing the cell size is an effective means to improve the efficiency of silicon carbide MOSFET. However, when the size of the planar cell is reduced to a certain extent, the process processing capability will restrict the further reduction of the cell size. Due to the registration deviation between each photolithography layer, it is necessary to give sufficient alignment deviation margin between each layer when designing the chip. This design will hinder the process of cell shrinkage. At the same time, since traditional silicon carbide MOSFET requires high-energy well ion implantation, the width of the JFET region at medium depth is narrow, which further hinders the expansion of electrons in the JFET region, increases the on-resistance of the JFET region, and affects the on-efficiency and safety and reliability of silicon carbide MOSFET devices.

[0005] Therefore, a novel self-aligned silicon carbide MOSFET device is proposed. Summary of the invention

[0006] The purpose of the utility model is to provide a self-aligned silicon carbide MOSFET device to solve the problems raised in the above background technology:

[0007] In order to achieve the above purpose, the utility model provides the following technical solutions:

[0008] A self-aligned silicon carbide MOSFET device comprises a drain, a silicon carbide substrate is arranged above the drain, a silicon carbide epitaxial layer is arranged above the silicon carbide substrate, a conductive base region is arranged on the silicon carbide epitaxial layer, a conductive contact layer and a P-well region are arranged on both sides of the upper end of the conductive base region, a conductive shielding layer and an N-drift region are arranged above the P-well region and the conductive contact layer, a conductor region is arranged above the N-drift region and the conductive shielding layer, a conductive metal layer is arranged above the two conductor regions, a conductive source region is arranged above the two conductive metal layers, a gate electrode is arranged between the two conductive source regions, a gate oxide layer and a mask layer are arranged in the gate electrode, the gate oxide layer and the mask layer are in contact, a conductive channel region is arranged between the gate electrode and the conductive base region, triangular grooves are arranged at both ends of the conductive channel region, and a source is arranged on the two conductive source regions and the gate electrode.

[0009] Preferably, the source electrode is located above the conductive source region and the gate electrode;

[0010] The interfaces of the source electrode, the conductive source region and the gate electrode are all in ohmic contact;

[0011] The interface between the drain electrode and the silicon carbide substrate is an ohmic contact,

[0012] By adopting the above technical solution, when the silicon carbide MOSFET device is used, the silicon carbide MOSFET device forms a longitudinal multiple conductive channel, and the electric field enters the silicon carbide MOSFET device by penetrating the P-well region, and is double buffered by the epitaxial trench and the buffer trench.

[0013] Preferably, a buffer groove is provided in the conductive shielding layer;

[0014] The doping ions of the buffer trench are nitrogen ions, carbon ions or phosphorus ions.

[0015] By adopting the above technical solution, the electric field strength borne by the gate dielectric of the silicon carbide MOSFET device in the power-off state is effectively reduced.

[0016] Preferably, the buffer trench is connected to the P-well region;

[0017] The N-drift region, the conductive contact layer and the conductive base region are connected in parallel.

[0018] By adopting the above technical solution, the gate oxide breakdown phenomenon is avoided before the device is broken down, and the device passes through a completely self-aligned mask area.

[0019] Preferably, the surface doping concentration of the P-well region is 2.5×1017 cm -3 ;

[0020] The doping concentration at the bottom of the P-well region near the boundary of the N-drift region is 1×1016cm -3 ,

[0021] By adopting the above technical solution, the conductive base region, the conductive source region, the conductive body region and the conductive channel region are prevented from having alignment deviations through the completely self-aligned mask region.

[0022] Preferably, the doping concentration of the N-drift region and the conductive contact layer is 5×1018 cm -3 ;

[0023] The doping concentration of the conductive contact layer is 7×1017 cm -3 ;

[0024] The doping concentration of the conductive source region is 6×1018 cm -3 ;

[0025] The thickness of the N-drift region is 50 to 80 um.

[0026] By adopting the above technical solution, the cell size of the planar silicon carbide MOSFET device can be effectively reduced and the cell density can be increased, thereby improving the working stability and reliability of the silicon carbide MOSFET device.

[0027] Preferably, one end of the two triangular grooves away from the conductive channel region is in contact with the N-drift region and the conductive shielding layer respectively;

[0028] The N-drift region is connected to the side of the conductor region,

[0029] By adopting the above technical solution, the electric field can be buffered by the triangular grooves. At the same time, the two groups of triangular grooves are self-symmetrically distributed, which can avoid the width of the JFET region being too narrow at a medium depth, and further expand the electrons in the JFET region.

[0030] Preferably, the doping concentration of the silicon carbide substrate is 5×1018cm -3 ;

[0031] The source is made of N-type polysilicon with a doping concentration of 1×1020cm -3 , doping ions are phosphorus ions and carbon ions,

[0032] By adopting the above technical solution, the on-resistance of the JFET region is reduced, and the on-efficiency and safety and reliability of the silicon carbide MOSFET device are improved.

[0033] Preferably, an epitaxial trench is provided in the silicon carbide epitaxial layer;

[0034] The epitaxial trench is connected to the conductive base region;

[0035] The epitaxial trench has a depth greater than 2.0 μm and a depth-to-width ratio greater than 2:1;

[0036] The distance between the two triangular grooves is no greater than 5.0 μm;

[0037] The thickness of the P-well region is no more than 2.5 μm, and the epitaxial trench is completely filled after the power transmission is completed.

[0038] By adopting the above technical solution, the JFET region of the silicon carbide MOSFET device can gradually become wider as the depth increases.

[0039] Preferably, the silicon carbide substrate, N-drift region and conductive source region are all made of N-type silicon carbide materials;

[0040] The doping ions of the N-type silicon carbide material are nitrogen ions, carbon ions or phosphorus ions;

[0041] The P-well region, the conductive contact layer, the N-drift region and the conductive base region are all made of P-type silicon carbide materials, and the doping ions of the P-type silicon carbide materials are one or more of boron ions, copper ions, carbon ions or aluminum ions.

[0042] By adopting the above technical solution, the on-resistance of the JFET region is reduced and the ability of the device to conduct current is enhanced.

[0043] Compared with the prior art, the beneficial effects of the utility model are:

[0044] 1. In the utility model, by opening an epitaxial trench in the silicon carbide epitaxial layer and a buffer trench in the conductive shielding layer, when the silicon carbide MOSFET device is used, the silicon carbide MOSFET device forms a longitudinal multiple conductive channel, and the electric field enters the silicon carbide MOSFET device by penetrating the P-well region. The double buffering of the epitaxial trench and the buffer trench can effectively reduce the electric field strength of the gate dielectric of the silicon carbide MOSFET device in the power-off state, so that the gate oxide breakdown phenomenon is avoided before the device is broken down, and the conductive base region, the conductive source region, the conductive body region and the conductive channel region are prevented from having alignment deviations through the fully self-aligned mask region, which can effectively reduce the cell size of the planar silicon carbide MOSFET device, improve the cell density, and thus improve the working stability and reliability of the silicon carbide MOSFET device;

[0045] 2. In the utility model, by arranging triangular grooves on both sides of the conductive channel region, when the silicon carbide MOSFET device requires high-energy well region ion injection, the electric field can be buffered by the triangular grooves. At the same time, the two groups of triangular grooves are self-symmetrically distributed, which can avoid the width of the JFET region being too narrow at a medium depth, and further expand the electrons in the JFET region, thereby reducing the on-resistance of the JFET region, improving the conduction efficiency and safety and reliability of the silicon carbide MOSFET device, and allowing the JFET region of the silicon carbide MOSFET device to gradually widen with increasing depth, thereby reducing the on-resistance of the JFET region and enhancing the device's ability to conduct current. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 The utility model is a schematic diagram of the overall structure of a self-aligned silicon carbide MOSFET device.

[0047] In the figure: 1: drain; 2: silicon carbide substrate; 3: silicon carbide epitaxial layer; 4: conductive base region; 5: conductive contact layer; 6: N-drift region; 7: conductor region; 8: conductive metal layer; 9: conductive source region; 10: source; 11: gate electrode; 12: gate oxide layer; 13: mask layer; 14: conductive channel region; 15: triangular trench; 16: conductive shielding layer; 17: P-well region; 161, buffer trench; 31, epitaxial trench. DETAILED DESCRIPTION

[0048] Example 1

[0049] See also Figure 1 A self-aligned silicon carbide MOSFET device comprises a drain 1, a silicon carbide substrate 2 is arranged above the drain 1, a silicon carbide epitaxial layer 3 is arranged above the silicon carbide substrate 2, a conductive base region 4 is arranged on the silicon carbide epitaxial layer 3, a conductive contact layer 5 and a P-well region 17 are arranged on both sides of the upper end of the conductive base region 4, a conductive shielding layer 16 and an N-drift region 6 are arranged above the P-well region 17 and the conductive contact layer 5, a conductive body region 7 is arranged above the N-drift region 6 and the conductive shielding layer 16, and two conductive A conductive metal layer 8 is arranged above the body region 7, a conductive source region 9 is arranged above the two conductive metal layers 8, a gate electrode 11 is arranged between the two conductive source regions 9, a gate oxide layer 12 and a mask layer 13 are arranged in the gate electrode 11, the gate oxide layer 12 and the mask layer 13 are in contact with each other, a conductive channel region 14 is arranged between the gate electrode 11 and the conductive base region 4, triangular grooves 15 are arranged at both ends of the conductive channel region 14, and a source 10 is arranged on the two conductive source regions 9 and the gate electrode 11.

[0050] The source electrode 10 is located above the conductive source region 9 and the gate electrode 11;

[0051] The interfaces of the source electrode 10, the conductive source region 9 and the gate electrode 11 are all ohmic contacts;

[0052] The interface between the drain electrode 1 and the silicon carbide substrate 2 is an ohmic contact.

[0053] A buffer groove 161 is provided in the conductive shielding layer 16;

[0054] The doping ions of the buffer trench 161 are nitrogen ions, carbon ions or phosphorus ions.

[0055] The buffer trench 161 is connected to the P-well region 17;

[0056] The N-drift region 6, the conductive contact layer 5 and the conductive base region 4 are connected in parallel, and the electric field enters the silicon carbide MOSFET device by penetrating the P-well region 17. Through the double buffering of the epitaxial trench 31 and the buffer trench 161, the electric field strength borne by the gate dielectric of the silicon carbide MOSFET device in the power-off state can be effectively reduced.

[0057] The surface doping concentration of the P-well region 17 is 2.5×1017 cm -3 ;

[0058] The doping concentration at the bottom of the P-well region 17 near the boundary of the N-drift region 6 is 1×1016cm -3 .

[0059] The doping concentration of the N-drift region 6 and the conductive contact layer 5 is 5×1018cm -3 ;

[0060] The doping concentration of the conductive contact layer 5 is 7×1017 cm -3 ;

[0061] The doping concentration of the conductive source region 9 is 6×1018cm -3 ;

[0062] The thickness of the N-drift region 6 is 50-80 um, which avoids gate oxide breakdown before the device is broken down, and through the completely self-aligned mask area, the conductive base region 4, the conductive source region 9, the conductive body region 7 and the conductive channel region 14 are prevented from alignment deviation.

[0063] One end of the two triangular grooves 15 away from the conductive channel region 14 is in contact with the N-drift region 6 and the conductive shielding layer 16 respectively;

[0064] The N-drift region 6 is connected to the side of the conductor region 7 .

[0065] The doping concentration of the silicon carbide substrate 2 is 5×1018 cm -3 ;

[0066] The source electrode 10 is made of N-type polysilicon material with a doping concentration of 1×1020cm-3 The doping ions are phosphorus ions and carbon ions, which can effectively reduce the cell size of planar silicon carbide MOSFET devices and increase the cell density, thereby improving the working stability and reliability of silicon carbide MOSFET devices.

[0067] The utility model uses steps: the utility model, when the silicon carbide MOSFET device is used, enables the silicon carbide MOSFET device to form longitudinal multiple conductive channels, and the electric field enters the silicon carbide MOSFET device by penetrating the P-well region 17, and the double buffering of the epitaxial groove 31 and the buffer groove 161 can effectively reduce the electric field strength of the gate dielectric of the silicon carbide MOSFET device in the power-off state, so that the gate oxide breakdown phenomenon is avoided before the device is broken down, and the conductive base region 4, the conductive source region 9, the conductive body region 7 and the conductive channel region 14 are prevented from having alignment deviations through the completely self-aligned mask region, which can effectively reduce the cell size of the planar silicon carbide MOSFET device, and improve the cell density, thereby improving the working stability and reliability of the silicon carbide MOSFET device.

[0068] Example 2

[0069] See also Figure 1 A self-aligned silicon carbide MOSFET device comprises a drain 1, a silicon carbide substrate 2 is arranged above the drain 1, a silicon carbide epitaxial layer 3 is arranged above the silicon carbide substrate 2, a conductive base region 4 is arranged on the silicon carbide epitaxial layer 3, a conductive contact layer 5 and a P-well region 17 are arranged on both sides of the upper end of the conductive base region 4, a conductive shielding layer 16 and an N-drift region 6 are arranged above the P-well region 17 and the conductive contact layer 5, a conductive body region 7 is arranged above the N-drift region 6 and the conductive shielding layer 16, and two conductive A conductive metal layer 8 is arranged above the body region 7, a conductive source region 9 is arranged above the two conductive metal layers 8, a gate electrode 11 is arranged between the two conductive source regions 9, a gate oxide layer 12 and a mask layer 13 are arranged in the gate electrode 11, the gate oxide layer 12 and the mask layer 13 are in contact with each other, a conductive channel region 14 is arranged between the gate electrode 11 and the conductive base region 4, triangular grooves 15 are arranged at both ends of the conductive channel region 14, and a source 10 is arranged on the two conductive source regions 9 and the gate electrode 11.

[0070] An epitaxial trench 31 is provided in the silicon carbide epitaxial layer 3;

[0071] The epitaxial trench 31 is connected to the conductive base region 4;

[0072] The epitaxial trench 31 has a depth greater than 2.0 μm and a depth-to-width ratio greater than 2:1;

[0073] The distance between the two triangular grooves 15 is no greater than 5.0 μm;

[0074] The thickness of the P-well region 17 is no more than 2.5 μm. After the power transmission is completed, the epitaxial trench 31 is completely filled. The two groups of triangular trenches 15 are symmetrically distributed, which can avoid the width of the JFET region being too narrow at a medium depth, further expanding the electrons in the JFET region, thereby reducing the on-resistance of the JFET region.

[0075] The silicon carbide substrate 2, the N-drift region 6 and the conductive source region 9 are all made of N-type silicon carbide materials;

[0076] The doping ions of N-type silicon carbide material are nitrogen ions, carbon ions or phosphorus ions;

[0077] The P-well region 17, the conductive contact layer 5, the N-drift region 6 and the conductive base region 4 are all made of P-type silicon carbide materials. The doping ions of the P-type silicon carbide materials are one or more of boron ions, copper ions, carbon ions or aluminum ions, which improve the conduction efficiency and safety and reliability of the silicon carbide MOSFET device, so that the JFET region of the silicon carbide MOSFET device can gradually widen with increasing depth.

[0078] The use steps of the utility model: According to the utility model, when the silicon carbide MOSFET device requires high-energy well region ion implantation, the electric field can be buffered by the triangular grooves 15, and at the same time, the two groups of triangular grooves 15 are symmetrically distributed, which can avoid the JFET region from being too narrow at a medium depth, and further expand the electrons in the JFET region, thereby reducing the on-resistance of the JFET region, improving the on-efficiency and safety and reliability of the silicon carbide MOSFET device, so that the JFET region of the silicon carbide MOSFET device can gradually become wider with increasing depth, thereby reducing the on-resistance of the JFET region and enhancing the device's ability to conduct current.

[0079] The above shows and describes the basic principle, main features and advantages of the utility model. Those skilled in the art should understand that the utility model is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the utility model and are not used to limit the utility model. Without departing from the spirit and scope of the utility model, the utility model may have various changes and improvements, which fall within the scope of the utility model to be protected. The scope of protection of the utility model is defined by the attached claims and their equivalents.

Claims

1. A self-aligned silicon carbide MOSFET device, comprising a drain (1), characterized in that: A silicon carbide substrate (2) is arranged above the drain (1), a silicon carbide epitaxial layer (3) is arranged above the silicon carbide substrate (2), a conductive base region (4) is arranged on the silicon carbide epitaxial layer (3), a conductive contact layer (5) and a P-well region (17) are arranged on both sides of the upper end of the conductive base region (4), a conductive shielding layer (16) and an N-drift region (6) are arranged above the P-well region (17) and the conductive contact layer (5), a conductive body region (7) is arranged above the N-drift region (6) and the conductive shielding layer (16), and a conductive metal is arranged above the two conductive body regions (7). A conductive source region (9) is disposed above each of the two conductive metal layers (8); a gate electrode (11) is disposed between the two conductive source regions (9); a gate oxide layer (12) and a mask layer (13) are disposed within the gate electrode (11); the gate oxide layer (12) and the mask layer (13) are in contact with each other; a conductive channel region (14) is disposed between the gate electrode (11) and the conductive base region (4); triangular grooves (15) are disposed at both ends of the conductive channel region (14); and a source electrode (10) is disposed on the two conductive source regions (9) and the gate electrode (11).

2. A self-aligned silicon carbide MOSFET device according to claim 1, characterized in that: The source electrode (10) is located above the conductive source region (9) and the gate electrode (11); The interfaces between the source electrode (10), the conductive source region (9) and the gate electrode (11) are all in ohmic contact; The interface between the drain electrode (1) and the silicon carbide substrate (2) is an ohmic contact.

3. A self-aligned silicon carbide MOSFET device according to claim 1, characterized in that: A buffer groove (161) is provided in the conductive shielding layer (16); The doping ions of the buffer trench (161) are nitrogen ions, carbon ions or phosphorus ions.

4. A self-aligned silicon carbide MOSFET device according to claim 3, characterized in that: The buffer groove (161) is connected to the P-well region (17); The N-drift region (6), the conductive contact layer (5) and the conductive base region (4) are connected in parallel.

5. A self-aligned silicon carbide MOSFET device according to claim 1, characterized in that: The surface doping concentration of the P well region (17) is 2.5×1017 cm -3 ; The doping concentration of the bottom of the P-well region (17) close to the boundary of the N-drift region (6) is 1×1016 cm -3 .

6. A self-aligned silicon carbide MOSFET device according to claim 1, characterized in that: The doping concentrations of the N-drift region (6) and the conductive contact layer (5) are both 5×1018 cm -3 ; The doping concentration of the conductive contact layer (5) is 7×1017 cm -3 ; The doping concentration of the conductive source region (9) is 6×1018 cm -3 ; The thickness of the N-drift region (6) is 50-80 um.

7. A self-aligned silicon carbide MOSFET device according to claim 1, characterized in that: One end of the two triangular grooves (15) away from the conductive channel region (14) is in contact with the N-drift region (6) and the conductive shielding layer (16) respectively; The N-drift region (6) is connected to the side of the conductor region (7).

8. A self-aligned silicon carbide MOSFET device according to claim 1, characterized in that: The doping concentration of the silicon carbide substrate (2) is 5×1018 cm -3 ; The source electrode (10) is made of N-type polysilicon material with a doping concentration of 1×1020 cm -3 , the doping ions are phosphorus ions and carbon ions.

9. A self-aligned silicon carbide MOSFET device according to claim 1, characterized in that: An epitaxial trench (31) is provided in the silicon carbide epitaxial layer (3); The epitaxial trench (31) is connected to the conductive base region (4); The epitaxial trench (31) has a depth greater than 2.0 μm and a depth-to-width ratio greater than 2:1; The distance between the two triangular grooves (15) is no greater than 5.0 μm; The thickness of the P-well region (17) is no more than 2.5 μm, and the epitaxial trench (31) is completely filled after the power transmission is completed.

10. The self-aligned silicon carbide MOSFET device according to claim 1, characterized in that: The silicon carbide substrate (2), the N-drift region (6) and the conductive source region (9) are all made of N-type silicon carbide materials; The doping ions of the N-type silicon carbide material are nitrogen ions, carbon ions or phosphorus ions; The P-well region (17), the conductive contact layer (5), the N-drift region (6) and the conductive base region (4) are all made of P-type silicon carbide materials, and the doping ions of the P-type silicon carbide materials are one or more of boron ions, copper ions, carbon ions or aluminum ions.

Images