SiC VDMOSFET capable of improving channel region area

Abstract

The utility model discloses a SiC VDMOSFET capable of improving the area of a channel region, and relates to the technical field of semiconductors. In the SiC VDMOSFET device, a conventional strip-shaped channel region is designed and arranged into a continuous boss shape, so that the area of the channel region in the device is increased by 60%-70%, and the through-current capability of the SiC VDMOSFET device is increased by 1.6-1.7 times compared with the conventional strip-shaped channel region, thereby not only improving the power density of the device, but also reducing the cost of the device.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a SiC VDMOSFET with increased channel area. Background Art

[0002] In the field of power electronics technology, traditional silicon-based power devices have always been the main products in the market, and their application scope covers many fields such as automobiles, photovoltaics, communications, and consumer electronics. However, with the continuous development of society, the requirements for power devices are becoming more and more stringent. Especially with the rapid development of new energy vehicles, photovoltaics and other fields, traditional silicon-based power devices have approached the performance limit limited by the material itself and cannot meet the use requirements of these application fields. Silicon carbide (SiC) is a third-generation wide bandgap semiconductor material. Because the material itself has excellent physical properties such as strong critical breakdown field, low intrinsic carrier concentration, fast saturated electron drift rate, and high thermal conductivity, the prepared power devices can achieve better performance, smaller chips, and higher power density compared to silicon-based devices. It is very suitable for applications in high voltage, high temperature, high frequency, high radiation and other fields.

[0003] Although SiC MOSFET devices have the advantages of high withstand voltage, low loss, and high switching frequency compared to Si MOSFET and Si IGBT devices, the gate oxide layer interface state density is large and there are many defects in the device, which leads to low channel electron mobility of the device, affecting the flow capacity. In order to better play the advantages of SiC's physical properties, the industry usually uses a driving voltage of ≥18V to open SiC MOSFET devices to ensure the flow level of the device. In addition to external drive, reducing the chip source cell size to further increase the power density of SiCMOSFET devices is also the main method to improve the flow capacity, and the industry is also doing research and development iterations of SiC MOSFET in this technical direction. Therefore, it can be seen that improving the flow capacity of SiC MOSFET devices has great benefits both in increasing the power density of the device and reducing the production cost of the device. Utility Model Content

[0004] The utility model significantly increases the channel area inside the device by designing and arranging the conventional strip-shaped channel region into a continuous boss shape in the SiC VDMOSFET device, thereby improving the current carrying capacity of the SiC VDMOSFET device, further improving the power density of the device, and also reducing the cost of the device.

[0005] The technical solution of the utility model is:

[0006] A SiCVD MOSFET with an increased channel area includes a back electrode metal layer, a back ohmic contact alloy layer, a SiC substrate layer and a SiC drift layer arranged in sequence from bottom to top;

[0007] A CSL layer extending downward is provided on the top surface of the SiC drift layer;

[0008] The CSL layer has a P-well region extending downward;

[0009] The P-well region is provided with an N+ region extending downward;

[0010] The N+ region in the source electrode A region is provided with a P+ region connected to the side thereof;

[0011] The top surface of the N+ region is provided with a front ohmic contact alloy layer connected thereto; the side of the front ohmic contact alloy layer is provided with a gate oxide layer and a Poly layer which are spaced apart therefrom and sequentially connected thereto from bottom to top;

[0012] The top surface of the Poly layer is provided with an isolation dielectric layer extending downward from the side to the top surface of the N+ region;

[0013] A front electrode metal layer is provided on the top surfaces of the isolation dielectric layer and the front ohmic contact alloy layer.

[0014] Specifically, the SiC substrate layer is an N-type SiC substrate layer;

[0015] The SiC drift layer is an N-type SiC drift layer.

[0016] Specifically, the CSL layer has a depth of 1.0um-1.2um.

[0017] Specifically, the depth of the P-well region is 0.8um-1.0um.

[0018] Specifically, the depth of the N+ region is 0.4 um.

[0019] Specifically, the depth of the P+ region is 0.6 um.

[0020] Specifically, the gate oxide layer has a thickness of 45nm-50nm.

[0021] The utility model increases the channel area inside the device by 60%-70% by designing and arranging the conventional strip-shaped channel area into a continuous boss shape in the SiC VDMOSFET device, and increases the current carrying capacity of the SiC VDMOSFET device by 1.6 times-1.7 times compared with the conventional strip-shaped channel area, which not only improves the power density of the device, but also reduces the cost of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a top view of the utility model ( Figure 1 The CSL layer 3, the P-well region 4, the gate oxide layer 7, the front ohmic contact alloy layer 10 and the front electrode metal layer 11 are hidden therein);

[0023] Figure 2 yes Figure 1 Structural diagram of the AA section in the source A region in the X direction;

[0024] Figure 3 yes Figure 1 Structural diagram of the BB section in the X direction in the source A region;

[0025] Figure 4 yes Figure 1 Structural diagram of the CC cross section in the source A region in the X direction;

[0026] Figure 5 It is a structural schematic diagram of step S100 of the utility model;

[0027] Figure 6 It is a structural schematic diagram of step S200 of the utility model;

[0028] Figure 7 It is a structural schematic diagram of step S300 of the utility model;

[0029] Figure 8 It is a structural schematic diagram of step S400 of the utility model;

[0030] Fig. 9 It is a structural schematic diagram of step S500 of the utility model;

[0031] Fig.10 It is a structural schematic diagram of step S700 of the utility model;

[0032] Fig.11 It is a structural schematic diagram of step S800 of the utility model;

[0033] Fig.12 It is a structural schematic diagram of step S900 of the utility model;

[0034] Fig.13 It is a structural schematic diagram of step S1000 of the utility model;

[0035] Fig.14 It is a structural schematic diagram of step S1100 of the utility model;

[0036] Fig.15 It is a structural schematic diagram of step S1200 of the utility model;

[0037] Fig.16 It is a structural schematic diagram of step S1300 of the utility model;

[0038] In the figure, 1 is the SiC substrate layer, 2 is the SiC drift layer, 3 is the CSL layer, 4 is the P-well region, 5 is the N+ region, 6 is the P+ region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the isolation dielectric layer, 10 is the front ohmic contact alloy layer, 11 is the front electrode metal layer, 12 is the back ohmic contact alloy layer, and 13 is the back electrode metal layer. DETAILED DESCRIPTION

[0039] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0040] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0041] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0042] The SiC VDMOSFET with increased channel area includes the following steps:

[0043] S100, such as Figure 5 As shown, a SiC drift layer 2 is epitaxially grown on a SiC substrate layer 1;

[0044] In step S100, the conductivity types of the SiC substrate layer 1 and the SiC drift layer 2 are both N-type, and the doping concentration of the SiC substrate layer 1 is 1E19 cm -2 , the doping concentration of SiC drift layer 2 is 5E15-1E16cm -2 .

[0045] S200, such as Figure 6As shown, a CSL layer 3 is initially formed on the top surface of the SiC drift layer 2 by oblique N ion implantation, serving as a current extension region of the device to reduce the on-resistance of the device;

[0046] The depth of the CSL layer 3 in step S200 is 1.0um-1.2um, and the doping concentration is 5E16-1E17cm -2 .

[0047] S300, such as Figure 7 As shown, a P-well region 4 is initially formed on the top surface of the CSL layer 3 by oblique Al ion implantation;

[0048] The depth of the P-well region 4 in step S300 is 0.8um-1.0um, and the doping concentration is 1E17-3E18cm -2 .

[0049] S400, such as Figure 8 As shown, an N+ region 5 is initially formed on the top surface of the P-well region 4 by oblique N ion implantation;

[0050] The depth of the N+ region 5 in step S400 is 0.4um and the doping concentration is 1E18-1E19cm -2 .

[0051] S500, such as Fig. 9 As shown, a P+ region 6 is initially formed on the top surface of the P-well region 4 by oblique Al ion implantation;

[0052] The depth of the P+ region 6 in step S500 is 0.6um and the doping concentration is 1E18-1E19cm -2 .

[0053] S600, the CSL layer 3, the P-well region 4, the N+ region 5 and the P+ region 6 are activated and completely formed by high temperature activation annealing;

[0054] The high temperature activation annealing temperature in step S600 is between 1600°C and 1900°C.

[0055] S700, such as Fig.10 As shown, a gate oxide layer 7 is grown on the top surface of the CSL layer 3 by introducing oxygen in a dry oxygen oxidation manner;

[0056] The thickness of the gate oxide layer 7 in step S700 is 45 nm-50 nm.

[0057] S800, such as Fig.11 As shown, a Poly layer 8 is formed on the top surface of the gate oxide layer 7 by polysilicon deposition to serve as the gate electrode of the device;

[0058] S900, such as Fig.12 As shown, an isolation dielectric layer 9 is formed on the top surface of the N+ region 5 and the Poly layer 8 by oxide deposition to isolate the gate electrode and the source electrode of the device to prevent the two from being short-circuited;

[0059] S1000, such as Fig.13 As shown, a front ohmic contact alloy layer 10 is formed on the top surfaces of the N+ region 5 and the P+ region 6 by Ni metal sputtering and then by rapid thermal annealing;

[0060] The thickness of the Ni metal in step S1000 is 100 nm.

[0061] S1100, such as Fig.14 As shown, a front electrode metal layer 11 is formed on the top of the device by AlCu metal sputtering, which serves as the source electrode of the device;

[0062] The thickness of the AlCu metal in step S1100 is 5000 nm.

[0063] S1200, such as Fig.15 As shown, a back ohmic contact alloy layer 12 is formed on the bottom surface of the SiC substrate layer 1 by Ni metal sputtering and then laser thermal annealing;

[0064] The thickness of the Ni metal in step S1200 is 100 nm.

[0065] S1300, such as Fig.16 As shown, a back electrode metal layer 13 is formed on the bottom surface of the back ohmic contact alloy layer 12 by Ti / Ni / Ag metal evaporation to serve as the drain electrode of the device;

[0066] The thickness of the Ti / Ni / Ag metal in step S1300 is 30nm / 300nm / 1200nm.

[0067] A SiCVD MOSFET with an increased channel area comprises a back electrode metal layer 13, a back ohmic contact alloy layer 12, a SiC substrate layer 1 and a SiC drift layer 2 arranged in sequence from bottom to top;

[0068] A CSL layer 3 extending downward is provided on the top surface of the SiC drift layer 2;

[0069] The CSL layer 3 has a P-well region 4 extending downward; the bottom surface of the P-well region 4 is higher than the bottom surface of the CSL layer 3;

[0070] The P-well region 4 is provided with an N+ region 5 extending downward;

[0071] The N+ region 5 in the source electrode A region is provided with a P+ region 6 connected to the side thereof; the depth of the P+ region 6 is greater than the depth of the N+ region 5;

[0072] The top surface of the N+ region 5 is provided with a front ohmic contact alloy layer 10 connected thereto; the side of the front ohmic contact alloy layer 10 is provided with a gate oxide layer 7 and a Poly layer 8 spaced apart therefrom and connected thereto in sequence from bottom to top;

[0073] The bottom surface of the front ohmic contact alloy layer 10 of the source electrode A region is connected to the top surfaces of the N+ region 5 and the P+ region 6 respectively;

[0074] The bottom surface of the front ohmic contact alloy layer 10 of the source electrode A region and the source electrode B region is connected to the top surface of the N+ region 5;

[0075] The top surface of the Poly layer 8 is provided with an isolation dielectric layer 9 extending downward from the side to the top surface of the N+ region 5; the top surface of the isolation dielectric layer 9 is higher than the top surface of the front ohmic contact alloy layer 10;

[0076] A front electrode metal layer 11 is provided on the top surfaces of the isolation dielectric layer 9 and the front ohmic contact alloy layer 10 .

[0077] The utility model improves the flow capacity of the device:

[0078] In switching power devices, improving the current flow capacity of the device can further improve the power density of the device and reduce the cost of the device at the same time. In SiC MOSFET devices, due to the low mobility of channel electrons, in order to better exert the conduction performance, the external driving voltage is generally recommended to be ≥18V to turn on the device. At the same time, the industry is also iteratively developing in the direction of reducing the size of the chip source cell to achieve higher power density of the device. This utility model patent increases the area of ​​the channel region in the SiCVDMOSFET device by 60%-70% compared to the conventional strip-shaped channel region, theoretically increasing the current flow capacity of the device by 1.6 times-1.7 times, which not only greatly improves the power density of the device, but also reduces the cost of the device.

Claims

1. A SiC VDMOSFET with an increased channel area, characterized in that: It comprises a back electrode metal layer (13), a back ohmic contact alloy layer (12), a SiC substrate layer (1) and a SiC drift layer (2) which are arranged in sequence from bottom to top; A CSL layer (3) extending downward is provided on the top surface of the SiC drift layer (2); The CSL layer (3) has a P-well region (4) extending downward; The P-well region (4) is provided with an N+ region (5) extending downward; The N+ region (5) is provided with a P+ region (6) connected to the side thereof; The top surface of the N+ region (5) is provided with a front ohmic contact alloy layer (10) connected thereto; the side of the front ohmic contact alloy layer (10) is provided with a gate oxide layer (7) and a Poly layer (8) which are spaced apart from and sequentially connected thereto from bottom to top; The top surface of the Poly layer (8) is provided with an isolation dielectric layer (9) extending downward from the side to the top surface of the N+ region (5); A front electrode metal layer (11) is provided on the top surfaces of the isolation dielectric layer (9) and the front ohmic contact alloy layer (10).

2. The SiC VDMOSFET with increased channel area according to claim 1, characterized in that: The SiC substrate layer (1) is an N-type SiC substrate layer; The SiC drift layer (2) is an N-type SiC drift layer.

3. The SiC VDMOSFET with increased channel area according to claim 1, characterized in that: The CSL layer (3) has a depth of 1.0 um to 1.2 um.

4. The SiC VDMOSFET with increased channel area according to claim 1, characterized in that: The depth of the P-well region (4) is 0.8um-1.0um.

5. The SiC VDMOSFET with increased channel area according to claim 1, characterized in that: The N+ region (5) has a depth of 0.4 um.

6. The SiC VDMOSFET with increased channel area according to claim 1, characterized in that: The depth of the P+ region (6) is 0.6 um.

7. The SiC VDMOSFET with increased channel area according to claim 1, characterized in that: The gate oxide layer (7) has a thickness of 45 nm to 50 nm.

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