Power device and power switchgear
By forming a groove with a bent portion in the longitudinally conductive field effect tube, the area of the interface of the active region is expanded, the problem of uneven current path is solved, and the utilization rate of the active region and the efficiency of the power device are improved.
Patent Information
- Application Number
- CN202421488462.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-26
- Publication Date
- 2025-05-06
- Estimated Expiration
- 2034-06-26
AI Technical Summary
In existing longitudinal conductive field effect tubes, when the common drain electrode is connected in a single chip, the current path is uneven, resulting in uneven distribution of the current density in the active region, and the utilization rate is low.
By forming a trench with a bent portion on the surface of the semiconductor layer adjacent to the first field effect tube and the second field effect tube, the relative area of the interface between the first active region and the second active region is expanded, so that the current line distribution is more uniform.
It improves the utilization rate of the active region, reduces the on-impedance of the power device, and improves the efficiency of the device.
Smart Images
Figure CN222840003U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a power device and a power switch device. Background Art
[0002] Nowadays, with the continuous improvement of the electrification level of society, the performance of power devices also needs to be continuously improved to meet higher requirements. In order to achieve higher performance indicators, power devices have mainly undergone several aspects of evolution, such as process advancement, device structure improvement and the use of wide bandgap materials. In terms of device structure improvement, power devices have undergone changes in device structures such as planar, trench, and super junction, further improving the power density and operating frequency of the device.
[0003] Among them, power devices mostly use vertically conductive field effect transistors MOSFET (Metal Oxide Semiconductor Field Effect Transistor, referred to as field effect transistor or MOS tube). Vertically conductive field effect transistors have the characteristics of high current density and strong voltage resistance.
[0004] In the related art, when the drain of a single-chip longitudinally conductive field effect tube is connected, the current density in the area with the shortest current path is the highest, and the current density in the area with the longest current path is the lowest. Currently, most longitudinally conductive field effect tubes are placed face to face in the form of two rectangular single field effect tubes. The current density in the area near the junction of the two field effect tubes is the highest, but the current density far from the junction is the lowest, which makes the current density distribution in the active area uneven, resulting in low utilization of the active area. Utility Model Content
[0005] In view of this, embodiments of the present application provide a power device and a power switch device to at least partially solve the above problems.
[0006] According to a first aspect of an embodiment of the present application, a power device is provided, which includes a metal layer and a semiconductor layer, wherein the metal layer forms a common drain of a first field effect transistor and a second field effect transistor; and a semiconductor layer, wherein one surface of the semiconductor layer is bonded to the metal layer, and a groove is formed on the other surface of the semiconductor layer facing away from the metal layer, wherein a first active region of the first field effect transistor is formed on one side of the groove, and a source of the first field effect transistor is arranged in the first active region, and a second active region of the second field effect transistor is formed on the other side of the groove, and a source of the second field effect transistor is arranged in the second active region, wherein the groove forms at least one bend on the other surface of the semiconductor layer.
[0007] In one embodiment of the present application, each bending portion is located between the first extension portion and the second extension portion of the groove, and the extension direction of the first extension portion and the extension direction of the second extension portion form an angle less than 90 degrees.
[0008] In one embodiment of the present application, an extending direction of the first extending portion and an extending direction of the second extending portion are substantially parallel.
[0009] In one embodiment of the present application, the smaller the distance between the first extension portion and the bending portion, the larger the width of the groove at the first extension portion; the smaller the distance between the second extension portion and the bending portion, the larger the width of the groove at the second extension portion.
[0010] In one embodiment of the present application, the smaller the distance between the first extension portion and the bending portion, the smaller the depth of the groove at the first extension portion; the smaller the distance between the second extension portion and the bending portion, the smaller the depth of the groove at the second extension portion.
[0011] In one embodiment of the present application, the depth of the trench at each location on the other surface of the semiconductor layer is consistent.
[0012] In one embodiment of the present application, a plurality of electrodes forming the source of the first field effect transistor and a plurality of electrodes forming the source of the second field effect transistor are symmetrically distributed on both sides of the trench.
[0013] In one embodiment of the present application, at least one bending portion includes a first bending portion and a second bending portion that are alternately arranged, the electrode forming the source of the first field effect transistor is arranged corresponding to the first bending portion, and the electrode forming the source of the second field effect transistor is arranged corresponding to the second bending portion.
[0014] In one embodiment of the present application, a plurality of electrodes forming the source of the first field effect transistor are uniformly distributed in the first active region, and a plurality of electrodes forming the source of the second field effect transistor are uniformly distributed in the second active region.
[0015] According to a second aspect of the embodiments of the present application, a power switch device is provided, comprising a power device according to any of the above embodiments.
[0016] According to the power device and power switch device provided in the embodiments of the present application, a groove with a bending portion is formed on the surface of the semiconductor layer adjacent to the first field effect transistor and the second field effect transistor that is opposite to the metal layer, thereby expanding the relative area of the interface between the first active area and the second active area, so that the current lines flowing through the first active area and the second active area are distributed more evenly, thereby improving the utilization rate of the active area, thereby reducing the on-resistance of the power device and making the power device more efficient. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.
[0018] Figure 1 A schematic diagram of current flow when a single-tube power device in the related art is working;
[0019] Figure 2 (a1-a3) are three views of a single-tube power device in the related art;
[0020] Figure 3 The current flow direction of a common drain dual-transistor power device applicable to an embodiment of the present application when it is working;
[0021] Figure 4 (b1-b3) are three views of a common drain dual-transistor power device in the related art;
[0022] Figure 5 A schematic diagram of an active region of a power device according to an embodiment of the present application;
[0023] Figure 6 is a schematic diagram of an active region of a power device according to another embodiment of the present application;
[0024] Figure 7 is a schematic diagram of an active region of a power device according to another embodiment of the present application;
[0025] Figure 8 is a schematic diagram of an active region of a power device according to another embodiment of the present application;
[0026] Fig. 9 (c1-c2) is a schematic diagram of the change of the bending portion of a power device according to an embodiment of the present application;
[0027] Fig.10 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION
[0028] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.
[0029] Specifically, power devices mostly use vertically conductive field effect transistors. The on-resistance of the field effect transistor is a key parameter, and its size affects the current allowed to pass through the field effect transistor and its working efficiency. Therefore, it is very important to design a reasonable on-resistance for power devices. The on-resistance is related to the active area and specific on-resistance of the power device, as shown in formula (1):
[0030] Rsp=A*Ron (1)
[0031] Among them, Rsp is the specific on-resistance of the power device, A is the active area of the power device, and Ron is the on-resistance of the power device. Usually, Rsp is determined by the process platform. When the process platform is determined, Rsp is a relatively stable value. Therefore, a reasonable on-resistance can be further designed according to the active area of the power device. This scheme has been proven to be effective in single-tube power devices.
[0032] For example, Figure 1 It is a schematic diagram of the current flow direction when a single-tube power device in the related technology is working, such as Figure 1 As shown, the power device is an N-channel enhancement type field effect transistor, wherein G represents the gate of the field effect transistor, D represents the drain of the field effect transistor, and S represents the source of the field effect transistor. When the field effect transistor is turned on, the current flows from the drain D to the source S.
[0033] Figure 2 (a1~a3) are three views of a single-tube power device in the related art, wherein a1 is a front view of the single-tube power device, a2 is a left view of the single-tube power device, and a3 is a top view of the single-tube power device.
[0034] It can be seen from the main view a1 that the semiconductor layer 200 of the single-tube power device is parallel to the metal layer 100; since the drain D of the single-tube power device is located in the metal layer 100, the source S is located in the semiconductor layer 200, and the active area is located in the semiconductor layer 200, it can be seen from the left view a2 that the current of the single-tube power device flows into the metal layer 100 and flows out of the semiconductor layer 200, and the top view of the entire active area is approximately regarded as a conductor with uniform current density; it can be seen from the top view a3 that the gate G of the single-tube power device is also located in the semiconductor layer 200, and except for the gate pin area, the remaining area is designed to be unfolded into blocks of rectangles, so that the projection surface of the semiconductor layer can be fully utilized.
[0035] Therefore, when the process platform for manufacturing the single-tube power device is determined, its specific on-resistance Rsp will also be determined accordingly. By designing a reasonable active area A and combining it with formula (1), an efficient on-resistance Ron can be obtained, thereby improving the working efficiency of the power device.
[0036] For example, Figure 3In order to be applicable to the current flow direction of a common drain dual-tube power device of an embodiment of the present application when it is working, the common drain dual-tube power device is usually formed by two symmetrical field effect transistors with drains interconnected, and the actual structure of the common drain dual-tube power device is mostly two single-tube power devices with rectangular planes, and the isolation technology of filling insulating materials is used to isolate their respective source regions from each other, thereby forming a common drain structure.
[0037] Among them, Q1 and Q2 represent two symmetrical field effect transistors, G1 and G2 represent the gates of the two field effect transistors, D represents the common drain of the two field effect transistors, S1 and S2 represent the sources of the two field effect transistors, and by applying a suitable turn-on voltage to the gates G1 and G2 of the dual-tube power device, the two field effect transistors of the dual-tube power device can be turned on to realize the switching action. At this time, the current of the dual-tube power device flows into the source S1 of one of the field effect transistors, passes through the common drain, and flows out from the source S2 of the other field effect transistor.
[0038] Figure 4 (b1~b3) are three views of the common drain dual-tube power device in the related technology, wherein b1 is the front view of the common drain dual-tube power device, b2 is the left view of the common drain dual-tube power device, and b3 is the top view of the common drain dual-tube power device.
[0039] It can be seen from the front view b1 that the semiconductor layer 200 of the common drain dual-tube power device is parallel to the metal layer 100, and the active area is located in the semiconductor layer 200; similarly, since the source S1 and S2 of the common drain dual-tube power device are located in the semiconductor layer 200, and the active area is located in the semiconductor layer 200, it can be seen from the left view b2 that the current of the common drain dual-tube power device flows into the semiconductor layer 200 of one of the field effect transistors Q1, flows through the interior of the common drain dual-tube power device, and then flows into the other field effect transistor Q2. The current flows out of the semiconductor layer 200 of the field effect transistor Q1; as can be seen from the top view b3, the two field effect transistors of the common drain dual-tube power device are placed symmetrically, and the adjacent boundary lines are shown as P1 in b3. The interface formed by the adjacent boundary lines is rectangular, and a plurality of source electrodes S and gate electrodes G are distributed on the semiconductor layer 200 of the field effect transistor Q1 and the field effect transistor Q2. The current flows into the semiconductor layer 200 of one of the field effect transistors Q1, flows through the interior of the common drain dual-tube power device, and then flows out of the semiconductor layer 200 of the other field effect transistor Q2.
[0040] It can be understood that, since the adjacent active areas of the two field effect tubes are isolated from each other by isolation technology, a rectangular interface is formed, and the current preferentially passes through a path with a short distance and low impedance, the current line density of the common drain dual-tube power device in the left view b2 is unevenly distributed, the current line density near the interface is strong, and the current line density far from the interface is weak. That is, the utilization efficiency of the active area is poor, so that the specific on-resistance of the common drain dual-tube power device is raised, resulting in a large on-resistance of the common drain dual-tube power device, increased heat loss, and poor utilization efficiency. If the area of the interface is increased only by increasing the length of the boundary line between the two field effect tubes, more current passes through the area near the interface to improve the utilization efficiency of the active area, then the common drain dual-tube power device will be subjected to stress damage due to the narrow and long outer contour, and the structure will be easily damaged after being subjected to multiple loads.
[0041] That is to say, the common drain dual-tube power device in the related technology has a high current density near the interface and a weak current density far away from the interface, which makes the current distribution in the active area uneven, affecting the utilization efficiency of the active area, and further resulting in high on-resistance of the common drain dual-tube power device, more serious heat loss of the device, and poor utilization efficiency.
[0042] Therefore, through the power device provided by the present application, a groove with a bending portion is formed on the surface of the semiconductor layer adjacent to the first field effect transistor and the second field effect transistor that is opposite to the metal layer, thereby expanding the relative area of the interface between the first active area and the second active area, so that the current lines flowing through the first active area and the second active area are distributed more uniformly, thereby improving the utilization rate of the active area, thereby reducing the on-resistance of the power device and making the power device more efficient.
[0043] The specific implementation of the embodiment of the present application is further explained below in conjunction with the accompanying drawings of the embodiment of the present application.
[0044] like Figure 4 As shown in b1, the power device 10 includes: a metal layer 100 and a semiconductor layer 200, wherein the metal layer 100 forms a common drain of a first field effect transistor MOSFET1 and a second field effect transistor MOSFET2; one surface of the semiconductor layer 200 is bonded to the metal layer 100, and a groove is formed on the other surface of the semiconductor layer 200 facing away from the metal layer 100. The power device 10 can be a common drain field effect transistor with a dual-tube longitudinal structure.
[0045] The metal layer 100 can be made of copper or silver, and the semiconductor layer 200 can be made of other semiconductor materials such as silicon or silicon carbide. The power device 10 can be a common drain field effect transistor composed of two N-channel enhancement field effect transistors with drains interconnected. The direction of the internal current flowing during operation is the same as that of the transistor. Figure 3The power device 10 may also be a common drain field effect transistor or a common source field effect transistor composed of multiple other types of field effect transistors with their drains or sources interconnected.
[0046] Figure 5 Schematic diagram of an active region of a power device according to an embodiment of the present application.
[0047] like Figure 5 As shown, a first active area Ar1 of a first field effect transistor MOSFET1 is formed on one side of the groove, and the first active area Ar1 is provided with sources S1 and S2 of the first field effect transistor MOSFET1, and a second active area Ar2 of a second field effect transistor MOSFET2 is formed on the other side of the groove, and the second active area Ar2 is provided with sources s1 and s2 of the second field effect transistor MOSFET2, wherein the groove forms at least one bend on the other surface of the semiconductor layer 200.
[0048] Depend on Figure 5 It can be seen that since the interface of the power device 10 is a groove with a bending portion, the current after it is turned on will flow from the interface formed by the bending portion. After the current flows into the first active area Ar1, it will choose a path close to the bending portion to flow into the second active area Ar2. In this way, the distribution of the current lines will be more uniform, reducing the problem of strong current line density near the interface and weak current line density far from the interface, thereby significantly improving the utilization efficiency of the active area.
[0049] In this way, by forming a groove with a bending portion on the surface of the semiconductor layer adjacent to the first field effect transistor and the second field effect transistor that is opposite to the metal layer, the relative area of the interface between the first active area and the second active area is expanded, so that the current lines flowing through the first active area and the second active area are distributed more evenly, thereby improving the utilization rate of the active area, thereby making the on-resistance of the power device more reasonable and the power device more efficient.
[0050] In one embodiment, each bending portion is located between the first extending portion and the second extending portion of the groove, and an extending direction of the first extending portion and an extending direction of the second extending portion form an angle less than 90 degrees.
[0051] For example, Figure 6 is a schematic diagram of an active region of a power device according to another embodiment of the present application, such as Figure 6 As shown, the first active area Ar1 and the second active area Ar2 of the power device 10 are located in the semiconductor layer 200, and the semiconductor layer 200 includes source electrodes S1, S2, S3, S4, s1, s2, s3 and s4, and a groove composed of a plurality of bending portions and extension portions, the first extension portion and the second extension portion are the side extension portions on the left and right sides of each bending portion, respectively, and the first extension portion is adjacent to the second extension portion.
[0052] For example: the extension direction of the first extension portion Y1 and the extension direction of the second extension portion Y2 form an angle less than 90 degrees, and the current flows from the relative interface between the first active area Ar1 and the second active area Ar2 to the second active area Ar2, wherein the relative interface is composed of the bending portion, the first extension portion and the second extension portion.
[0053] In this way, by designing the extension portion with an inclined angle, the current can flow through paths with short distances and low impedance as much as possible, so that the current line density is evenly distributed and the utilization rate of the active area is improved.
[0054] In one embodiment, an extending direction of the first extending portion and an extending direction of the second extending portion are substantially parallel.
[0055] For example, Figure 7 is a schematic diagram of an active region of a power device according to another embodiment of the present application, Figure 8 Schematic diagram of an active region of a power device according to another embodiment of the present application.
[0056] like Figure 7 and Figure 8 As shown, the first active area Ar1 and the second active area Ar2 of the power device 10 are located in the semiconductor layer 200, and the semiconductor layer 200 includes a plurality of source electrodes S5, S6, S7, S8, s5, s6, s7 and s8, and a groove composed of a plurality of bending portions and extension portions, the first extension portion and the second extension portion are the sides on the left and right sides of each bending portion, respectively, and the first extension portion is adjacent to the second extension portion.
[0057] For example: Figure 7 In the figure, the extension direction of the first extension portion y1 and the extension direction of the second extension portion y2 are roughly parallel, and the current flows from the relative interface between the first active area Ar1 and the second active area Ar2 to the second active area Ar2, wherein the relative interface is composed of the bending portion, the first extension portion and the second extension portion.
[0058] In this way, by designing the extension parts to be parallel to each other, the current can flow through as many paths with short distance and low impedance as possible, so that the current line density is evenly distributed and the utilization rate of the active area is improved.
[0059] In one embodiment, the smaller the distance between the first extension portion and the bending portion, the larger the width of the groove at the first extension portion; and the smaller the distance between the second extension portion and the bending portion, the larger the width of the groove at the second extension portion.
[0060] For example, Fig. 9(c1~c2) are schematic diagrams of the changes in the bending portion of a power device according to an embodiment of the present application, wherein c1 is a schematic diagram of the bending portion of the power device when the first extension portion Y1 is far away from the bending portion, and c2 is a schematic diagram of the bending portion of the power device when the first extension portion Y1 is close to the bending portion.
[0061] When the distance between the first extension portion or the second extension portion and the bending portion is smaller, in order to increase the utilization rate of the active area, it is necessary to expand the relative area of the interface between the first active area Ar1 and the second active area Ar2. Therefore, by adjusting the width W at the first extension portion or the second extension portion, the wider the width W, the larger the relative area of the interface. At this time, the number of bending portions will also change.
[0062] In this way, the utilization rate of the active area is improved, thereby making the on-resistance of the power device more reasonable and the use efficiency of the power device higher.
[0063] Similarly, in one embodiment, the smaller the distance between the first extension portion and the bending portion, the smaller the depth of the groove at the first extension portion, and the smaller the distance between the second extension portion and the bending portion, the smaller the depth of the groove at the second extension portion.
[0064] In other words, continue to refer to Fig. 9 When the distance between the first extension portion and the bending portion is smaller, in order to expand the utilization rate of the active area, it is necessary to expand the relative area of the interface between the first active area Ar1 and the second active area Ar2. Therefore, by adjusting the width W at the first extension portion or the second extension portion, when the width W of the bending portion increases, the depth H of the bending portion can be reduced. By designing appropriate width W and depth H, the relative area of the interface is increased.
[0065] In this way, the utilization rate of the active area is improved, thereby making the on-resistance of the power device more reasonable and the use efficiency of the power device higher.
[0066] In one embodiment, the depth of the trench is uniform at various locations on the other surface of the semiconductor layer.
[0067] Specifically, for a common drain field effect transistor with a double-tube vertical structure, the semiconductor layers 200 of the two field effect transistors are adjacent, and a groove is formed on the surface of the semiconductor layer 200 of one field effect transistor facing away from the metal layer 100, then a groove of the same depth is also formed on the surface of the semiconductor layer 200 of the other field effect transistor facing away from the metal layer 100.
[0068] In one embodiment, a plurality of electrodes forming the source of the first field effect transistor and a plurality of electrodes forming the source of the second field effect transistor are symmetrically distributed on both sides of the trench.
[0069] In another embodiment, a plurality of electrodes forming the source of the first field effect transistor are uniformly distributed in the first active region, and a plurality of electrodes forming the source of the second field effect transistor are uniformly distributed in the second active region.
[0070] That is to say, Figure 6 , Figure 7 , Figure 8 and Fig. 9 In the embodiment, the multiple source electrodes S on the first active area Ar1 and the second active area Ar2 are symmetrically distributed on both sides of the groove, and the multiple electrodes forming the source S of the first field effect transistor MOSFET1 are evenly distributed in the first active area Ar1, and the multiple electrodes forming the source S of the second field effect transistor MOSFET2 are evenly distributed in the second active area Ar2.
[0071] That is, Figure 6 As shown, multiple electrodes S1, S2, S3 and S4 forming the source S of the first field effect transistor MOSFET1 are evenly distributed, and multiple electrodes s1, s2, s3 and s4 forming the source S of the second field effect transistor MOSFET2 are evenly distributed, and S1 is symmetrical to s1. Similarly, S2, S3 and S4 are symmetrical to s2, s3 and s4 respectively.
[0072] In one embodiment, at least one bending portion includes a first bending portion and a second bending portion that are alternately arranged, the electrode forming the source of the first field effect transistor is arranged corresponding to the first bending portion, and the electrode forming the source of the second field effect transistor is arranged corresponding to the second bending portion.
[0073] Continue to refer to Figure 6 The first bending portion may be a lower bending portion, and the second bending portion may be an upper bending portion, wherein the first bending portion of the first bending portion bend1 corresponds to the source S1 of the first field effect transistor MOSFET1, and the second bending portion of the first bending portion bend1 corresponds to the source s1 of the second field effect transistor MOSFET2.
[0074] It should be noted that the gate G of the first field effect transistor may also correspond to the first bending portion, and the gate G of the second field effect transistor may also correspond to the second bending portion, which is not limited here.
[0075] Fig.10 This is a schematic diagram of the structure of a power switch device according to an embodiment of the present application. The specific embodiments of the present application do not limit the specific implementation of the electronic device. Fig.10 As shown, the power switch device 20 includes a power device 10 according to any one of the above embodiments.
[0076] Through the electronic device of this embodiment, a groove with a bending portion is formed on the surface of the semiconductor layer adjacent to the first field effect transistor and the second field effect transistor that is opposite to the metal layer, thereby expanding the relative area of the interface between the first active area and the second active area, so that the current lines flowing through the first active area and the second active area are more evenly distributed, thereby improving the utilization rate of the active area, thereby making the on-resistance of the power device more reasonable and the use efficiency of the power device higher.
[0077] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.
[0078] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present application.
[0079] The above implementation methods are only used to illustrate the embodiments of the present application, and are not limitations on the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present application. The scope of patent protection of the embodiments of the present application should be limited by the claims.
Claims
1. A power device, characterized in that: include: A metal layer, forming a common drain of the first field effect transistor and the second field effect transistor; A semiconductor layer, one surface of the semiconductor layer is bonded to the metal layer, a groove is formed on the other surface of the semiconductor layer facing away from the metal layer, one side of the groove forms a first active area of the first field effect transistor, the first active area is provided with a source of the first field effect transistor, and the other side of the groove forms a second active area of the second field effect transistor, the second active area is provided with a source of the second field effect transistor, wherein the groove forms at least one bending portion on the other surface of the semiconductor layer.
2. The power device according to claim 1, characterized in that: Each bending portion is located between the first extending portion and the second extending portion of the groove, and an extending direction of the first extending portion and an extending direction of the second extending portion form an angle less than 90 degrees.
3. The power device according to claim 2, characterized in that: An extending direction of the first extending portion and an extending direction of the second extending portion are substantially parallel.
4. The power device according to claim 2, characterized in that: The smaller the distance between the first extension portion and the bending portion is, the larger the width of the groove at the first extension portion is; and the smaller the distance between the second extension portion and the bending portion is, the larger the width of the groove at the second extension portion is.
5. The power device according to claim 2, characterized in that: The smaller the distance between the first extension portion and the bending portion is, the smaller the depth of the groove at the first extension portion is; and the smaller the distance between the second extension portion and the bending portion is, the smaller the depth of the groove at the second extension portion is.
6. The power device according to claim 1, characterized in that: The depth of the trench is uniform at each position on the other surface of the semiconductor layer.
7. The power device according to claim 1, characterized in that: A plurality of electrodes forming the source of the first field effect transistor and a plurality of electrodes forming the source of the second field effect transistor are symmetrically distributed on both sides of the groove.
8. The power device according to claim 7, characterized in that: The at least one bending portion includes a first bending portion and a second bending portion that are alternately arranged, The electrode forming the source of the first field effect transistor is arranged corresponding to the first bending portion, and the electrode forming the source of the second field effect transistor is arranged corresponding to the second bending portion.
9. The power device according to claim 1, characterized in that: A plurality of electrodes forming the source of the first field effect transistor are evenly distributed in the first active region, and a plurality of electrodes forming the source of the second field effect transistor are evenly distributed in the second active region.
10. A power switch device, characterized in that: include: A power device according to any one of claims 1 to 9.