Display panel and display device

Abstract

The utility model discloses a display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area, and the non-display area comprises a binding area located on one side of the display area and a first peripheral area located between the binding area and the display area; a plurality of sub-pixels located in the display area; the driving circuit is located in the non-display area and electrically connected with the sub-pixels of the display area; the data lines are located in the display area and extend to the non-display area, and the sub-pixels are electrically connected with the data lines; the plurality of binding pads are located in the binding area; the first power line is located in the non-display first peripheral area, and the first power line is electrically connected with the binding bonding pad; the signal transmission lines are at least located in the first peripheral area and electrically connected with the driving circuit; in the direction perpendicular to the display panel, the multiple signal transmission lines are overlapped with the first power lines; the ratio of the overlapping area of any two signal transmission lines and the first power line is larger than or equal to 0.95 and smaller than or equal to 1.05.

Description

Technical Field

[0001] The utility model relates to display technology, and more specifically, to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) is an active light-emitting display device with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, display devices using OLED as the light-emitting element and thin film transistor (TFT) for signal control have become the mainstream products in the current display field.

[0003] In some technologies, the display panel has a problem of uneven brightness. Utility Model Content

[0004] The utility model provides a display panel, comprising: a display area and a non-display area surrounding the display area, the non-display area comprising a binding area located on one side of the display area and a first peripheral area located between the binding area and the display area; a plurality of sub-pixels located in the display area; a plurality of drive signal lines located in the display area and extending along a first direction, the plurality of drive signal lines being electrically connected to the plurality of sub-pixels; a drive circuit located in the non-display area, the drive circuit being electrically connected to the plurality of drive signal lines; a plurality of data lines located in the display area and extending to the non-display area along a second direction, the plurality of sub-pixels being electrically connected to the plurality of data lines, the first direction and the second direction intersecting each other. fork; a plurality of first power sub-lines, located in the display area and extending along the second direction, the plurality of sub-pixels being electrically connected to the plurality of first power sub-lines; a plurality of binding pads, located in the binding area; a first power line, located in the non-display area, the first power line being electrically connected to the plurality of first power sub-lines and the binding pads; a plurality of signal transmission lines, located at least in the first peripheral area, the plurality of signal transmission lines being electrically connected to the drive circuit; in a direction perpendicular to the display panel, the plurality of signal transmission lines overlap with the first power line; wherein the ratio of the overlapping area between any two of the plurality of signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05.

[0005] In an exemplary embodiment, the first power line includes a first main body extending along the first direction and a first extension portion extending along the second direction, the first main body is located in the first peripheral area, the first extension portion is located in the first peripheral area and extends to the binding area, one end of the first extension portion is connected to the first main body, and the other end of the first extension portion is electrically connected to the binding pad; the first direction is parallel to the extension direction of the edge of the display area close to the first peripheral area; each of the plurality of signal transmission lines includes a first straight portion, a second straight portion and a connecting portion, the first straight portion and the second straight portion extend along the first direction, the second straight portion is located on one side of the second direction of the first straight portion, the first straight portion and the second straight portion are connected to each other through the connecting portion, the first straight portion is electrically connected to the driving circuit, and the second straight portion is configured to be electrically connected to the integrated circuit; the first main body overlaps with the first straight portion of a portion of the plurality of signal transmission lines, and the first extension portion overlaps with the second straight portion of the plurality of signal transmission lines.

[0006] In an exemplary embodiment, the first power line further includes at least one first compensation portion, the first compensation portion is connected to the first extension portion, and in a direction perpendicular to the display panel, the first compensation portion overlaps with the second straight line portion of another part of the plurality of signal transmission lines; the ratio of the overlapping areas of any two of the signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the overlapping area of ​​each of the signal transmission lines and the first main body portion is a first area, the overlapping area of ​​each of the signal transmission lines and the first compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0007] In an exemplary embodiment, the first compensating portions are distributed on one side or both sides of the first extending portion along the first direction, and a single first compensating portion overlaps with the second straight portion of at least one of the signal transmission lines.

[0008] In an exemplary embodiment, the first power line further includes at least one second compensation portion, the second compensation portion is connected to the first extension portion, and the second compensation portion and the first compensation portion are distributed on both sides of the first extension portion along the first direction; in a direction perpendicular to the display panel, the second compensation portion overlaps with the second straight line portions of another part of the plurality of signal transmission lines; the ratio of the overlapping areas of any two of the signal transmission lines with the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the overlapping area of ​​each of the signal transmission lines with the first main body portion is a first area, the sum of the overlapping areas of each of the signal transmission lines with the first compensation portion and the second compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0009] In an exemplary embodiment, the first power line further includes at least one third compensation portion, the third compensation portion overlaps with the second straight line portion of a portion of the plurality of signal transmission lines, and is the same as the signal transmission line overlapped by the third compensation portion and the signal transmission line overlapped by the first main body portion; the ratio of the overlapping areas of any two of the signal transmission lines with the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the sum of the overlapping areas of each of the signal transmission lines with the first main body portion and the third compensation portion is a first area, the overlapping area of ​​each of the signal transmission lines with the first compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05; or, the sum of the overlapping areas of each of the signal transmission lines with the first main body portion and the third compensation portion is a first area, the sum of the overlapping areas of each of the signal transmission lines with the first compensation portion and the second compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0010] In an exemplary embodiment, a plurality of the third compensating portions are distributed on both sides of the first extending portion along the first direction, and a single third compensating portion overlaps with at least one of the second straight line portions.

[0011] In an exemplary embodiment, along the second direction, a line width of the second straight line portion of the signal transmission line that does not overlap with the first body portion is greater than a line width of the second straight line portion of the signal transmission line that overlaps with the first body portion.

[0012] In an exemplary embodiment, the line widths of the second straight line portions of the signal transmission line not overlapping the first body portion are equal, and the line widths of the second straight line portions of the signal transmission line overlapping the first body portion are equal.

[0013] In an exemplary embodiment, the first extension portion includes a first narrow neck portion and a first wide neck portion, and along the first direction, the line width of the first narrow neck portion is smaller than the line width of the first wide neck portion; in a direction perpendicular to the display panel, the second straight line portion of the signal transmission line overlapping with the first main body portion overlaps with the first narrow neck portion; the second straight line portion of the signal transmission line that does not overlap with the first main body portion overlaps with the first wide neck portion.

[0014] In an exemplary embodiment, the first power line includes one first main body portion and two first extension portions, the two first extension portions are arranged along the first direction and are electrically connected to different binding pads; the two first extension portions are respectively located on both sides of the integrated circuit along the first direction.

[0015] In an exemplary embodiment, the display panel also includes a second power line, which is located in the non-display area and surrounds the display area, the portion of the second power line located in the first peripheral area is located on both sides of the first extension portion along the first direction, and the second power line overlaps with multiple signal transmission lines.

[0016] In an exemplary embodiment, a portion of the second power line located in the first peripheral area includes a second main body portion extending along the first direction and a second extension portion extending along the second direction, one end of the second extension portion is connected to the second main body portion, and the other end of the second extension portion is electrically connected to the binding pad; in a direction perpendicular to the display panel, the second main body portion overlaps with the connecting portion, and the second extension portion overlaps with the second straight line portion.

[0017] In an exemplary embodiment, the non-display area also includes a second peripheral area surrounding the display area and away from one side of the binding area; the second peripheral area includes the driving circuit, and the driving circuit includes at least one of a gate driving circuit or a light emitting control driving circuit.

[0018] In an exemplary embodiment, the plurality of signal transmission lines include at least one of a gate drive control line and a light emission control line; the gate drive control line is electrically connected to the gate drive circuit, and the light emission control line is electrically connected to the light emission control drive circuit.

[0019] An embodiment of the utility model further provides a display device, comprising the display panel as described above.

[0020] The display panel proposed in the embodiment of the utility model sets the ratio of the overlapping area between any two signal transmission lines located in the first peripheral area and the first power line to be greater than or equal to 0.95 and less than or equal to 1.05, so that the capacitance generated by the overlap between each signal transmission line of the multiple signal transmission lines and the first power line is similar, thereby reducing the difference in signals transmitted by the multiple signal transmission lines, ensuring the display effect of the display panel, and solving the problem of uneven brightness of the display panel.

[0021] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by implementing the utility model. The purpose and other advantages of the utility model can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the technical solution of the utility model and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the utility model and do not constitute a limitation on the technical solution of the utility model.

[0023] Figure 1 This is a schematic diagram of the structure of the display panel in the embodiment of the utility model;

[0024] Figure 2 is a schematic structural diagram of a display panel in yet another exemplary embodiment;

[0025] Figure 3 In the exemplary embodiment Figure 2 An enlarged schematic diagram of the dotted area C;

[0026] Figure 4 In yet another exemplary embodiment Figure 2 An enlarged schematic diagram of the dotted area C;

[0027] Figure 5 In yet another exemplary embodiment Figure 2 An enlarged schematic diagram of the dotted area C;

[0028] Figure 6 In yet another exemplary embodiment Figure 2 An enlarged schematic diagram of the dotted area C;

[0029] Figure 7 In yet another exemplary embodiment Figure 2 An enlarged schematic diagram of the dotted area C;

[0030] Figure 8is an equivalent circuit diagram of a gate driving circuit in an exemplary embodiment. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the utility model more clear, the embodiments of the utility model will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0032] The utility model describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the utility model. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0033] The present invention includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features and elements of the present invention may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present invention may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0034] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be appreciated by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0035] In the drawings, the size of one or more components, the thickness of a layer, or a region may be exaggerated for clarity. In addition, the drawings schematically illustrate ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0036] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0037] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on the present utility model. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the circumstances.

[0038] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this utility model can be understood according to the circumstances.

[0039] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0040] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0041] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0042] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0043] The embodiments of the present utility model will be described in detail below with reference to the accompanying drawings.

[0044] Figure 1 Schematic diagram of the structure of the display panel in the embodiment of the utility model. Figure 1 As shown, the display panel provided in this embodiment includes: a display area 100 and a non-display area located around the display area 100. The non-display area includes: a binding area 700 located on one side of the display area 100 along the second direction Y, a first peripheral area 200 located between the display area 100 and the binding area 700, and a second peripheral area 300 located outside the display area 100 and away from the binding area 400. The first peripheral area 200 is connected to the second peripheral area 300 and surrounds the display area 100. The display area 100 includes at least a plurality of sub-pixels P arranged regularly, for example, the plurality of sub-pixels P can be arranged in an array along the first direction X and the second direction Y, and the first direction X and the second direction Y intersect. The plurality of sub-pixels P are configured to display dynamic pictures or still images, and the display area 100 can be referred to as an effective area (AA). A column of sub-pixels P arranged along the second direction Y may be connected to the same data line 101, and a plurality of data lines 101 may be connected to an integrated circuit 120 subsequently bound to the display panel, and the integrated circuit 120 provides data signals to the corresponding sub-pixels P through the data lines 101 to drive the sub-pixels P to display. In an exemplary embodiment, the display panel may be deformable, such as curled, bent, folded, or rolled up. The display panel includes an upper frame and a lower frame relatively arranged along the second direction Y, and a left frame and a right frame relatively arranged along the first direction X, the lower frame being a frame on the side where the binding area 700 is located, the frame on the side opposite to the binding area 700 along the second direction Y may be referred to as an upper frame, and the right frame is located on the side of the left frame along the first direction X.

[0045] In an exemplary embodiment, the shape of the display area 100 may be a quadrilateral, a circle, an ellipse, a polygon of other shapes or an irregular shape, etc., and the corner shape of the display area 100 may be a rounded corner, which is not limited in the present invention. In an exemplary embodiment, the edge shape of the display area at different frames varies with the shape of the display area, for example, it may be a straight line, a curve, a fold line, etc., which is not limited in the present invention.

[0046] In an exemplary embodiment, the first peripheral area 200 may include a fan-out area 400, a bending area 500 and a driver chip area 600 arranged in sequence in a direction away from the display area 100. The fan-out area 400 is connected to the display area 100 and may include at least a plurality of data lead-out lines. The power line, data line 101 and other signal lines located in the display area 100 may pass through the fan-out area 400 in the form of fan-out routing and be connected to the corresponding signal supply end. The subsequent integrated circuit (IC) 120 may be bound and connected to the driver chip area 600, and the integrated circuit 120 is configured to be connected to the plurality of data lead-out lines. The binding area 700 may include at least a plurality of bonding pads 701, and a flexible printed circuit (FPC) or a chip on flex (COF) may be bound and connected to the bonding pads 701 of the binding area 700.

[0047] In an exemplary embodiment, the first peripheral area 200 includes at least a power line for transmitting a voltage signal to the plurality of sub-pixels P. Figure 1 As shown, the power line may include a first power line 210, which may be connected to a high voltage power line (VDD) of the display area 100 and configured to transmit a high voltage signal, such as a positive voltage signal, to a plurality of sub-pixels P of the display area 100. The first power line 210 is connected to a bonding pad 701 of the bonding area 700.

[0048] In an exemplary embodiment, the second peripheral area 300 includes at least a circuit area 301, which can be arranged on both sides of the display area 100 along the first direction X and can be connected to the display area 100. The circuit area 301 includes multiple driving circuits, such as a gate driving circuit. Multiple signal transmission lines S1 of the multiple driving circuits can pass through the fan-out area 400 in a fan-out routing manner and be connected to the integrated circuit 120, thereby receiving signals from the integrated circuit 120 and driving the sub-pixel P.

[0049] As the display quality requirements of display panels increase, the resolution and refresh rate of display panels are getting higher and higher, the number of sub-pixels P in each row of the display area 100 along the first direction X increases, the wiring load of the driving circuit connected to the sub-pixels P in this row increases, and the rising and falling edges in the pixel charging process increase, resulting in a shorter pixel charging time and a poor display effect. Figure 1 In the structure shown, the number of signal transmission lines S1 is increased, for example, four clock signal lines are used to provide clock signals for the gate driving circuit. However, when the frame of the display panel becomes narrower, the size of the fan-out area 400 along the second direction Y becomes smaller, which is not conducive to the wiring arrangement in the fan-out area 400. Figure 1 As shown, taking the signal transmission line S1 as the clock signal line as an example, a part of the four clock signal lines overlap with the first power line 210, while another part of the clock signal lines do not overlap with the first power line 210. Capacitance is generated at the intersection of the clock signal line and the first power line 210, resulting in different loads on different clock signal lines, which in turn causes different charging times for pixels by different clock signal lines, resulting in uneven brightness of the display panel, especially at low grayscales.

[0050] The utility model provides a display panel, comprising: a display area and a non-display area surrounding the display area, the non-display area comprising a binding area located on one side of the display area and a first peripheral area located between the binding area and the display area; a plurality of sub-pixels located in the display area; a plurality of drive signal lines located in the display area and extending along a first direction, the plurality of drive signal lines being electrically connected to the plurality of sub-pixels; a drive circuit located in the non-display area, the drive circuit being electrically connected to the plurality of drive signal lines; a plurality of data lines located in the display area and extending to the non-display area along a second direction, the plurality of sub-pixels being electrically connected to the plurality of data lines, the first direction and the second direction intersecting each other. fork; a plurality of first power sub-lines, located in the display area and extending along the second direction, the plurality of sub-pixels being electrically connected to the plurality of first power sub-lines; a plurality of binding pads, located in the binding area; a first power line, located in the non-display area, the first power line being electrically connected to the plurality of first power sub-lines and the binding pads; a plurality of signal transmission lines, located at least in the first peripheral area, the plurality of signal transmission lines being electrically connected to the drive circuit; in a direction perpendicular to the display panel, the plurality of signal transmission lines overlap with the first power line; wherein the ratio of the overlapping area between any two of the plurality of signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05.

[0051] The display panel provided by the embodiment of the utility model sets the ratio of the overlapping area between any two signal transmission lines located in the first peripheral area and the first power line to be greater than or equal to 0.95 and less than or equal to 1.05, so that the capacitance generated by the overlap between each signal transmission line of the multiple signal transmission lines and the first power line is similar, thereby reducing the difference in signals transmitted by the multiple signal transmission lines and ensuring the display effect of the display panel.

[0052] In an exemplary embodiment, the first power line includes a first main body extending along the first direction and a first extension portion extending along the second direction, the first main body is located in the first peripheral area, the first extension portion is located in the first peripheral area and extends to the binding area, one end of the first extension portion is connected to the first main body, and the other end of the first extension portion is electrically connected to the binding pad; the first direction is parallel to the extension direction of the edge of the display area close to the first peripheral area; each of the plurality of signal transmission lines includes a first straight portion, a second straight portion and a connecting portion, the first straight portion and the second straight portion extend along the first direction, the second straight portion is located on one side of the second direction of the first straight portion, the first straight portion and the second straight portion are connected to each other through the connecting portion, the first straight portion is electrically connected to the driving circuit, and the second straight portion is configured to be electrically connected to the integrated circuit; the first main body overlaps with the first straight portion of a portion of the plurality of signal transmission lines, and the first extension portion overlaps with the second straight portion of the plurality of signal transmission lines.

[0053] In an exemplary embodiment, the first power line further includes at least one first compensation portion, the first compensation portion is connected to the first extension portion, and in a direction perpendicular to the display panel, the first compensation portion overlaps with the second straight line portion of another part of the plurality of signal transmission lines; the ratio of the overlapping areas of any two of the signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the overlapping area of ​​each of the signal transmission lines and the first main body portion is a first area, the overlapping area of ​​each of the signal transmission lines and the first compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0054] In an exemplary embodiment, the first compensating portions are distributed on one side or both sides of the first extending portion along the first direction, and a single first compensating portion overlaps with the second straight line portion of at least one of the signal transmission lines.

[0055] In an exemplary embodiment, the first power line further includes at least one second compensation portion, the second compensation portion is connected to the first extension portion, and the second compensation portion and the first compensation portion are distributed on both sides of the first extension portion along the first direction; in a direction perpendicular to the display panel, the second compensation portion overlaps with the second straight line portions of another part of the plurality of signal transmission lines; the ratio of the overlapping areas of any two of the signal transmission lines with the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the overlapping area of ​​each of the signal transmission lines with the first main body portion is a first area, the sum of the overlapping areas of each of the signal transmission lines with the first compensation portion and the second compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0056] In an exemplary embodiment, the first power line further includes at least one third compensation portion, the third compensation portion overlaps with the second straight line portion of a portion of the plurality of signal transmission lines, and is the same as the signal transmission line overlapped by the third compensation portion and the signal transmission line overlapped by the first main body portion; the ratio of the overlapping areas of any two of the signal transmission lines with the first power line is greater than or equal to 0.95 and less than or equal to 1.05, including: the sum of the overlapping areas of each of the signal transmission lines with the first main body portion and the third compensation portion is a first area, the overlapping area of ​​each of the signal transmission lines with the first compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05; or, the sum of the overlapping areas of each of the signal transmission lines with the first main body portion and the third compensation portion is a first area, the sum of the overlapping areas of each of the signal transmission lines with the first compensation portion and the second compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05.

[0057] In an exemplary embodiment, a plurality of the third compensating portions are distributed on both sides of the first extending portion along the first direction, and a single third compensating portion overlaps with at least one of the second straight line portions.

[0058] In an exemplary embodiment, along the second direction, a line width of the second straight line portion of the signal transmission line that does not overlap with the first body portion is greater than a line width of the second straight line portion of the signal transmission line that overlaps with the first body portion.

[0059] In an exemplary embodiment, the line widths of the second straight line portions of the signal transmission line not overlapping the first body portion are equal, and the line widths of the second straight line portions of the signal transmission line overlapping the first body portion are equal.

[0060] In an exemplary embodiment, the first extension portion includes a first narrow neck portion and a first wide neck portion, and along the first direction, the line width of the first narrow neck portion is smaller than the line width of the first wide neck portion; in a direction perpendicular to the display panel, the second straight line portion of the signal transmission line overlapping with the first main body portion overlaps with the first narrow neck portion; the second straight line portion of the signal transmission line that does not overlap with the first main body portion overlaps with the first wide neck portion.

[0061] In an exemplary embodiment, the first power line includes one first main body portion and two first extension portions, the two first extension portions are arranged along the first direction and are electrically connected to different binding pads; the two first extension portions are respectively located on both sides of the integrated circuit along the first direction.

[0062] In an exemplary embodiment, the display panel also includes a second power line, which is located in the non-display area and surrounds the display area, the portion of the second power line located in the first peripheral area is located on both sides of the first extension portion along the first direction, and the second power line overlaps with multiple signal transmission lines.

[0063] In an exemplary embodiment, a portion of the second power line located in the first peripheral area includes a second main body portion extending along the first direction and a second extension portion extending along the second direction, one end of the second extension portion is connected to the second main body portion, and the other end of the second extension portion is electrically connected to the binding pad; in a direction perpendicular to the display panel, the second main body portion overlaps with the connecting portion, and the second extension portion overlaps with the second straight line portion.

[0064] In an exemplary embodiment, the non-display area also includes a second peripheral area surrounding the display area and away from one side of the binding area; the second peripheral area includes the driving circuit, and the driving circuit includes at least one of a gate driving circuit or a light emitting control driving circuit.

[0065] In an exemplary embodiment, the plurality of signal transmission lines include at least one of a gate drive control line and a light emission control line; the gate drive control line is electrically connected to the gate drive circuit, and the light emission control line is electrically connected to the light emission control drive circuit.

[0066] Figure 2FIG. 1 is a schematic diagram of the structure of a display panel in another exemplary embodiment. Figure 2 As shown, the display area 100 includes a plurality of first power sub-lines 230 extending along the second direction Y, a column of sub-pixels P arranged along the second direction Y is electrically connected to the same first power sub-line 230, and a plurality of first power sub-lines 230 are electrically connected to the first power line 210. The power lines of the first peripheral area 200 also include a second power line 220, which is connected to a low voltage power line (VSS) of the second peripheral area 300 to transmit a low voltage signal, such as a negative voltage signal, to the plurality of sub-pixels P of the display area 100. The second power line 220 may be distributed in the first peripheral area 200 and the second peripheral area 300, and the second power line 220 may surround the display area 100. The first power line 210 and the second power line 220 are respectively connected to the binding pads 701 of the binding area 700.

[0067] In an exemplary embodiment, the plurality of driving circuits may include at least a gate driving circuit (Gate GOA) 310 and a light emitting control driving circuit (EM GOA) 320. The display area 100 further includes a plurality of driving signal lines extending along the first direction X. The pixel driving circuits of a row of sub-pixels P arranged along the first direction X are electrically connected to the same driving signal line. The plurality of driving signal lines may include a scanning signal line (Gate line) 330, a light emitting signal line (EM line) 340, and a reset signal line (not shown). Figure 2 As shown, the scanning signal line 330 is electrically connected to the gate driving circuit 310 , and the light emitting signal line 340 is electrically connected to the light emitting control driving circuit 320 .

[0068] In an exemplary embodiment, a plurality of signal transmission lines are at least located in the first peripheral region 200, one end of the plurality of signal transmission lines is electrically connected to the driving circuit, and the other end can be electrically connected to the integrated circuit 120 or the bonding pad 701 to receive corresponding signals. For example, the plurality of signal transmission lines may include a gate drive control line of the gate drive circuit 310, the gate drive control line includes a clock signal line T, a high voltage transmission line, and a low voltage transmission line, etc. The clock signal line T may be connected to the first clock signal terminal GCK1 and the second clock signal terminal GCK2 of the gate drive circuit 310, the high voltage transmission line may connect the first power line 210 to the first power terminal VGH of the gate drive circuit 310, and the low voltage transmission line may connect the second power line 220 to the second power terminal VGL; the plurality of signal transmission lines may also include a light emitting control line 340 of the light emitting control drive circuit 320, etc. In the following figures, the signal transmission line is taken as an example of the clock signal line T to illustrate the scheme of the embodiment of the utility model, and the utility model does not limit the type of the signal transmission line.

[0069] In an exemplary embodiment, the plurality of clock signal lines T of the gate driving circuit 310 and / or the light emission control driving circuit may pass through the fan-out region 400 in a fan-out routing manner and be electrically connected to the integrated circuit 120. Figure 2 In the figure, multiple clock signal lines T overlap with the first power line 210 and the second power line 220 respectively. Since the line width perpendicular to the extension direction of the line is basically the same, when the first power line 210 or the second power line 220 overlaps with multiple signal transmission lines T, the capacitance generated at the overlapping point of the lines is basically the same, which will not cause differences in the loads of different clock signal lines T.

[0070] In an exemplary embodiment, the multiple clock signal lines T, the first power line 210 and the second power line 220 on the display panel may be arranged in bilateral symmetry along the first direction X, and the present invention is not limited thereto. Figure 3 In the exemplary embodiment Figure 2 The enlarged schematic diagram of the dotted area C. Figure 3As shown, the first power line 210 of the first peripheral area 200 includes a first main body 211 and a first extension 212, the first main body 211 can extend along the first direction X, the first extension 212 can extend along the second direction Y, one end of the first extension 212 can be connected to the first main body 211, and the other end of the first extension 212 can be connected to the corresponding binding pad 701 to receive the corresponding high voltage signal. In an exemplary embodiment, the first direction X can be an extension direction parallel to the edge of the display area 100 close to the first peripheral area 200, and the second direction Y can intersect with the first direction X, for example, the second direction Y can be perpendicular to the first direction X. The first peripheral area 200 may include a plurality of clock signal lines T arranged in sequence along the second direction Y. In a direction perpendicular to the display panel, the first extension portion 212 overlaps with multiple clock signal lines T, the first main body portion 211 overlaps with a part of the multiple clock signal lines T, and the first power line 210 also includes a first compensation portion 213 connected to the first extension portion 212, the first compensation portion 213 overlaps with another part of the multiple clock signal lines T, the overlapping area between each clock signal line T and the first main body portion 211 is a first area, and the overlapping area between each clock signal line T and the first compensation portion 213 is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05. In this embodiment, by setting the first compensation part 213 on the first power line 210, and setting the first area where each clock signal line T overlaps with the first main body 211 and the second area where each clock signal line T overlaps with the first compensation part 213 to be approximately equal, the first compensation part 213 is used to compensate the clock signal line T that does not overlap with the first main body 211, so that the overlapping area of ​​each clock signal line T and the first power line 210 is greater than or equal to 0.95 and less than or equal to 1.05, avoiding the inconsistency of the transmission signals of multiple clock signal lines T caused by the different capacitances generated at the overlap, which helps to ensure the uniform display brightness of the display panel. In addition, by setting the first compensation part 213, the path for water vapor to invade the display panel can be increased, which helps to prevent water vapor invasion and improve the display defects caused by water vapor invasion of the display panel.

[0071] In an exemplary embodiment, the first area is equal to the second area.

[0072] In an exemplary embodiment, if Figure 3As shown, the plurality of clock signal lines T include a first signal line 11, a second signal line 12, a third signal line 13, and a fourth signal line 14 arranged in sequence along the second direction Y. In a direction perpendicular to the display panel, the first main body 211 may overlap with the first signal line 11 and the second signal line 12, and does not overlap with the third signal line 13 and the fourth signal line 14. The first compensation portion 213 overlaps with the third signal line 13 and the fourth signal line 14, and does not overlap with the first signal line 11 and the second signal line 12. The first extension portion 212 overlaps with the first signal line 11, the second signal line 12, the third signal line 13, and the fourth signal line 14. In other embodiments, the plurality of clock signal lines T may include n signal lines, the first main body 211 may overlap with 1 to n-1 signal lines, and the first compensation portion 213 overlaps with the remaining signal lines of the n signal lines, where n is an integer greater than or equal to 2, for example, n may be greater than or equal to 4, and the present invention is not limited thereto.

[0073] In an exemplary embodiment, if Figure 3 As shown, each clock signal line T may include a first straight portion L1, a second straight portion L2 and a connecting portion L3. The first straight portion L1 and the second straight portion L2 may extend along the first direction X. The second straight portion L2 is located on one side of the first straight portion L1 in the second direction Y. The first straight portion L1 and the second straight portion L2 are connected to each other through the connecting portion L3. The first straight portion L1 may be electrically connected to the driving circuit, and the second straight portion L2 may be electrically connected to the integrated circuit 120 later. The first main portion 211 may overlap with the first straight portion L1 of the first signal line 11 and the first straight portion L1 of the second signal line 12. The first compensation portion 213 may overlap with the second straight portion L2 of the third signal line 13 and the second straight portion L2 of the fourth signal line 14. The first extension portion 212 overlaps with the second straight portion L2 of the first signal line 11, the second straight portion L2 of the second signal line 12, the second straight portion L2 of the third signal line 13 and the second straight portion L2 of the fourth signal line 14. In other embodiments, the first power line 210 may include a plurality of first compensation portions 213 , and each first compensation portion 213 may overlap with at least one second straight portion L2 , which is not limited in the present invention.

[0074] In an exemplary embodiment, the first compensation portion 213 may be located on one side of the first extension portion 212 along the first direction X. For example, the first compensation portion 213 may be located on the left or right side of the first extension portion 212 along the first direction X, or a plurality of first compensation portions 213 may be distributed on one side or both sides of the first extension portion 212 along the first direction X. The orthographic projection of the first compensation portion 213 on the display panel may be a rectangle, a circle, an ellipse, a triangle, other quadrilaterals and polygons, and an irregular shape, etc., and the present invention is not limited thereto.

[0075] In an exemplary embodiment, the second power line 220 located in the first peripheral area 200 can be arranged on both sides of the first extension portion 212 along the first direction X, that is, the second power line 220 can be arranged on the side of the first extension portion 212 close to the left frame or the right frame of the display panel. The second power line 220 of the first peripheral area 200 includes a second main body portion 221 and a second extension portion 222. The second main body portion 221 can extend along the first direction X, and the second extension portion 222 can extend along the second direction Y. One end of the second extension portion 222 can be connected to the second main body portion 221, and the other end of the second extension portion 222 can be connected to the corresponding binding pad 701 to receive the corresponding low voltage signal. The second power line 220 can overlap with the first signal line 11, the second signal line 12, the third signal line 13 and the fourth signal line 14, as shown in FIG. Figure 3 As shown, the second main body 221 of the second power line 220 may overlap with the connecting portion L3 of the first signal line 11, the connecting portion L3 of the second signal line 12, the connecting portion L3 of the third signal line 13, and the connecting portion L3 of the fourth signal line 14, and the second power line 220 may overlap with the second straight portion L2 of the first signal line 11, the second straight portion L2 of the second signal line 12, the second straight portion L2 of the third signal line 13, and the second straight portion L2 of the fourth signal line 14, but the present invention does not impose any restrictions on this.

[0076] In an exemplary embodiment, the first power line 210 may include two first extensions 212, and the two first extensions 212 may be sequentially arranged along the first direction X and connected to different binding pads 701. After the display panel is bound and connected to the integrated circuit 120, the two first extensions 212 may be distributed on both sides of the integrated circuit 120 along the first direction X.

[0077] Figure 4 In yet another exemplary embodiment Figure 2 An enlarged schematic diagram of the dashed area C. Figure 4 and Figure 3 The difference between the first compensation part 213 and the first power line 210 is that the shape of the first compensation part 213 is different, and the first power line 210 also includes a second compensation part 214. Other contents can refer to the above description. Figure 3 The description will not be repeated here.

[0078] In an exemplary embodiment, if Figure 4As shown, the first main body portion 211 may overlap with the first straight portion L1 of the first signal line 11 and the first straight portion L1 of the second signal line 12, the first compensation portion 213 may overlap with the second straight portion L2 of the third signal line 13 and the second straight portion L2 of the fourth signal line 14, and the second compensation portion 214 may overlap with the second straight portion L2 of the third signal line 13 and the second straight portion L2 of the fourth signal line 14. The overlapping area of ​​each clock signal line T with the first main body portion 211 is the first area, and the sum of the overlapping areas of each clock signal line T with the first compensation portion 213 and the second compensation portion 214 is the second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05. By arranging the first compensation part 213 and the second compensation part 214 on the first power line 210, the first compensation part 213 and the second compensation part 214 are used to compensate for the clock signal line T that does not overlap with the first main body 211, so that the overlapping area of ​​the first power line 210 and each clock signal line T is substantially equal, avoiding the inconsistency of the transmission signals between the multiple clock signal lines T caused by the different capacitances generated at the overlapping parts, which helps to ensure the uniform display brightness of the display panel. Figure 3 As shown in the solution, the solution of this embodiment helps to reduce the size of the compensation part located on one side of the first extension part 212 by providing the first compensation part 213 and the second compensation part 214, thereby facilitating the wiring design.

[0079] In an exemplary embodiment, if Figure 4 As shown, the first compensating portion 213 and the second compensating portion 214 are both connected to the first extending portion 212, and the first compensating portion 213 and the second compensating portion 214 can be located at both ends of the first extending portion 212 along the first direction X. Figure 4 As shown, the orthographic projections of the first compensation portion 213 and the second compensation portion 214 on the display panel are rectangles with one side being a curve. In other embodiments, the shapes of the first compensation portion 213 and the second compensation portion 214 may be different, and the orthographic projections of the first compensation portion 213 and the second compensation portion 214 may be other shapes, and the present invention does not impose any limitation on this.

[0080] Figure 5 In yet another exemplary embodiment Figure 2 An enlarged schematic diagram of the dashed area C. Figure 5 and Figure 4 The difference is that the first power line 210 also includes a plurality of third compensation parts 215. Other contents can refer to the above description. Figure 4 The description will not be repeated here.

[0081] In an exemplary embodiment, a plurality of third compensation portions 215 may be connected to the first extension portion 212, and the plurality of third compensation portions 215 may be distributed on one side or both sides of the first extension portion 212 along the first direction X, the third compensation portion 215 overlaps with the second straight portion L2, and the clock signal line T overlapped with the third compensation portion 215 is the same as the clock signal line T overlapped with the first main body portion 211. The sum of the overlapping areas of each clock signal line T with the first main body portion 211 and the third compensation portion 215 is the first area, and the sum of the overlapping areas of each clock signal line T with the first compensation portion 213 and the second compensation portion 214 is the second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05. In this embodiment, by adding the third compensation portion 215, the paths for water vapor to invade the display panel can be increased at different positions, which helps to prevent water vapor invasion and improve the display defects caused by water vapor invasion of the display panel.

[0082] In an exemplary embodiment, if Figure 5 As shown, four third compensation portions 215 may be distributed on both sides of the first extension portion 212 along the first direction X, wherein two third compensation portions 215 may overlap with the first signal line 11, and the other two third compensation portions 215 may overlap with the second signal line 12. In other embodiments, any number of third compensation portions 215 may be provided as required, and a single third compensation portion 215 may overlap with a greater number of signal lines, which is not limited in the present invention.

[0083] Figure 6 In yet another exemplary embodiment Figure 2 An enlarged schematic diagram of the dashed area C. Figure 6 and Figure 3 The difference between the first power line 210 and the clock signal line T is the structure of the first power line 210 and the clock signal line T. The other contents can refer to the above description. Figure 3 The description will not be repeated here.

[0084] In an exemplary embodiment, if Figure 6As shown, the first main portion 211 of the first power line 210 overlaps with the first straight portion L1 of the first signal line 11 and the first straight portion L1 of the second signal line 12, and does not overlap with the third signal line 13 and the fourth signal line 14. The first extension portion 212 of the first power line 210 overlaps with the second straight portion L2 of the first signal line 11, the second straight portion L2 of the second signal line 12, the second straight portion L2 of the third signal line 13, and the second straight portion L2 of the fourth signal line 14. Along the second direction Y, the line width of the second straight portion L2 of the first signal line 11 can be a first width d1, the line width of the second straight portion L2 of the second signal line 12 can be a second width d2, the line width of the second straight portion L2 of the third signal line 13 can be a third width d3, and the line width of the second straight portion L2 of the fourth signal line 14 can be a fourth width d4. The first width d1 and the second width d2 can be equal, the third width d3 and the fourth width d4 can be equal, and the third width d3 can be greater than the first width d1, so that the ratio of the overlapping area between any two clock signal lines T and the first power line 210 is greater than or equal to 0.95 and less than or equal to 1.05, and the overlapping area between each clock signal line T and the first power line 210 is approximately equal.

[0085] exist Figure 6 In the embodiment, the first width d1 and the second width d2 may be kept unchanged, and the values ​​of the third width d3 and the fourth width d4 may be increased; or the third width d3 and the fourth width d4 may be kept unchanged, and the values ​​of the first width d1 and the second width d2 may be reduced, and the present invention does not impose any limitation on this.

[0086] Figure 7 In yet another exemplary embodiment Figure 2 An enlarged schematic diagram of the dashed area C. Figure 7 and Figure 3 The difference lies in the structure of the first power line 210. For other contents, please refer to the above description. Figure 3 The description will not be repeated here.

[0087] In an exemplary embodiment, if Figure 7As shown, the first main body 211 of the first power line 210 overlaps with the first straight portion L1 of the first signal line 11 and the first straight portion L1 of the second signal line 12, and does not overlap with the third signal line 13 and the fourth signal line 14. The first extension portion 212 of the first power line 210 includes a first narrow neck portion 216 and a first wide neck portion 217. In the first direction X, the line width between the opposite side surfaces of the first narrow neck portion 216 is a fifth width d5, and the line width between the opposite side surfaces of the first wide neck portion 217 is a sixth width d6. The fifth width d5 ​​is less than the sixth width d6. The first narrow neck portion 216 overlaps with the second straight portion L2 of the first signal line 11 and the second straight portion L2 of the second signal line 12. The first wide neck portion 217 overlaps with the second straight portion L2 of the third signal line 13 and the fourth signal line 14. The second straight portions L2 of the clock signal lines T and the first power line 210 overlap with each other, so that the overlapping area between the first narrow neck portion 216 and the second straight portion L2 of the first signal line 11 and the second straight portion L2 of the second signal line 12 is smaller than the overlapping area between the first wide neck portion 217 and the second straight portion L2 of the third signal line 13 and the second straight portion L2 of the fourth signal line 14, so that the overlapping area of ​​each clock signal line T and the first power line 210 is substantially equal, and the ratio of the overlapping area of ​​any two clock signal lines T to the first power line 210 is greater than or equal to 0.95 and less than or equal to 1.05.

[0088] In an exemplary embodiment, Figures 3 to 7 The schemes in the above can be combined with each other arbitrarily. For example, a compensation part can be added while changing the line width, and the utility model does not limit this. The above figures are all illustrated by taking the signal transmission line as a clock signal line T as an example. The signal transmission line can also be a signal line that transmits other signals. The number of signal transmission lines and the overlapping relationship with the first power line can be set as needed, and the utility model does not limit this.

[0089] Figure 8 FIG. 1 is an equivalent circuit diagram of a gate drive circuit in an exemplary embodiment. Figure 8 As shown, the gate driving circuit includes: a first scanning transistor GT1 to an eighth scanning transistor GT8, a first scanning capacitor GC1 and a second scanning capacitor GC2.

[0090] In an exemplary embodiment, a gate electrode of the first scanning transistor GT1 is electrically connected to the first clock signal terminal GCK1, a first electrode of the first scanning transistor GT1 is electrically connected to the input terminal GIN, and a second electrode of the first scanning transistor GT1 is electrically connected to the first node G1; a gate electrode of the second scanning transistor GT2 is electrically connected to the first node G1, a first electrode of the second scanning transistor GT2 is electrically connected to the first clock signal terminal GCK1, and a second electrode of the second scanning transistor GT2 is electrically connected to the second node G2; a gate electrode of the third scanning transistor GT3 is electrically connected to the first clock signal terminal GCK1, a first electrode of the third scanning transistor GT3 is electrically connected to the second power supply terminal VGL, and a second electrode of the third scanning transistor GT3 is electrically connected to the second node G2; a gate electrode of the fourth scanning transistor GT4 is electrically connected to the second node G2, a first electrode of the fourth scanning transistor GT4 is electrically connected to the first power supply terminal VGH, and a second electrode of the fourth scanning transistor GT4 is electrically connected to the output terminal GOUT; a gate electrode of the fifth scanning transistor GT5 is electrically connected to the third node G3, and a first electrode of the fifth scanning transistor GT5 is electrically connected to the output terminal GOUT; One electrode of the fifth scanning transistor GT5 is electrically connected to the second clock signal terminal GCK2, and the second electrode of the fifth scanning transistor GT5 is electrically connected to the output terminal GOUT; the gate electrode of the sixth scanning transistor GT6 is electrically connected to the second node G2, the first electrode of the sixth scanning transistor GT6 is electrically connected to the first power supply terminal VGH, and the second electrode of the sixth scanning transistor GT6 is electrically connected to the first electrode of the seventh scanning transistor GT7; the gate electrode of the seventh scanning transistor GT7 is electrically connected to the second clock signal terminal GCK2, and the second electrode of the seventh scanning transistor GT7 is electrically connected to the first node G1; the gate electrode of the eighth scanning transistor GT8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth scanning transistor GT8 is electrically connected to the first node G1, and the second electrode of the eighth scanning transistor GT8 is electrically connected to the third node G3; one end of the first scanning capacitor GC1 is electrically connected to the first power supply terminal VGH, and the other end of the first scanning capacitor GC1 is electrically connected to the second node G2; the first plate GC21 of the second scanning capacitor GC2 is electrically connected to the output terminal GOUT, and the second plate GC22 of the second scanning capacitor GC2 is electrically connected to the third node G3.

[0091] In an exemplary embodiment, the first to eighth scanning transistors GT1 to GT8 may be P-type transistors or may be N-type transistors.

[0092] In an exemplary embodiment, the first power terminal VGH can be connected to the first power line 210 through a high voltage transmission line to continuously provide a high level signal, and the second power terminal VGL can be connected to the second power line 220 through a low voltage transmission line to continuously provide a low level signal.

[0093] In an exemplary embodiment, four clock signal lines can be used to provide clock signals for the gate drive circuit 310, or six, eight, or a greater number of clock signal lines can be used to provide clock signals for the gate drive circuit 310. The utility model does not limit the circuit structure used by the gate drive circuit 310 and the number of clock signal lines used.

[0094] The embodiment of the utility model further provides a display device, including the display panel described in any of the above embodiments. The display device can be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function, but the embodiment of the utility model is not limited thereto.

[0095] Although the implementation methods disclosed in the utility model are as above, the above contents are only implementation methods adopted to facilitate the understanding of the utility model, and are not used to limit the utility model. Any technician in the field to which the utility model belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the utility model, but the scope of patent protection of the utility model shall still be defined by the attached claims.

Claims

1. A display panel, characterized in that: include: a display area and a non-display area surrounding the display area, wherein the non-display area includes a binding area located at one side of the display area and a first peripheral area located between the binding area and the display area; A plurality of sub-pixels are located in the display area; A plurality of driving signal lines, located in the display area and extending along a first direction, the plurality of driving signal lines being electrically connected to the plurality of sub-pixels; A driving circuit, located in the non-display area, the driving circuit being electrically connected to the plurality of driving signal lines; a plurality of data lines, located in the display area and extending along a second direction to the non-display area, the plurality of sub-pixels and the plurality of data lines are electrically connected, and the first direction intersects with the second direction; a plurality of first power supply sub-lines, located in the display area and extending along the second direction, the plurality of sub-pixels being electrically connected to the plurality of first power supply sub-lines; A plurality of binding pads, located in the binding area; A first power line, located in the non-display area, the first power line being electrically connected to the plurality of first power sub-lines and the binding pad; a plurality of signal transmission lines, at least located in the first peripheral area, the plurality of signal transmission lines being electrically connected to the driving circuit; in a direction perpendicular to the display panel, the plurality of signal transmission lines overlap with the first power line; Wherein, a ratio of an overlapping area between any two of the plurality of signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.

05.

2. The display panel according to claim 1, characterized in that: The first power line includes a first main body extending along the first direction and a first extension extending along the second direction, the first main body is located in the first peripheral area, the first extension is located in the first peripheral area and extends to the binding area, one end of the first extension is connected to the first main body, and the other end of the first extension is electrically connected to the binding pad; the first direction is parallel to the extension direction of the edge of the display area close to the first peripheral area; Each of the plurality of signal transmission lines comprises a first straight portion, a second straight portion and a connecting portion, the first straight portion and the second straight portion extending along the first direction, the second straight portion being located on one side of the first straight portion in the second direction, the first straight portion and the second straight portion being connected to each other via the connecting portion, the first straight portion being electrically connected to the driving circuit, and the second straight portion being configured to be electrically connected to the integrated circuit; The first main body portion overlaps with the first straight line portions of a portion of the signal transmission lines, and the first extension portion overlaps with the second straight line portions of the plurality of signal transmission lines.

3. The display panel according to claim 2, characterized in that: The first power line further includes at least one first compensation portion, the first compensation portion is connected to the first extension portion, and in a direction perpendicular to the display panel, the first compensation portion overlaps with the second straight line portion of another part of the signal transmission lines among the plurality of signal transmission lines; The ratio of the overlapping areas of any two of the signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, comprising: The overlapping area between each signal transmission line and the first main body is a first area, and the overlapping area between each signal transmission line and the first compensation part is a second area. The ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.

05.

4. The display panel according to claim 3, characterized in that: The first compensating portion is distributed on one side or both sides of the first extending portion along the first direction, and a single first compensating portion overlaps with the second straight portion of at least one of the signal transmission lines.

5. The display panel according to claim 3, characterized in that: The first power line further includes at least one second compensation portion, the second compensation portion is connected to the first extension portion, and the second compensation portion and the first compensation portion are distributed on both sides of the first extension portion along the first direction; in a direction perpendicular to the display panel, the second compensation portion overlaps with the second straight line portion of another part of the signal transmission lines among the plurality of signal transmission lines; The ratio of the overlapping areas of any two of the signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, comprising: The overlapping area between each signal transmission line and the first main body is a first area, the sum of the overlapping areas between each signal transmission line and the first compensation part and the second compensation part is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.

05.

6. The display panel according to claim 3 or 5, characterized in that: The first power line further includes at least one third compensation portion, the third compensation portion overlaps with the second straight line portion of a portion of the signal transmission lines among the plurality of signal transmission lines, and is the same as the signal transmission line overlapped with the third compensation portion and the signal transmission line overlapped with the first main portion; The ratio of the overlapping areas of any two of the signal transmission lines and the first power line is greater than or equal to 0.95 and less than or equal to 1.05, comprising: The sum of the overlapping areas of each of the signal transmission lines with the first main portion and the third compensation portion is a first area, the overlapping area of ​​each of the signal transmission lines with the first compensation portion is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.05; or, The first power line also includes at least one second compensation part, the sum of the overlapping areas of each signal transmission line with the first main part and the third compensation part is a first area, the sum of the overlapping areas of each signal transmission line with the first compensation part and the second compensation part is a second area, and the ratio of the first area to the second area is greater than or equal to 0.95 and less than or equal to 1.

05.

7. The display panel according to claim 6, characterized in that: The plurality of third compensating portions are distributed on both sides of the first extending portion along the first direction, and a single third compensating portion overlaps with at least one of the second straight line portions.

8. The display panel according to claim 2, characterized in that: In the second direction, a line width of the second straight line portion of the signal transmission line that does not overlap with the first main body portion is greater than a line width of the second straight line portion of the signal transmission line that overlaps with the first main body portion.

9. The display panel according to claim 8, characterized in that: The line widths of the second straight line portions of the signal transmission line that do not overlap with the first main body portion are equal, and the line widths of the second straight line portions of the signal transmission line that overlap with the first main body portion are equal.

10. The display panel according to claim 2, characterized in that: The first extension portion includes a first narrow neck portion and a first wide neck portion, and along the first direction, the line width of the first narrow neck portion is smaller than the line width of the first wide neck portion; In a direction perpendicular to the display panel, the second straight portion of the signal transmission line overlapping the first main body overlaps the first narrow neck portion; the second straight portion of the signal transmission line not overlapping the first main body overlaps the first wide neck portion.

11. The display panel according to claim 2, characterized in that: The first power line includes a first main body and two first extensions, the two first extensions are arranged along the first direction and are electrically connected to different binding pads; The two first extensions are respectively located at two sides of the integrated circuit along the first direction.

12. The display panel according to claim 2, characterized in that: The display panel also includes a second power line, which is located in the non-display area and surrounds the display area. The portion of the second power line located in the first peripheral area is located on both sides of the first extension portion along the first direction, and the second power line overlaps with multiple signal transmission lines.

13. The display panel according to claim 12, characterized in that: The portion of the second power line located in the first peripheral area includes a second main body extending along the first direction and a second extension portion extending along the second direction, one end of the second extension portion is connected to the second main body portion, and the other end of the second extension portion is electrically connected to the binding pad; In a direction perpendicular to the display panel, the second main body portion overlaps with the connecting portion, and the second extending portion overlaps with the second straight portion.

14. The display panel according to claim 1, characterized in that: The non-display area also includes a second peripheral area surrounding the display area and away from one side of the binding area; the second peripheral area includes the driving circuit, and the driving circuit includes at least one of a gate driving circuit or a light emitting control driving circuit.

15. The display panel according to claim 14, characterized in that: The plurality of signal transmission lines include at least one of a gate drive control line and a light emitting control line; the gate drive control line is electrically connected to the gate drive circuit, and the light emitting control line is electrically connected to the light emitting control drive circuit.

16. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 15.

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