Semiconductor structure

Abstract

A semiconductor structure includes a source / drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source / drain feature. The semiconductor structure includes a silicide layer over the source / drain features. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure comprises a metal layer between the side wall of the seed layer and the side wall of the dielectric layer, and the side wall of each silicide layer, the barrier layer and the metal layer are in direct contact with the side wall of the dielectric layer. The semiconductor structure includes a source / drain contact over the seed layer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure. Background Art

[0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have enabled the production of many generations of integrated circuits, each with smaller and more complex circuits than the previous one. As integrated circuits evolve, functional density (i.e., the number of interconnected components per unit chip area) generally increases while geometry size (i.e., the smallest component (or line) that can be produced by the manufacturing process) decreases. This scaling process generally provides many benefits by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of integrated circuit structures (such as three-dimensional transistors) and processes. To achieve these results, integrated circuit processing and manufacturing must also evolve in a similar manner. For example, as component dimensions continue to decrease, structural defects (such as voids) and contact resistance in source / drain contacts become more challenging. Although solutions to these challenges appear adequate, they are still not fully met in all aspects. Utility Model Content

[0003] According to at least one embodiment of the present disclosure, a semiconductor structure includes: a source / drain feature located in a semiconductor layer protruding from a substrate; a dielectric layer located above the source / drain feature; a silicide layer located above the source / drain feature; a barrier layer located above the silicide layer; a seed layer located above the barrier layer; a metal layer between a side wall of the seed layer and a side wall of the dielectric layer, a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacting the side wall of the dielectric layer; and a source / drain contact located above the seed layer.

[0004] According to at least one embodiment of the present disclosure, a semiconductor structure includes a gate, a source / drain feature adjacent to the gate, a dielectric layer between the gate and the source / drain feature, a silicide layer above the source / drain feature, a barrier layer above the silicide layer, a seed layer above the barrier layer, a metal layer between a side wall of the seed layer and a side wall of the dielectric layer, a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacts the side wall of the dielectric layer, and a source / drain contact above the seed layer.

[0005] According to at least one embodiment of the present disclosure, a semiconductor structure includes a semiconductor fin. An insulating region surrounding a bottom of the semiconductor fin. A source / drain feature located above the semiconductor fin. A dielectric layer located above the source / drain feature. A silicide layer located above the source / drain feature. A barrier layer located above the silicide layer. A seed layer located above the barrier layer. A metal layer between a side wall of the seed layer and a side wall of the dielectric layer, a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacts the side wall of the dielectric layer. A source / drain contact located above the seed layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a 3-dimensional perspective view of an example semiconductor device (e.g., a fin field effect transistor, or FinFET) according to some embodiments of the present disclosure;

[0008] Figure 2A is a flow chart of an example method of manufacturing a semiconductor device according to some embodiments;

[0009] Figure 2B and Figure 2C According to some embodiments of the present disclosure, a portion Figure 2A Example flow chart of the example method;

[0010] Figure 3 , Figure 5 , Fig.11 , Fig.13 is a cross-sectional view of an exemplary semiconductor device or a portion thereof according to some embodiments of the present disclosure, similar to Figure 1 An example semiconductor device along line BB is Figure 2A various manufacturing steps of the exemplary method;

[0011] Figure 4 , 8 , 10, 12, 14, 17, 19, 21, 23, 25, 27, 29, 31, 33 and 34 are cross-sectional views of exemplary semiconductor devices or portions thereof according to some embodiments of the present disclosure, similar to Figure 1 The example element is along the AA line. Figure 2A and / or Figures 2B to 2C Various manufacturing steps of an exemplary method;

[0012] Figure 6 , 7, 9, 15, 16, 18, 20, 22, 24, 26, 28, 30, 32, 35 and 36 are cross-sectional views of example semiconductor devices or portions thereof according to some embodiments of the present disclosure, similar to Figure 1 The example element is along the CC line. Figure 2A and / or Figures 2B to 2C Various fabrication steps in an exemplary method.

[0013]

Explanation of symbols

[0014] 100: Components

[0015] 102:Substrate

[0016] 104: Fin

[0017] 106: Insulation area

[0018] 108: Gate dielectric layer

[0019] 110: Gate

[0020] 120: Gate structure

[0021] 112S: Source / Drain Region

[0022] 112D: Source / drain region

[0023] 200: Method

[0024] 202: Operation

[0025] 204: Operation

[0026] 206: Operation

[0027] 208: Operation

[0028] 210: Operation

[0029] 212: Operation

[0030] 214: Operation

[0031] 216: Operation

[0032] 218: Operation

[0033] 250: Method

[0034] 252: Operation

[0035] 254: Operation

[0036] 256: Operation

[0037] 258: Operation

[0038] 260: Operation

[0039] 262: Operation

[0040] 264: Operation

[0041] 266: Operation

[0042] 268: Operation

[0043] 270: Operation

[0044] 300: Components

[0045] 302:Substrate

[0046] 304: Fin

[0047] 306: Insulation area

[0048] 308: Groove

[0049] 310: dummy gate structure

[0050] 311: Channel Area

[0051] 312: Mask

[0052] 314: Lightly doped drain region

[0053] 320:Padding

[0054] 322: Pad

[0055] 330: Source / Drain Characteristics

[0056] 344: Contact Etch Stop Layer

[0057] 346: Interlayer dielectric layer

[0058] 347: Dielectric layer

[0059] 348: Gate trench

[0060] 356: Gate dielectric layer

[0061] 358: Gate

[0062] 360:Metal Gate Structure

[0063] 380: contact opening

[0064] 384:Metal layer

[0065] 384b: Part

[0066] 384r:Part

[0067] 384s:Part

[0068] 384t:Part

[0069] 386: Silicide layer

[0070] 388: Barrier layer

[0071] 388b: Part

[0072] 388t:Part

[0073] 390:Metal layer

[0074] 390b: Part

[0075] 390bb:Partial

[0076] 390s:Part

[0077] 390t:Part

[0078] 391:Polymer layer

[0079] 392:Metal layer

[0080] 394: Source / drain contact

[0081] 402: Directional deposition process

[0082] 404: Directional processing technology

[0083] 406: Etching process

[0084] 408: Etching process

[0085] 410: Selective Deposition Process

[0086] D1: Depth

[0087] D2: Total thickness (total depth)

[0088] T1: Thickness

[0089] T2: Thickness

[0090] T3:Thickness

[0091] T4:Thickness

[0092] T5:Thickness

[0093] T': thickness DETAILED DESCRIPTION

[0094] The following disclosure provides many different embodiments or examples for implementing the different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, in various examples, the disclosure may repeat reference numbers and / or letters. This repetition is for the purpose of simplicity and clarity, and does not itself define the relationship between the various embodiments and / or configurations discussed.

[0095] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," and "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and likewise the spatially relative descriptors used herein may be interpreted accordingly. As used herein, the terms "about" and "approximately" mean plus or minus 10% of the recited value, e.g., "about 0.5" includes the range 0.45 to 0.55, "about 10" includes 9 to 11, and "about 1000" includes 900 to 1100.

[0096] Figure 1 1 is an exemplary perspective view of a non-planar semiconductor device 100 (hereinafter referred to as device 100), such as a FinFET or a multi-gate transistor (e.g., a gate all around transistor, or GAA transistor, a vertical multi-gate transistor, etc.), according to various embodiments. Device 100 includes a substrate 102 and a fin 104 protruding therefrom. An insulating region 106 is formed on opposite sides of the fin 104, and the fin 104 protrudes upwardly from the insulating region 106. A gate dielectric layer 108 spans the channel region of the fin 104, and is formed along the sidewalls of the fin 104 and above the upper surface of the fin 104. A gate 110 is formed on the gate dielectric layer 108, together with a gate structure 120. Source / drain regions 112D and 112S (with source / drain features formed thereon, not depicted) are disposed on the fin 104 and on opposite sides of the gate dielectric layer 108 and the gate 110. Source / drain regions 112D and 112S extend outward from gate 110 . Figure 1 is a reference diagram provided to illustrate some rear cross-sectional views. For example, Figure 3 , 5The cross-sectional views of 11 and 13 are taken along line BB (ie, along the Y axis), which extends along the longitudinal axis of the gate structure 120 of the device 100. Figure 4 , 8 , 10, 12, 14, 17, 19, 21, 23, 25, 27, 29, 31, 33 and 34 are taken along line AA (i.e., along the X-axis), which is along the horizontal axis of the fin 104 and extends in the direction of the channel region of the fin 104 between the source / drain regions 112D and 112S as current penetrates. Figure 6 , 7 The cross-sections of , 9, 15, 16, 18, 20, 22, 24, 26, 28, 30, 32, 35 and 36 are taken along line CC (i.e., along the Y axis), extending parallel to the longitudinal axis of the gate structure 120, and passing through the source / drain regions 112S / 112D. The following figures will be referred to through these cross-sections for clarity.

[0097] Figure 2A Flowchart of method 200 for forming a non-planar semiconductor device according to one or more embodiments of the present disclosure. For example, at least a portion of the operations in method 200 may be used to fabricate a fin field effect transistor, a multi-gate transistor (e.g., a gate-wrap transistor, a vertical transistor, etc.) including a nanosheet transistor or a nanowire transistor element, a vertical transistor, or the like. It should be noted that method 200 is merely an example and is not intended to be limited to the present disclosure. Therefore, it should be understood that more operations may be performed in Figure 2A The method 200 is provided before, during, and after. Certain other operations may be only briefly mentioned here. In some embodiments, the operations of the method 200 may be similar to the exemplary FinFET device 300 (hereinafter referred to as device 300) in various manufacturing processes such as Figures 3 to 36 This is related to the cross-sectional view, which will be explained in more detail later. Figure 2B and Figure 2C 2 is a flow chart of a method 250 for generating a portion of a component 300 according to one or more embodiments of the present disclosure. In addition, the embodiments of the component 300 are not limited to the depicted embodiment. For example, the component 300 may include many other components, such as an inductor, an electrical fuse, a capacitor, a coil, etc., which are not shown here for simplicity.

[0098] refer to Figure 2A and Figure 3, method 200 provides a substrate 302 of device 300 at operation 202. Substrate 302 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI), or the like, which may be doped (e.g., with the addition of a P-type dopant or an N-type dopant) or undoped. Substrate 302 may be a wafer, such as a silicon wafer. Generally, a semiconductor on insulator substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, which is generally a silicon substrate or a glass substrate. Other substrates, such as multi-layer or gradient substrates may also be used. In some embodiments, the semiconductor material of substrate 302 may include silicon, germanium, a silicon carbide compound semiconductor, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, a semiconductor alloy including silicon germanium, gallium arsenic phosphide, aluminum indium arsenic, aluminum gallium arsenic, gallium indium arsenic, gallium indium phosphide and / or gallium indium arsenic phosphide, or a combination thereof.

[0099] Also refer to Figure 2A and Figure 3 , the method 200 forms a (semiconductor) fin 304 at operation 204 and protrudes or extends vertically from the substrate 302. The fin 304 can be better understood as a semiconductor layer and protrudes from the substrate 302. Although the two fins 304 are Figure 3 (and subsequent figures), it should be understood that the device 300 may include any number of fins 304 and be included in the scope of the present disclosure. In some embodiments, the fins 304 are generated by patterning the substrate 302 by techniques such as photolithography and etching. For example, a mask layer (not depicted) including a pad oxide layer and an upper pad nitride layer is formed on the substrate 302. The pad oxide layer can be a thin layer and include silicon oxide such as generated by a thermal oxidation process. The pad oxide layer can function as an adhesion layer between the substrate 302 and the upper pad nitride layer. In some embodiments, the composition of the pad nitride layer is silicon nitride, silicon oxynitride, silicon carbide, the like, or a combination thereof. The pad oxide layer and the pad nitride layer can be generated by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), respectively.

[0100] The mask layer can be patterned by photolithography. In general, photolithography utilizes depositing a photoresist material (not depicted), irradiating (or exposing), and developing to remove a portion of the photoresist material. The remaining photoresist material, such as the mask layer in this example, can protect the underlying material during subsequent processes such as etching. For example, the photoresist material is used to pattern the pad oxide layer and the pad nitride layer to generate a patterned mask, which is subsequently used to pattern the exposed portion of the substrate 302 to generate the trench 308, thereby defining the Figure 3304 with separation grooves 308 as described in the figure. When multiple fins are generated, the grooves 308 are disposed in the middle of each adjacent fin 304. In some embodiments, the fins 304 can be generated by etching the substrate 302 grooves 308, such as reactive ion etching (RIE), neutral beam etching (NBE), similar methods or combinations thereof. The etching can be performed under non-isotropic conditions. In some embodiments, the grooves 308 can be parallel to each other in strips (viewed from above) and closely arranged with each other. In some embodiments, the grooves 308 can be continuous and surround each fin 304. In this regard, although not depicted herein, the upper surface of the fin 304 overlaps the patterned mask until removed by a subsequent process step.

[0101] The fin 304 may be patterned by other suitable methods. In one example, the fin 304 may be patterned using one or more photolithography processes, including double patterning processes and multiple patterning processes. In general, double patterning processes and multiple patterning processes combine photolithography processes and self-alignment processes so that patterns can be generated and have, for example, a pitch that is smaller than that of a single direct photolithography process. For example, in one embodiment, a sacrificial layer (not depicted) is generated on the substrate 302 and patterned using a photolithography process. A pad (not depicted) is generated next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining pad or mandrel can be used to pattern the fin 304.

[0102] In other examples, the upper portion of the substrate 302 may be replaced or overlapped with a suitable material, such as an epitaxial material (not depicted) suitable for the type of semiconductor device to be generated (e.g., p-type or n-type). The epitaxial material may be grown on the substrate 302 by any suitable epitaxial process. The substrate 302 containing the epitaxial material on the upper portion is then patterned by the above-mentioned photolithography process to form the fin 304 containing the epitaxial material.

[0103] Also refer to Figure 2A and Figure 3In operation 206, the method 200 forms an insulating region 306 on the substrate 302 and surrounds the bottom of the fin 304. The insulating region 306 formed of a dielectric material (or insulating material) can electrically isolate adjacent fins 304 from each other. The dielectric material can be an oxide such as silicon oxide (SiO or SiO2), a nitride, the like, or a combination thereof. The dielectric material can be formed by high density plasma chemical vapor deposition (HDPCVD), flow chemical vapor deposition (FCVD) (e.g., deposition based on chemical vapor deposition of materials in a mobile plasma system, followed by annealing or curing to densify the deposited material to other materials, such as oxides), spin coating, the like, or a combination thereof. Other dielectric materials and / or other formation processes can be used to form the insulating region 306. In the depicted embodiment, the dielectric material of the insulating region 306 includes silicon oxide formed by flow chemical vapor deposition. The annealing process can be performed after the dielectric material is deposited. A planarization process, such as a chemical mechanical polishing / grinding (CMP) process, may remove any excess dielectric material so that the surface of the upper dielectric material and the upper surface of the fin 304 are substantially coplanar. A patterned mask on the upper surface of the fin 304 may also be removed by the planarization process.

[0104] Then, if Figure 3 In the depicted trench 308, a dielectric material is buried to create an insulating region 306. In some embodiments, the insulating region 306 comprises a shallow trench isolation (STI) feature. The insulating region 306 is buried so that the upper portion of the fin 304 protrudes from the insulating region 306 and is between them. The upper surface of each insulating region 306 can have a flat surface (as shown), a protruding surface, a concave surface (e.g., a recess), or a combination thereof. The upper surface of the insulating region 306 can be contoured by a suitable etching process, such as a process that is selective to the material of the insulating region 306 with respect to the substrate 302 (and the fin 304). For example, a dry etching process or a wet etching process using diluted hydrofluoric acid (DHF) can be used to recess the dielectric material to create the insulating region 306.

[0105] As another example of forming the fin 304 and the insulating region 306, a dielectric layer (not depicted) may be grown on the upper surface of the substrate 302, trenches may be etched from the dielectric layer, a homoepitaxial structure may be grown epitaxially in the trenches, and the dielectric layer is buried in the homoepitaxial structure, which protrudes from the dielectric layer to form the fin 304. In another example, a dielectric layer (not depicted) may be grown on the upper surface of the substrate 302, trenches may be etched from the dielectric layer, a homoepitaxial structure may be grown epitaxially in the trenches from a material different from the substrate 302, and the dielectric layer is buried in the homoepitaxial structure, which protrudes from the dielectric layer to form the fin 304.

[0106] In embodiments where epitaxial material or epitaxial structures (e.g., heteroepitaxial structures or homoepitaxial structures) are grown, the grown material or structure may be doped in situ during the growth process, which may eliminate a prior or subsequent implantation process, although both in situ doping and implantation doping may be used simultaneously. In addition, it may be advantageous to have different materials for epitaxial growth of N-type component regions (e.g., regions configured to provide N-type metal oxide semiconductor (NMOS) components) and epitaxial growth of P-type component regions (e.g., regions configured to provide P-type metal oxide semiconductor (PMOS) components). In various embodiments, fin 304 may include silicon germanium (SiGe). x Ge 1-x , where x is between 0 and 1), silicon carbide, pure or nearly pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or the like. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, gallium indium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0107] refer to Figure 2A , Figure 4 and Figure 5 , the method 200 generates a dummy gate structure 310 in the channel region 311 of the fin 304 at operation 208. It is to be understood that other dummy gate structures 310 may be generated in the fin 304 while still being within the scope of the present disclosure.

[0108] In some embodiments, the dummy gate structure 310 may include a dummy gate dielectric layer on the fin 304 and a dummy gate on the dummy gate dielectric layer (not depicted separately). The dummy gate structure 310 may optionally include an interfacial layer between the fin 304 and the dummy gate dielectric layer, which may include an oxide, such as silicon oxide. The gate dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, multiple layers thereof, or the like. The dummy gate may include polysilicon.

[0109] The various layers of the dummy gate structure 310 may be deposited on the fin 304 as a capping layer by any suitable method, such as chemical vapor deposition, atomic layer deposition (ALD) or physical vapor deposition (PVD), thermal growth or chemical growth, and then planarized by, for example, chemical mechanical polishing. A mask layer comprising silicon nitride or the like may be deposited on each capping layer of the dummy gate structure 310. The mask layer may be patterned by a series of photolithography and etching processes to generate a mask 312. The pattern of the mask 312 may then be transferred to the capping layer by any suitable etching process to generate the dummy gate structure 310. The dummy gate structure 310 passes through or covers a portion of the fin 304 (e.g., the channel region 311), and the longitudinal direction of the dummy gate structure 310 (e.g., along the longitudinal direction of the dummy gate structure 310) may be substantially the same as that of the fin 304. Figure 1 The BB line of the fin 304 is substantially perpendicular to the longitudinal direction of the fin 304 (eg Figure 1 AA line).

[0110] refer to Figure 2A and Figure 4 The method 200 then generates some lightly doped drain (LDD) regions 314. The lightly doped drain regions 314 can be formed in portions of the fins 304 in each device region by a plasma doping process. The plasma doping process can include generating a patterned mask (not depicted) such as a patterned photoresist to cover regions of the device 300, which can be protected from the plasma doping process. Portions of the lightly doped drain regions 314 can extend downward along the first dummy gate structure 310 to the channel region 311. Figure 5 An example of a lightly doped drain region 314 is depicted but is not limited thereto. Other structures, shapes, and methods of forming the lightly doped drain region 314 are possible and are fully intended to be included in the scope of the present disclosure. For example, the lightly doped drain region 314 can be formed after the gate pad 320 / 322 is formed, which is described in more detail below. In some embodiments, the lightly doped drain region 314 is deleted from the device 300.

[0111] Also refer to Figure 4 After forming the lightly doped drain regions 314 and 316, a first gate pad 320 is formed around (along and in contact with) the dummy gate structure 310, and a second gate pad 322 is formed around (along and in contact with) the first gate pad 320. For example, the first gate pad 320 may be formed on the bidirectional sidewalls of the dummy gate structure 310, and the second gate pad 322 may be formed on the first gate pad 320. It is to be understood that any number of gate pads may be formed around the dummy gate structure 310 and still fall within the scope of the present disclosure.

[0112] The first gate liner 320 may be a liner of a low dielectric constant material (e.g., a dielectric constant lower than that of silicon oxide, about 3.9) and may include a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, the like, or a combination thereof. The second gate liner 322 may include a suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon carbide nitride, the like, or a combination thereof. According to various embodiments, the first gate liner 320 and the second gate liner 322 include different materials to provide etching selectivity between the two materials in subsequent processes. The first gate liner 320 and the second gate liner 322 may be formed by first conformally depositing a dielectric layer on the dummy gate structure 310, and the deposition method may be any suitable process, such as thermal oxidation, chemical vapor deposition, or the like, and then removing a portion of the dielectric layer by a suitable etching process (e.g., isotropic etching or anisotropic etching). Along the sidewalls of the dummy gate structure 310, the first gate liner 320 and the second gate liner 322 are left. The first gate pad 320 and the second gate pad may sometimes be collectively referred to as gate pads 320 / 322 .

[0113] refer to Figure 2A , Figure 4 , Figure 6 , Figure 7 In operation 210, method 200 forms a first source / drain feature 330 on fin 304. In the present embodiment, source / drain feature 330 may include silicon germanium doped with a P-type dopant (e.g., boron, indium, the like, or a combination thereof) to form a P-type device (e.g., a PFET). Alternatively, source / drain feature 330 may include silicon (Si) or silicon carbide (SiC) doped with an N-type dopant (e.g., phosphorus, arsenic, the like, or a combination thereof) to form an N-type device (e.g., a NFET).

[0114] The source / drain features 330 may be generated by first etching the fins 304 to generate recesses (not depicted) adjacent to each dummy gate structure 310, wherein the etching may be any suitable etching process, such as a dry etching process. For example, the recesses may be generated by an anisotropic dry etching process using the dummy gate structure 310 as an etching mask. Next, the source / drain features 330 are generated in the recesses by epitaxially growing a semiconductor material (e.g., silicon, silicon carbide, or silicon germanium) from the fins 304 that expose the recesses. This process may be achieved using any suitable method, such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. The generated source / drain features 330 are alternately arranged with respect to their corresponding dummy gate structures 310, wherein each dummy gate structure 310 is inserted between a pair of adjacent source / drain features 330 along the longitudinal extension of each fin 304 (e.g., Figure 1 AA line depicted).

[0115] The source / drain features 330 may have a dopant (e.g., impurity) concentration that varies with the location of the source / drain features 330. In some embodiments, the source / drain features 330 are doped in situ while the semiconductor material is epitaxially grown in the recesses. In some embodiments, the source / drain features 330 are doped after epitaxially growing the semiconductor material in the recesses. After doping the semiconductor material, an annealing process may be performed to activate the impurities.

[0116] like Figure 4 , Figure 6 and Figure 7 As depicted, source / drain features 330 may have upper surfaces elevated from the surface of fin 304 (e.g., elevated upward, in a direction other than the recessed portion of fin 304) and may have faces oriented along different crystallographic planes. In some embodiments, source / drain features 330 extend below the upper surface of insulating region 306. Figure 6 In some embodiments, the source / drain features 330 of adjacent fins 304 may be separated from each other. Figure 7 In some embodiments, source / drain features 330 of adjacent fins 304 may merge to create a continuous epitaxial source / drain feature. Figure 6 and Figure 7 The examples of the shapes of the source / drain features 330 provided are not limited thereto. For example, the source / drain features 330 can be configured as wraparound source / drain features that are epitaxially grown from the upper portion of the fin 304 without being recessed into the fin 304 .

[0117] refer to Figure 8 and Fig. 9 In operation 212, the method 200 forms an interlayer dielectric (ILD) layer 346 over the source / drain features 330 and adjacent to the dummy gate structure 310. In some embodiments, a contact etch stop layer (CESL) 344 is formed on the device 300 before forming the interlayer dielectric layer 346. The interlayer dielectric layer 346 and the contact etch stop layer 344 include different materials to provide etching selectivity between the two during subsequent manufacturing processes. The contact etch stop layer 344 can include any suitable dielectric material, such as silicon nitride, silicon oxynitride, silicon oxide, the like, or a combination thereof, and can be formed by any suitable method, such as chemical vapor deposition, atomic layer deposition, physical vapor deposition, the like, or a combination thereof.

[0118] Next, refer to Figure 8 and Fig. 9, an interlayer dielectric layer 346 is formed on the contact etch stop layer 344 and the dummy gate structure 310. In some embodiments, the interlayer dielectric layer 346 includes any suitable dielectric material, such as silicon dioxide, a low-k material, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), the like, or a combination thereof. It can also be deposited by any suitable deposition method, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, flow chemical vapor deposition, or the like. After the interlayer dielectric layer 346 is formed, a dielectric layer 347 will be formed on the interlayer dielectric layer 346. The function of the dielectric layer 347 can be a protective layer to prevent or reduce the loss of the interlayer dielectric layer 346 in the etching process in the subsequent process. In this regard, the dielectric layer 347 and the interlayer dielectric layer 346 can include different compositions to improve the etching selectivity between the two. The dielectric layer 347 may be formed using a suitable material, such as silicon nitride, silicon carbide, the like, or a combination thereof, and may be formed using a suitable method, such as chemical vapor deposition, plasma enhanced chemical vapor deposition, flow chemical vapor deposition, or the like. After the dielectric layer 347 is formed, a planarization process, such as a chemical mechanical polishing process, may be performed to flatten the upper surface of the dielectric layer 347. The chemical mechanical polishing process may also remove the mask 312 and a portion of the contact etch stop layer 344 disposed on the dummy gate structure 310. After the planarization process, the upper surface of the dielectric layer 347 is substantially at the same level as the upper surface of the dummy gate structure 310 depicted herein. In some embodiments, the dielectric layer 347 is removed, so that the interlayer dielectric layer 346, after being planarized, is substantially at the same level as the upper surface of the dummy gate structure 310.

[0119] refer to Figure 2A and Fig.10 , Fig.11 , Fig.12 and Fig.13 , method 200 replaces dummy gate structure 310 with metal gate structure 360 ​​in operation 214. An example of a replacement gate process (sometimes referred to as a gate last process) is performed to replace dummy gate structure 310 with metal gate structure 360, which may also be referred to as a replacement gate structure or an active gate structure.

[0120] refer to Fig.10 and Fig.11, method 200 removes dummy gate structure 310 to form gate trench 348. In some embodiments, dummy gate structure 310 is removed by one or more etching steps between first gate liner 320 to expose channel region 311 of fin 304. In some embodiments, dummy gate dielectric layer (not depicted) may be used as an etch stop layer when dummy gate is etched. In some embodiments, upper portion of first gate liner 320, second gate liner 322, or both may be removed (or shortened) by a suitable etching process to expose upper interlayer dielectric layer 346.

[0121] refer to Fig.12 and Fig.13 , the method 200 forms a metal gate structure in the gate trench 348. The metal gate structure 360 ​​is connected to the source / drain features to form a device, such as an N-type device or a P-type device.

[0122] In some embodiments, forming the metal gate structure 360 ​​includes conformally depositing a gate dielectric layer 356 in the gate trench 348 across the channel region 311 and the first gate pad 320. The gate dielectric layer 356 may include any suitable dielectric material, such as silicon oxide, silicon nitride, a high dielectric constant material (i.e., a material having a dielectric constant greater than that of silicon oxide, typically 3.9), the like, or a combination thereof. The high dielectric constant material may include oxides of hafnium, zirconium, lanthanum, magnesium, barium, titanium, lead, silicates thereof, the like, or a combination thereof. The gate dielectric layer 356 may be formed by any suitable method, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic beam deposition (MBD), the like, or a combination thereof. In some embodiments, before forming the gate dielectric layer 356, an interfacial layer (not depicted) may be formed in the gate trench 348 on the channel region 311. The interfacial layer may include an oxide such as silicon oxide, and may be formed by any suitable method, such as atomic layer deposition, chemical vapor deposition, thermal oxidation, chemical oxidation, the like, or a combination thereof.

[0123] Next, the method 200 forms a gate 358 on the gate dielectric layer 356 in operation 214, such that a metal gate structure 360 ​​is in the gate trench 348. The gate 358 may include any suitable metal, such as tungsten (W), copper (Cu), ruthenium (Ru), aluminum (Al), gold (Au), cobalt (Co). The gate 358 may be formed by any suitable method, such as physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, the like, or a combination thereof, to form a capping layer on the gate dielectric layer 356, followed by a planarization process such as chemical mechanical polishing to expose the upper surface of the first gate pad 320 and the second gate pad 322. Although not depicted herein, the gate 358 may additionally include a barrier layer, a seed layer, the like, or a combination thereof. In one example, the barrier layer may include titanium, tantalum, titanium nitride, tantalum nitride, the like, or a combination thereof, and may be deposited by any method, such as chemical vapor deposition or atomic layer deposition.

[0124] In some embodiments, although not depicted, one or more work function layers may be conformally formed on the gate dielectric layer 356 prior to forming the gate 358. The work function layer may include a P-type work function layer, an N-type work function layer, multiple layers of the above, or a combination thereof. The work function layer discussed herein may also be referred to as a work function metal. Examples of work function layers may include titanium nitride, tantalum nitride, ruthenium, molybdenum, aluminum, zirconium silicide, molybdenum silicide, tantalum silicide, nickel silicide, tungsten nitride, titanium, silver, tantalum aluminum, tantalum aluminum carbide, tantalum aluminum nitride, tantalum carbide, tantalum nitride, tantalum silicide, manganese, zirconium, the like, or a combination thereof. The work function value is related to the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value so that the target threshold voltage V t can be achieved. The work function layer can be deposited by chemical vapor deposition, physical vapor deposition, atomic layer deposition, the like, or a combination thereof. Other layers (not depicted) such as a capping layer, an adhesive layer (or an adhesion layer), the like, or a combination thereof, can also be generated between the gate dielectric layer 356 and the gate 358. The generation method can be any suitable method, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, atomic beam deposition, the like, or a combination thereof. In some embodiments, the capping layer can include silicon, silicon oxide, silicon nitride, the like, or a combination thereof. The adhesive layer can be titanium, tantalum, titanium nitride, tantalum nitride, the like, or a combination thereof, respectively. In some embodiments, the work function layer, the capping layer, the adhesive layer and / or their counterparts can be formed in a U-shape on the first silicon oxide layer 350, respectively, and the layer is also generated in a U-shape.

[0125] Common Reference Figure 2A and Figures 14 to 35 , method 200 generates source / drain contacts 394 on source / drain features 330 in operation 216. In this embodiment, reference Figure 2B and Figure 2C, operation 216 is performed by method 250. For clarity, method 250 is a portion of element 300, such as Fig.14 and Fig.15 The part enclosed by the dotted line. Specifically, Fig.16 , 18 , 20, 22, 24, 26, 28, 30, 32 and 35, which are the same as Fig.15 The viewing angle (i.e. along Figure 1 ), an embodiment of component 300 in various manufacturing steps in method 250 is listed. Fig.17 , 19 , 21, 23, 25, 27, 29, 31, 33 and 34, which are the same as Fig.14 The viewing angle (i.e. along Figure 1 AA line), an embodiment of the component 300 in various manufacturing steps in the method 250 is listed.

[0126] refer to Figure 2B , Fig.14 and Fig.15 , the method 250 generates a contact opening 380 to expose the source / drain features 330 at operation 252 .

[0127] Generating contact opening 380 includes generating a patterned mask (e.g., a patterned photoresist) over dielectric layer 347 and using it as an etching mask, and then etching dielectric layer 347, interlayer dielectric layer 346, and contact etch stop layer 344. After patterning interlayer dielectric layer 346 and contact etch stop layer 344, the patterned mask is then removed, and the removal method can be any suitable method, such as plasma ashing or photoresist stripping. In some embodiments, generating contact opening 380 removes a portion of source / drain features 330, such as Fig.15 shown.

[0128] refer to Figure 2B , Fig.16 and Fig.17 The method 250 performs a directional deposition process 402 in operation 254 to form a first metal layer 384 in the contact opening 380 , wherein a portion of the first metal layer 384 is then used to form a silicide layer 386 on the source / drain features 330 .

[0129] Directional deposition process 402 is performed using a plasma source, and plasma-based chemical vapor deposition is performed, such as capacitively coupled plasma (CCP) or inductively coupled plasma (ICP) to achieve directional deposition. Capacitively coupled plasma sources use capacitive coupling to a radio frequency (RF) power supply to generate plasma, while inductively coupled plasma sources use an inductor (such as a coil) to generate electromagnetic induction-generated energy to generate plasma. An electric field is generated between electrodes to ionize reactants, including precursors and / or reactant gases, and is generated in a reaction chamber. During operation, a suitable plasma source ionizes the reactants provided in the reaction chamber to generate plasma, including charged particles (such as ions, electrons, etc.). The charged particles are accelerated in a predetermined direction in the reactants to a sample pre-fixed in the reaction chamber, and the reaction products are deposited on the substrate surface in a corresponding predetermined direction.

[0130] In this embodiment, the directional deposition process 402 selectively generates the first metal layer 384 on the horizontal surfaces of the component 300 (e.g., extending along the XY plane) relative to the vertical surfaces (e.g., extending along the XZ plane and the YZ plane). In other words, the directional deposition process 402 generates more first metal layer 384 on the horizontal surfaces than on the vertical surfaces. Fig.16 and Fig.17 As described, the first metal layer 384 is conformal to the contact opening 380 and the interlayer dielectric layer 346, and includes an upper portion 384t of the interlayer dielectric layer 346, a bottom portion 384b on the source / drain feature 330, and a sidewall portion 384s along the sidewall of the contact opening 380. In this embodiment, the upper portion 384t has a thickness T1, the bottom portion 384b has a thickness T2, and the sidewall portion 384s has a thickness T3, wherein T1 and T2 are each greater than T3, and T2 is greater than T1. In some examples, although not depicted, T2 may be similar to or the same as T1. In some embodiments, as Fig.17 As shown by the dashed line, the portion of the first metal layer 384 adjacent to the upper sidewall of the contact opening 380 has a rounded profile instead of a sharp corner, so the change in thickness from the upper portion 384t (T1) to the sidewall portion 384s (T3) is gradual.

[0131] In the present embodiment, the first metal layer 384 includes titanium (Ti), tungsten (W), nickel (Ni), cobalt (Co), molybdenum (Mo), the like or a combination thereof. In this regard, the directional deposition process 402 may be performed using reaction precursors TiCl4, WCl5, MoCl5, Ni(CO)4, Co2(CO6)[HCC(C(CH3)3)], the like or a combination thereof, and a reactor body such as hydrogen (H2), argon (Ar) or a combination thereof. The specific composition of the reactants may be selected based on the composition of the first metal layer 384. In some embodiments, the reactants are introduced at a flow rate of about 10 sccm to about 1000 sccm. The plasma may be generated by a capacitively coupled plasma source or an inductively coupled plasma source, with a power of about 100 W to 2000 W and a chamber pressure of about 0.1 Torr to about 10 Torr. It is noteworthy that the reactants and process parameters provided herein are for exemplary purposes only and are not intended to limit the present embodiment thereto. In addition, although the details of the directional deposition process 402 have been discussed in the above paragraphs as a plasma-directed reaction, the present disclosure may also use an etching method-directed reaction to form the first metal layer 384 without the use of plasma. In addition, in some examples, the directional deposition process 402 may be performed by plasma-directed physical vapor deposition.

[0132] In the present embodiment, the directional deposition process 402 may be performed at an elevated temperature, such as from about 300° C. to 600° C., so that the bottom portion 384 b of the first metal layer 384 and the upper portion of the underlying source / drain features 330 form a silicide layer 386 comprising metal. In this regard, the bottom portion 384 b undergoes a silicide reaction to form a composition different from that of the upper portion 384 t and the spacer portion 384 s.

[0133] Next, refer to Figure 2B , Fig.18 and Fig.19 In operation 256 , the method 250 performs a directional treatment process 404 on the first metal layer 384 and the silicide layer 386 to form a barrier layer 388 on the silicide layer 386 .

[0134] Similar to operation 254, directional treatment process 404 is also plasma-based chemical vapor deposition, using a capacitively coupled plasma or an inductively coupled plasma source. However, unlike directional deposition process 402, directional treatment process 404 provides a plasma containing a non-metallic reactant to react with the metal containing first metal layer 384 and at least a portion of silicide layer 386. In some embodiments, directional treatment process 404 is performed in situ, i.e., device 300 remains in the same reaction chamber after being subjected to the directional deposition process and replacing the metal-containing precursor with the non-metallic reactant, as described in more detail below.

[0135] In this embodiment, reference Fig.18 and Fig.19 , the directional processing 404 selectively grows the barrier layer 388 on the horizontal surfaces of the device 300 (e.g., extending along the XY plane) relative to the vertical surfaces (e.g., extending along the XZ plane and the YZ plane). In other words, the directional processing 404 grows more barrier layer 388 on the horizontal plane than on the vertical plane. In this embodiment, the non-metallic reactant reacts with the upper portion 384t of the first metal layer 384 to form the upper portion 388t of the barrier layer 388 and reacts with the upper portion of the silicide layer 386 to form the bottom portion 388b of the barrier layer 388. In this regard, the upper portion 388t has a thickness T1 and the lower portion 388b has a thickness T4 that is less than T2. ​​The directional processing 404 limits the amount of non-metallic reactant on the sidewall portion 384s of the first metal layer 384 so that little or no barrier layer 388 is grown along the sidewalls of the contact opening 380. For the embodiment where the first metal layer 384 has a rounded profile instead of a sharp corner at the upper sidewall portion adjacent to the contact opening 380, as shown in FIG. Fig.19 As shown in the dashed line, a portion of the barrier layer 388 is also grown along the sidewalls of the contact opening 380 and above the sidewall portions 384 s of the first metal layer 384 .

[0136] In the present embodiment, the directional treatment process 404 is performed with a reactant comprising a non-metallic reactant and an inert carrier gas. The non-metallic reactant may comprise a nitrogen-containing gas, such as nitrogen (N2), ammonia (NH3), hydrazine (N2H4), the like, or a combination thereof. The inert carrier gas may comprise argon. In this regard, the directional treatment process 404 may be considered a nitridation process and generates a barrier layer 388 comprising a metal nitride, wherein the metal of the metal nitride is obtained from the first metal layer 384 (and the silicide layer 386). For example, the metal nitride layer may comprise titanium, tungsten, nickel, cobalt, molybdenum, the like, or a combination thereof. In some embodiments, the non-metallic precursor is introduced at a flow rate of about 50 sccm to about 1000 sccm. The plasma may be generated by a capacitively coupled plasma source or an inductively coupled plasma source at a power of about 100 W to 5000 W. The chamber pressure is about 0.5 Torr to about 30 Torr. It should be noted that the reactants and process parameters provided herein are for exemplary purposes only and are not intended to limit the present embodiment thereto.

[0137] The directional treatment process 404 chemically modifies portions of the first metal layer 384 (e.g., the upper portion 384t) and the silicide layer 386 extending along the horizontal surfaces of the device 300, while not modifying or significantly modifying portions of the first metal layer 384 extending along the vertical surfaces (e.g., the sidewall portions 384s). This selective modification increases the difference in the composition of the material layer at the bottom of the contact opening 380 and those along the sidewalls, and thus the etch selectivity is improved, thereby improving the removal selectivity of the material layer along the sidewalls relative to those at the bottom of the contact opening 380. In this regard, other non-metallic reactants may also be used in the directional treatment process 404, as long as the composition of the final barrier layer 388 is suitable for the intended application of the device 300. Non-limiting examples of non-metallic reactants include chlorine (Cl), carbon (C), and oxygen (O) or combinations thereof, corresponding to the directional treatment process 404 to perform a chlorination process, a carbonization process, and an oxidation process.

[0138] refer to Figure 2B , Fig. 20 and Fig.21 , the method 200 deposits a second metal layer 390 on the barrier layer 388 in operation 258 .

[0139] In the present embodiment, the second metal layer 390 comprises a seed layer for the subsequently formed source / drain contacts 394, and therefore has the same composition as the source / drain contacts 394. The second metal layer 390 may be conformally formed on the contact opening 380 by any suitable method, such as physical vapor deposition. In the present embodiment, the second metal layer 390 is not formed by a directional deposition process, such as the directional deposition process 402. Therefore, the second metal layer 390 comprises an upper portion 390t, a lower portion 390b, and a sidewall portion 390s, which are substantially formed on the upper portion 388t, the bottom portion 388b, and the sidewall portion 384s with a uniform thickness T5, respectively. In an exemplary embodiment, the second metal layer 390 may comprise a seed layer containing tungsten deposited by a physical vapor deposition process. The second metal layer 390 may comprise other metals such as copper. Other suitable metals may also be included in the second metal layer 390. In this embodiment, the total thickness T′ of the material layer on the sidewall of the contact opening 380 is the thickness of the sidewall portions 384s and 390s, and is approximately the sum of T3 and T5. Fig. 20 shown.

[0140] Refer to 2B, 2C and Figure 22 to Figure 29The method 200 performs a series of deposition and etching processes, collectively referred to as coating and etching pull-back (CEPB) processes, in operations 260 to 266 to selectively remove the material layer extending along the sidewalls of the contact opening 380 without removing or substantially removing the material layer extending along the bottom of the contact opening 380. In the present embodiment, the coating and etching pull-back processes are configured to remove most (or all) of the sidewall portions 390s and 384s of the second metal layer 390 and the first metal layer 384, respectively. However, the bottom portions 390b and 388b and the silicide layer 386 remain or remain mostly in the contact opening 380.

[0141] refer to Figure 2B , Fig. 22 and Fig.23 In operation 260 of the method 200 , a polymer layer 391 is deposited on the second metal layer 390 to fill the contact opening 380 .

[0142] The polymer layer 391 comprises a carbon-based organic material, such as a bottom anti-reflective layer (BARC) material, which has an etch selectivity compared to the surrounding material layers including the second metal layer 390. Therefore, the polymer layer 391 can be selectively removed without removing or substantially removing the surrounding material layers. The polymer layer 391 can be deposited by any suitable method, such as spin coating, chemical vapor deposition, flow chemical vapor deposition, the like, or a combination thereof. In some embodiments, a portion of the polymer layer 391 is formed on the upper surface of the interlayer dielectric layer 346, such as Fig. 22 and Fig.23 Depicted.

[0143] refer to Figure 2C , Fig.24 and Fig.25 In operation 262 , the method 200 removes an upper portion of the polymer layer 391 to expose a sidewall portion of the second metal layer 390 .

[0144] In some embodiments, the polymer layer 391 is removed using a suitable process for removing the photoresist layer. For example, the upper surface of the polymer layer 391 can be removed by plasma ashing, photoresist stripping, the like, or a combination thereof. The plasma ashing process can be performed with a fluorine-containing gas, such as CF4, oxygen (O2), nitrogen (N2), hydrogen, the like, or a combination thereof. In this embodiment, removing the polymer layer 391 does not remove or substantially removes a portion of the second metal layer because there is an etching selectivity between the polymer layer 391 and the second metal layer 390.

[0145] In some embodiments, the removal of the upper portion of the polymer layer 391 is controlled by adjusting the time of the removal process. For example, the depth D1 corresponds to the upper portion of the polymer layer 391 that is removed, and it increases as the time of the etching process increases. In some examples, the ratio of the depth D1 to the total thickness (or total depth) D2 of the polymer layer 391 can be less than about 0.5, although the present embodiment is not limited thereto.

[0146] refer to Figure 2C , Fig.26 and Fig. 27 In operation 264 , the method 250 removes the upper sidewall portions of the first metal layer 384 and the second metal layer 390 exposed in the contact opening 380 .

[0147] In some embodiments, the upper sidewall portion of the first metal layer 384 (e.g., sidewall portion 384s) and the second metal layer 390 (e.g., sidewall portion 390s) are removed by an etching process 406, such as conformal wet etching. In this embodiment, the etching process 406 is selective and does not remove or substantially removes a portion of the polymer layer 391. The etchant used in the etching process 406 may include hydrochloric acid (HCl), ozone deionized water (DIO3 water), sulfuric acid (H2SO4), the like, or a combination thereof. In some embodiments, the upper portion 390t of the second metal layer 390 and the upper portion 388t of the barrier layer 388 are also removed following the etching process 406.

[0148] Next, refer to Figure 2C , Fig.28 and Fig.29 In operation 266 , the method 250 removes the remaining portion of the polymer layer 391 and the bottom sidewall portions of the first metal layer 384 and the second metal layer, thereby exposing the sidewalls of the interlayer dielectric layer 346 in the contact opening 380 again.

[0149] The remaining portion of the polymer layer 391 may be removed by a method similar to operation 262. For example, the polymer layer 391 may be removed using a plasma ashing process using at least one fluorine-containing gas. Due to the selectivity of etching between the polymer layer 391 and the second metal layer 390, the removal of the polymer layer 391 stops at the bottom portion 390b of the second metal layer 390. After removing the remaining portion of the polymer layer 391, the sidewall portion 390s of the second metal layer 390 is exposed to the contact opening 380.

[0150] Thereafter, the remaining sidewall portions of the second metal layer 390 and the first metal layer 384 are removed from the contact opening 380 using an etching process 408, which is similar to the etching process 406 in operation 264. For example, the remaining sidewall portions of the second metal layer 390 and the first metal layer 384 can be removed in a conformal wet etching process using hydrochloric acid, ozone deionized water, sulfuric acid, the like, or a combination thereof. In some embodiments, after removing the remaining sidewall portions of the second metal layer 390 and the first metal layer 384, the remaining portion 384r of the first metal layer remains between the sidewalls of the remaining portion of the second metal layer (i.e., the bottom portion 390bb, discussed in detail below) and the adjacent sidewalls of the interlayer dielectric layer 346. In this regard, the sidewalls of the first metal layer 384 (i.e., the remaining portion 384r), the barrier layer 388 (i.e., the bottom portion 388b), and the silicide layer 386 are vertically aligned (along the Z-axis) along the sidewalls of the interlayer dielectric layer 346.

[0151] In some embodiments, when the remaining metal layers such as the second metal layer 390 and the first metal layer 384 are removed from the sidewalls of the contact opening 380, the etching process 408 is stopped (i.e., endpoint control). In this regard, if the total thickness T' of the metal layers on the sidewalls of the contact opening 380 (or the sidewalls of the interlayer dielectric layer 346) is less than 0.01 mm, the etching process 408 may be stopped (i.e., endpoint control). Fig. 20 and Fig.26 ) is too large, completely removing this material layer by the etching process 408 may cause the bottom portion 390bb to be too thin, and may even inadvertently remove the bottom portion 390bb in some cases. On the other hand, if the etching process 408 is configured so that the bottom portion 390bb is retained, the material layer on the sidewalls will not be completely removed. Any residual material layer on the sidewalls of the contact opening 380 may cause structural problems, such as pores and reduction in grain size, and may generate a first metal layer for a subsequently generated source / drain contact (e.g., source / drain contact 394), resulting in an increase in the contact resistance of the source / drain contact and a loss in the performance yield of the device 300.

[0152] Therefore, in order to achieve more complete removal of the metal layer on the sidewall of the contact opening 380 without causing a significant loss of the material layer at the bottom of the contact opening 380, the present disclosure provides a method for reducing or limiting the total thickness T', namely, by implementing a directional deposition process 402 and a directional treatment process 404. If a non-directional deposition process is implemented (instead of the directional deposition process 402), the sidewall portion 384s of the first metal layer 384 will have a thickness greater than T3. In addition, if a uniform deposition process is implemented (instead of the directional treatment process 404), a barrier layer 388 will be generated on the first metal layer 384 and the second metal layer 390 along the sidewall of the contact opening 380 (such as Fig. 20The total thickness T' of the material layer may exceed the sum of T3 and T5. In this regard, the total thickness T' may be too large to be completely removed by the etching process 408, resulting in structural problems in the subsequently generated source / drain contacts, as described above.

[0153] refer to Figure 2C , Fig.30 and Fig.31 The method 250 performs a selective deposition process in operation 268 to form a third metal layer 392 in the contact opening 380 .

[0154] The selective deposition process 410 may be performed by physical vapor deposition, wherein the third metal layer 392 is selectively grown from the second metal layer 390 (i.e., the bottom portion 390bb) rather than the interlayer dielectric layer 346. In other words, the third metal layer 392 is grown from the second metal layer 390 along the Z axis from bottom to top, such as Fig.30 As shown by the dashed arrow. Therefore, the selective growth causes the third metal layer 392 to protrude outward from the contact opening 380, as depicted in Figure 30. In some embodiments, the sidewalls of the third metal layer 392 directly contact the interlayer dielectric layer 346, so that the sidewalls of the third metal layer 392, the first metal layer 384 (i.e., the remaining portion 384r), the barrier layer 388, and the silicide layer 386 are vertically aligned (along the Z axis).

[0155] The third metal layer 392 may include any suitable metal, such as titanium, tungsten, nickel, cobalt, molybdenum, copper, ruthenium, aluminum, the like, or a combination thereof. The third metal layer 392 may be formed by reacting a metal halide precursor with a gas such as hydrogen. In an exemplary embodiment, the third metal layer 392 includes tungsten and is formed by reacting tungsten chloride or tungsten fluoride with hydrogen in a physical vapor deposition chamber.

[0156] refer to Figure 2C , Fig.32 and Fig.33 The method 250 planarizes the third metal layer 392 in operation 270 to remove the protruding portions of the third metal layer and form source / drain contacts 394 in the contact openings 380. The third metal layer 392 may be planarized by any suitable method, such as chemical mechanical polishing.

[0157] Fig.34 and Fig.353 is a schematic diagram of the device 300 including the generated source / drain contact 394 coupled to the source / drain feature 330. In the present embodiment, the source / drain contact 394 is coupled to the source / drain feature 330 through a plurality of conductive layers, wherein the conductive layers include the second metal layer (i.e., the bottom portion 390bb), the barrier layer 388 (i.e., the bottom portion 388b), and the silicide layer 386. The remaining portion 384r of the first metal layer 384 is still left between the second metal layer 390 and the interlayer dielectric layer 346.

[0158] In some embodiments, Fig.35 As shown, the source / drain contacts 394 and the plurality of conductive layers completely cover the source / drain features 330. In other words, the bottommost portion of the plurality of conductive layers is completely disposed on the source / drain features rather than on the interlayer dielectric layer 346. In some embodiments, reference Fig.36 , which depicts a portion of the device 300, the source / drain contacts 394 and the plurality of conductive layers extend laterally along the Y axis, so that the bottommost portion of the plurality of conductive layers is partially disposed in the interlayer dielectric layer 346. This may be caused by a shift in coverage during the patterning of the contact opening 380 (e.g., operation 252), so that the contact opening 380 extends laterally into the interlayer dielectric layer 346. It is worth noting that the portion depicted in Fig.36 The embodiment of can be generated by operations 252 to 270 in method 250, the details of which are described above.

[0159] After this, return to Figure 1 , method 200 may perform further processing on device 300 at operation 218. For example, wiring features (e.g., vias and conductive lines) may be generated in various metallization layers (e.g., dielectric layers similar to interlayer dielectric layer 346) to electrically couple components of device 300 to other features.

[0160] The present disclosure provides semiconductor devices (e.g., fin field effect transistors, nano-layer transistor devices) and methods for their generation, including selectively generating a silicide layer and a barrier layer in a contact opening between a source / drain feature and a source / drain contact. In some embodiments, the method includes performing a directional deposition process to generate a metal layer on the source / drain feature, performing a directional treatment process in the metal layer to generate a barrier layer, and selectively removing a sidewall portion of the metal layer by a series of coating and etching processes. In some embodiments, performing a directional deposition process allows the metal layer and the source / drain feature to react to generate a silicide layer. In some embodiments, the directional deposition and treatment processes are respectively performed by a plasma-guided chemical vapor deposition process. The present disclosure provides a method for reducing or limiting the total thickness of a sidewall portion of a metal layer (e.g., a metal layer) in a contact opening, which is achieved by performing a directional deposition process and a directional treatment process, so that the removal of the metal layer along the sidewall portion of the contact opening can be more complete without causing a significant loss of a material layer at the bottom of the contact opening.

[0161] According to at least one embodiment provided by the present disclosure, a method includes: generating a semiconductor layer protruding from a substrate; generating a source / drain feature on the semiconductor layer; generating a contact opening exposing the source / drain feature; depositing a first metal layer in the contact opening, the first metal layer having a first portion on the source / drain feature and a second portion along a side wall of the contact opening, wherein the first portion has a first thickness and the second portion has a second thickness less than the first thickness; processing the first metal layer to selectively generate a barrier layer along the side wall of the contact opening; depositing a second metal layer over the barrier layer; removing portions of the second metal layer, the barrier layer, and the first metal layer along the side wall of the contact opening; and generating a source / drain contact over the second metal layer, the barrier layer, and the remaining portion of the first metal layer over the source / drain feature.

[0162] In some embodiments, the deposition of the first metal layer is achieved by a directional deposition process.

[0163] In some embodiments, the deposition of the first metal layer causes the first portion of the first metal layer to react with the source / drain feature to form a metal silicide.

[0164] In some embodiments, the processing of the first metal layer is achieved by a directional processing.

[0165] In some embodiments, the processing of the first metal layer includes using a nitrogen plasma to react with the first metal layer so that the barrier layer includes a metal nitride.

[0166] In some embodiments, the depositing of the second metal layer includes performing a physical vapor deposition process.

[0167] In some embodiments, the generation of the source / drain contact includes: depositing a third metal layer by a bottom-up process, wherein the third metal layer and the second metal layer include the same metal; and performing a planarization process on the third metal layer to generate the source / drain contact.

[0168] In some embodiments, the removal includes: depositing a polymer layer on the second metal layer to fill the contact opening; removing a portion of the polymer layer to expose multiple upper sidewall portions of the second metal layer and the first metal layer; removing the exposed multiple upper sidewall portions; removing a residual portion of the polymer layer to expose multiple residual sidewall portions of the second metal layer and the first metal layer; and performing a wet etching process to remove the exposed multiple residual sidewall portions.

[0169] In some embodiments, the performing of the wet etching process partially removes the remaining portion of the second metal layer in the source / drain features.

[0170] According to at least one embodiment provided by the present disclosure, a method includes: forming a source / drain feature adjacent to a channel region and above a semiconductor substrate; forming a dielectric layer above the source / drain feature; forming a contact opening in the dielectric layer to expose the source / drain feature; performing a directional deposition process to form a first metal layer in the contact opening, wherein the amount of the first metal layer formed on a bottom surface of the contact opening is greater than that along a sidewall surface of the contact opening; performing a directional treatment process on the first metal layer to form a barrier layer, wherein the amount of the barrier layer formed on the bottom surface of the contact opening is greater than that along the sidewall surface of the contact opening; depositing a seed layer above the barrier layer; removing portions of the seed layer and the first metal layer on the sidewall surface of the contact opening to expose the dielectric layer; depositing a second metal layer above the seed layer, the barrier layer, and the remaining portion of the first metal layer above the bottom surface of the contact opening; and planarizing the second metal layer to form a source / drain contact.

[0171] In some embodiments, the performing of the directional deposition process includes performing a plasma deposition of a metal precursor.

[0172] In some embodiments, the plasma deposition is performed at an increasing temperature so that the first metal layer reacts with the source / drain and forms a silicide layer on the bottom surface of the contact opening.

[0173] In some embodiments, the performing of the directional processing includes performing a plasma deposition of nitrogen to form a metal nitride in the barrier layer.

[0174] In some embodiments, the removal includes: generating a polymer layer to fill the contact opening; etching a portion of the polymer layer to expose multiple upper sidewall portions of the seed layer and the first metal layer; etching the exposed multiple upper sidewall portions; etching a residual portion of the polymer layer to expose multiple residual sidewall portions of the second metal layer and the first metal layer; and etching the exposed multiple residual sidewall portions.

[0175] In some embodiments, the depositing of the second metal layer includes selectively growing the second metal layer on the remaining portion of the seed layer relative to the dielectric layer.

[0176] According to at least one embodiment of the present disclosure, a semiconductor structure includes: a source / drain feature located in a semiconductor layer protruding from a substrate; a dielectric layer located above the source / drain feature; a silicide layer located above the source / drain feature; a barrier layer located above the silicide layer; a seed layer located above the barrier layer; a metal layer between a side wall of the seed layer and a side wall of the dielectric layer, a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacting the side wall of the dielectric layer; and a source / drain contact located above the seed layer.

[0177] In some embodiments, the silicide layer and the barrier layer include the same metal.

[0178] In some embodiments, the metal layer includes at least one material selected from the group consisting of titanium, tungsten, cobalt, nickel, molybdenum, and combinations thereof.

[0179] In some embodiments, the barrier layer comprises at least one material of nitrogen, carbon, oxygen and chlorine.

[0180] In some embodiments, the barrier layer extends laterally to the dielectric layer.

[0181] In some embodiments, the source / drain contact directly contacts the sidewall of the dielectric layer.

[0182] In some embodiments, the barrier layer contacts the seed layer and the metal layer.

[0183] In some embodiments, a gate is further included, adjacent to the source / drain feature.

[0184] According to at least one embodiment of the present disclosure, a semiconductor structure includes a gate, a source / drain feature adjacent to the gate, a dielectric layer between the gate and the source / drain feature, a silicide layer above the source / drain feature, a barrier layer above the silicide layer, a seed layer above the barrier layer, a metal layer between a side wall of the seed layer and a side wall of the dielectric layer, a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacts the side wall of the dielectric layer, and a source / drain contact above the seed layer.

[0185] In some embodiments, the source / drain contacts directly contact the sidewall of the dielectric layer.

[0186] In some embodiments, the barrier layer contacts the seed layer and the metal layer.

[0187] According to at least one embodiment of the present disclosure, a semiconductor structure includes a semiconductor fin. An insulating region surrounding a bottom of the semiconductor fin. A source / drain feature located above the semiconductor fin. A dielectric layer located above the source / drain feature. A silicide layer located above the source / drain feature. A barrier layer located above the silicide layer. A seed layer located above the barrier layer. A metal layer between a side wall of the seed layer and a side wall of the dielectric layer, a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacts the side wall of the dielectric layer. A source / drain contact located above the seed layer.

[0188] In some embodiments, the barrier layer contacts the seed layer and the metal layer.

[0189] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processing procedures and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may be variously modified, substituted, and altered without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: Include: a source / drain feature in a semiconductor layer protruding from a substrate; a dielectric layer overlying the source / drain features; a silicide layer located above the source / drain feature; a barrier layer on the silicide layer; a seed layer on the barrier layer; a metal layer, between a side wall of the seed layer and a side wall of the dielectric layer, and a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacts the side wall of the dielectric layer; and A source / drain contact is located above the seed layer.

2. The semiconductor structure according to claim 1, wherein: The barrier layer laterally extends to the dielectric layer.

3. The semiconductor structure according to claim 1, wherein: The source / drain contact directly contacts the sidewall of the dielectric layer.

4. The semiconductor structure according to claim 1, wherein: The barrier layer contacts the seed layer and the metal layer.

5. The semiconductor structure according to claim 1, wherein: Also included is a gate adjacent to the source / drain feature.

6. A semiconductor structure, characterized in that: Include: a gate; a source / drain feature adjacent to the gate; a dielectric layer between the gate and the source / drain features; a silicide layer located above the source / drain feature; a barrier layer on the silicide layer; a seed layer on the barrier layer; a metal layer, between a side wall of the seed layer and a side wall of the dielectric layer, and a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacts the side wall of the dielectric layer; and A source / drain contact is located above the seed layer.

7. The semiconductor structure according to claim 6, wherein: The source / drain contact directly contacts the sidewall of the dielectric layer.

8. The semiconductor structure according to claim 6, wherein: The barrier layer contacts the seed layer and the metal layer.

9. A semiconductor structure, characterized in that: Include: a semiconductor fin; an insulating region surrounding a bottom portion of the semiconductor fin; a source / drain feature located above the semiconductor fin; a dielectric layer overlying the source / drain features; a silicide layer located above the source / drain feature; a barrier layer on the silicide layer; a seed layer on the barrier layer; a metal layer, between a side wall of the seed layer and a side wall of the dielectric layer, and a side wall of any one of the silicide layer, the barrier layer, and the metal layer directly contacts the side wall of the dielectric layer; and A source / drain contact is located above the seed layer.

10. The semiconductor structure according to claim 9, wherein: The barrier layer contacts the seed layer and the metal layer.

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