Quantization circuit and image sensor

Abstract

The utility model provides a quantization circuit and an image sensor, and the quantization circuit comprises a charging and discharging module which carries out the charging operation based on the difference between a first current signal and a second current signal in a first time, and carries out the discharging operation based on the second current signal in a second time, so as to obtain a capacitor voltage signal; and the comparison output module is connected with the charging and discharging module and is used for comparing the capacitor voltage signal with the reference voltage signal to obtain an output signal so as to quantify the second current signal based on the duty ratio of the output signal. According to the quantization circuit and the image sensor provided by the utility model, the quantization of current or voltage is effectively realized, and the quantization circuit is simple in structure, can effectively save the area overhead of a chip, and is relatively high in conversion rate.

Description

Technical Field

[0001] The utility model relates to the technical field of image sensors, in particular to a quantization circuit and an image sensor. Background Art

[0002] With the development of image sensors, the application fields are gradually expanding, and the performance requirements are gradually increasing, especially for automotive application chips, which need to meet the requirements of international standards. However, it is difficult for chips in the existing technology to effectively quantize current or voltage. For example, for some image sensors, the voltage or current quantization circuit located in the peripheral circuit area requires a large area overhead, and the conversion rate is difficult to meet the requirements, making it difficult to achieve effective current or voltage quantization, which can easily cause chip safety risks.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the utility model and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the utility model. Utility Model Content

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a quantization circuit and an image sensor, which effectively realize the quantization of current or voltage, have a simple circuit structure, can effectively save chip area overhead, and have a fast conversion rate.

[0005] In order to achieve the above-mentioned object and other related objects, the utility model provides a quantization circuit, the quantization circuit comprising:

[0006] a charge and discharge module, which performs a charge operation based on a difference between a first current signal and a second current signal within a first time and performs a discharge operation based on the second current signal within a second time to obtain a capacitor voltage signal;

[0007] A comparison output module is connected to the charge and discharge module, and obtains an output signal by comparing the capacitor voltage signal with a reference voltage signal, so as to quantize the second current signal based on the duty cycle of the output signal.

[0008] Optionally, the second current signal is the sum of the third current signal and the fourth current signal. In this case, the third current signal is quantized based on the duty cycle of the output signal.

[0009] Optionally, the charging and discharging module includes:

[0010] A first current unit, used to generate the first current signal to perform a charging operation;

[0011] A third current unit, used for transmitting the third current signal to perform a discharge operation;

[0012] a fourth current unit, configured to generate the fourth current signal for performing a discharge operation;

[0013] The charge and discharge control unit is respectively connected to the first current unit, the third current unit and the fourth current unit, and is used to simultaneously start the charging operation and the discharging operation within a first time under the control of the output signal, and to close the charging operation and continue the discharging operation within a second time.

[0014] Optionally, the first current unit includes a first MOS tube and a second MOS tube; the control end of the first MOS tube is connected to a first control voltage signal, the first end is connected to a second end of the second MOS tube, and the second end is connected to a power supply voltage signal; the control end of the second MOS tube is connected to a first bias signal, and the first end serves as a current supply end of the first current unit;

[0015] And / or, the third current unit includes a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube; the control end of the third MOS tube is connected to the control end of the fourth MOS tube and connected to the second bias signal, the first end is connected to the third current signal, and the second end is connected to the first end of the fifth MOS tube; the first end of the fourth MOS tube serves as the current supply end of the third current unit, and the second end is connected to the first end of the sixth MOS tube; the control end of the fifth MOS tube is connected to the control end of the sixth MOS tube and connected to the first end of the third MOS tube, and the second ends of the fifth MOS tube and the sixth MOS tube are connected to the reference ground;

[0016] And / or, the fourth current unit includes a seventh MOS tube and an eighth MOS tube; the control end of the seventh MOS tube is connected to the second bias signal, the first end serves as the current supply end of the fourth current unit, and the second end is connected to the first end of the eighth MOS tube; the control end of the eighth MOS tube is connected to the second control voltage signal, and the second end is connected to the reference ground;

[0017] And / or, the charge and discharge control unit includes a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a capacitor; the control end of the ninth MOS tube is connected to the output signal, the first end is connected to the first end of the tenth MOS tube, the second end is connected to the second end of the eleventh MOS tube and connected to the current supply end of the first current unit; the control end of the tenth MOS tube is connected to its first end, and the second end is connected to the reference ground; the control end of the eleventh MOS tube is connected to the inverted signal of the output signal, the first end is connected to the first end of the capacitor and connected to the current supply ends of the third current unit and the fourth current unit; the first end of the capacitor serves as the output end of the charge and discharge module, and the second end is connected to the reference ground.

[0018] Optionally, the charge and discharge module further includes a voltage control providing unit, configured to provide a first voltage control signal to the first current unit and a second voltage control signal to the fourth current unit.

[0019] Optionally, the voltage control providing unit includes a first voltage control signal providing part and a second voltage control signal providing part, the current mirror ratio of the first current unit and the first voltage control signal providing part satisfies M:1, and the current mirror ratio of the fourth current unit and the second voltage control signal providing part satisfies N:1, wherein M and N are both positive integers greater than or equal to 1 and M is greater than N.

[0020] Optionally, the first control voltage signal providing part includes an operational amplifier, a twelfth MOS transistor, a thirteenth MOS transistor and a first resistor; the first input end of the operational amplifier is connected to the reference voltage signal, the second input end is connected to the first end of the first resistor, the output end is connected to the control end of the twelfth MOS transistor, and is also connected to the first end of the first resistor and serves as the first output end of the control voltage providing unit; the first end of the twelfth MOS transistor is connected to the second end of the thirteenth MOS transistor, and the second end is connected to the power supply voltage signal; the control end of the thirteenth MOS transistor is connected to the first bias signal, and the first end is connected to the first end of the first resistor; the second end of the first resistor is connected to the reference ground;

[0021] The second control voltage signal providing part includes a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube; the control end of the fourteenth MOS tube is connected to the output end of the operational amplifier, the first end is connected to the second end of the fifteenth MOS tube, and the second end is connected to the power supply voltage signal; the control end of the fifteenth MOS tube is connected to the first bias signal, the first end is connected to the first end of the sixteenth MOS tube and the control end of the seventeenth MOS tube and serves as the second output end of the control voltage providing unit; the control end of the sixteenth MOS tube is connected to the second bias signal, and the second end is connected to the first end of the seventeenth MOS tube; the second end of the seventeenth MOS tube is connected to the reference ground.

[0022] Optionally, the voltage control providing unit further includes a Miller compensation part connected between the output end of the operational amplifier and the first end of the first resistor.

[0023] Optionally, the Miller compensation part includes a Miller capacitor connected between the output end of the operational amplifier and the first end of the first resistor; or, the Miller compensation part also includes a compensation resistor, and the compensation resistor and the Miller capacitor are connected in series between the output end of the operational amplifier and the first end of the first resistor.

[0024] Optionally, the comparison output module includes a comparator, an inverter and a D flip-flop; the first input end of the comparator is connected to a reference voltage signal, the second input end is connected to the output end of the charge and discharge module, and the output end is connected to the input end of the inverter; the output end of the inverter is connected to the data end of the D flip-flop; the clock end of the D flip-flop is connected to the clock signal, and the output end serves as the output end of the comparison output module.

[0025] Optionally, the quantization circuit further includes an input conversion module, configured to convert an input voltage signal to be quantized into a corresponding current signal.

[0026] Optionally, the input conversion module includes:

[0027] A voltage amplifying unit, used for amplifying the voltage signal to be quantized to obtain a voltage amplified signal;

[0028] The voltage-current conversion unit is connected to the voltage amplification unit and is used to convert the voltage amplification signal into a corresponding current signal.

[0029] Optionally, the input conversion module further includes a Miller compensation unit connected between the voltage amplification unit and the voltage-current conversion unit.

[0030] Optionally, the voltage amplification unit comprises a two-stage operational amplifier connected in unity gain negative feedback;

[0031] And / or, the voltage-current conversion unit includes an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube and a second resistor; the control end of the eighteenth MOS tube is connected to the control end of the nineteenth MOS tube and connected to the voltage amplification signal, the first end is connected to the second end of the 20th MOS tube, and the second end is connected to the power supply voltage signal; the first end of the nineteenth MOS tube is connected to the second end of the twenty-first MOS tube, and the second end is connected to the power supply voltage signal; the control end of the 20th MOS tube is connected to the control end of the twenty-first MOS tube and connected to the first bias signal, and the first end is connected to the first end of the second resistor; the first end of the twenty-first MOS tube serves as the output end of the input conversion module; the first end of the second resistor is connected to the output end of the voltage amplification unit, and the second end is connected to the reference ground; wherein, when the input conversion module further includes a Miller compensation unit, the first end of the second resistor is connected to the output end of the voltage amplification unit via the Miller compensation unit.

[0032] The utility model also provides an image sensor, comprising the quantization circuit as described in any one of the above solutions.

[0033] As described above, the quantization circuit and image sensor of the utility model, through the design of the charge and discharge module and the comparison output module or the design of the input conversion module, the charge and discharge module and the comparison output module, propose a new quantization circuit structure, which can quantize the analog electrical signal without the help of a counter, which is beneficial to reduce the quantization error and improve the quantization accuracy. It can be applied to the peripheral circuit of the image sensor. When quantizing the peripheral voltage and current of the image sensor, compared with the single slope ADC in the direct multiplexing readout circuit, the quantization circuit structure is simple, can effectively save chip area overhead, and has a faster conversion rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of the quantization circuit in the first embodiment.

[0035] Figure 2 It shows a circuit diagram of the charge-discharge module and the comparison output module in the first embodiment.

[0036] Figure 3 Shown is a circuit diagram of a control voltage providing unit in the first embodiment.

[0037] Figure 4 It is a schematic diagram of the structure of the quantization circuit in the second embodiment.

[0038] Figure 5 It is a circuit diagram of the input conversion module in the second embodiment.

[0039] Component number description

[0040] 100 Quantization Circuit

[0041] 110 Charge and discharge module

[0042] 111 First current unit

[0043] 112 Third current unit

[0044] 113 Fourth current unit

[0045] 114 Charge and discharge control unit

[0046] 115 Control pressure providing unit

[0047] 115a First control voltage signal providing part

[0048] 115b Second control voltage signal providing part

[0049] 115c Miller compensation part

[0050] 120 Comparison output module

[0051] 130 Input conversion module

[0052] 131 Voltage Amplifier Unit

[0053] 132 Voltage-current conversion unit

[0054] 133 Miller compensation unit DETAILED DESCRIPTION

[0055] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] See also Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the utility model in a schematic manner, and the illustrations only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0057] Embodiment 1

[0058] like Figure 1 As shown, this embodiment provides a quantization circuit 100, including a charge and discharge module 110 and a comparison output module 120; wherein:

[0059] The charge and discharge module 110 performs a charging operation based on the difference between the first current signal I1 and the second current signal I2 within the first time T1, and performs a discharging operation based on the second current signal I2 within the second time T2 to obtain a capacitor voltage signal Vcap. In one example, the second current signal I2 is the sum of the third current signal I3 and the fourth current signal I4, wherein the third current signal I3 is regarded as a signal to be quantified, and at this time, the signal to be quantified is a current signal to be quantified; of course, in other examples, the second current signal I2 can also be directly regarded as a signal to be quantified.

[0060] In one embodiment, Figure 2 As shown, the charge and discharge module 110 includes a first current unit 111, a third current unit 112, a fourth current unit 113 and a charge and discharge control unit 114. Further, as shown in Figure 3 As shown, the charge and discharge module 110 further includes a voltage control providing unit 115 .

[0061] The first current unit 111 is used to generate a first current signal I1 for performing a charging operation. Figure 2As shown, the first current unit 111 includes a first MOS tube M1 and a second MOS tube M2, the control end of the first MOS tube M1 is connected to the first control voltage signal Vc1, the first end of the first MOS tube M1 is connected to the second end of the second MOS tube M2, the second end of the first MOS tube M1 is connected to the power supply voltage signal AVDD, the control end of the second MOS tube M2 is connected to the first bias signal Vb1, and the first end of the second MOS tube M2 serves as the current supply end of the first current unit 111; wherein the first MOS tube M1 and the second MOS tube M2 are PMOS tubes, at this time, the control end refers to the gate, the first end refers to the drain, and the second end refers to the source.

[0062] The third current unit 112 is used to transmit the third current signal I3 to perform a discharge operation. Figure 2 As shown, the third current unit 112 includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5 and a sixth MOS transistor M6, the control end of the third MOS transistor M3 is connected to the control end of the fourth MOS transistor M4 and connected to the second bias signal Vb2, the first end of the third MOS transistor M3 is connected to the third current signal I3, the second end of the third MOS transistor M3 is connected to the first end of the fifth MOS transistor M5, the first end of the fourth MOS transistor M4 serves as a current supply end of the third current unit I3, the second end of the fourth MOS transistor M4 is connected to the first end of the sixth MOS transistor M6, the control end of the fifth MOS transistor M5 is connected to the control end of the sixth MOS transistor M6 and connected to the first end of the third MOS transistor M3, and the second end of the fifth MOS transistor M5 and the second end of the sixth MOS transistor M6 are connected to the reference ground; wherein the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the sixth MOS transistor M6 are NMOS transistors, at this time, the control end refers to the gate, the first end refers to the drain, and the second end refers to the source.

[0063] The fourth current unit 113 is used to generate a fourth current signal I4 for performing a discharge operation. Figure 2 As shown, the fourth current unit 113 includes a seventh MOS tube M7 and an eighth MOS tube M8, the control end of the seventh MOS tube M7 is connected to the second bias signal Vb2, the first end of the seventh MOS tube M7 serves as the current supply end of the fourth current unit 113, the second end of the seventh MOS tube M7 is connected to the first end of the eighth MOS tube M8, the control end of the eighth MOS tube M8 is connected to the second control voltage signal Vc2, and the second end of the eighth MOS tube M8 is connected to the reference ground; wherein the seventh MOS tube M7 and the eighth MOS tube M8 are NMOS tubes, at this time, the control end refers to the gate, the first end refers to the drain, and the second end refers to the source.

[0064] The charge and discharge control unit 114 is connected to the first current unit 111, the third current unit 112 and the fourth current unit 113 respectively, and is used to start the charging operation and the discharging operation at the same time within the first time T1 under the control of the output signal Out to perform the charging operation based on the difference between the first current signal I1 and the second current signal I2, and to close the charging operation and continue the discharging operation within the second time T2 to perform the discharging operation based on the second current signal I2. Specifically, Figure 2 As shown, the charge and discharge control unit 114 includes a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11 and a capacitor C, the control end of the ninth MOS transistor M9 is connected to the output signal Out, the first end of the ninth MOS transistor M9 is connected to the first end of the tenth MOS transistor M10, the second end of the ninth MOS transistor M9 is connected to the second end of the eleventh MOS transistor M11 and connected to the current supply end of the first current unit 111, the control end of the tenth MOS transistor M10 is connected to its first end, the second end of the tenth MOS transistor M10 is connected to the reference ground, the control end of the eleventh MOS transistor M11 is connected to the inverted signal Outb of the output signal, the first end of the eleventh MOS transistor M11 is connected to the first end of the capacitor C and connected to the current supply ends of the third current unit 112 and the fourth current unit 113, the first end of the capacitor C serves as the output end of the charge and discharge module 110, and the second end of the capacitor C is connected to the reference ground; wherein, the ninth MOS transistor M9 and the eleventh MOS transistor M11 are PMOS transistors, the tenth MOS transistor is an NMOS transistor, at this time, the control end refers to the gate, the first end refers to the drain, and the second end refers to the source.

[0065] The control voltage providing unit 115 is used to provide a first control voltage signal Vc1 to the first current unit 111 and a second control voltage signal Vc2 to the fourth current unit 113. Figure 3As shown, the control voltage providing unit 115 includes a first control voltage signal providing part 115a and a second control voltage signal providing part 115b, and further includes a Miller compensation part 115c; wherein, the current mirror ratio of the first current unit 111 and the first control voltage signal providing part 115a satisfies M:1, and the current mirror ratio of the fourth current unit 113 and the second control voltage signal providing part 115b satisfies N:1, and M and N are both positive integers greater than or equal to 1 and M is greater than N. Specifically, the first control voltage signal providing part 115a includes an operational amplifier AMP1, a twelfth MOS tube M12, a thirteenth MOS tube M13 and a first resistor R1; the first input terminal (for example, the negative input terminal) of the operational amplifier AMP1 is connected to the reference voltage signal Vbg, the second input terminal (for example, the positive input terminal) of the operational amplifier AMP1 is connected to the first end of the first resistor R1, the output terminal of the operational amplifier AMP1 is connected to the control terminal of the twelfth MOS tube M12, the output terminal of the operational amplifier AMP1 is also connected to the first end of the first resistor R1 and serves as the first output terminal of the control voltage providing unit 115, the first end of the twelfth MOS tube M12 is connected to the second end of the thirteenth MOS tube M13, the second end of the twelfth MOS tube M12 is connected to the power supply voltage signal AVDD, the control end of the thirteenth MOS tube M13 is connected to the first bias signal Vb1, the first end of the thirteenth MOS tube M13 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the reference ground. The second control voltage signal providing part 115b includes a fourteenth MOS tube M14, a fifteenth MOS tube M15, a sixteenth MOS tube M16 and a seventeenth MOS tube M17. The control end of the fourteenth MOS tube M14 is connected to the output end of the operational amplifier AMP1, the first end of the fourteenth MOS tube M14 is connected to the second end of the fifteenth MOS tube M15, the second end of the fourteenth MOS tube M14 is connected to the power supply voltage signal AVDD, the control end of the fifteenth MOS tube M15 is connected to the first bias signal Vb1, the first end of the fifteenth MOS tube M15 is connected to the first end of the sixteenth MOS tube M16 and the control end of the seventeenth MOS tube M17 and serves as the second output end of the control voltage providing unit 115, the control end of the sixteenth MOS tube M16 is connected to the second bias signal Vb2, the second end of the sixteenth MOS tube M16 is connected to the first end of the seventeenth MOS tube M17, and the second end of the seventeenth MOS tube M17 is connected to the reference ground. Among them, the operational amplifier AMP1 is a two-stage operational amplifier, the twelfth MOS tube M12, the thirteenth MOS tube M13, the fourteenth MOS tube M14 and the fifteenth MOS tube M15 are PMOS tubes, the sixteenth MOS tube M16 and the seventeenth MOS tube M17 are NMOS tubes, at this time, the control end refers to the gate, the first end refers to the drain, and the second end refers to the source.The Miller compensation part 155c is connected between the output end of the operational amplifier AMP1 and the first end of the first resistor R1; the Miller compensation part 155c includes a Miller capacitor Cm, and even includes a compensation resistor (not shown in the figure); the Miller capacitor Cm is connected between the output end of the operational amplifier AMP1 and the first end of the first resistor R1, and when the compensation resistor is included, the compensation resistor and the Miller capacitor Cm are connected in series between the output end of the operational amplifier AMP1 and the first end of the first resistor R1.

[0066] The comparison output module 120 is connected to the charge and discharge module 110, and obtains the output signal Out by comparing the capacitor voltage signal Vcap with the reference voltage signal Vref, so as to quantize the second current signal I2 based on the duty cycle of the output signal Out. In one example, when the second current signal I2 is the sum of the third current signal I3 and the fourth current signal I4, the comparison output module 120 quantizes the third current signal I3 based on the duty cycle of the output signal Out.

[0067] In one embodiment, Figure 2 As shown, the comparison output module 120 includes a comparator CMP, an inverter INV and a D flip-flop DFF, a first input terminal (e.g., a negative input terminal) of the comparator CMP is connected to a reference voltage signal Vref, a second input terminal (e.g., a positive input terminal) of the comparator CMP is connected to the output terminal of the charge and discharge module 110, an output terminal of the comparator CMP is connected to an input terminal of the inverter INV, an output terminal of the inverter INV is connected to a data terminal of the D flip-flop DFF, a clock terminal of the D flip-flop DFF is connected to a clock signal clk, and an output terminal of the D flip-flop DFF serves as an output terminal of the comparison output module 120.

[0068] Correspondingly, this embodiment further provides a quantization method, comprising the following steps; wherein the quantization method is implemented using the quantization circuit 100 described above.

[0069] A charging operation is performed based on the difference between the first current signal I1 and the second current signal I2 within the first time T1, and a discharging operation is performed based on the second current signal I2 within the second time T2 to obtain a capacitor voltage signal Vcap. In one example, the second current signal I2 is the sum of the third current signal I3 and the fourth current signal I4, wherein the third current signal I3 is regarded as a signal to be quantified, and at this time, the signal to be quantified is a current signal to be quantified. In practical applications, the capacitor voltage signal Vcap is obtained by performing a charging and discharging operation through the charging and discharging module 110, and the relevant content is detailed above and will not be repeated here.

[0070] The output signal Out is obtained by comparing the capacitor voltage signal Vcap with the reference voltage signal Vref, so as to quantize the second current signal I2 based on the duty cycle of the output signal Out. In one example, when the second current signal I2 is the sum of the third current signal I3 and the fourth current signal I4, this step is to quantize the third current signal I3 based on the duty cycle of the output signal Out. In practical applications, the comparison and quantization operations are performed by the comparison output module 120, and the relevant contents are described above and will not be repeated here.

[0071] Next, please combine Figure 2 and Figure 3 , the quantization process involved in the quantization circuit 100 and the quantization method of this embodiment is described in detail.

[0072] In the voltage control providing unit 115, the operational amplifier AMP1 is a two-stage operational amplifier connected to form a unit gain negative feedback, and its closed-loop system gain satisfies Formula 1: Wherein, V1 is the node voltage value of the first end of the first resistor, Vbg is the value of the reference voltage signal, A0 is the gain of the two-stage operational amplifier, and β is the feedback coefficient; since the voltage at the output end is completely fed back to the input end, β is 1, and since the gain A0 of the two-stage operational amplifier is very large, the formula 2 can be approximately obtained: Thus, the current flowing through the branch where the first resistor R1 is located satisfies Formula 3: Among them, IR1 is the value of the current flowing through the branch where the first resistor is located, and R1 is the value of the first resistor; the twelfth MOS tube M12, the thirteenth MOS tube M13, the fourteenth MOS tube M14 and the fifteenth MOS tube M15 constitute a common source and common gate current mirror, wherein the width-to-length ratio of the twelfth MOS tube M12 is consistent with the width-to-length ratio of the fourteenth MOS tube M14, that is, the current mirror ratio of the common source and common gate current mirror is 1:1, therefore, the current flowing through the branch where the fourteenth MOS tube M14 is located is equal to the value of the current flowing through the branch where the first resistor is located.

[0073] In the first current unit 111, the first MOS transistor M1 and the second MOS transistor M2 and the twelfth MOS transistor M12 and the thirteenth MOS transistor M13 in the control voltage providing unit 115 form a cascode current mirror, wherein the width-to-length ratio of the first MOS transistor M1 and the width-to-length ratio of the twelfth MOS transistor M12 satisfy M:1, that is, the current mirror ratio of the cascode current mirror is M:1, so that the first current signal I1 satisfies Formula 4: I1 is the value of the first current signal, and M is the current mirror ratio of the above-mentioned common-source common-gate current mirror.

[0074] In the third current unit 112, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5 and the sixth MOS transistor M6 form a cascode current mirror, wherein the width-to-length ratio of the fifth MOS transistor M5 is consistent with the width-to-length ratio of the sixth MOS transistor M6, that is, the current mirror ratio of the cascode current mirror is 1:1, so that the transmission of the third current signal I3 is realized through the current mirror.

[0075] In the fourth current unit 113, the seventh MOS transistor M7 and the eighth MOS transistor M8 and the sixteenth MOS transistor M16 and the seventeenth MOS transistor M17 in the control voltage providing unit 115 form a cascode current mirror, wherein the width-to-length ratio of the eighth MOS transistor M8 and the width-to-length ratio of the seventeenth MOS transistor M17 satisfy N:1, that is, the current mirror ratio of the cascode current mirror is N:1, so that the fourth current signal I4 satisfies Formula 5: I4 is the value of the fourth current signal, and N is the current mirror ratio of the cascode current mirror. In addition, the first current signal I1 is greater than the sum of the third current signal I3 and the fourth current signal I4, that is, I1>I3+I4, therefore, M>N.

[0076] In the charge and discharge control unit 114 and the comparison output module 120, the ninth MOS transistor M9 is controlled by the output signal Out, and the eleventh MOS transistor M11 is controlled by the inverted signal Outb of the output signal; within the first time T1, the output signal Out is at a high level, the inverted signal Outb of the output signal is at a low level, the ninth MOS transistor M9 is turned off and the eleventh MOS transistor M11 is turned on, the capacitor C is charged based on the first current signal I1 and the capacitor C is discharged based on the sum of the third current signal I3 and the fourth current signal I4. Since the charging current is greater than the discharging current, the capacitor voltage signal Vcap rises, that is, the voltage at the positive input terminal of the comparator CMP increases. Rising, when Vcap>Vref, the output of the comparator CMP flips to a high level, at this time, the output of the D flip-flop DFF flips to a low level; in the second time T2, the output signal Out is a low level, the inverted signal Outb of the output signal is a high level, the ninth MOS tube M9 is turned on and the eleventh MOS tube M11 is turned off, and the capacitor C is discharged based on the sum of the third current signal I3 and the fourth current signal I4, and the capacitor voltage signal Vcap drops, that is, the voltage at the positive input end of the comparator CMP drops, when Vcap<Vref, the output of the comparator CMP flips to a low level, at this time, the output of the D flip-flop DFF flips to a high level. When the charge and discharge are balanced, there is formula six: Combining Formula 4 and Formula 5, we get Formula 7: Finally, the third current signal I3 is converted into a duty cycle Duty of the output signal to achieve quantization of the third current signal I3.

[0077] Embodiment 2

[0078] like Figure 4 As shown, the quantization circuit 100 of this embodiment is different from that of the first embodiment in that it further includes an input conversion module 130; wherein the input conversion module 130 is used to convert the input voltage signal to be quantized into a corresponding current signal, for example, into a third current signal I3. At this time, the signal to be quantized is a voltage signal to be quantized.

[0079] In one embodiment, Figure 5 As shown, the input conversion module 130 includes a voltage amplification unit 131 and a voltage-current conversion unit 132 , and further includes a Miller compensation unit 133 .

[0080] The voltage amplifying unit 131 is used to amplify the voltage signal to be quantized Vq to obtain a voltage amplified signal Va. Figure 5 As shown, the voltage amplification unit 131 includes a two-stage operational amplifier AMP2 connected to form a unit gain negative feedback, wherein the negative input terminal of the two-stage operational amplifier AMP2 is connected to the voltage signal Vq to be quantized, the positive input terminal of the two-stage operational amplifier AMP2 is connected to its output terminal and connected to the first end of the second resistor R2 in the voltage-current conversion unit 132, and the output terminal of the two-stage operational amplifier AMP2 serves as the output terminal of the voltage amplification unit 131.

[0081] The voltage-current conversion unit 132 is connected to the voltage amplification unit 131, and is used to convert the voltage amplification signal Va into a corresponding current signal, for example, into a third current signal I3. Figure 5As shown, the voltage-current conversion unit 132 includes an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21 and a second resistor R2, the control end of the eighteenth MOS tube M18 is connected to the control end of the nineteenth MOS tube M19 and is connected to the voltage amplification signal Va, the first end of the eighteenth MOS tube M18 is connected to the second end of the twentieth MOS tube M20, the second end of the eighteenth MOS tube M18 is connected to the power supply voltage signal AVDD, the first end of the nineteenth MOS tube M19 is connected to the second end of the twenty-first MOS tube M21, the second end of the nineteenth MOS tube M19 is connected to the power supply voltage signal AVDD, and the twentieth MOS tube M21 is connected to the power supply voltage signal AVDD. The control end of the 21st MOS tube M20 is connected to the control end of the 21st MOS tube M21 and is connected to the first bias signal Vb1, the first end of the 20th MOS tube M20 is connected to the first end of the second resistor R2, the first end of the 21st MOS tube M21 is used as the output end of the input conversion module 130, the first end of the second resistor R2 is connected to the output end of the voltage amplification unit 131, and the second end of the second resistor R2 is connected to the reference ground; wherein the value of the second resistor R2 is equal to the value of the first resistor R1, the eighteenth MOS tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20 and the twenty-first MOS tube M21 are PMOS tubes, at this time, the control end refers to the gate, the first end refers to the drain, and the second end refers to the source.

[0082] The Miller compensation unit 133 is connected between the voltage amplification unit 131 and the voltage-current conversion unit 132, and is used to compensate for the frequency characteristics of the voltage amplification unit 131; at this time, the positive input terminal of the two-stage operational amplifier AMP2 in the voltage amplification unit 131 and the first end of the second resistor R2 in the voltage-current conversion unit 132 are no longer directly connected to the output terminal of the two-stage operational amplifier AMP2, but are connected to the output terminal of the two-stage operational amplifier AMP2 via the Miller compensation unit 133. In one example, the Miller compensation unit 133 includes a Miller capacitor (not shown in the figure), and of course, in other examples, the Miller compensation unit 133 also includes a compensation resistor (not shown in the figure), and at this time, the Miller capacitor and the compensation resistor are connected in series between the voltage amplification unit 131 and the voltage-current conversion unit 132.

[0083] Accordingly, the quantization method of this embodiment is different from that of the first embodiment in that it further includes a step of converting the input voltage signal Vq to be quantized into a corresponding current signal (for example, into a third current signal I3). In practical applications, the conversion from voltage to current is realized by the input conversion module 130, and the relevant contents are described above and will not be repeated here.

[0084] Next, please combine Figure 5 , the quantization process involved in the quantization circuit 100 and the quantization method of this embodiment is described in detail.

[0085] In the voltage amplifying unit 131, the two-stage operational amplifier AMP2 connected to form a unit gain negative feedback can obtain Formula 8: Wherein, Va is the node voltage value of the first end of the second resistor, and Vq is the value of the voltage signal to be quantized.

[0086] In the voltage-current conversion unit 132, the current flowing through the branch where the second resistor R2 is located satisfies Formula 9: Among them, IR2 is the value of the current flowing through the branch where the second resistor is located, and R2 is the value of the second resistor; the eighteenth MOS tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20 and the twenty-first MOS tube M21 constitute a common source and common gate current mirror, wherein the width-to-length ratio of the eighteenth MOS tube M18 is consistent with the width-to-length ratio of the nineteenth MOS tube M19, that is, the current mirror ratio of the common source and common gate current mirror is 1:1, therefore, the current flowing through the branch where the nineteenth MOS tube M19 is located is equal to the value of the current flowing through the branch where the second resistor is located, so that the voltage signal Va to be quantized is converted into the third current signal I3.

[0087] Finally, the third current signal I3 is quantized as in the first embodiment; formula 10 is obtained: The value of the second resistor R2 is designed to be equal to the value of the first resistor R1, and Formula 11 can be obtained: Finally, the voltage signal Vq to be quantized is converted into the duty cycle Duty of the output signal, thereby realizing the quantization of the voltage signal Vq to be quantized.

[0088] Embodiment 3

[0089] This embodiment provides an image sensor, including the quantization circuit described in Embodiment 1 or Embodiment 2. The quantization circuit can be arranged in the peripheral circuit area of ​​the image sensor. Furthermore, the image sensor can be applied to electronic devices, for example, the electronic devices can be security monitoring, vehicle-mounted electronics, mobile phone cameras, machine vision and other devices.

[0090] In summary, the utility model of a quantization circuit and an image sensor, through the design of a charge-discharge module and a comparison output module or the design of an input conversion module, a charge-discharge module and a comparison output module, proposes a new quantization circuit structure, which can quantize analog electrical signals without the aid of a counter, which is conducive to reducing quantization errors and improving quantization accuracy. It can be applied to the peripheral circuits of image sensors. When quantizing the peripheral voltage and current of image sensors, compared with the single slope ADC in the direct multiplexing readout circuit, the quantization circuit structure is simple, which can effectively save chip area overhead, and the conversion rate is faster. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.

Claims

1. A quantization circuit, characterized in that: The quantization circuit comprises: a charge and discharge module, which performs a charge operation based on a difference between a first current signal and a second current signal within a first time and performs a discharge operation based on the second current signal within a second time to obtain a capacitor voltage signal; A comparison output module is connected to the charge and discharge module, and obtains an output signal by comparing the capacitor voltage signal with a reference voltage signal, so as to quantize the second current signal based on the duty cycle of the output signal.

2. The quantization circuit according to claim 1, characterized in that: The second current signal is the sum of the third current signal and the fourth current signal. At this time, the third current signal is quantized based on the duty cycle of the output signal.

3. The quantization circuit according to claim 2, characterized in that: The charging and discharging module comprises: A first current unit, used to generate the first current signal to perform a charging operation; A third current unit, used for transmitting the third current signal to perform a discharge operation; a fourth current unit, configured to generate the fourth current signal for performing a discharge operation; The charge and discharge control unit is respectively connected to the first current unit, the third current unit and the fourth current unit, and is used to simultaneously start the charging operation and the discharging operation within a first time under the control of the output signal, and to close the charging operation and continue the discharging operation within a second time.

4. The quantization circuit according to claim 3, characterized in that: The first current unit includes a first MOS tube and a second MOS tube; the control end of the first MOS tube is connected to the first control voltage signal, the first end is connected to the second end of the second MOS tube, and the second end is connected to the power supply voltage signal; the control end of the second MOS tube is connected to the first bias signal, and the first end serves as the current supply end of the first current unit; And / or, the third current unit includes a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube; the control end of the third MOS tube is connected to the control end of the fourth MOS tube and connected to the second bias signal, the first end is connected to the third current signal, and the second end is connected to the first end of the fifth MOS tube; the first end of the fourth MOS tube serves as the current supply end of the third current unit, and the second end is connected to the first end of the sixth MOS tube; the control end of the fifth MOS tube is connected to the control end of the sixth MOS tube and connected to the first end of the third MOS tube, and the second ends of the fifth MOS tube and the sixth MOS tube are connected to the reference ground; And / or, the fourth current unit includes a seventh MOS tube and an eighth MOS tube; the control end of the seventh MOS tube is connected to the second bias signal, the first end serves as the current supply end of the fourth current unit, and the second end is connected to the first end of the eighth MOS tube; the control end of the eighth MOS tube is connected to the second control voltage signal, and the second end is connected to the reference ground; And / or, the charge and discharge control unit includes a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube and a capacitor; the control end of the ninth MOS tube is connected to the output signal, the first end is connected to the first end of the tenth MOS tube, the second end is connected to the second end of the eleventh MOS tube and connected to the current supply end of the first current unit; the control end of the tenth MOS tube is connected to its first end, and the second end is connected to the reference ground; the control end of the eleventh MOS tube is connected to the inverted signal of the output signal, the first end is connected to the first end of the capacitor and connected to the current supply ends of the third current unit and the fourth current unit; the first end of the capacitor serves as the output end of the charge and discharge module, and the second end is connected to the reference ground.

5. The quantization circuit according to claim 3, characterized in that: The charge and discharge module further includes a voltage control providing unit, which is used to provide a first voltage control signal to the first current unit and a second voltage control signal to the fourth current unit.

6. The quantization circuit according to claim 5, characterized in that: The voltage control providing unit includes a first voltage control signal providing part and a second voltage control signal providing part, the current mirror ratio of the first current unit and the first voltage control signal providing part satisfies M:1, and the current mirror ratio of the fourth current unit and the second voltage control signal providing part satisfies N:1, wherein M and N are both positive integers greater than or equal to 1 and M is greater than N.

7. The quantization circuit according to claim 6, characterized in that: The first control voltage signal providing part includes an operational amplifier, a twelfth MOS transistor, a thirteenth MOS transistor and a first resistor; the first input end of the operational amplifier is connected to the reference voltage signal, the second input end is connected to the first end of the first resistor, the output end is connected to the control end of the twelfth MOS transistor, and is also connected to the first end of the first resistor and serves as the first output end of the control voltage providing unit; the first end of the twelfth MOS transistor is connected to the second end of the thirteenth MOS transistor, and the second end is connected to the power supply voltage signal; the control end of the thirteenth MOS transistor is connected to the first bias signal, and the first end is connected to the first end of the first resistor; the second end of the first resistor is connected to the reference ground; The second control voltage signal providing part includes a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube and a seventeenth MOS tube; the control end of the fourteenth MOS tube is connected to the output end of the operational amplifier, the first end is connected to the second end of the fifteenth MOS tube, and the second end is connected to the power supply voltage signal; the control end of the fifteenth MOS tube is connected to the first bias signal, the first end is connected to the first end of the sixteenth MOS tube and the control end of the seventeenth MOS tube and serves as the second output end of the control voltage providing unit; the control end of the sixteenth MOS tube is connected to the second bias signal, and the second end is connected to the first end of the seventeenth MOS tube; the second end of the seventeenth MOS tube is connected to the reference ground.

8. The quantization circuit according to claim 7, characterized in that: The control voltage providing unit further includes a Miller compensation part connected between the output end of the operational amplifier and the first end of the first resistor.

9. The quantization circuit according to claim 8, characterized in that: The Miller compensation part includes a Miller capacitor connected between the output end of the operational amplifier and the first end of the first resistor; or, the Miller compensation part also includes a compensation resistor, and the compensation resistor and the Miller capacitor are connected in series between the output end of the operational amplifier and the first end of the first resistor.

10. The quantization circuit according to claim 1, characterized in that: The comparison output module includes a comparator, an inverter and a D flip-flop; the first input end of the comparator is connected to a reference voltage signal, the second input end is connected to the output end of the charge and discharge module, and the output end is connected to the input end of the inverter; the output end of the inverter is connected to the data end of the D flip-flop; The clock end of the D flip-flop is connected to the clock signal, and the output end serves as the output end of the comparison output module.

11. The quantization circuit according to any one of claims 1 to 10, characterized in that: The quantization circuit also includes an input conversion module, which is used to convert the input voltage signal to be quantized into a corresponding current signal.

12. The quantization circuit according to claim 11, characterized in that: The input conversion module comprises: A voltage amplifying unit, used for amplifying the voltage signal to be quantized to obtain a voltage amplified signal; The voltage-current conversion unit is connected to the voltage amplification unit and is used to convert the voltage amplification signal into a corresponding current signal.

13. The quantization circuit according to claim 12, characterized in that: The input conversion module further includes a Miller compensation unit connected between the voltage amplification unit and the voltage-current conversion unit.

14. The quantization circuit according to claim 12 or 13, characterized in that: The voltage amplification unit includes a two-stage operational amplifier connected in unity gain negative feedback; And / or, the voltage-current conversion unit includes an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube, a twenty-first MOS tube and a second resistor; the control end of the eighteenth MOS tube is connected to the control end of the nineteenth MOS tube and connected to the voltage amplification signal, the first end is connected to the second end of the 20th MOS tube, and the second end is connected to the power supply voltage signal; the first end of the nineteenth MOS tube is connected to the second end of the twenty-first MOS tube, and the second end is connected to the power supply voltage signal; the control end of the 20th MOS tube is connected to the control end of the twenty-first MOS tube and connected to the first bias signal, and the first end is connected to the first end of the second resistor; the first end of the twenty-first MOS tube serves as the output end of the input conversion module; the first end of the second resistor is connected to the output end of the voltage amplification unit, and the second end is connected to the reference ground; wherein, when the input conversion module further includes a Miller compensation unit, the first end of the second resistor is connected to the output end of the voltage amplification unit via the Miller compensation unit.

15. An image sensor, characterized in that: The method comprises a quantization circuit as claimed in any one of claims 1 to 14.

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