ESD protection device based on SOI technology and semiconductor device

Abstract

The utility model provides an ESD protection device based on an SOI technology and a semiconductor device. The ESD protection device comprises an SOI substrate, a diode array and a polycrystalline silicon layer. The SOI substrate comprises bottom layer silicon, a buried oxide layer and top layer silicon; the diode array is formed on the top layer silicon, the diode array comprises a plurality of diode rows, and each diode row comprises a plurality of P + doped regions and a plurality of N + doped regions which are alternately arranged along the row direction; the plurality of diode rows are arranged along the column direction, and the plurality of P + doped regions and the plurality of N + doped regions in two adjacent rows are distributed in a staggered manner along the column direction so as to correspondingly form a plurality of diode columns along the column direction; in each diode row and each diode column, a well region is formed between the adjacent P + doped region and N + doped region; the polycrystalline silicon layer is at least arranged on the surface of a part of the well region. The ESD protection device provided by the utility model can reduce the damage to a chip caused by electrostatic discharge in an SOI (Silicon On Insulator) process.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to an ESD protection device and a semiconductor device based on SOI technology. Background Art

[0002] Electrostatic discharge (ESD) protection is an important part of integrated circuit (IC) design. As manufacturing processes become more and more advanced, especially in SOI (Silicon-On-Insulator) processes, due to the presence of buried oxide (BOX), the thickness of the top silicon is much thinner than that of the traditional bulk silicon process, which makes it more difficult to discharge the ESD current. At the same time, the current tends to be more concentrated, making the heat dissipation problem of semiconductor devices more serious. Therefore, semiconductor devices are more likely to be burned and fail. How to improve the discharge capacity of ESD devices in SOI processes to improve the protection performance of ESD devices for chips has become an urgent problem to be solved in the prior art. Utility Model Content

[0003] The utility model provides an ESD protection device and a semiconductor device based on SOI process, so as to improve the protection performance of the ESD device on the chip in the existing SOI process.

[0004] To achieve the above-mentioned purpose and other related purposes, the utility model provides an ESD protection device based on SOI process, comprising: an SOI substrate, a diode array and a polysilicon layer; the SOI substrate comprises a bottom silicon, a buried oxide layer and a top silicon arranged in sequence from bottom to top; the diode array is formed on the top silicon, the diode array comprises a plurality of diode rows, each of the diode rows comprises a plurality of P+ doped regions and a plurality of N+ doped regions alternately arranged along the row direction; the plurality of diode rows are arranged along the column direction, and the plurality of P+ doped regions and the plurality of N+ doped regions in two adjacent rows are staggered along the column direction to form a plurality of diode columns correspondingly along the column direction; in each of the diode rows and each of the diode columns, a well region is formed between adjacent P+ doped regions and adjacent N+ doped regions; the polysilicon layer is at least arranged on the surface of a portion of the well region.

[0005] In an example of the ESD protection device of the present invention, the polysilicon layer is disposed on the surface of the well region in the diode row or on the surface of the well region in the diode column.

[0006] In an example of the ESD protection device of the present invention, along the thickness direction of the SOI substrate, the polysilicon layer protrudes from the surfaces of the P+ doping region and the N+ doping region.

[0007] In an example of the ESD protection device of the present invention, metal silicide layers are provided on the surfaces of the P+ doped region and the N+ doped region, and the metal silicide layers above adjacent P+ doped regions and the N+ doped regions are insulated.

[0008] In an example of the ESD protection device of the present invention, the width of the well region in the diode row is consistent with the width of the well region in the diode column.

[0009] In an example of the ESD protection device of the present invention, adjacent diodes in the diode row and adjacent diodes in the diode column are connected in parallel.

[0010] In an example of the ESD protection device of the present invention, the P+ doped region, the N+ doped region and the well region all extend deep into the buried oxide layer.

[0011] In an example of the ESD protection device of the present invention, the well region is an N-well or a P-well.

[0012] In an example of the ESD protection device of the present invention, a shallow trench isolation structure is arranged around the diode array.

[0013] The utility model also provides a semiconductor device, which includes the ESD protection device in any one of the above examples.

[0014] The ESD protection device based on SOI process provided by the utility model, on the one hand, since the ESD protection device includes a diode array, the diode array includes a plurality of diode rows and a plurality of diode columns formed by arranging the diode rows in the column direction, the diode array includes both diodes formed in the row direction and diodes formed in the column direction, so the diode array can simultaneously have two current release paths in the row direction and the column direction, thereby reducing the on-resistance of the ESD protection device per unit area, improving the protection performance of the ESD protection device per unit area, and being more suitable for the manufacturing process of advanced semiconductor devices. On the other hand, since the surface of some well regions is provided with a polysilicon layer, two diodes with different on-resistances will exist in the diode array at the same time, that is, the diode on-resistance corresponding to the well region with a polysilicon layer on the surface is small and the discharge current is large; while the diode on-resistance corresponding to the well region without a polysilicon layer on the surface is relatively high, the power consumption is large, and the heat generation is high; the two diodes with different on-resistances exist at the same time, so that the ESD protection device can better take into account the performance of on-resistance, discharge current, circuit power consumption and heat generation, which is conducive to improving the comprehensive protection performance of the ESD protection device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the utility model. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0016] Figure 1 It is a structural schematic diagram of a polysilicon diode in the prior art;

[0017] Figure 2 It is a structural schematic diagram of a silicide blocking diode in the prior art;

[0018] Figure 3 A schematic diagram of a diode array structure composed of polysilicon diodes or silicide barrier diodes;

[0019] Figure 4 This is a schematic diagram of the diode array structure of an embodiment of the utility model;

[0020] Figure 5 for Figure 4 A schematic diagram of the local structure of a diode row in a diode array;

[0021] Figure 6 for Figure 4 A schematic diagram of the local structure of a diode column in a diode array;

[0022] Figure 7 A partial cross-sectional view of a polysilicon diode in one embodiment of the utility model;

[0023] Figure 8 It is a partial cross-sectional view of a silicide barrier diode in one embodiment of the utility model.

[0024] Component number description

[0025] 10. ESD protection device; 11. SOI substrate; 111. Bottom silicon; 112. Buried oxide layer; 113. Top silicon; 12. Diode array; 121. P+ doped region; 122. N+ doped region; 123. Well region; 124. Diode row; 125. Diode column; 126. First metal wire; 127. Second metal wire; 13. Metal silicide layer; 14. Shallow trench isolation structure; 15. Polysilicon layer; 20. Polysilicon diode; 30. Silicide blocking diode. DETAILED DESCRIPTION

[0026] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] In the present invention, it should be noted that, if the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, if the terms "first" and "second" appear, they are only used for description and distinction purposes, and cannot be understood as indicating or implying relative importance.

[0029] In the prior art, diodes are widely used in ESD protection devices 10 in SOI processes due to their simple structure, fast response speed, and good compatibility with SOI processes. Figure 1 and Figure 2 A common diode structure currently used in ESD protection devices 10 is shown.

[0030] Figure 1 The schematic diagram of the structure of a polysilicon diode 20 is shown. The polysilicon diode 20 includes a P+ doping region 121 used as a diode anode and an N+ doping region 122 used as a diode cathode, and a well region 123 is formed between adjacent P+ doping regions 121 and N+ doping regions 122. The polysilicon diode 20 is provided with a polysilicon layer 15 above the well region 123 between the P+ doping region 121 and the N+ doping region 122. In this way, when the polysilicon diode 20 discharges current, it can have a smaller on-resistance.

[0031] It should be noted that, it is understood by those skilled in the art that, during the formation of the polysilicon diode 20, at the location of the well region 123 below the polysilicon layer 15, as shown in FIG. Figure 7Generally, LDD (Lightly Doped Drain) is formed at positions Ⅰ and Ⅱ shown in the figure. The doping concentration of the LDD region is greater than that of the well region 123. Therefore, after the polysilicon layer 15 is coated, the current between the adjacent P+ doping region 121 and the N+ doping region 122 is more likely to flow on the surface of the well region 123 close to the polysilicon layer 15. As a result, in the polysilicon diode 20, the current flows shallowly at the well region 123, making it easier to obtain a smaller on-resistance. At the same time, Figure 7 As shown in the figure, since an LDD region is formed between adjacent P+ doping regions 121 and N+ doping regions 122, a current path formed between regions I and II becomes shorter than that of a silicide blocking diode 30 without an LDD region, thereby also reducing the on-resistance of the polysilicon diode 20 to a certain extent. Figure 2 A schematic diagram of the structure of a silicide blocking diode 30 is shown. The silicide blocking diode 30 includes a P+ doping region 121 used as a diode anode and an N+ doping region 122 used as a diode cathode, and a well region 123 is formed between adjacent P+ doping regions 121 and N+ doping regions 122. No polysilicon layer 15 is provided above the well region 123 corresponding to the silicide blocking diode 30. In this way, when the silicide blocking diode 30 discharges current, the current flow path at the well region 123 is deeper than that of the polysilicon diode 20, so it can have a relatively high on-resistance.

[0032] In the prior art, generally used Figure 1 or Figure 2 The diodes shown form a diode array 12 for use, such as Figure 3 As shown. Figure 3 It can be seen from the diode array 12 that the current conduction path in the diode array 12 is only in the row direction, so the discharge path of the ESD protection device 10 per unit area is limited, which in turn makes the protection performance of the ESD protection device 10 limited and difficult to meet the requirements of more advanced SOI manufacturing processes. At the same time, the diode array 12 uses a single diode structure, which makes the on-resistance of the ESD protection device 10 relatively simple and difficult to adjust, limiting the improvement of the comprehensive performance of the ESD protection device 10. Based on this, the present invention proposes an ESD protection device 10 and a semiconductor device based on SOI technology.

[0033] See also Figures 4 to 8The ESD protection device 10 and semiconductor device based on SOI process provided by the utility model can improve the conduction performance of ESD per unit area and the protection performance of the ESD protection device 10 for semiconductor devices per unit area by arranging a diode array 12 on the SOI substrate 11 and making the diode array 12 have two current release paths in the row direction and the column direction. At the same time, since there are two diodes with different on-resistances in the diode array 12, the ESD protection device 10 can better take into account the on-resistance, discharge current, heat generation and other performances, which is conducive to improving the comprehensive protection performance of the ESD protection device 10.

[0034] See also Figures 4 to 8 , the ESD protection device 10 includes an SOI substrate 11, a diode array 12 and a polysilicon layer 15. SOI technology is an advanced semiconductor manufacturing process, which involves forming a silicon crystal layer on an insulating layer to realize the manufacture of various electronic devices and integrated circuits. The SOI substrate 11 includes a bottom silicon 111, a buried oxide layer 112 and a top silicon 113 arranged from bottom to top. The bottom silicon 111 is usually a silicon wafer, which serves as the basis of the entire SOI substrate 11 structure. The buried oxide layer 112 is a layer of high-quality silicon dioxide (SiO2) grown or deposited on the bottom silicon 111 as an insulating layer. This layer is very thin, usually ranging from tens of nanometers to hundreds of nanometers, and it can insulate and isolate the bottom silicon 111 from the top silicon 113. The top silicon 113 is a layer of single crystal silicon grown or transferred on the buried oxide layer 112. This layer of single crystal silicon is very thin, usually in the range of hundreds of nanometers to several microns, and is the active area for forming transistors and other semiconductor devices.

[0035] The diode array 12 is formed on the top silicon 113, and there are many ways to form it, such as diffusion, ion implantation, epitaxial growth or polysilicon doping, etc. The specific method to be selected is mainly determined by factors such as the required diode characteristics (such as doping concentration, junction depth, uniformity, etc.), process compatibility, cost and production efficiency.

[0036] See also Figures 4 to 6 In this embodiment, the diode array 12 includes a plurality of diode rows 124, each diode row 124 includes a plurality of diode rows 124 along the row direction (eg Figure 4 A plurality of P+ doping regions 121 used as diode anodes and a plurality of N+ doping regions 122 used as diode cathodes are alternately arranged (in the X direction). A plurality of diode rows 124 are arranged along the column direction, and the plurality of P+ doping regions 121 and the plurality of N+ doping regions 122 in two adjacent rows are staggered along the column direction to form a plurality of diodes along the column direction (e.g., Figure 4A plurality of diode columns 125 are formed correspondingly (in the Y direction). Each diode column 125 includes a plurality of P+ doped regions 121 used as diode anodes and a plurality of N+ doped regions 122 used as diode cathodes, which are alternately arranged along the column direction. In each diode row 124 and each diode column 125, a well region 123 is formed between adjacent P+ doped regions 121 and N+ doped regions 122. The specific number of diodes arranged in each diode row 124 and each diode column 125 is not limited. The number of diodes arranged in each diode row 124 and each diode column 125 may be equal or unequal, and the specifications and types of the diodes arranged at the same time may be the same or different. By providing diode rows 124 and diode columns 125 composed of diode rows 124, the diode array 12 can include diodes arranged along the row direction and diodes arranged along the column direction at the same time, so that when the ESD protection device 10 discharges, the following is formed. Figure 4 There are two current release paths in the row direction and the column direction as shown by the arrows in the figure. Thus, the current discharge paths per unit area of ​​the ESD protection device 10 can be increased, thereby improving the conduction performance of the ESD per unit area.

[0037] The polysilicon layer 15 is at least disposed on the surface of a portion of the well region 123. Here, the polysilicon layer 15 is at least disposed on the surface of a portion of the well region 123 means that the polysilicon layer 15 is disposed on at least a portion of the surface of the well region 123 in the diode array 12, and the polysilicon layer 15 is not disposed on at least a portion of the surface. The diode corresponding to the well region 123 with the polysilicon layer 15 disposed on the surface is a polysilicon diode 20, and the diode corresponding to the well region 123 without the polysilicon layer 15 disposed on the surface is a silicide blocking diode 30, that is, the polysilicon diode 20 and the silicide blocking diode 30 exist in the diode array 12 at the same time.

[0038] The locations of the polysilicon diodes 20 and the silicide blocking diodes 30 are not limited. For example, the polysilicon diodes 20 can be arranged in the diode row 124, and the silicide blocking diodes 30 can be arranged in the diode column 125. Alternatively, part of the polysilicon diodes 20 and part of the silicide blocking diodes 30 can be arranged in the diode row 124, and the other part of the polysilicon diodes 20 and the silicide blocking diodes 30 can be arranged in the diode column 125. There are also multiple arrangements. The number of polysilicon diodes 20 and silicide blocking diodes 30 is also not limited. They can be the same number or different numbers, which is specifically determined by the on-resistance and leakage rate of the ESD protection device 10. The polysilicon layer 15 can be formed on the upper surface of the well region 123 by physical vapor deposition or chemical vapor deposition.

[0039] In this embodiment, since the surface of the partial well region 123 is provided with a polysilicon layer 15, two diodes with different on-resistances will exist simultaneously in the diode array 12, namely, the polysilicon diode 20 and the silicide blocking diode 30, and the polysilicon diode 20 has a relatively small on-resistance and a relatively large discharge current; while the silicide blocking diode 30 has a relatively high on-resistance, a relatively large power consumption, and a relatively high heat generation; therefore, the two diodes with different on-resistances exist simultaneously, so that the ESD protection device 10 can better balance the performances such as on-resistance, discharge current, circuit power consumption, and heat generation, which is beneficial to improving the comprehensive protection performance of the ESD protection device 10. At the same time, by adopting the above-mentioned diode array 12 structure, the on-resistance of the ESD protection device 10 itself can be adjusted by adjusting the quantitative ratio between the polysilicon diode 20 and the silicide blocking diode 30 per unit area, and the adjustment method is simple and easy to implement, thereby making it easier to expand the scope of use of the ESD protection device 10.

[0040] Although the locations of the polysilicon diode 20 and the silicide blocking diode 30 are not limited under the premise of meeting the protection performance requirements of the ESD protection device 10, preferably, in order to facilitate the molding and manufacturing of the diode array 12, in an example of the ESD protection device 10 of the present utility model, the polysilicon layer 15 is arranged on the surface of the well region 123 in the diode row 124. That is, the surface of the well region 123 of the diodes in the diode row 124 is provided with a polysilicon layer 15 to form the polysilicon diode 20, while the surface of the well region 123 of the diodes in the diode column 125 is not provided with a polysilicon layer 15 to form the silicide blocking diode 30. This arrangement can simplify the molding process of the ESD protection device 10 and save manufacturing costs. In another embodiment, the polysilicon layer 15 may be disposed on the surface of the well region 123 in the diode column 125, that is, the surface of the well region 123 of the diodes in the diode column 125 is provided with the polysilicon layer 15 to form the polysilicon diode 20, while the surface of the well region 123 of the diodes in the diode row 124 is not provided with the polysilicon layer 15 to form the silicide blocking diode 30. This arrangement can also achieve the above-mentioned beneficial effects.

[0041] See also Figure 7In an example of the ESD protection device 10 of the utility model, along the thickness direction of the SOI substrate 11, the polysilicon layer 15 protrudes from the surface of the P+ doping area 121 and the N+ doping area 122. The specific height of the polysilicon layer 15 protruding from the surface of the P+ doping area 121 and the N+ doping area 122 is not limited, and is subject to satisfying the conduction performance and process requirements. In this embodiment, since the polysilicon layer 15 protrudes from the surface of the P+ doping area 121 and the N+ doping area 122, the protruding portion of the polysilicon layer 15 can be used for self-alignment technology during the manufacturing and assembly process of the ESD protection device 10, ensuring the assembly alignment accuracy during the manufacturing process of the ESD protection device 10, and simplifying the process complexity in production.

[0042] In an example of the ESD protection device 10 of the present utility model, a metal silicide layer 13 is provided on the surface of the P+ doping region 121 and the N+ doping region 122, and the metal silicide layers 13 above the adjacent P+ doping region 121 and the N+ doping region 122 are insulated. The metal silicide layer 13 can be formed on the surface of the diode array 12 by any method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. The material of the metal silicide layer 13 can be any silicide that can reduce the contact resistance when the diode discharges, such as titanium silicide (TiSi2), cobalt silicide (CoSi2), nickel silicide (NiSi) and tungsten silicide (WSi2). Since the metal silicide layer 13 is provided above the P+ doping region 121 and the N+ doping region 122, the contact resistance of the P+ doping region 121 and the N+ doping region 122 can be reduced, thereby improving the rapid response performance and current discharge capacity of the ESD protection device 10.

[0043] It should be noted that, in one embodiment, please refer to Figure 7 and Figure 8 When the diode is a polysilicon diode 20, in addition to the polysilicon layer 15, a metal silicide layer 13 may be provided above the well region 123, but the metal silicide layer 13 above the well region 123 is insulated from the metal silicide layers 13 above the P+ doping region 121 and the N+ doping region 122 on both sides. When the diode is a silicide blocking diode 30, no metal silicide layer 13 is provided above the well region 123. This arrangement facilitates the formation of the metal silicide layer 13 on the surface of the diode array 12.

[0044] In an example of the ESD protection device 10 of the utility model, the well region 123 provided between the adjacent P+ doping region 121 and the N+ doping region 122 is an N-type well. In the N-type well, the P+ doping region 121 forms a PN junction with the N-well. In another embodiment, the well region 123 provided between the adjacent P+ doping region 121 and the N+ doping region 122 is a P-type well. In the P-type well, the N+ doping region 122 forms a PN junction with the P-well. It should be noted that in the diode array 12, the doping concentration of the P+ doping region 121, the N+ doping region 122, the N-well region or the P-well region is not limited, and is subject to meeting the ESD protection performance requirements for semiconductor devices.

[0045] The width of the well region 123 between the adjacent P+ doping region 121 and the N+ doping region 122 affects the trigger voltage of the ESD protection device 10. Under the condition that the ESD trigger voltage requirement is met, preferably, refer to Figure 5 and Figure 6 In an example of the ESD protection device 10 of the present utility model, the width of the well region 123 in the diode row 124 is consistent with the width of the well region 123 in the diode column 125. Specifically, please refer to Figure 7 In the partial cross-sectional view of the diodes in the diode row 124, the width of the well region 123 between the adjacent P+ doping regions 121 and N+ doping regions 122 is a. Figure 8 In the partial cross-sectional view of the diodes in the diode column 125, the width of the well region 123 between the adjacent P+ doping region 121 and the N+ doping region 122 is b, and the dimension a is equal to the dimension b. This arrangement can simplify the design dimension of the well region 123, thereby simplifying the ESD molding process and further reducing the ESD molding cost.

[0046] Under the premise of meeting the ESD protection performance requirements for semiconductor chips, multiple diodes in the diode array 12 can be connected in parallel, or in combination of series and parallel. Preferably, in an example of the ESD protection device 10 of the present utility model, refer to Figure 4, adjacent diodes in the diode row 124 and adjacent diodes in the diode column 125 are connected in parallel. That is, multiple diodes are connected in parallel in the diode row 124; multiple diodes are also connected in parallel in the diode column 125. When multiple diodes are connected in parallel, all P+ doped regions 121 are correspondingly provided with a first metal wire 126, and the first metal wire 126 electrically connects the P+ doped region 121 and the anode end; all N+ doped regions 122 are provided with a second metal wire 127, and the second metal wire 127 electrically connects the N+ doped region 122 and the cathode end. Since all diodes are connected in parallel, the diode array 12 can provide a current path with lower impedance when the ESD protection device 10 is discharging current, so that the electrostatic current can be quickly discharged when the ESD trigger occurs, thereby protecting the more sensitive circuits on the semiconductor device.

[0047] Along the thickness direction of the SOI substrate 11, the depth of the P+ doped region 121, the N+ doped region 122 and the well region 123 formed on the top silicon 113 is related to the ESD protection performance and process requirements. Under the premise of meeting the ESD process requirements and protection performance requirements, preferably, in an example of the ESD protection device 10 of the present invention, the P+ doped region 121, the N+ doped region 122 and the well region 123 are all formed to penetrate into the buried oxide layer 112. Figure 7 and Figure 8 As shown, along the thickness direction of the SOI substrate 11, the P+ doped region 121, the N+ doped region 122 and the well region 123 penetrate the top silicon 113 and are in contact with the upper surface of the buried oxide layer 112 below. This arrangement, on the one hand, helps to improve the robustness of the ESD protection device 10, thereby improving the service life and response speed of the ESD protection device 10. Among them, the robustness of the ESD protection device 10 refers to the ESD protection device 10 withstanding electrostatic discharge events without causing self-damage or performance degradation. On the other hand, since the depths of the P+ doped region 121, the N+ doped region 122 and the well region 123 are equal, it is convenient to control the depth of the P+ doped region 121, the N+ doped region 122 and the well region 123 during the molding process, and the molding process of the ESD protection device 10 can be further simplified.

[0048] See also Figure 5 and Figure 6In an example of the ESD protection device 10 of the present invention, a shallow trench isolation structure 14 is provided around the diode array 12. The shallow trench isolation structure 14 can be an overall closed-loop structure provided along the periphery of the diode array 12, or it can be a plurality of long strip trench docking structures provided along the column direction and the row direction of the diode array 12, as long as the isolation effect can be achieved around the diode array 12. In order to obtain a better isolation effect, in this embodiment, the shallow trench isolation structure 14 penetrates into the buried oxide layer 112. By providing the shallow trench isolation structure 14 on the periphery of the diode array 12, the mutual interference between the ESD protection device 10 and the adjacent devices can be reduced, and the reliability of the protection performance of the ESD protection device 10 can be improved.

[0049] In the present invention, a semiconductor device is also provided. In an example of the semiconductor device of the present invention, the semiconductor device may be a MOS transistor, an RF-SOI device, a MEMS device, an FD-SOI transistor, etc. The semiconductor device includes an ESD protection device 10 in any of the above examples. The ESD protection device 10 can provide a low-impedance path for guiding current to flow to the ground when an ESD event occurs to protect sensitive components in the semiconductor device. It should be noted that the specific connection structure of the ESD protection device 10 in the semiconductor device can refer to the relevant structural description in the prior art, which will not be repeated here.

[0050] In summary, the utility model provides an ESD protection device and a semiconductor device. Since the ESD protection device is provided with a diode array, it can have two current release paths in the row direction and the column direction at the same time, thereby reducing the on-resistance per unit area of ​​the ESD protection device, improving the ESD protection performance per unit area, and being more suitable for advanced semiconductor chip manufacturing processes. On the other hand, since a polysilicon layer is provided on the surface of some well regions, two diodes with different on-resistances will exist in the diode array at the same time, that is, the diode on-resistance corresponding to the well region with a polysilicon layer on the surface is small and the discharge current is large; while the diode on-resistance corresponding to the well region without a polysilicon layer on the surface is relatively high, the power consumption is large, and the heat generation is high; the two diodes with different on-resistances exist at the same time, so that the ESD protection device can better take into account the performance of on-resistance, discharge current, circuit power consumption and heat generation, which is conducive to improving the comprehensive protection performance of the ESD protection device.

[0051] Therefore, the utility model effectively overcomes some practical problems in the prior art and thus has high utilization value and use significance. The above embodiments are only illustrative of the principle and efficacy of the utility model, and are not used to limit the utility model. Anyone familiar with this technology can modify or change the above embodiments without violating the spirit and scope of the utility model. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the relevant technical field without departing from the spirit and technical ideas disclosed by the utility model should still be covered by the claims of the utility model.

Claims

1. An ESD protection device based on SOI process, characterized in that: include: SOI substrate, the SOI substrate includes a bottom silicon layer, a buried oxide layer and a top silicon layer arranged in sequence from bottom to top; A diode array formed on the top silicon layer; The diode array comprises a plurality of diode rows, each of which comprises a plurality of P+ doping regions and a plurality of N+ doping regions alternately arranged along the row direction; the plurality of diode rows are arranged along the column direction, and the plurality of P+ doping regions and the plurality of N+ doping regions in two adjacent rows are staggeredly distributed along the column direction, so as to form a plurality of diode columns correspondingly along the column direction; in each of the diode rows and each of the diode columns, a well region is formed between adjacent P+ doping regions and adjacent N+ doping regions; The polysilicon layer is disposed on at least a portion of the surface of the well region.

2. The ESD protection device according to claim 1, characterized in that: The polysilicon layer is disposed on a surface of the well region in the diode row or on a surface of the well region in the diode column.

3. The ESD protection device according to claim 1, characterized in that: Along the thickness direction of the SOI substrate, the polysilicon layer protrudes from the surfaces of the P+ doping region and the N+ doping region.

4. The ESD protection device according to claim 1, characterized in that: A metal silicide layer is disposed on the surfaces of the P+ doping region and the N+ doping region, and the metal silicide layers above the adjacent P+ doping regions and the N+ doping regions are insulated from each other.

5. The ESD protection device according to claim 1, characterized in that: The width of the well region in the diode row is consistent with the width of the well region in the diode column.

6. The ESD protection device according to claim 1, characterized in that: The adjacent diodes in the diode row and the adjacent diodes in the diode column are connected in parallel.

7. The ESD protection device according to claim 1, characterized in that: The P+ doping region, the N+ doping region and the well region all extend deep into the buried oxide layer.

8. The ESD protection device according to claim 1, characterized in that: The well region is an N-well or a P-well.

9. The ESD protection device according to any one of claims 1 to 8, characterized in that: Shallow trench isolation structures are arranged around the diode array.

10. A semiconductor device, characterized in that: An ESD protection device comprising any one of claims 1 to 9.

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