Solar cell
By setting electrical connection points in the isolation area of the solar cell to form a bypass, the battery efficiency loss problem caused by local shadow shading of photovoltaic modules is solved, and the power loss under shadow conditions is reduced.
Patent Information
- Application Number
- CN202421618721.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-10
- Publication Date
- 2025-05-23
- Estimated Expiration
- 2034-07-10
AI Technical Summary
Photovoltaic modules are blocked by dust, leaves and other debris in the wild environment, especially when local shadows are blocked, resulting in battery efficiency loss.
An electrical connection point is provided in the isolation region of the solar cell, as an electrical connection point between the P and N regions, forming a bypass path to reduce the power loss of the battery.
Through the bypass, the power loss of the battery during local shadow occlusion is reduced, and about 70% of the original power is basically retained.
Smart Images

Figure CN222897497U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the photovoltaic field, in particular to a solar cell. Background Art
[0002] Photovoltaic modules are usually installed in sunny areas, such as roofs, hillsides, deserts, Gobi deserts, etc. The outdoor environment is complex, and during use, there are often dust, leaves and other debris blocking the module. If a partial shadow occurs, the module will suffer huge losses.
[0003] In view of this, it is necessary to provide an improved solar cell to solve the above technical problems. Utility Model Content
[0004] The utility model provides a solar cell, which optimizes the isolation area between the P area and the N area on the back of the cell, and solves the problem of cell efficiency loss caused by shadow shading.
[0005] In order to achieve one of the above-mentioned purposes of the utility model, the utility model adopts the following technical solutions:
[0006] A solar cell comprises a P region, an N region, and an isolation region between the P region and the N region on the back side thereof. The solar cell also comprises an electrical connection point located in a partial area of the isolation region, wherein the electrical connection point electrically connects the P region and the N region.
[0007] Furthermore, the proportion of the isolation area having the electrical connection points to all the isolation areas is 1% to 50%.
[0008] Furthermore, there is at least one isolation region without an electrical connection point between the two isolation regions having the electrical connection points.
[0009] Furthermore, a plurality of the N regions and a plurality of the P regions are alternately arranged along the OY direction, and each of the N regions is electrically connected only to the P region on one side thereof in the OY direction.
[0010] Furthermore, each electrical connection point in the isolation region includes a plurality of sub-connection points, and the plurality of sub-connection points are arranged in the isolation region at intervals along the OX direction.
[0011] Further, the P region includes a plurality of first main gate regions extending along the OX direction and a plurality of first auxiliary gate regions extending along the OY direction, the plurality of first auxiliary gate regions are arranged along the OX direction, and the first auxiliary gate regions are connected to the first main gate regions;
[0012] The N region includes a plurality of second main gate regions extending along the OX direction and a plurality of second sub-gate regions extending along the OY direction, wherein the plurality of second sub-gate regions are arranged along the OX direction, and the second sub-gate regions are connected to the second main gate regions; the first main gate regions and the second main gate regions are alternately arranged along the OY direction, and the first sub-gate regions and the second sub-gate regions are alternately arranged along the OX direction;
[0013] The sub-connection point is located in an isolation region around the first sub-gate region, or the sub-connection point is located in an isolation region around the second sub-gate region.
[0014] Further, the sub-connection point connects the first main gate region and the second auxiliary gate region; or the sub-connection point connects the second main gate region and the first auxiliary gate region; or the sub-connection point connects the first auxiliary gate region and the second auxiliary gate region.
[0015] Furthermore, the sum of the areas of all the electrical connection points accounts for 0.1% to 1% of the sum of the areas of all the isolation regions; and / or, in each of the isolation regions, the area of the electrical connection points accounts for 0.1% to 2%.
[0016] Furthermore, the solar cell also includes an anti-reflection layer, a first electrode and a second electrode located on the back of the P region and the N region, the first electrode is connected to the P region through the anti-reflection layer, and the second electrode is connected to the N region through the anti-reflection layer.
[0017] Furthermore, the solar cell also includes a suede structure, a passivation layer and an anti-reflection layer located on the front side of the silicon substrate.
[0018] The beneficial effect of the utility model is that the solar cell of the utility model, by setting an electrical connection point in a partial area of the isolation area as the electrical connection point between the P area and the N area, can serve as a bypass path to reduce the power loss of the battery when a part of the battery cell is blocked by a shadow. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a schematic structural diagram of the back side of a solar cell in one embodiment of the utility model;
[0020] Figure 2 for Figure 1 A partial enlarged view of a unit in the figure;
[0021] Figure 3 is a schematic diagram of a unit in another embodiment;
[0022] Figure 4 is a schematic diagram of a unit in another embodiment;
[0023] Figure 5 Figure 1 This is a schematic structural diagram of the back side of a solar cell in one embodiment of the utility model;
[0024] Figure 6 It is a schematic structural diagram of a solar cell in one embodiment of the utility model.
[0025] Among them, 100-solar cell, 101-silicon substrate, 102-front passivation layer, 103-front anti-reflection layer, 104-back passivation layer, 105-back anti-reflection layer, 1-P region, 11-first main gate region, 12-second auxiliary gate region, 2-N region, 21-second main gate region, 22-second auxiliary gate region, 3-isolation region, 4-electrical connection point, 5-first electrode, 6-second electrode. DETAILED DESCRIPTION
[0026] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.
[0027] In the various drawings of the present invention, for the convenience of illustration, some dimensions of structures or parts are exaggerated relative to other structures or parts, and therefore, are only used to illustrate the basic structure of the subject matter of the present invention.
[0028] Please refer to Figure 1 to Figure 6 As shown, the solar cell 100 of the utility model includes a silicon substrate 101, a front passivation layer 102 and a front anti-reflection layer 103 located on the front side of the silicon substrate 101, a P region 1 and an N region 2 located on the back side of the silicon substrate 101, an isolation region 3 located between the P region 1 and the N region 2, an electrical connection point 4 located in a partial area of the isolation region 3, a back passivation layer 104, a back anti-reflection layer 105, a first electrode 5 located in the P region 1, and a second electrode 6 located in the N region 2.
[0029] The silicon substrate 101 is an N-type silicon wafer, and the front side thereof has a velvet structure, which can increase the light limiting property of the front side and improve the battery efficiency.
[0030] The front passivation layer 102 passivates the surface of the silicon substrate 101, reduces interface recombination, and improves battery efficiency. The front passivation layer 102 is preferably an aluminum oxide layer, which can be prepared by ALD process, and the thickness can be accurately controlled to 3nm to 5nm.
[0031] The front anti-reflection layer 103 can reduce the front reflectivity. The front anti-reflection layer 103 is selected from a laminated film of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the front anti-reflection layer 103 is 60nm to 130nm, preferably 70nm to 80nm.
[0032] In the present invention, the front passivation layer 102 and the front anti-reflection layer 103 are optional film layers.
[0033] The P region 1 is a patterned boron diffusion region and includes a plurality of first main gate regions 11 extending along the OX direction and a plurality of first auxiliary gate regions 12 extending along the OY direction. The plurality of first auxiliary gate regions 12 are arranged along the OX direction and are connected to the first main gate region 11 .
[0034] Specifically, the first auxiliary gate region 12 crosses the first main gate region 11 along the OY direction, that is, the first auxiliary gate region 12 extends from the first main gate region 11 to both sides along the OY direction. Preferably, the first auxiliary gate region 12 and the first main gate region 11 are perpendicular to each other.
[0035] The N region 2 includes a tunneling layer 21 and an N-type polysilicon layer 22 to prevent the second electrode 6 from directly contacting the silicon substrate 101. The N region 2 includes a plurality of second main gate regions 21 extending along the OX direction and a plurality of second auxiliary gate regions 22 extending along the OY direction. The plurality of second auxiliary gate regions 22 are arranged along the OX direction, and the second auxiliary gate regions 22 are connected to the second main gate region 21.
[0036] Specifically, the second auxiliary gate region 22 crosses the second main gate region 21 along the OY direction, that is, the second auxiliary gate region 22 extends from the second main gate region 21 to both sides along the OY direction. Preferably, the second auxiliary gate region 22 and the second main gate region 21 are perpendicular to each other.
[0037] The first main gate region 11 and the second main gate region 21 are alternately arranged along the OY direction, and the first sub-gate region 12 and the second sub-gate region 22 are alternately arranged along the OX direction, and the entire P region 1 and the entire N region 2 are distributed in a forked shape, which is conducive to the collection of carriers. Those skilled in the art usually focus on the first main gate region 11 and the second main gate region 21, and believe that the P region 1 and the N region 2 are alternately arranged along the OY direction as a whole.
[0038] The width of the first sub-gate region 12 is 2:1 to 4:1, preferably 3:1. The P region 1 forms a PN junction with the silicon substrate 101. The width of the P region 1 is greater than that of the N region 2, which is more conducive to generating a large number of electrons and holes and improving battery efficiency.
[0039] Specifically, the width of the first auxiliary gate region is 540nm-660nm, and the width of the second auxiliary gate region is 180nm-220nm. In one embodiment, the width of the first auxiliary gate region is 600nm, and the width of the second auxiliary gate region is 200nm.
[0040] The isolation region 3 is located between the P region 1 and the N region 2, isolating the P region 1 and the N region 2 to prevent them from being connected to each other. Preferably, the width of the isolation region 3 is 50 μm to 100 μm. If it is too small, the preparation process is difficult.
[0041] The utility model breaks the limitation of completely isolating the P region 1 and the N region 2 in the traditional back-side battery (BC battery), and sets an electrical connection point 4 at a part of the isolation area 3, which serves as a local electrical connection point between the P region 1 and the N region 2 and can be regarded as a bypass diode. When a part of the battery cell is shaded, the electrical connection 4 bypasses the P region 1 and the N region 2, which can reduce the power loss of the battery.
[0042] In the present application, "partial area of the isolation area 3" includes two meanings: one is a part of the isolation area 3 among all the isolation areas 3, and the other is a part of any isolation area 3. Therefore, the electrical connection point 4 is located at a part of the isolation area 3, and the P area 1 and the N area 2 on the back are not fully connected as a conductive body, and are only electrically connected through the electrical connection point 4. The electrical connection point 4 constitutes the electrical connection point / leakage point of the P area 1 and the N area 2, and can be regarded as a bypass diode. When the battery cell is partially shaded, it reduces the power loss of the battery; when there is no shadow, the leakage phenomenon is very weak and will not affect the normal current collection of the battery.
[0043] Furthermore, the proportion of isolation regions 3 having the electrical connection points 4 to all isolation regions 3 is 1% to 50%, that is, a portion of isolation regions 3 have no electrical connection points 4, which can avoid serious leakage in N region 2 and P region 1 and reduce battery efficiency.
[0044] Preferably, there is at least one isolation region 3 without electrical connection point 4 between two isolation regions 3 with the electrical connection point 4, so as to avoid the P region 1 and the surrounding N region 2 being connected as a whole, and also avoid the N region 2 and the surrounding P region 1 being connected as a whole.
[0045] In a specific embodiment, a plurality of N regions 2 and a plurality of P regions 1 are alternately arranged along the OY direction, and each N region 2 is electrically connected only to the P region 1 on one side of the N region 2 in the OY direction, and is not electrically connected to the P region 1 on the other side; similarly, each P region 1 is electrically connected only to the N region 2 on one side of the N region 2 in the OY direction. Therefore, only adjacent P regions 1 and N regions 2 are electrically connected, rather than all P regions 1 and N regions 2 on the back being electrically connected as one.
[0046] Furthermore, each electrical connection point 4 in the isolation area 3 includes a plurality of sub-connection points, and preferably, the plurality of sub-connection points are arranged in the isolation area 3 at intervals along the OX direction. With such a design, the area of each sub-connection point is reduced, and the leakage rate is low; and the multi-point distribution forms a plurality of small bypass paths, and when any area is blocked by a shadow, bypass can be achieved quickly.
[0047] Specifically, the sub-connection point is located in the isolation region 3 around the first sub-gate region 12, or the sub-connection point is located in the isolation region 3 around the second sub-gate region 22. Preferably, the sub-connection point is located at the end of the P region 1 or the N region 2, so that the CT (cycle time) of the laser film opening can be optimized.
[0048] In an optional embodiment, Figure 2 and Figure 3 As shown, the sub-connection point connects the first auxiliary gate region 12 and the second auxiliary gate region 22, and the current of the auxiliary gate region is smaller than the current of the main gate region. Therefore, in the absence of shielding, the probability of leakage is small.
[0049] In an optional embodiment, the sub-connection point connects the first main gate region 11 and the second auxiliary gate region 22; or Figure 4 As shown, the sub-connection point connects the second main gate region 21 and the first auxiliary gate region 12, and can be quickly bypassed when blocked by a shadow to avoid generating a hot spot.
[0050] In addition, in the entire battery cell, the sum of the areas of all the electrical connection points 4 accounts for 0.1% to 1% of the sum of the areas of all the isolation areas 3; such a design can ensure that the battery can bypass through the electrical connection points 4 when shadows are blocked, while avoiding serious leakage.
[0051] Preferably, in each of the isolation regions 3 , the area of the electrical connection point 4 accounts for 0.1% to 2%.
[0052] Based on any of the above embodiments, the resistance of the electrical connection point 4 is preferably less than the resistance of the isolation region 3, and can be used as a conductive path when blocked by a shadow. And the resistance of the electrical connection point 4 is preferably not less than the resistance of the P region 1, or the resistance of the electrical connection point 4 is preferably not less than the resistance of the N region 2. Under normal circumstances without shadow blocking, holes and electrons are collected to the first electrode 5 and the second electrode 6 respectively, and will not bypass through the electrical connection point 4; only when blocked by a shadow, the resistance of the P region 1 and the N region 2 increases, and the N region 2 and the P region 1 are connected through the electrical connection point 4.
[0053] In the present invention, the electrical connection point 4 is made of the same material as the N region 2, and it can also be understood that the electrical connection point 4 is a connection portion of the N region 2 extending to the isolation region 3 to connect with the P region 1. With this design, the electrical connection point 4 is formed together with the N region 2, and the process is simple.
[0054] Alternatively, the electrical connection point 4 is made of the same material as the P region 1. It can also be understood that the electrical connection point 4 is a connection portion extending from the P region 1 to the isolation region 3 to connect with the N region 2. With this design, the electrical connection point 4 is formed together with the P region 1, and the process is simple.
[0055] The back passivation layer 104 is used to passivate the P region 1 and the N region 2, and is preferably an aluminum oxide layer with a thickness of 3 nm to 5 nm.
[0056] The back anti-reflection layer 105 reduces the back reflectivity. The back anti-reflection layer 105 is selected from a laminated film of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the back anti-reflection layer 105 is 60nm to 130nm, preferably 70nm to 80nm.
[0057] The first electrode 5 passes through the back anti-reflection layer 105 and the back passivation layer 104 to contact the P region 1; the second electrode 6 passes through the back anti-reflection layer 105 and the back passivation layer 104 to contact the N region 2. Of course, the back passivation layer 104 and the back anti-reflection layer 105 may not be provided, and the first electrode 5 is directly formed in the P region 1, and the second electrode 6 is directly formed in the N region 2.
[0058] The first electrode 5 in contact with the P region 1 includes a first main gate and a first sub-gate. The first main gate is located in the first main gate region, and the width of the first main gate is smaller than the width of the first main gate region. The first sub-gate is located in the first sub-gate region, and the width of the first sub-gate is smaller than the width of the first sub-gate region. The width of the first sub-gate is 30 μm to 40 μm.
[0059] The second electrode 6 in contact with the N region 2 includes a second main gate and a second sub-gate, wherein the second main gate is located in the second main gate region, and the width of the second main gate is smaller than the width of the second main gate region. The second sub-gate is located in the second sub-gate region, and the width of the second sub-gate is smaller than the width of the second sub-gate region. The width of the second sub-gate is 30 μm to 40 μm.
[0060] In summary, the solar cell 100 of the present invention, by setting an electrical connection point 4 in a partial area of the isolation area 3 as an electrical connection point between the P area 1 and the N area 2, can bypass the P area 1 and the N area 2 when a part of the battery cell is blocked by a shadow, thereby reducing the power loss of the battery and basically retaining about 70% of the original power.
[0061] In addition, the utility model also provides a method for preparing a solar cell 100, comprising the following steps:
[0062] A patterned P region 1 is formed on the back side of the silicon substrate;
[0063] A patterned N region 2 is formed on the back side of the silicon substrate, and an isolation region 3 is provided between the N region 2 and the P region 1;
[0064] An electrical connection point 4 is formed at a portion of the isolation region 3 , and the electrical connection point 4 electrically connects the P region 1 and the N region 2 .
[0065] The structural positional relationship among the P region 1 , the N region 2 , the isolation region 3 and the electrical connection point 4 is the same as that of the solar cell 100 , which will not be described in detail here. The following will focus on the formation process.
[0066] In the first type of embodiments, the electrical connection point 4 and the N region 2 are formed simultaneously.
[0067] The method for preparing the solar cell is as follows: firstly, a patterned P region 1 is formed, and then a patterned N region 2 and the electrical connection point 4 are formed simultaneously.
[0068] The formation of the patterned P region 1 comprises the following steps:
[0069] Boron diffusion is performed on the entire back side of the silicon substrate to form a boron diffusion layer; wherein the doping concentration of the boron diffusion layer is 5E18cm -3 ~5E19cm -3 The square resistance is 250ohm / sq~350ohm / sq, and the junction depth is 0.5μm~0.1μm.
[0070] Laser film opening is used to remove the boron diffusion layer outside the P region 1 to form a patterned P region 1. The laser uses a green laser with a power of 50W to 120W; or a purple laser with a power of 30W to 60W. Ultraviolet picosecond or green picosecond laser is preferred, as these lasers have low damage and low cost; femtosecond laser can also be used.
[0071] The formation of the patterned N region 2 comprises the following steps:
[0072] forming a tunneling layer and an N-type amorphous silicon layer on the entire back surface, preferably depositing the tunneling layer by a PECVD process, and growing the phosphorus-doped amorphous silicon layer by an in-situ doping method;
[0073] Annealing, the N-type amorphous silicon layer is transformed into an N-type polycrystalline silicon layer;
[0074] Laser film opening leaves only the tunneling layer and polysilicon layer at the locations of the N region 2 and the electrical connection point 4, and simultaneously forms the N region 2 and the electrical connection point 4. The laser film opening process here is the same as the laser film opening process when forming the P region 1, and will not be repeated here.
[0075] Specifically, the tunneling layer is selected from a silicon oxide layer (SiOx) or a silicon carbide layer (SiC), and has a thickness of 1nm to 3nm, preferably 1nm to 2.5nm, more preferably 1nm to 2nm, or, 1.5nm to 2nm, or 1.5nm to 2.5nm. The utility model optimizes the thickness according to the density of the tunneling layer 31. When the tunneling layer 31 is SiOx, the thickness is 1.4nm to 2.3nm; when the tunneling layer 31 is SiC, the film layer is more dense, and the thickness is 1nm to 1.8nm.
[0076] The N-type polysilicon layer is a phosphorus-doped polysilicon layer, a carbon-doped polysilicon layer, or a nitrogen-doped polysilicon layer. Phosphorus-doping is used as an example for the following description. The annealing temperature is 850°C to 980°C, and the doping concentration of the N-type polysilicon layer is 3E20cm -3 ~5E20cm -3 ; The thickness is 80nm to 130nm, and can be set to 90nm, or 95nm, or 100nm, or 105nm, or 110nm, or 115nm, or 120nm.
[0077] Furthermore, the method for preparing the solar cell further comprises:
[0078] A front passivation layer 102 and a back passivation layer 104 are formed on the entire front and back sides respectively. For example, an aluminum oxide passivation layer is deposited by an ALD process, which can form a good passivation effect on both the P region 1 and the N region 2, with a thickness of 3nm to 6nm, preferably 3nm to 5nm.
[0079] A front anti-reflection layer 103 and a back anti-reflection layer 105 are formed on the entire front and back sides, respectively. The front anti-reflection layer 103 and the back anti-reflection layer 105 are laminated films composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the front anti-reflection layer 103 and the back anti-reflection layer 105 is 60nm to 130nm, preferably 70nm to 80nm, to reduce reflectivity.
[0080] A first electrode 5 and a second electrode 6 are formed in the P region 1 and the N region 2, respectively. Specifically, the first electrode 5 and the second electrode 6 can be formed by screen printing and sintering, and the first electrode 5 passes through the back anti-reflection layer 105 and the back passivation layer 104 to contact the P region 1; the second electrode 6 passes through the back anti-reflection layer 105 and the back passivation layer 104 to contact the N-type polysilicon layer.
[0081] Specifically, the second sub-grid is printed→drying→the first sub-grid is printed→drying→the first main grid and the second main grid are printed→sintering.
[0082] In the second embodiment, the electrical connection point 4 is formed synchronously with the P region 1. The method for preparing the solar cell is as follows: first, the patterned P region 1 and the electrical connection point 4 are formed synchronously, and then the patterned N region 2 is formed. The difference from the first embodiment is only the following steps.
[0083] The formation of the patterned P region 1 comprises the following steps:
[0084] Boron diffusion is performed on the entire back side of the silicon substrate;
[0085] Laser film opening is performed, leaving only the boron diffusion layer at the location of the P region 1 and the electrical connection point 4, and patterned P region 1 and electrical connection point 4 are formed simultaneously.
[0086] The formation of the patterned N region 2 comprises the following steps:
[0087] forming a tunneling layer and an N-type amorphous silicon layer on the entire back side;
[0088] Annealing, the N-type amorphous silicon layer is transformed into an N-type polycrystalline silicon layer;
[0089] Laser film opening is performed, leaving only the tunneling layer and the N-type polysilicon layer at the location of the N region 2 .
[0090] The other steps are the same as those in the first embodiment and will not be described in detail here.
[0091] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
[0092] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the utility model. They are not intended to limit the protection scope of the utility model. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the utility model should be included in the protection scope of the utility model.
Claims
1. A solar cell, comprising a P region, an N region, and an isolation region between the P region and the N region on the back side thereof, characterized in that: The solar cell further includes an electrical connection point located in a partial area of the isolation region, wherein the electrical connection point electrically connects the P region and the N region.
2. The solar cell according to claim 1, characterized in that: The proportion of the isolation area having the electrical connection point to all the isolation areas is 1% to 50%.
3. The solar cell according to claim 2, characterized in that: There is at least one isolation region without an electrical connection point between the two isolation regions with the electrical connection points.
4. The solar cell according to claim 3, characterized in that: A plurality of the N regions and a plurality of the P regions are alternately arranged along the OY direction, and each of the N regions is electrically connected only to the P region on one side thereof in the OY direction.
5. The solar cell according to claim 1, characterized in that: Each electrical connection point in the isolation region includes a plurality of sub-connection points, and the plurality of sub-connection points are arranged in the isolation region at intervals along the OX direction.
6. The solar cell according to claim 5, characterized in that: The P region includes a plurality of first main gate regions extending along the OX direction and a plurality of first auxiliary gate regions extending along the OY direction, wherein the plurality of first auxiliary gate regions are arranged along the OX direction, and the first auxiliary gate regions are connected to the first main gate regions; The N region includes a plurality of second main gate regions extending along the OX direction and a plurality of second sub-gate regions extending along the OY direction, wherein the plurality of second sub-gate regions are arranged along the OX direction, and the second sub-gate regions are connected to the second main gate regions; the first main gate regions and the second main gate regions are alternately arranged along the OY direction, and the first sub-gate regions and the second sub-gate regions are alternately arranged along the OX direction; The sub-connection point is located in an isolation region around the first sub-gate region, or the sub-connection point is located in an isolation region around the second sub-gate region.
7. The solar cell according to claim 6, characterized in that: The sub-connection point connects the first main gate region and the second auxiliary gate region; or the sub-connection point connects the second main gate region and the first auxiliary gate region; or the sub-connection point connects the first auxiliary gate region and the second auxiliary gate region.
8. The solar cell according to claim 1, characterized in that: The sum of the areas of all the electrical connection points accounts for 0.1% to 1% of the sum of the areas of all the isolation regions; and / or, in each of the isolation regions, the area of the electrical connection points accounts for 0.1% to 2%.
9. The solar cell according to any one of claims 1 to 8, characterized in that: The solar cell further includes an anti-reflection layer, a first electrode and a second electrode located on the back of the P region and the N region. The first electrode is connected to the P region through the anti-reflection layer, and the second electrode is connected to the N region through the anti-reflection layer.
10. The solar cell according to any one of claims 1 to 8, characterized in that: The solar cell further comprises a suede structure, a passivation layer and an anti-reflection layer located on the front side of the silicon substrate.