Display device

Abstract

A display device is disclosed. The display device includes a substrate including a display area and a non-display area adjacent to the display area; a first dam over the substrate in the non-display area; and a second dam in the non-display area over the substrate, closer to an edge of the non-display area than the first dam, and including a first organic layer over the substrate and a second organic layer over the first organic layer and spaced apart from a first side of the first organic layer facing the first dam. Accordingly, corrosion of the fan-out lines can be prevented or reduced.

Description

Technical Field

[0001] One or more embodiments relate to a display device having a dam in a non-display area. Background Art

[0002] The display device may include a display area for displaying an image and a non-display area surrounding the display area. Pixels, which are the smallest unit for displaying an image, may be arranged in the display area. Each of the pixels may include a pixel circuit and a light-emitting element connected to the pixel circuit. Fan-out lines for providing signals and voltages to the pixels may be positioned in the non-display area.

[0003] The dam may be formed in the non-display region to prevent or reduce overflow of organic and / or inorganic substances during a process of forming an encapsulation layer covering the light emitting element. Utility Model Content

[0004] The utility model aims to provide a display device for preventing corrosion of fan-out lines in a non-display area.

[0005] According to one or more embodiments, a display device may include: a substrate including a display area and a non-display area adjacent to the display area; a first dam above the substrate in the non-display area; and a second dam above the substrate in the non-display area, closer to an edge of the non-display area than the first dam, and including a first organic layer above the substrate and a second organic layer above the first organic layer and spaced apart from a first side of the first organic layer facing the first dam.

[0006] The first side of the first organic layer and one side of the second organic layer facing the first dam may have a stepped shape.

[0007] The second organic layer may contact a second side of the first organic layer opposite to the first side.

[0008] The display device may further include an insulating structure, which is between the substrate and the first dam and includes: a first region contacting the first organic layer and separated from the second organic layer; and a second region contacting the first organic layer and the second organic layer, and an opening is defined in the insulating structure to expose at least a portion of the upper surface of the substrate, and the first organic layer may fill the opening.

[0009] The display device may further include a blocking pattern between the first organic layer and the second organic layer and protruding from the second dam toward the first dam.

[0010] The blocking pattern may be at an edge of the second dam, and may extend along the first side of the first organic layer.

[0011] The display device may also include: a first power line on the substrate and overlapping the non-display area; and a second power line on the substrate, overlapping the non-display area and spaced apart from the first power line, and the blocking pattern may include a first blocking pattern connected to the first power line and on the same layer as the first power line, and a second blocking pattern connected to the second power line and on the same layer as the second power line.

[0012] The display device may also include: a first power line on the substrate and overlapping the non-display area; and a second power line on the substrate, overlapping the non-display area and spaced apart from the first power line, and the blocking pattern may include a first blocking pattern connected to the first power line and on a different layer from the first power line, and a second blocking pattern connected to the second power line and on a different layer from the second power line.

[0013] The display device may further include: a first inorganic encapsulating layer on the first dam and extending to a first side of the first organic layer; and a second inorganic encapsulating layer on the first inorganic encapsulating layer, and the first inorganic encapsulating layer may contact the second organic layer.

[0014] The display device may further include: a first inorganic encapsulating layer on the first dam and extending to the first side of the first organic layer; and a second inorganic encapsulating layer on the first inorganic encapsulating layer, and the first inorganic encapsulating layer may be spaced apart from the second organic layer.

[0015] In a display device and a method for manufacturing the same according to one or more embodiments of the present disclosure, the display device may include: a first organic layer in a non-display area; and a second organic layer on the first organic layer and having a step shape together with the first side of the first organic layer. The portion of the interlayer insulating layer overlapping the edge of the first organic layer facing the first dam may be damaged due to the etching process. Because the second organic layer does not cover the first side of the first organic layer, the first organic layer overlapping the second organic layer may not cover the damaged portion of the interlayer insulating layer. Therefore, the portion of the interlayer insulating layer overlapping the second organic layer will not be damaged, so even if moisture flows in from the outside of the second dam including the first organic layer and the second organic layer through the inflow path, the corrosion of the fan-out line can be prevented or reduced.

[0016] In addition, since there is no damage to the interlayer insulating layer immediately below the first organic layer, stress applied to the interlayer insulating layer covering the fan-out line is reduced, so that the possibility of cracks occurring inside the display device can be prevented or reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0018] Figure 1is a plan view showing a display device according to one or more embodiments of the present disclosure.

[0019] Figure 2 is a circuit diagram illustrating a pixel according to one or more embodiments of the present disclosure.

[0020] Figure 3 It is along Figure 1 A cross-sectional view taken along line II'.

[0021] Figure 4 According to one or more embodiments of the present disclosure Figure 1 An enlarged plan view of area "A".

[0022] Figure 5 It is shown along Figure 4 A cross-sectional view of an example of a cross section taken along line II-II' in FIG.

[0023] Figure 6 It is shown along Figure 4 A cross-sectional view of an example of a cross-section taken along line III-III' in FIG.

[0024] Figure 7 It is shown Figure 5 A cross-sectional view of another example in FIG.

[0025] Figure 8 It is shown Figure 6 A cross-sectional view of another example in FIG.

[0026] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 It shows the manufacturing Figure 5 and Figure 6 A cross-sectional view of a method of displaying a device.

[0027] Fig.17 According to one or more embodiments of the present disclosure Figure 1 An enlarged plan view of area "A".

[0028] Fig.18 It is along Fig.17 A cross-sectional view taken along line III-III'. DETAILED DESCRIPTION

[0029] By referring to the detailed description and drawings of the embodiments, the aspects of some embodiments of the present disclosure can be more easily understood. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects of the present disclosure can be omitted. Unless otherwise noted, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0030] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown here. When describing an embodiment, the use of "may", "may" or "may not" corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and replacements within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically possible. The various embodiments may be implemented independently of one another, or may be implemented together in association.

[0031] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. As such, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of an element.

[0032] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structures or functional descriptions disclosed herein are merely exemplary. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but include shape deviations caused by, for example, manufacturing.

[0033] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0034] For ease of explanation, spatial relative terms such as "under ...", "below ...", "lower", "under ...", "under ...", "above ...", "upper", "upper side", etc. may be used here to describe the relationship between one element or feature and another (some) element or feature as shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "under" "under" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "under ..." and "under ..." can cover both upper and lower orientations. The device can be oriented in addition (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used here should be interpreted accordingly. Similarly, when a first part is described as being arranged "on" a second part, this indicates that the first part is arranged at the upper or lower side of the second part based on the direction of gravity (not limited to the upper side of the second part).

[0035] In addition, the phrase "in a plan view" refers to the situation of viewing a portion of an object from above, and the phrase "in a schematic cross-sectional view" refers to the situation of viewing a schematic cross-section obtained by vertically cutting a portion of an object from the side. The term "overlapping" or its variants means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlapping" may include stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "spaced apart from" or "placed next to" or "deviation from" and any other suitable equivalents that will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, although still facing each other.

[0036] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on" another element, layer, region, or component, "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component in a manner in which one or more intervening elements, layers, regions, or components may be present. In addition, this may be collectively referred to as direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or one or more intervening layers, regions, or components may be present. The one or more intervening components may include switches, resistors, capacitors, and the like. When describing the embodiments, unless explicitly described as directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled to" or "directly on" means that one component is directly connected or coupled to another component, or is directly on another component without intervening components.

[0037] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly below" the other part, but also the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components, such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0038] For the purposes of this disclosure, expressions such as "at least one of..." or "any one of..." or "one or more of..." modify the entire list of elements when following a list of elements without modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one of the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XY, YZ, and XZ as examples) or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0039] It will be understood that, although the terms "first", "second", "third", etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below can be referred to as the second element, component, region, layer or part. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used here to distinguish elements of different categories (or groups). For simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0040] In the example, the x-direction, the y-direction and / or the z-direction are not limited to the three axes of the rectangular coordinate system, but can be interpreted in a broader sense. For example, the x-direction, the y-direction and the z-direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The x-direction can include the +x direction and the -x direction, the y-direction can include the +y direction and the -y direction, and the z-direction can include the +z direction and the -z direction. The same situation applies to the first direction, the second direction and / or the third direction.

[0041] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "one (kind / person)" are also intended to include plural forms, and the plural forms are also intended to include singular forms. It will also be understood that when the terms "comprise", "have", "include" and variations thereof are used in this specification, the stated features, wholes, steps, operations, elements and / or components are indicated, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups are not excluded.

[0042] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in the reverse order of the described order.

[0043] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and refers to the acceptable deviation range of the particular value determined by those of ordinary skill in the art. For example, "about" may refer to within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0045] Figure 1 is a plan view showing a display device according to one or more embodiments of the present disclosure.

[0046] Reference Figure 1 , the display device 100 according to one or more embodiments of the present disclosure may include a display area DA and a non-display area PA. The non-display area PA may be adjacent to the display area DA. For example, the non-display area PA may surround the display area DA.

[0047] A plurality of pixels PX may be arranged in the display area DA. The pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 crossing the first direction DR1. Each of the pixels PX may emit light having a color (eg, a preset color). An image may be displayed in the display area DA by light emitted from each of the pixels PX.

[0048] The first power line PL1 and the second power line PL2 may be positioned in the non-display area PA. The first power line PL1 and the second power line PL2 may supply power voltages to the pixels PX. For example, the first power line PL1 may supply a low power voltage (eg, Figure 2 The second power line PL2 may supply a high power voltage (eg, a low power voltage ELVSS) to the pixel PX. Figure 2 high power voltage ELVDD).

[0049] The first power line PL1 may include a first portion PL1a surrounding at least a portion of the display area DA and a second portion PL1b connected to one end of the first portion PL1a and extending in a direction opposite to the first direction DR1. The second portion PL1b may be connected to a first power source and may transmit a low power voltage to the first portion PL1a.

[0050] The second power line PL2 may include a first portion PL2a oriented in a direction opposite to the first direction DR1 from the display area DA and extending in a second direction DR2, and a second portion PL2b connected to the first portion PL2a and extending in a direction opposite to the first direction. The second portion PL2b may be connected to a second power source and may transmit a high power voltage to the first portion PL2a.

[0051] The non-display area PA may include a bending area BA. Some of the components of the display device 100 may be bent in the bending area BA. For example, a portion of the second portion PL1b of the first power line PL1 and a portion of the second portion PL2b of the second power line PL2 may be positioned in the bending area BA and may be bent.

[0052] At least one first dam DM1 may be positioned in the non-display area PA. The first dam DM1 may surround the display area DA (eg, in a plan view). For example, the first dam DM1 may include one dam or two or more dams spaced apart from each other. That is, the first dam DM1 may include at least one dam.

[0053] The second dam DM2 may be positioned in the non-display area PA. The second dam DM2 may be spaced apart from the first dam DM1 and may surround the first dam DM1. In addition, the second dam DM2 may be closer to the edge of the non-display area PA than the first dam DM1. For example, a portion of the second dam DM2 may be positioned in the bending area BA. Therefore, a portion of the second dam DM2 may be bent in the bending area BA.

[0054] The first dam DM1 may block an organic substance of an organic encapsulation layer forming an encapsulation layer for sealing the display area DA from flowing out of the first dam DM1. The second dam DM2 may prevent or reduce an inorganic encapsulation layer of the encapsulation layer from being formed outside the second dam DM2.

[0055] Figure 2 is a circuit diagram showing a pixel according to one or more embodiments of the present disclosure. For example, Figure 2 It can be shown Figure 1 One of the pixels PX in.

[0056] Reference Figure 2 , the pixel PX according to one or more embodiments of the present disclosure may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor CAP, and a light emitting element EL.

[0057] The first transistor T1 may be connected between the first node N1 and the second node N2. The first transistor T1 may include a source electrode (eg, Figure 3 ), a drain electrode connected to the second node N2 (eg, Figure 3 The drain electrode DE in the middle) and the gate electrode connected to the third node N3 (eg, Figure 3 The gate electrode GE in the circuit).

[0058] The second transistor T2 may be connected between the data line and the first node N1. The second transistor T2 may include a source electrode for receiving the data voltage DV, a drain electrode connected to the first node N1, and a gate electrode for receiving the first gate signal GS1.

[0059] The third transistor T3 may be connected between the second node N2 and the third node N3. The third transistor T3 may include a source electrode connected to the third node N3, a drain electrode connected to the second node N2, and a gate electrode for receiving the first gate signal GS1.

[0060] The fourth transistor T4 may be connected between the initialization voltage line and the third node N3. The fourth transistor T4 may include a source electrode for receiving the initialization voltage VINT, a drain electrode connected to the third node N3, and a gate electrode for receiving the second gate signal GS2.

[0061] The fifth transistor T5 may be connected between a second power supply providing the high power voltage ELVDD and the first node N1. The fifth transistor T5 may include a source electrode for receiving the high power voltage ELVDD, a drain electrode connected to the first node N1, and a gate electrode for receiving the emission control signal EM.

[0062] The sixth transistor T6 may be connected between the second node N2 and the fourth node N4. The sixth transistor T6 may include a source electrode connected to the second node N2, a drain electrode connected to the fourth node N4, and a gate electrode for receiving the emission control signal EM.

[0063] The seventh transistor T7 may be connected between the initialization voltage line and the fourth node N4. The seventh transistor T7 may include a source electrode for receiving the initialization voltage VINT, a drain electrode connected to the fourth node N4, and a gate electrode for receiving the second gate signal GS2.

[0064] The capacitor CAP may be connected between the second power source and the third node N3. The capacitor CAP may include a first capacitor electrode (eg, Figure 3 A first capacitor electrode CE1 in the embodiment of the present invention and a second capacitor electrode (eg, Figure 3 The second capacitor electrode CE2 in the capacitor.

[0065] The light emitting element EL may be connected between the fourth node N4 and a first power supply providing a low power voltage ELVSS. The low power voltage ELVSS may be lower than the high power voltage ELVDD. The light emitting element EL may include a first electrode connected to the fourth node N4 and a second electrode for receiving the low power voltage ELVSS.

[0066] In one or more embodiments, one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a PMOS transistor. However, the embodiments of the present disclosure are not limited thereto, and in one or more other embodiments, one or more of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be an NMOS (n-channel metal oxide silicon) transistor or a CMOS (complementary metal oxide silicon) transistor.

[0067] exist Figure 2 In the embodiment, one of the pixels PX may be shown as including seven transistors and one capacitor, but the embodiments of the present disclosure are not limited thereto. For example, the pixel PX may include 2 to 6 or 8 or more transistors, and may include two or more capacitors.

[0068] Figure 3 It is along Figure 1 A cross-sectional view taken along line II'.

[0069] Reference Figure 1 , Figure 2 and Figure 3 The display device 100 may include a substrate SUB, a buffer layer 110, an active pattern ACT, a first gate insulating layer 120, a first gate pattern, a second gate insulating layer 130, a second gate pattern, an interlayer insulating layer 140, a first data pattern, a first planarization layer 150, a second data pattern, a second planarization layer 160, a pixel defining layer 170, a light emitting element 180 and an encapsulation layer 190.

[0070] The substrate SUB may be a transparent insulating substrate. For example, the substrate SUB may include glass, quartz, plastic, etc. These may be used alone or in combination with each other.

[0071] The buffer layer 110 may be positioned on the substrate SUB. The buffer layer 110 may prevent or reduce diffusion of impurities from the substrate SUB to the active pattern ACT.

[0072] The buffer layer 110 may include an inorganic insulating material. The inorganic insulating material may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), etc. These may be used alone or in combination.

[0073] The active pattern ACT may be positioned on the buffer layer 110. The active pattern ACT may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. The active pattern ACT may include a source region SR and a drain region DR doped with impurities and a channel region CR between the source region SR and the drain region DR.

[0074] The first gate insulating layer 120 may be positioned on the buffer layer 110. The first gate insulating layer 120 may cover the active pattern ACT on the buffer layer 110. For example, the first gate insulating layer 120 may have a substantially uniform thickness along the contour of the active pattern ACT. Alternatively, the first gate insulating layer 120 may fully cover the active pattern ACT and may have a substantially flat upper surface without forming a step around the active pattern ACT.

[0075] The first gate insulating layer 120 may include an inorganic insulating material. The inorganic insulating material may include silicon nitride, silicon oxide, silicon oxynitride, etc. These may be used alone or in combination.

[0076] The first gate pattern may be positioned on the first gate insulating layer 120. The first gate pattern may include a gate electrode GE and a first capacitor electrode CE1. The gate electrode GE may overlap the channel region CR of the active pattern ACT.

[0077] The first gate pattern may include metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive material, etc. These may be used alone or in combination. For example, the first gate pattern may include molybdenum.

[0078] The second gate insulating layer 130 may be positioned on the first gate insulating layer 120. The second gate insulating layer 130 may cover the first gate pattern on the first gate insulating layer 120. For example, the second gate insulating layer 130 may have a substantially uniform thickness along the contour of the first gate pattern. Alternatively, the second gate insulating layer 130 may fully cover the first gate pattern and may have a substantially flat upper surface without forming a step around the first gate pattern.

[0079] The second gate insulating layer 130 may include an inorganic insulating material. The inorganic insulating material may include silicon nitride, silicon oxide, silicon oxynitride, etc. These may be used alone or in combination.

[0080] The second gate pattern may be positioned on the second gate insulating layer 130. The second gate pattern may include a second capacitor electrode CE2 and an initialization voltage line. The second capacitor electrode CE2 may overlap the first capacitor electrode CE1.

[0081] The second gate pattern may include metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive material, etc. These may be used alone or in combination. For example, the second gate pattern may include molybdenum (Mo).

[0082] Therefore, the second capacitor electrode CE2 may form a capacitor CAP together with the first capacitor electrode CE1.

[0083] The interlayer insulating layer 140 may be positioned on the second gate insulating layer 130. The interlayer insulating layer 140 may cover the second gate pattern on the second gate insulating layer 130. For example, the interlayer insulating layer 140 may have a substantially uniform thickness along the contour of the second gate pattern. Alternatively, the interlayer insulating layer 140 may fully cover the second gate pattern and may have a substantially flat upper surface without forming a step around the second gate pattern.

[0084] The interlayer insulating layer 140 may include an inorganic insulating material. The inorganic insulating material may include silicon nitride, silicon oxide, silicon oxynitride, etc. These may be used alone or in combination.

[0085] The first data pattern may be positioned on the interlayer insulating layer 140. The first data pattern may include a source electrode SE and a drain electrode DE. The source electrode SE and the drain electrode DE may be connected to the source region SR and the drain region DR of the active pattern ACT, respectively.

[0086] The first data pattern may include metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive material, etc. These may be used alone or in combination. For example, the first data pattern may include aluminum and titanium.

[0087] Thus, the active pattern ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE may form a transistor. For example, the transistor may be connected to Figure 3 Corresponding to the sixth transistor T6 in.

[0088] The first planarization layer 150 may be disposed on the interlayer insulating layer 140. The first planarization layer 150 may cover the first data pattern on the interlayer insulating layer 140. For example, the first planarization layer 150 may not generate a step around the first data pattern and may have a substantially flat top surface. The first planarization layer 150 may include an organic insulating material such as polyimide. However, embodiments of the present disclosure may not be limited thereto.

[0089] The second data pattern may be positioned on the first planarization layer 150. The second data pattern may include a connection electrode CE and a data line. The connection electrode CE may be connected to the drain electrode DE or to the source electrode SE.

[0090] The second data pattern may include metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive material, etc. These may be used alone or in combination. For example, the second data pattern may include aluminum and titanium.

[0091] The second planarization layer 160 may be positioned on the first planarization layer 150. The second planarization layer 160 may cover the second data pattern on the first planarization layer 150. For example, the second planarization layer 160 may not generate a step around the second data pattern and may have a substantially flat top surface. The second planarization layer 160 may include an organic insulating material such as polyimide.

[0092] The light emitting element 180 may include a first electrode 181 , a light emitting layer 182 , and a second electrode 183 .

[0093] The first electrode 181 may be disposed on the second planarization layer 160. The first electrode 181 may be connected to the connection electrode CE. The first electrode 181 may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, etc. These may be used alone or in combination. For example, the first electrode 181 may include silver and indium tin oxide (ITO).

[0094] The pixel defining layer 170 may be positioned on the second planarization layer 160. The pixel defining layer 170 may partially cover the first electrode 181 on the second planarization layer 160. In addition, an opening exposing at least a portion of the first electrode 181 may be defined in the pixel defining layer 170. For example, the opening of the pixel defining layer 170 may expose a central portion of the first electrode 181, and the pixel defining layer 170 may cover an edge of the first electrode 181. The pixel defining layer 170 may include an organic insulating material such as polyimide.

[0095] The light-emitting layer 182 may be positioned on the first electrode 181 exposed through the opening of the pixel defining layer 170. For example, the light-emitting layer 182 may include an organic light-emitting material and quantum dots. For example, the organic light-emitting material may include a low molecular weight organic compound or a high molecular weight organic compound. The second electrode 183 may be positioned on the light-emitting layer 182. In addition, the second electrode 183 may be positioned on the pixel defining layer 170. The second electrode 183 may include a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a transparent conductive material, etc. For example, the second electrode 183 may include aluminum, platinum, silver, magnesium, gold, chromium, tungsten, titanium, etc. These may be used alone or in combination.

[0096] The encapsulation layer 190 may cover the light emitting element 180. The encapsulation layer 190 may seal the display area DA, and may protect the light emitting element 180 from external impurities.

[0097] The encapsulation layer 190 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation layer 190 may include a first inorganic encapsulation layer 191, a second inorganic encapsulation layer 193 positioned on (eg, above) the first inorganic encapsulation layer 191, and an organic encapsulation layer 192 between the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193.

[0098] The first inorganic encapsulating layer 191 may be positioned on the second electrode 183. The first inorganic encapsulating layer 191 may have a substantially uniform thickness along a contour of the second electrode 183.

[0099] The organic encapsulating layer 192 may be positioned on the first inorganic encapsulating layer 191. The organic encapsulating layer 192 may not generate a step around the first inorganic encapsulating layer 191, and may have a substantially flat upper surface.

[0100] The second inorganic encapsulating layer 193 may be positioned on the organic encapsulating layer 192. The second inorganic encapsulating layer 193 may have a substantially uniform thickness and a substantially flat upper surface.

[0101] Figure 4 According to one or more embodiments of the present disclosure Figure 1 An enlarged plan view of area "A". Figure 5 It is shown along Figure 4 A cross-sectional view of an example of a cross-section taken along line II-II'. Figure 6 It is shown along Figure 4 A cross-sectional view of an example of a cross-section taken along line III-III'.

[0102] Reference Figure 1 , Figure 4 and Figure 5 The display device 100 may include a substrate SUB, a buffer layer 110, a first gate insulating layer 120, a second gate insulating layer 130, a first fan-out line FL1, a second fan-out line FL2, an interlayer insulating layer 140, a first power line PL1, a second power line PL2, a blocking pattern BP, a first dam DM1, a second dam DM2 and an encapsulation layer 190.

[0103] The buffer layer 110 may be positioned on the substrate SUB. The first gate insulating layer 120 may be positioned on the buffer layer 110. The second gate insulating layer 130 may be positioned on the first gate insulating layer 120.

[0104] The first fan-out line FL1 and the first gate pattern may be positioned at the same layer and may include the same material. For example, the first fan-out line FL1 and the first gate pattern may be formed by the same process. In addition, the second fan-out line FL2 and the second gate pattern may be positioned at the same layer and may include the same material. For example, the second fan-out line FL2 and the second gate pattern may be formed by the same process.

[0105] Each of the first fan-out line FL1 and the second fan-out line FL2 may extend in a first oblique direction between the first direction DR1 and a direction opposite to the second direction DR2. In addition, in a plan view, the first fan-out line FL1 and the second fan-out line FL2 may not overlap each other. For example, the first fan-out line FL1 and the second fan-out line FL2 adjacent to each other may be arranged to be spaced apart from each other in a second oblique direction perpendicular to the first oblique direction.

[0106] like Figure 5 As shown in FIG. 1 , the interlayer insulating layer 140 may be positioned on the second gate insulating layer 130 . The 1-1th dam DM1 - 1 and the 1-2th dam DM1 - 2 may be positioned on the interlayer insulating layer 140 .

[0107] The insulating structure may be defined as a structure including a buffer layer 110, a first gate insulating layer 120, a second gate insulating layer 130, and an interlayer insulating layer 140. The insulating structure may include a first area IA1 and a second area IA2.

[0108] An opening 155 exposing at least a portion of the upper surface of the substrate SUB may be defined in the insulating structure. The first area IA1 may be an area located in the first direction DR1 from the opening 155. In addition, the second area IA2 may be an area located in a direction opposite to the first direction DR1 from the opening 155.

[0109] The first power line PL1 and the second power line PL2 may be positioned on the interlayer insulating layer 140. Each of the first power line PL1 and the second power line PL2 may be positioned at the same layer as the first data pattern or the second data pattern, and may include the same material. In one or more embodiments, the first power line PL1 and the second power line PL2 may be positioned at the same layer as the second data pattern, and may include the same material.

[0110] The first dam DM1 may include a 1-1th dam DM1-1 and a 1-2th dam DM1-2. Figure 4 and Figure 5 It is shown that the first dam DM1 includes two dams, but the embodiments of the present disclosure may not be limited thereto. For example, the first dam DM1 may include at least one dam.

[0111] The 1-1st dam DM1-1 may surround the display area DA. The 1-2nd dam DM1-2 may be spaced apart from the 1-1st dam DM1-1, and may surround the 1-1st dam DM1-1.

[0112] The second dam DM2 may be spaced apart from the first dam DM1 and may surround the first dam DM1 on a plane. For example, the second dam DM2 may be spaced apart from the 1-2 dam DM1-2 and may surround the 1-2 dam DM1-2.

[0113] The 1-1st dam DM1-1 may include a first sublayer 161 and a second sublayer 171 positioned on the first sublayer 161. The first sublayer 161 and the second planarization layer 160 may include substantially the same material. The second sublayer 171 and the pixel defining layer 170 may include substantially the same material.

[0114] The 1-2 dam DM1-2 may include a first sublayer 152, a second sublayer 162 positioned on the first sublayer 152, and a third sublayer 172 positioned on the second sublayer 162. The first sublayer 152 and the first planarization layer 150 may include substantially the same material. The second sublayer 162 and the second planarization layer 160 may include substantially the same material. The third sublayer 172 and the pixel defining layer 170 may include substantially the same material.

[0115] The second dam DM2 may include a first organic layer 153 , a second organic layer 163 positioned on the first organic layer 153 , a third organic layer 173 positioned on the second organic layer 163 , and a fourth organic layer 174 positioned on the third organic layer 173 .

[0116] The first organic layer 153 may include substantially the same material as the first planarization layer 150. In one or more embodiments, the first organic layer 153 may fill the opening 155 of the insulating structure. For example, the first organic layer 153 may contact a portion of the upper surface of the substrate SUB exposed by the opening 155, and may extend to a portion of the upper surface of the interlayer insulating layer 140.

[0117] The second organic layer 163 may include substantially the same material as the second planarization layer 160. The second organic layer 163 may be spaced apart from the first side 154 of the first organic layer 153 facing the first direction DR1. For example, the second organic layer 163 may not contact the first side 154 of the first organic layer 153, and may not contact a portion of the interlayer insulating layer 140 adjacent to the first area IA1. In one or more embodiments, the first side 154 of the first organic layer 153 may have a stepped shape together with a side of the second organic layer 163 facing the first dam DM1.

[0118] An edge of the second dam DM2 facing the first dam DM1 may contact the first area IA1 through the first organic layer 153. In this case, the second organic layer 163 of the second dam DM2 may not contact the first area IA1.

[0119] The second organic layer 163 may contact a second side (eg, Figure 5 For example, the second organic layer 163 may cover the second side of the first organic layer 153 and may contact the second area IA2.

[0120] The third organic layer 173 may contact one side of the second organic layer 163 and may not contact the other side. For example, the third organic layer 173 may not contact the side of the second organic layer 163 facing the first dam DM1. In addition, the third organic layer 173 may contact the other side of the second organic layer 163 facing the direction opposite to the first direction DR1.

[0121] The third organic layer 173 may include substantially the same material as the pixel defining layer 170. In addition, the fourth organic layer 174 may include substantially the same material as the third organic layer 173. For example, the fourth organic layer 174 may be formed by the same process as the third organic layer 173, or may be formed by a separate (individual) process from the third organic layer 173.

[0122] The encapsulation layer 190 may include a first inorganic encapsulation layer 191, an organic encapsulation layer 192, and a second inorganic encapsulation layer 193. The encapsulation layer 190 may be positioned on the interlayer insulating layer 140. The encapsulation layer 190 may cover at least a portion of the first dam DM1 and the second dam DM2 on the interlayer insulating layer 140.

[0123] The edge of the organic encapsulation layer 192 may be positioned on the first dam DM1. For example, the edge of the organic encapsulation layer 192 may be positioned to overlap with the edge of the first dam DM1 facing the first direction DR1. For example, the edge of the organic encapsulation layer 192 may be closer to the display area DA than the edge of the first dam DM1 adjacent to the second dam DM2. Therefore, the first dam DM1 may prevent or reduce the organic material of the organic encapsulation layer 192 from overflowing to the outside of the first dam DM1.

[0124] The edge of the encapsulation layer 190 may be positioned on the second dam DM2. For example, the edge of the first inorganic encapsulation layer 191 and the edge of the second inorganic encapsulation layer 193 may be positioned on the second dam DM2 (e.g., positioned on a portion of the second dam DM2). Therefore, the second dam DM2 may prevent or reduce the first inorganic encapsulation layer 191 and the second inorganic encapsulation layer 193 from being formed in an area outside the second dam DM2 (e.g., an area of ​​the second dam DM2 facing a direction opposite to the first direction DR1).

[0125] Because the edge of the organic encapsulation layer 192 is positioned on or adjacent to the first dam DM1, the first and second inorganic encapsulation layers 191 and 193 of the encapsulation layer 190 may be positioned between the first and second dams DM1 and DM2. For example, the organic encapsulation layer 192 of the encapsulation layer 190 may not be positioned between the first and second dams DM1 and DM2.

[0126] In one or more embodiments, the first inorganic encapsulating layer 191 may contact the first organic layer 153 and the second organic layer 163. In addition, the first inorganic encapsulating layer 191 may overlap the first area IA1. For example, the first inorganic encapsulating layer 191 may contact the first side 154 of the first organic layer 153 facing the first dam DM1 and the side of the second organic layer 163 facing the first dam DM1. Figure 4 and Figure 6 , the blocking pattern BP may include a first blocking pattern BP1 and a second blocking pattern BP2.

[0127] The first barrier pattern BP1 may be connected to the first power line PL1. In addition, the second barrier pattern BP2 may be connected to the second power line PL2.

[0128] In one or more embodiments, the second barrier pattern BP2 and the second power line PL2 may be positioned at the same layer and may include the same material. For example, the second barrier pattern BP2 and the second power line PL2 may be formed by the same process. The second barrier pattern BP2 may extend between the first organic layer 153 and the second organic layer 163 along the first side 154 of the first organic layer 153.

[0129] In one or more embodiments, the first barrier pattern BP1 and the first power line PL1 may be positioned at the same layer. That is, the first barrier pattern BP1 and the first power line PL1 may be formed by the same process. For example, the first barrier pattern BP1 may be positioned on the interlayer insulating layer 140 and may contact the lower portion of the first organic layer 153. For example, the first barrier pattern BP1 may be positioned Figure 6 . ...

[0130] In one or more embodiments, the first barrier pattern BP1 and the first data pattern may include substantially the same material. For example, the first barrier pattern BP1 may include aluminum and titanium.

[0131] In one or more embodiments, the second barrier pattern BP2 and the second data pattern may include substantially the same material. For example, the second barrier pattern BP2 may include aluminum and titanium.

[0132] If the first barrier pattern BP1 is not connected to the first power line PL1, static electricity may be generated in the first barrier pattern BP1, and the display device (eg, Figure 1The display device 100 in the embodiment of the present invention may be damaged. However, since the first barrier pattern BP1 is connected to the first power line PL1 for transmitting the low power voltage ELVSS, static electricity is not generated in the barrier pattern BP. In addition, since the second barrier pattern BP2 is connected to the second power line PL2 for transmitting the high power voltage ELVDD, static electricity may not be generated and may be substantially the same as the first barrier pattern BP1 described above.

[0133] The second barrier pattern BP2 may be positioned on the interlayer insulating layer 140, and may extend along the first side 154 of the first organic layer 153 to a point between the first organic layer 153 and the second organic layer 163. In this case, the second barrier pattern BP2 may overlap the first area IA1 of the insulating structure.

[0134] Despite Figure 6 Only the second barrier pattern BP2 is shown in FIG. 1 , but the position of the first barrier pattern BP1 may be substantially the same as that of the second barrier pattern BP2. For example, in one or more embodiments, a cross-sectional view cut along an imaginary line passing through both the first power line PL1 and the first barrier pattern BP1 may be the same as that of FIG. Figure 6 The cross-sectional views have substantially the same position and structure.

[0135] Figure 7 It is shown Figure 5 A cross-sectional view of another example in FIG. Figure 7 is based on the display device (e.g. Figure 1 One or more other embodiments of the display device 100) are provided along Figure 4 A cross-sectional view taken along line II-II'. Figure 8 It is shown Figure 6 A cross-sectional view of another example in FIG.

[0136] In the following, the references will be omitted or simplified. Figure 5 and Figure 6 The components of the display device 100 are described in overlapping manner.

[0137] Reference Figure 7 and Figure 8 , the first inorganic encapsulation layer 191' and the second inorganic encapsulation layer 193' may be positioned on the first organic layer 153. In one or more embodiments, the first inorganic encapsulation layer 191' and the second inorganic encapsulation layer 193' may be spaced apart from the second organic layer 163. For example, the first inorganic encapsulation layer 191' and the second inorganic encapsulation layer 193' may contact the first organic layer 153 along the first side 154 of the first organic layer 153 without contacting the second organic layer 163. For example, the portion where the first inorganic encapsulation layer 191' and the second inorganic encapsulation layer 193' contact the second dam DM2 may be the first organic layer 153.

[0138] As described above, a portion of the second dam DM2 may be positioned in the bending area BA. The encapsulation layer 190 may not cover an upper portion of each of the first organic layer 153 and the second organic layer 163 within the bending area BA. Therefore, a moisture inflow path may be generated in a portion where the encapsulation layer 190 does not cover an upper portion of each of the first organic layer 153 and the second organic layer 163.

[0139] Meanwhile, a portion of the interlayer insulating layer 140 overlapping the edge of the first organic layer 153 facing the first dam DM1 may be damaged by the etching process. In this case, since the second organic layer 163 does not cover the first side 154 of the first organic layer 153, the first organic layer 153 overlapping the second organic layer 163 may not cover the damaged portion of the interlayer insulating layer 140.

[0140] Therefore, a portion of the interlayer insulating layer 140 overlapping the second organic layer 163 may not be damaged, and thus even if moisture flows through the inflow path from the outside of the second dam DM2 , corrosion of the fan-out line FL may be prevented or reduced.

[0141] In addition, a portion of the interlayer insulating layer 140 overlapping the second organic layer 163 may not be damaged, and thus stress applied to the interlayer insulating layer 140 covering the fan-out line FL may be reduced. Therefore, cracks occurring inside the display device 100 may be prevented or reduced.

[0142] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 It shows the manufacturing Figure 5 and Figure 6 A cross-sectional view of a method of displaying a device.

[0143] Reference Fig. 9 , can form an insulating structure (e.g., Figure 6 The buffer layer 110, the first gate insulating layer 120, the second gate insulating layer 130 and the interlayer insulating layer 140 in the insulating structure), the first fan-out line FL1 and the second fan-out line FL2. In addition, an opening (eg, Figure 5 The opening 155 in the substrate SUB is formed so that at least a portion of the upper surface of the substrate SUB can be exposed.

[0144] Reference Fig.10, a first organic layer 153 may be formed in the opening 155. In addition, a first sublayer 161 of the 1-1st dam DM1-1 and a first sublayer 152 of the 1-2nd dam DM1-2 may be formed on the insulating structure. Then, a preliminary power line PPL may be formed on the first organic layer 153, the first sublayer 161 of the 1-1st dam DM1-1, the first sublayer 152 of the 1-2nd dam DM1-2, and the interlayer insulating layer 140. For example, the preliminary power line PPL may contact the first organic layer 153, the first sublayer 161 of the 1-1st dam DM1-1, the first sublayer 152 of the 1-2nd dam DM1-2, and the interlayer insulating layer 140.

[0145] Reference Fig.11 , a photosensitive layer PR may be formed on a portion of the preliminary power line PPL adjacent to the first sublayer 161 of the 1-1th dam DM1-1. A portion of the preliminary power line PPL not positioned under the photosensitive layer PR may be removed through an etching process.

[0146] Reference Fig.12 , a power line PL may be formed on the interlayer insulating layer 140 by an etching process. The power line PL may be a portion of the initial power line PPL that is not removed by the etching process. For example, the power line PL may cover a portion of the first sublayer 161 of the 1-1 dam DM1-1. In addition, the interlayer insulating layer 140 may be thinner than the first sublayer 161 of the 1-1 dam DM1-1 by an etching process. Fig. 9 The interlayer insulating layer 140 is thin.

[0147] In one or more embodiments, the power line PL may cover the first sublayer 152 of the 1-2 dam DM1-2 along the first sublayer 161 of the 1-1 dam DM1-1. Figure 5 , Figure 6 , Figure 7 and Figure 8 As shown in FIG. 1 , the power line PL may cover a portion of the first sublayer 152 of the 1-2 th dam DM1 - 2 .

[0148] The power line PL can be Figure 4 The first power line PL1 or the second power line PL2 in.

[0149] Reference Fig.13 , a second organic layer 163 may be formed on the first organic layer 153. In addition, a second sublayer 171 of the 1-1st dam DM1-1 and a second sublayer 162 of the 1-2nd dam DM1-2 may be formed. Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13After the manufacturing process of FIG. 1 , the first inorganic encapsulating layer 191 and the second inorganic encapsulating layer 193 may cover the first organic layer 153 , a portion of the second organic layer 163 , the first dam DM1 , and the interlayer insulating layer 140 .

[0150] Therefore, it is possible to produce Figure 5 The display device 100 in FIG.

[0151] As described above, through the etching process, the upper portion of the interlayer insulating layer 140 adjacent to the first fan-out line FL1 may be thinned, and a portion of the interlayer insulating layer 140 may be damaged. According to the manufacturing method of the display device 100, the damaged portion of the interlayer insulating layer 140 may not be covered by the second organic layer 163. Therefore, according to the etching process, moisture does not flow into the damaged portion of the interlayer insulating layer 140 and the upper portion of the interlayer insulating layer 140 adjacent to the damaged portion, and corrosion in the first fan-out line FL1 and the second fan-out line FL2 may be prevented or reduced.

[0152] Reference Fig.14 , Fig.15 and Fig.16 , Fig.14 , Fig.15 and Fig.16 1 is a cross-sectional view showing a process of forming a region including a blocking pattern BP. Fig. 9 , Fig.10 , Fig.11 , Fig.12 and Fig.13 A method of manufacturing an assembly of an overlay is described.

[0153] Reference Fig.14 ,exist Fig.11 In the process of forming the first dam DM1, the photosensitive layer PR may be formed in a region adjacent to an edge of the second dam DM2 facing the first dam DM1. Portions of the preliminary power lines PPL not positioned under the photosensitive layer PR may be removed through an etching process.

[0154] Reference Fig.15 , a power line PL and a blocking pattern BP may be formed on the interlayer insulating layer 140 through an etching process. For example, the power line PL may cover the first sublayer 161 of the 1-1th dam DM1-1. In addition, the blocking pattern BP may cover a portion of the second dam DM2.

[0155] The power line PL and the blocking pattern BP may include the same material. For example, the power line PL and the blocking pattern BP may be formed by the same process. In addition, the blocking pattern BP may be Figure 4 One of the first and second barrier patterns BP1 and BP2 in the embodiment.

[0156] In one or more embodiments, the power line PL may cover the first sublayer 152 of the 1-2 th dam DM1 - 2 along the first sublayer 161 of the 1-1 th dam DM1 - 1 .

[0157] Reference Fig.16 , the second organic layer 163 may be positioned on the blocking pattern BP. For example, the blocking pattern BP may be positioned between the first organic layer 153 and the second organic layer 163 along the first side 154 of the first organic layer 153 facing the first dam DM1.

[0158] exist Fig.14 , Fig.15 and Fig.16 After the manufacturing process of FIG. 1 , a portion of the first organic layer 153 , a portion of the second organic layer 163 , the blocking pattern BP, the first dam DM1 , and the interlayer insulating layer 140 may be covered by the first and second inorganic encapsulating layers 191 and 193 .

[0159] Therefore, it is possible to produce Figure 6 The display device 100 in FIG.

[0160] Fig.17 According to one or more other embodiments of the present disclosure Figure 1 An enlarged plan view of area "A". Fig.18 It is along Fig.17 A cross-sectional view taken along line III-III'.

[0161] In the following, the references will be omitted or simplified. Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The components of the display device 100 are described in overlapping manner.

[0162] Reference Fig.17 and Fig.18 The first barrier pattern BP1' may be connected to the first power line PL1 and may be located at a different layer from the first power line PL1. In addition, the second barrier pattern BP2' may be connected to the second power line PL2 and may be located at a different layer from the second power line PL2.

[0163] For example, Fig.18 As shown in , the second barrier pattern BP2' and the first power line PL1 may be positioned at the same layer and may be connected to the second power line PL2. For example, the second barrier pattern BP2' may contact the lower portion of the first organic layer 153 along the interlayer insulating layer 140 from the edge of the second dam DM2 facing the first dam DM1. In this case, the second barrier pattern BP2' may not contact the second organic layer 163.

[0164] In one or more embodiments, the first barrier pattern BP1′ and the second power line PL2 may be positioned at the same layer and may contact the first and second organic layers 153 and 163. For example, the first barrier pattern BP1′ may contact the second organic layer 163 along the first side 154 of the first organic layer 153.

[0165] The display device according to the embodiment may be applied to a display device included in a computer, a notebook, a mobile phone, a smart phone, a smart pad, a PMP, a PDA, an MP3 player, and the like.

[0166] Although the display device according to the embodiment has been described with reference to the accompanying drawings, the illustrated embodiment is an example and may be modified and changed by a person skilled in the art without departing from the technical spirit described in the claims and their functional equivalents to be included herein.

Claims

1. A display device, characterized in that: The display device comprises: A substrate, comprising a display area and a non-display area adjacent to the display area; a first dam disposed in the non-display area over the substrate; and A second dam is above the substrate in the non-display area and is closer to an edge of the non-display area than the first dam, and includes: a first organic layer above the substrate; and a second organic layer above the first organic layer and spaced apart from a first side of the first organic layer facing the first dam.

2. The display device according to claim 1, characterized in that The first side of the first organic layer and one side of the second organic layer facing the first dam have a step shape.

3. The display device according to claim 1, characterized in that The second organic layer contacts a second side of the first organic layer opposite the first side.

4. The display device according to claim 1, characterized in that The display device further includes an insulating structure between the substrate and the first dam, and including: a first region contacting the first organic layer and spaced apart from the second organic layer; and a second region contacting the first organic layer and the second organic layer, and wherein an opening is defined in the insulating structure to expose at least a portion of the upper surface of the substrate, and Wherein, the first organic layer fills the opening.

5. The display device according to claim 1, characterized in that The display device further includes a blocking pattern between the first organic layer and the second organic layer and protruding from the second dam toward the first dam.

6. The display device according to claim 5, characterized in that: The barrier pattern is at an edge of the second dam and extends along the first side of the first organic layer.

7. The display device according to claim 5, characterized in that: The display device further includes: a first power line on the substrate and overlapping the non-display area; and a second power line, on the substrate, overlapping the non-display area and spaced apart from the first power line, and Wherein, the blocking pattern comprises: a first blocking pattern connected to the first power line and at the same layer as the first power line; and The second blocking pattern is connected to the second power line and is in the same layer as the second power line.

8. The display device according to claim 5, characterized in that The display device further includes: a first power line on the substrate and overlapping the non-display area; and a second power line, on the substrate, overlapping the non-display area and spaced apart from the first power line, and Wherein, the blocking pattern comprises: a first blocking pattern connected to the first power line and on a different layer from the first power line; and The second blocking pattern is connected to the second power line and is on a different layer from the second power line.

9. The display device according to claim 1, characterized in that: The display device further includes: a first inorganic encapsulation layer on the first dam and extending to the first side of the first organic layer; and A second inorganic encapsulating layer is on the first inorganic encapsulating layer, and wherein the first inorganic encapsulating layer contacts the second organic layer.

10. The display device according to claim 1, characterized in that: The display device further includes: a first inorganic encapsulation layer on the first dam and extending to the first side of the first organic layer; and A second inorganic encapsulating layer is on the first inorganic encapsulating layer, and wherein the first inorganic encapsulating layer is spaced apart from the second organic layer.

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