Display device

Abstract

The display device may include a substrate, an active pattern, a first conductive layer, a second conductive layer, a shielding pattern, and a light emitting element. The active pattern may be disposed on the substrate. The active pattern may include a first region, a second region, a third region, a first channel region, and a second channel region. The first conductive layer may be disposed on the active pattern. The first conductive layer may include a first gate electrode overlapping each of the first channel region and the second channel region. The second conductive layer may be disposed on the first conductive layer. The second conductive layer may include a first memory electrode overlapping a second region of the active pattern. The shielding pattern may be disposed on the second conductive layer. The shield pattern may overlap the first gate electrode and the first memory electrode and include a black substance. The light-emitting element may be disposed on the shielding pattern. According to the invention, the low-frequency characteristic of the display device can be improved.

Description

[0001] This application is a divisional application with an application date of October 18, 2023, application number 2023227921508, and invention name “Display Device”. Technical Field

[0002] The utility model relates to a display device. More specifically, the utility model relates to a display device including an oxide semiconductor. Background Art

[0003] Recently, there has been an increasing demand for technology for reducing power consumption of display devices, and thus a low-frequency driving method for driving a display device at a relatively low frequency has been studied.

[0004] In the case of a low frequency driving method, the leakage current of the pixel circuit may increase, thereby causing a difference in pixel brightness between consecutive frames. Utility Model Content

[0005] The utility model aims to provide a display device with improved low-frequency characteristics.

[0006] However, the purpose of the present invention is not limited to such a purpose, and various extensions can be made without departing from the scope of the concept and field of the present invention.

[0007] A display device according to an embodiment of the present utility model may include a substrate, an active pattern, a first conductive layer, a second conductive layer, a shielding pattern, and a light-emitting element. The active pattern may be configured on the substrate. The active pattern may include a first region, a second region, a third region, a first channel region, and a second channel region. The first conductive layer may be configured on the active pattern. The first conductive layer may include a first gate electrode overlapping each of the first channel region and the second channel region. The second conductive layer may be configured on the first conductive layer. The second conductive layer may include a first storage electrode overlapping the second region of the active pattern. The shielding pattern may be configured on the second conductive layer. The shielding pattern may overlap the first gate electrode and the first storage electrode and include a black substance. The light-emitting element may be configured on the shielding pattern.

[0008] In one embodiment, the display device may further include an interlayer insulating layer and a first via insulating layer. The interlayer insulating layer may be disposed on the second conductive layer. The first via insulating layer may be disposed between the interlayer insulating layer and the light emitting element.

[0009] In one embodiment, the first via insulating layer may cover the shielding pattern.

[0010] In one embodiment, the display device may further define a via hole penetrating the first via insulating layer. The shielding pattern may include: a first shielding pattern disposed adjacent to the via hole; and a second shielding pattern disposed apart from the first shielding pattern and having a different planar shape from the first shielding pattern.

[0011] In one embodiment, the display device may further include an interlayer insulating layer, a first via insulating layer, and a second via insulating layer. The interlayer insulating layer may be disposed on the second conductive layer. The first via insulating layer may be disposed on the interlayer insulating layer. The second via insulating layer may be disposed between the first via insulating layer and the light emitting element. The second via insulating layer may cover the shielding pattern.

[0012] In one embodiment, the display device may further define a via hole penetrating the second via insulating layer. The shielding pattern may include: a first shielding pattern disposed adjacent to the via hole; and a second shielding pattern disposed apart from the first shielding pattern and having a different planar shape from the first shielding pattern.

[0013] In one embodiment, the display device further includes an interlayer insulating layer, a first via insulating layer, a second via insulating layer, and a third via insulating layer. The interlayer insulating layer may be disposed on the second conductive layer. The first via insulating layer may be disposed on the interlayer insulating layer. The second via insulating layer may be disposed on the first via insulating layer. The third via insulating layer may be disposed between the second via insulating layer and the light emitting element. The third via insulating layer may cover the shielding pattern.

[0014] In one embodiment, the display device may further define a via hole penetrating the third via insulating layer. The shielding pattern may include: a first shielding pattern disposed adjacent to the via hole; and a second shielding pattern disposed apart from the first shielding pattern and having a different planar shape from the first shielding pattern.

[0015] In one embodiment, the first gate electrode may constitute a driving initialization transistor together with the first region, the second region, the third region, the first channel region, and the second channel region of the active pattern.

[0016] In one embodiment, the active pattern may further include a fourth region, a fifth region, a third channel region, and a fourth channel region.

[0017] In one embodiment, the first conductive layer may be disposed on the active pattern. The first conductive layer may further include a second gate electrode. The shielding pattern may overlap with the second gate electrode.

[0018] In one embodiment, the second conductive layer may be disposed on the first conductive layer. The second conductive layer may further include a second storage electrode overlapping the fourth region. The shielding pattern may overlap the second storage electrode.

[0019] In one embodiment, the second gate electrode may constitute a diode transistor together with the third region, the fourth region, the fifth region, the third channel region, and the fourth channel region of the active pattern.

[0020] A display device according to another embodiment of the utility model may include a substrate, an active pattern, a first conductive layer, a second conductive layer, an electrode pattern, a shielding pattern, and a light emitting element. The active pattern may be arranged on the substrate. The active pattern may include a first region, a second region, a third region, a fourth region, a fifth region, a first channel region, a second channel region, a third channel region, and a fourth channel region. The first conductive layer may be arranged on the active pattern. The first conductive layer may include a first gate electrode overlapping each of the first channel region and the second channel region. The second conductive layer may include a second gate electrode overlapping each of the third channel region and the fourth channel region. The second conductive layer may be arranged on the first conductive layer. The second conductive layer may include a first storage electrode overlapping the second region of the active pattern and a second storage electrode overlapping the fourth region. The shielding pattern may be arranged on the second conductive layer. The electrode pattern may be arranged on the second conductive layer. The electrode pattern may be connected to the third region of the active pattern. The shielding pattern may overlap the first gate electrode, the second gate electrode, the first storage electrode, and the second storage electrode, and contain a black substance. The light emitting element may be disposed on the shielding pattern.

[0021] In one embodiment, the display device may further include an interlayer insulating layer and a first via insulating layer. The interlayer insulating layer may be disposed on the second conductive layer. The first via insulating layer may be disposed between the interlayer insulating layer and the light emitting element.

[0022] In one embodiment, the first via insulating layer may cover the shielding pattern and the electrode pattern. The display device may further define a via that passes through the first via insulating layer. The shielding pattern may include: a first shielding pattern, which is arranged adjacent to the via; and a second shielding pattern, which is arranged apart from the first shielding pattern and has a different planar shape from the first shielding pattern.

[0023] In one embodiment, the display device may further include a second via insulating layer. The second via insulating layer may be arranged between the first via insulating layer and the light emitting element. The second via insulating layer may cover the shielding pattern. The display device may further define a via that passes through the second via insulating layer. The shielding pattern may include: a first shielding pattern, arranged adjacent to the via; and a second shielding pattern, arranged apart from the first shielding pattern, having a planar shape different from that of the first shielding pattern.

[0024] In one embodiment, the display device further includes a second via insulation layer and a third via insulation layer. The second via insulation layer may be arranged on the first via insulation layer. The third via insulation layer may be arranged between the second via insulation layer and the light emitting element. The third via insulation layer may cover the shielding pattern. The display device may further define a via that passes through the third via insulation layer. The shielding pattern may include: a first shielding pattern, arranged adjacent to the via; and a second shielding pattern, arranged apart from the first shielding pattern, having a planar shape different from that of the first shielding pattern.

[0025] In one embodiment, the first gate electrode may constitute a driving initialization transistor together with the first region, the second region, the third region, the first channel region, and the second channel region of the active pattern.

[0026] In one embodiment, the second gate electrode may constitute a diode transistor together with the third region, the fourth region, the fifth region, the third channel region, and the fourth channel region of the active pattern.

[0027] The display device according to an embodiment of the utility model may include a shielding pattern covering the third transistor, the fourth transistor, the first holding capacitor and the second holding capacitor. The shielding pattern may contain a black substance to block light. The display device may improve low-frequency driving characteristics by including the shielding pattern.

[0028] In addition, the shielding pattern included in the display device can be covered by a via layer (e.g., a first via insulating layer, a second via insulating layer, a third via insulating layer, etc.). According to this, the shielding pattern can be prevented from being damaged in subsequent processes (e.g., a contact hole forming process, etc.). By this, the low-frequency driving characteristics of the display device can be improved, and the display device has a strong structure.

[0029] However, the effects of the present invention are not limited to the above-mentioned effects, and various extensions can be made without departing from the scope of the concept and field of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a plan view showing a display device according to an embodiment of the present utility model.

[0031] Figure 2 It is enlarged to show Figure 1 Floor plan of area A.

[0032] Figure 3 is included in Figure 2 Circuit diagram of a sub-pixel in a pixel.

[0033] Figures 4 to 16 Yes means Figure 1 A configuration diagram of a display device.

[0034] Fig.17 It is along Fig.14 Cross-sectional view of line I-I'.

[0035] Figures 18 to 24 It is used to illustrate Figure 1 A cross-sectional view of a method for manufacturing a display device.

[0036] Figure 25 to Figure 26 It is used to illustrate Figure 1 A cross-sectional view of another embodiment of a display device.

[0037] Fig. 27 It is a diagram for explaining the effect of improving the low-frequency driving characteristics of the display device according to the embodiment of the present invention.

[0038] (Explanation of Reference Numerals)

[0039] SUB: Substrate ACT: Active pattern

[0040] CL1: first conductive layer CL2: second conductive layer

[0041] BVIA: Shielded Pattern OLED: Light Emitting Element DETAILED DESCRIPTION

[0042] Hereinafter, the embodiments of the present invention will be described in more detail with reference to the attached drawings. The same reference numerals will be used for the same components in the drawings, and repeated descriptions of the same components will be omitted.

[0043] Figure 1 It is a plan view showing a display device according to an embodiment of the present utility model.

[0044] Reference Figure 1According to an embodiment of the present invention, the display device DD may include a display area DA and a peripheral area PA. The display area DA may be defined as an area that can generate light or adjust the transmittance of light provided from an external light source to display an image. The peripheral area PA may be defined as an area that does not display an image. In addition, the peripheral area PA may surround at least a portion of the display area DA. For example, the peripheral area PA may surround the display area DA as a whole.

[0045] A plurality of pixels PX may be disposed in the display area DA. For example, each of the plurality of pixels PX may include a driving element and a light emitting element.

[0046] The plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2 crossing the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be orthogonal.

[0047] A driving unit for driving the plurality of pixels PX may be disposed in the peripheral area PA. For example, the driving unit may include a data driving unit, a gate driving unit, a light emitting driving unit, a power supply voltage generating unit, a timing controller, etc. The plurality of pixels PX may emit light based on signals transmitted from the driving unit.

[0048] Figure 2 It is enlarged to show Figure 1 Floor plan of area A.

[0049] For example, Figure 2 It is used to describe the Figure 1 FIG. 4 is a diagram of multiple sub-pixels SPX1 , SPX2 , SPX3 , and SPX4 in each of the multiple pixels PX.

[0050] Reference Figure 1 as well as Figure 2 , the plurality of pixels PX may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , a third sub-pixel SPX3 , and a fourth sub-pixel SPX4 .

[0051] The first sub-pixel SPX1 and the second sub-pixel SPX2 may be arranged along the first column C1. The third sub-pixel SPX3 and the fourth sub-pixel SPX4 may be arranged along the second column C2. The second column C2 may be adjacent to the first column C1.

[0052] In addition, the first sub-pixel SPX1 and the third sub-pixel SPX3 may be arranged along the first row R1, the second sub-pixel SPX2 and the fourth sub-pixel SPX4 may be arranged along the second row R2, and the second row R2 may be adjacent to the first row R1.

[0053] In this way, the arrangement of sub-pixels can be repeated to preset rows and columns. For example, the first sub-pixel SPX1 and the second sub-pixel SPX2 can be arranged along odd columns, and the third sub-pixel SPX3 and the fourth sub-pixel SPX4 can be arranged along even columns. In addition, the first sub-pixel SPX1 and the third sub-pixel SPX3 can be arranged along odd rows, and the second sub-pixel SPX2 and the fourth sub-pixel SPX4 can be arranged along even rows.

[0054] Each of the first sub-pixel SPX1, the second sub-pixel SPX2, the third sub-pixel SPX3, and the fourth sub-pixel SPX4 may be connected to an initialization voltage line. The initialization voltage line may include a first initialization voltage line VINT and a second initialization voltage line VAINT. According to the structure in which the first initialization voltage line VINT and the second initialization voltage line VAINT have a separation, color deviation may be improved at low brightness.

[0055] The initialization voltage line may have a mesh structure on a plane. The first initialization voltage line VINT may include a transverse portion VINTa extending along the first direction DR1 and a longitudinal portion VINTb extending along the second direction DR2. The second initialization voltage line VAINT may also include a transverse portion VAINTa extending along the first direction DR1 and a longitudinal portion VAINTb extending along the second direction DR2.

[0056] The initialization voltage lines extending parallel to the first direction DR1 may be alternately arranged along the second direction DR2. For example, each of the first subpixel SPX1 and the third subpixel SPX3 may be connected to the first initialization voltage line VINT. Each of the second subpixel SPX2 and the fourth subpixel SPX4 may be connected to the second initialization voltage line VAINT.

[0057] The initialization voltage line may be electrically connected to the sub-pixel through the vias HOa and HOb. For example, the first sub-pixel SPX1 located in the first row R1 may overlap only with the lateral portion VINTa of the first initialization voltage line VINT. The second initialization voltage line VAINT may be located in the second row R2. Thus, the first sub-pixel SPX1 may not overlap with the lateral portion VAINTa of the second initialization voltage line VAINT. On the other hand, the second sub-pixel SPX2 located in the second row R2 may overlap only with the lateral portion VAINTa of the second initialization voltage line VAINT. Thus, the second sub-pixel SPX2 may not overlap with the lateral portion VINTa of the first initialization voltage line VINT. However, with the formation of the vias HOa and HOb, through the connection wiring, the first sub-pixel SPX1 may receive the transmission of the second initialization voltage through the second initialization voltage line VAINT, and the second sub-pixel SPX2 may receive the transmission of the first initialization voltage through the first initialization voltage line VINT.

[0058] exist Figure 2 In the figure, each of the plurality of pixels PX is shown to have the initialization voltage line, but the present invention is not limited thereto. For example, the initialization voltage line may be shared by each of the plurality of pixels PX and an adjacent pixel.

[0059] Figure 3 is included in Figure 2 Circuit diagram of each sub-pixel in a pixel.

[0060] Reference Figure 1 , Figure 2 as well as Figure 3 The first sub-pixel SPX1 may include a light emitting element OLED and a pixel circuit PXCa. The pixel circuit PXCa may provide a driving current to the light emitting element OLED, and the light emitting element OLED may generate light based on the driving current.

[0061] The light emitting element OLED may be electrically connected to the pixel circuit PXCa. The light emitting element OLED may be electrically connected to the second power supply voltage line ELVSS. The light emitting element OLED may receive the supply of the driving current from the pixel circuit PXCa to generate light. For example, the light emitting element OLED may be an organic light emitting diode.

[0062] The pixel circuit PXCa may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , a seventh transistor T7 , and an eighth transistor T8 .

[0063] The first terminal of the first transistor T1 may be connected to the data voltage line DATA through the second transistor T2 and may be connected to the first power voltage line ELVDD through the fifth transistor T5. The second terminal of the first transistor T1 may be connected to the light emitting element OLED. The gate terminal of the first transistor T1 may be connected to the storage capacitor CST.

[0064] A first terminal of the second transistor T2 may be connected to the data voltage line DATA. A second terminal of the second transistor T2 may be connected to the first terminal of the first transistor T1. A gate terminal of the second transistor T2 may be connected to the first gate signal line GW.

[0065] The third transistor T3 may include a first sub-transistor T3-1 and a second sub-transistor T3-2 connected in series. The first terminal of the first sub-transistor T3-1 may be connected to the second terminal of the second sub-transistor T3-2. The second terminal of the first sub-transistor T3-1 may be connected to the gate terminal of the first transistor T1. The first terminal of the second sub-transistor T3-2 may be connected to the second terminal of the first transistor T1. The gate terminal of the first sub-transistor T3-1 and the gate terminal of the second sub-transistor T3-2 may be connected to the first gate signal line GW, respectively.

[0066] The fourth transistor T4 may include a third sub-transistor T4-1 and a fourth sub-transistor T4-2 connected in series. The first terminal of the third sub-transistor T4-1 may be connected to the second terminal of the fourth sub-transistor T4-2. The second terminal of the third sub-transistor T4-1 may be connected to the gate terminal of the first transistor T1. The first terminal of the fourth sub-transistor T4-2 may be connected to the first initialization voltage line VINT. The gate terminal of the third sub-transistor T4-1 and the gate terminal of the fourth sub-transistor T4-2 may be connected to the second gate signal line GI, respectively.

[0067] A first terminal of the fifth transistor T5 may be connected to the first power voltage line ELVDD, a second terminal of the fifth transistor T5 may be connected to the first terminal of the first transistor T1, and a gate terminal of the fifth transistor T5 may be connected to the light emission control line EM.

[0068] A first terminal of the sixth transistor T6 may be connected to the second terminal of the first transistor T1, a second terminal of the sixth transistor T6 may be connected to the light emitting element OLED, and a gate terminal of the sixth transistor T6 may be connected to the light emitting control line EM.

[0069] A first terminal of the seventh transistor T7 may be connected to the second initialization voltage line VAINT, a second terminal of the seventh transistor T7 may be connected to the light emitting element OLED, and a gate terminal of the seventh transistor T7 may be connected to the third gate signal line GB.

[0070] A first terminal of the eighth transistor T8 may be connected to a bias voltage line VBIAS. A second terminal of the eighth transistor T8 may be connected to the first terminal of the first transistor T1. A gate terminal of the eighth transistor T8 may be connected to a bias control line EB.

[0071] The pixel circuit PXCa may include a storage capacitor CST, two hold capacitors N3 Hold, N4 Hold, and a diode parasitic capacitor COLED.

[0072] A first terminal of the storage capacitor CST may be connected to the first power voltage line ELVDD. A second terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor T1.

[0073] A first terminal of the first holding capacitor N3 Hold may be connected to the first power voltage line ELVDD. A second terminal of the first holding capacitor N3 Hold may be connected to each of the first terminal of the first sub-transistor T3 - 1 and the second terminal of the second sub-transistor T3 - 2 .

[0074] A first terminal of the second holding capacitor N4 Hold may be connected to each of the first terminal of the third sub-transistor T4 - 1 and the second terminal of the fourth sub-transistor T4 - 2 . A second terminal of the second holding capacitor N4 Hold may be connected to a bias voltage line VBIAS.

[0075] One end of the diode parasitic capacitor COLED may be connected to the anode electrode of the light emitting element OLED, and the other end of the diode parasitic capacitor COLED may be connected to the cathode electrode of the light emitting element OLED.

[0076] Figure 3 The circuit structure of the pixel circuit PXCa shown is an example and can be modified in various ways.

[0077] Figures 4 to 16 Yes means Figure 1 A configuration diagram of a display device.

[0078] The display device may include pixel circuits of a plurality of sub-pixels arranged adjacent to each other. The plurality of pixel circuits may include substantially the same structure. For example, it may be, Figures 4 to 16 The first portion SEC1 is the first sub-pixel (eg, Figure 2 The second portion SEC2 is a portion of the first sub-pixel SPX1 of the embodiment of the present invention, and the second portion SEC2 is a portion of the second sub-pixel (eg, Figure 2The first portion SEC1 and the second portion SEC2 are used to illustrate a shielding pattern (eg, Fig.10 The shielding pattern of BVIA and Fig.16 For this purpose, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are omitted, and the third transistor T3 and the fourth transistor T4 are centered. Figure 3 The description will focus on the first part SEC1 in the structure corresponding to the pixel circuit PXCa).

[0079] Reference Figure 1 as well as Figure 4 , the display device DD may include an active pattern ACT.

[0080] The active pattern ACT may include first to fourth channel regions CH1, CH2, CH3, CH4 spaced apart from each other. The active pattern ACT may include first to fifth regions SE1, SE2, SE3, SE4, SE5 spaced apart from each other. The first channel region CH1 may be disposed adjacent to the first region SE1 and the second region SE2. The second channel region CH2 may be disposed adjacent to the second region SE2 and the third region SE3. The third channel region CH3 may be disposed adjacent to the third region SE3 and the fourth region SE4. The fourth channel region CH4 may be disposed adjacent to the fourth region SE4 and the fifth region SE5.

[0081] The first to fifth regions SE1, SE2, SE3, SE4, and SE5 may function as electrodes, signal lines, input terminals of transistors, output terminals of transistors, and / or one terminal of a capacitor.

[0082] The first to fourth channel regions CH1, CH2, CH3, and CH4 may be connected to a first conductive layer (eg, Figure 5 The first conductive layer CL1 overlaps with the first conductive layer CL2 and may be a channel region (or an active region) of the third transistor T3 and the fourth transistor T4.

[0083] Reference Figure 5 as well as Figure 6 , the display device may further include a first conductive layer CL1.

[0084] The first conductive layer CL1 may be disposed on the active pattern ACT. Specifically, a first gate insulating layer may be disposed on the active pattern ACT, and the first conductive layer CL1 may be disposed on the first gate insulating layer.

[0085] The first conductive layer CL1 may include a first gate pattern 201 and a second gate pattern 203. The first gate pattern 201 and the second gate pattern 203 may be disposed on the same layer.

[0086] The first gate pattern 201 may be Figure 3 The second gate pattern 203 may correspond to the second gate signal line GI. Figure 3 The first conductive layer CL1 may overlap with the active pattern ACT. Specifically, a portion of the first gate pattern 201 may overlap with the first channel region CH1 and the second channel region CH2 of the active pattern ACT. A portion of the second gate pattern 203 may overlap with the third channel region CH3 and the fourth channel region CH4. Thus, the first conductive layer CL1 may define the gate electrode of the transistor. In other words, the active pattern ACT and the first conductive layer CL1 may define a reference Figure 3 The aforementioned third transistor T3 and fourth transistor T4.

[0087] The third transistor T3 may be defined by a portion of the second gate pattern 203 and the third region SE3, the third channel region CH3, the fourth region SE4, the fourth channel region CH4, and the fifth region SE5 of the active pattern ACT. The third channel region CH3 may be Figure 3 The channel region of the first sub-transistor T3-1, the fourth channel region CH4 may be Figure 3 That is, the second gate pattern 203 may define a second gate electrode by overlapping the third channel region CH3 and the fourth channel region CH4 of the active pattern ACT. Each of the second gate electrodes may define a gate electrode of each of the first sub-transistor T3-1 and the second sub-transistor T3-2.

[0088] The fourth transistor T4 may be defined by a portion of the first gate pattern 201 and the first region SE1, the first channel region CH1, the second region SE2, the second channel region CH2, and the third region SE3 of the active pattern ACT. The first channel region CH1 may be Figure 3 The channel region of the third sub-transistor T4-1, the second channel region CH2 may be Figure 3 That is, the first gate pattern 201 may define a first gate electrode by overlapping the first channel region CH1 and the second channel region CH2 of the active pattern ACT. Each of the first gate electrodes may mean a gate electrode of each of the third sub-transistor T4-1 and the fourth sub-transistor T4-2.

[0089] Reference Figure 7 as well as Figure 8 , the display device may further include a second conductive layer CL2.

[0090] The second conductive layer CL2 may be disposed on the first conductive layer CL1. Specifically, the second gate insulating layer may be disposed on the first conductive layer CL1, and the second conductive layer CL2 may be disposed on the second gate insulating layer.

[0091] The second conductive layer CL2 may include a bias pattern VBIAS and a storage pattern CS1E. The bias pattern VBIAS and the storage pattern CS1E may be disposed in the same layer.

[0092] The second conductive layer CL2 may overlap the active pattern ACT. Specifically, a portion of the bias pattern VBIAS may overlap the second region SE2 of the active pattern ACT. A portion of the storage pattern CS1E may overlap the fourth region SE4 of the active pattern ACT. Thus, the second conductive layer CL2 may define a capacitor. In other words, the active pattern ACT and the second conductive layer CL2 may define a reference Figure 3 The aforementioned first holding capacitor N3 Hold and the second holding capacitor N4 Hold.

[0093] The second holding capacitor N4 Hold may be defined by a portion of the bias pattern VBIAS and the second region SE2 of the active pattern ACT. That is, the bias pattern VBIAS may overlap the second region SE2 of the active pattern ACT to form the second holding capacitor N4 Hold. The first storage electrode may be a portion where the bias pattern VBIAS overlaps the second region SE2.

[0094] The first holding capacitor N3 Hold may be defined by a portion of the storage pattern CS1E and the fourth region SE4 of the active pattern ACT. That is, the storage pattern CS1E may overlap the fourth region SE4 of the active pattern ACT to form the first holding capacitor N3 Hold. The second storage electrode may be a portion where the storage pattern CS1E overlaps the fourth region SE4.

[0095] Reference Fig. 9 as well as Fig.12 , the display device may further include a third conductive layer CL3.

[0096] The third conductive layer CL3 may be disposed on the second conductive layer CL2. Specifically, an interlayer insulating layer may be disposed on the second conductive layer CL2, and the third conductive layer CL3 may be disposed on the interlayer insulating layer.

[0097] The third conductive layer CL3 may include a first lower electrode pattern CE1, a second lower electrode pattern CE2, a third lower electrode pattern CE3, a fourth lower electrode pattern CE4, a fifth lower electrode pattern CE5, a sixth lower electrode pattern CE6, a seventh lower electrode pattern CE7, and an eighth lower electrode pattern CE8. The first lower electrode pattern CE1, the second lower electrode pattern CE2, the third lower electrode pattern CE3, the fourth lower electrode pattern CE4, the fifth lower electrode pattern CE5, the sixth lower electrode pattern CE6, the seventh lower electrode pattern CE7, and the eighth lower electrode pattern CE8 may be disposed on the same layer.

[0098] Each of the first to third lower electrode patterns CE1, CE2, CE3 and the sixth to eighth lower electrode patterns CE6, CE7, CE8 may extend in the second direction DR2. Each of the fourth lower electrode pattern CE4 and the fifth lower electrode pattern CE5 may have an island shape. A first contact hole CNT1 penetrating the interlayer insulating layer ILD may be defined in an area corresponding to each of the first lower electrode pattern CE1, the fourth lower electrode pattern CE4, and the sixth lower electrode pattern CE6. For example, the first contact hole CNT1 may be defined at a position where the first lower electrode pattern CE1 overlaps with the active pattern ACT, at a position where the fourth lower electrode pattern CE4 overlaps with the active pattern ACT, and at a position where the sixth lower electrode pattern CE6 overlaps with the active pattern ACT.

[0099] A portion of the first lower electrode pattern CE1 may overlap a portion of the bias pattern VBIAS, a portion of the active pattern ACT, a portion of the first gate pattern 201 , a portion of the storage pattern CS1E, and a portion of the second gate pattern 203 .

[0100] A portion of the second lower electrode pattern CE2 may overlap a portion of the active pattern ACT and a portion of the second gate pattern 203. The second lower electrode pattern CE2 may be in electrical contact with the third region SE3 of the active pattern ACT.

[0101] A portion of the third lower electrode pattern CE3 may overlap a portion of the bias pattern VBIAS, a portion of the active pattern ACT, a portion of the first gate pattern 201, a portion of the storage pattern CS1E, and a portion of the second gate pattern 203. A portion of the third lower electrode pattern CE3 may electrically contact the storage pattern CS1E.

[0102] A portion of the fourth lower electrode pattern CE4 may overlap a portion of the active pattern ACT.

[0103] A portion of the fifth lower electrode pattern CE5 may overlap a portion of the bias pattern VBIAS.

[0104] A portion of the sixth lower electrode pattern CE6 may overlap a portion of the bias pattern VBIAS, a portion of the active pattern ACT, a portion of the first gate pattern 201 , a portion of the storage pattern CS1E, and a portion of the second gate pattern 203 .

[0105] A portion of the seventh lower electrode pattern CE7 may overlap a portion of the active pattern ACT and a portion of the second gate pattern 203 .

[0106] A portion of the eighth lower electrode pattern CE8 may overlap a portion of the bias pattern VBIAS, a portion of the active pattern ACT, a portion of the first gate pattern 201 , a portion of the storage pattern CS1E, and a portion of the second gate pattern 203 .

[0107] Reference Fig.10 as well as Fig.12 , the display device may further include a shielding pattern BVIA.

[0108] A shielding pattern BVIA may be disposed on the third conductive layer CL3 . In one embodiment, the shielding pattern BVIA may be disposed on the same layer as the interlayer insulating layer ILD.

[0109] The shielding pattern BVIA may overlap the third transistor T3 , the fourth transistor T4 , the first hold capacitor N3 Hold, and the second hold capacitor N4 Hold.

[0110] At this time, the shielding pattern BVIA may not overlap with the first via hole HOa. For detailed description of the asymmetric shape of the shielding pattern BVIA located in each of the first portion SEC1 and the second portion SEC2, refer to Fig.15 as well as Fig.16 This will be described later.

[0111] The shielding pattern BVIA may include a black substance. For example, the black substance may include an inorganic substance or an organic substance. For example, the organic black substance may include a dark resin, etc. According to this, the shielding pattern BVIA may minimize the influence of light received in the third transistor T3, the fourth transistor T4, the first holding capacitor N3 Hold, and the second holding capacitor N4 Hold.

[0112] Reference Fig.11 as well as Fig.12 , the display device may further include a fourth conductive layer CL4a.

[0113] The fourth conductive layer CL4a may be disposed on the third conductive layer CL3. Specifically, the first via insulating layer may be disposed on the third conductive layer CL3, and the fourth conductive layer CL4a may be disposed on the first via insulating layer.

[0114] The fourth conductive layer CL4a may include a first intermediate electrode pattern 401a, a second intermediate electrode pattern 402a, a third intermediate electrode pattern 403a, a fourth intermediate electrode pattern 404a, a fifth intermediate electrode pattern 405a, and a sixth intermediate electrode pattern 406a. The first intermediate electrode pattern 401a, the second intermediate electrode pattern 402a, the third intermediate electrode pattern 403a, the fourth intermediate electrode pattern 404a, the fifth intermediate electrode pattern 405a, and the sixth intermediate electrode pattern 406a may be disposed on the same layer.

[0115] Each of the first and second intermediate electrode patterns 401a and 402a may extend in the first direction DR1, each of the third and fifth intermediate electrode patterns 403a and 405a may extend in the second direction DR2, and each of the fourth and sixth intermediate electrode patterns 404a and 406a may have an island shape.

[0116] The first via hole insulating layer may define a first via hole HOa. The first via hole insulating layer may define a first via hole HOa exposing at least a portion of the sixth lower electrode pattern CE6. For detailed description of the first via hole HOa, refer to Fig.15 as well as Fig.16 This will be described later.

[0117] The first intermediate electrode pattern 401 a may overlap the active pattern ACT, the bias pattern VBIAS, the first, third, fifth, sixth, and eighth lower electrode patterns CE1, CE3, CE5, CE6, and CE8, the first shielding pattern BVIA1, and the second shielding pattern BVIA2.

[0118] The second intermediate electrode pattern 402 a may overlap the active pattern ACT, the storage pattern CS1E, the first, third, sixth, and eighth lower electrode patterns CE1, CE3, CE6, and CE8, the first shielding pattern BVIA1, and the second shielding pattern BVIA2.

[0119] The third intermediate electrode pattern 403a may overlap the active pattern ACT and the second lower electrode pattern CE2. The fourth intermediate electrode pattern 404a may overlap the active pattern ACT, the storage pattern CS1E, the third lower electrode pattern CE3, and the fourth lower electrode pattern CE4. The fifth intermediate electrode pattern 405a may overlap the active pattern ACT and the seventh lower electrode pattern CE7. The sixth intermediate electrode pattern 406a may overlap the storage pattern CS1E and the eighth lower electrode pattern CE8.

[0120] exist Fig.11 as well as Fig.12 The second intermediate electrode pattern 402a is described as the first initialization voltage line VINT, but in the following description Fig.15 The second middle electrode pattern 402b may also be a second initialization voltage line VAINT. For detailed description of the second middle electrode pattern 402b, refer to Fig.15 as well as Fig.16 This will be described later.

[0121] Reference Fig.13 as well as Fig.14 , the display device may further include a fifth conductive layer CL5.

[0122] The fifth conductive layer CL5 may be disposed on the fourth conductive layer CL4a. Specifically, the second via insulating layer may be disposed on the fourth conductive layer CL4a, and the fifth conductive layer CL5 may be disposed on the second via insulating layer.

[0123] The fifth conductive layer CL5 may include a first upper electrode pattern 501, a second upper electrode pattern 502, a third upper electrode pattern 503, and a fourth upper electrode pattern 504. The first upper electrode pattern 501, the second upper electrode pattern 502, the third upper electrode pattern 503, and the fourth upper electrode pattern 504 may be disposed on the same layer.

[0124] Each of the first upper electrode pattern 501 , the second upper electrode pattern 502 , the third upper electrode pattern 503 , and the fourth upper electrode pattern 504 may extend in the second direction DR2 .

[0125] Each of the second upper electrode pattern 502 and the fourth upper electrode pattern 504 may include a portion protruding in the first direction DR1 , and each of the first upper electrode pattern 501 and the third upper electrode pattern 503 may include a portion protruding in a direction opposite to the first direction DR1 .

[0126] The second via insulating layer VIA2 may define an intermediate via hole HO2 . The second via insulating layer VIA2 may define an intermediate via hole HO2 exposing at least a portion of the fourth intermediate electrode pattern 404 a .

[0127] The first upper electrode pattern 501 may overlap the active pattern ACT, the first gate pattern 201 , the second gate pattern 203 , the bias pattern VBIAS, the storage pattern CS1E, the first lower electrode pattern CE1 , the first shielding pattern BVIA1 , the first intermediate electrode pattern 401 a , and the second intermediate electrode pattern 402 a .

[0128] The second upper electrode pattern 502 may overlap with the active pattern ACT, the first gate pattern 201, the second gate pattern 203, the bias pattern VBIAS, the storage pattern CS1E, the third lower electrode pattern CE3, the fourth lower electrode pattern CE4, the fifth lower electrode pattern CE5, the first shielding pattern BVIA1, the first intermediate electrode pattern 401a, the second intermediate electrode pattern 402a, and the fourth intermediate electrode pattern 404a. A portion of the second upper electrode pattern 502 may be in electrical contact with the fourth intermediate electrode pattern 404a.

[0129] The third upper electrode pattern 503 may overlap the active pattern ACT, the first gate pattern 201 , the second gate pattern 203 , the bias pattern VBIAS, the storage pattern CS1E, the sixth lower electrode pattern CE6 , the second shielding pattern BVIA2 , the first intermediate electrode pattern 401 a , and the second intermediate electrode pattern 402 a .

[0130] The fourth upper electrode pattern 504 may overlap the active pattern ACT, the first gate pattern 201, the second gate pattern 203, the bias pattern VBIAS, the storage pattern CS1E, the eighth lower electrode pattern CE8, the second shielding pattern BVIA2, the first intermediate electrode pattern 401a, the second intermediate electrode pattern 402a, and the sixth intermediate electrode pattern 406a.

[0131] like Fig.14 As shown, the first shielding pattern BVIA1 and the second shielding pattern BVIA2 may have different planar shapes. In detail, the first shielding pattern BVIA1 located in the first portion SEC1 and the second shielding pattern BVIA2 located in the second portion SEC2 may have different planar shapes. For example, the second shielding pattern BVIA2 may be adjacent to the first hole HOa, and the first shielding pattern BVIA1 may be separated from the second shielding pattern BVIA2.

[0132] Reference Figure 2 , Figure 3 , Fig.11 as well as Fig.15 , the display device may have a structure in which the first initialization voltage line VINT and the second initialization voltage line VAINT are separated.

[0133] Fig.11 The second middle electrode pattern 402a may be a first initialization voltage line VINT. The second middle electrode pattern 402a may be connected to the first initialization voltage line VINT. Figure 2 The first row R1 corresponds to the first initialization voltage line VINT.

[0134] In the case where the second intermediate electrode pattern 402a is the first initialization voltage line VINT, the second intermediate electrode pattern 402a located in the second portion SEC2 may define a first via hole HOa. The first via hole HOa may be formed at the first initialization voltage line VINT. Figure 2 The second column C2 overlaps the position of the first via hole HOa.

[0135] like Figure 5 As shown, the display device may further include a fourth conductive layer CL4b.

[0136] The fourth conductive layer CL4b may be disposed on the third conductive layer CL3. Specifically, the first via insulating layer may be disposed on the third conductive layer CL3, and the fourth conductive layer CL4b may be disposed on the first via insulating layer.

[0137] The fourth conductive layer CL4b may include a first intermediate electrode pattern 401b, a second intermediate electrode pattern 402b, a third intermediate electrode pattern 403b, a fourth intermediate electrode pattern 404b, a fifth intermediate electrode pattern 405b, and a sixth intermediate electrode pattern 406b. The first intermediate electrode pattern 401b, the second intermediate electrode pattern 402b, the third intermediate electrode pattern 403b, the fourth intermediate electrode pattern 404b, the fifth intermediate electrode pattern 405b, and the sixth intermediate electrode pattern 406b may be disposed on the same layer.

[0138] Each of the first and second intermediate electrode patterns 401b and 402b may extend in the first direction DR1. Each of the third and fifth intermediate electrode patterns 403b and 405b may extend in the second direction DR2. Each of the fourth and sixth intermediate electrode patterns 404b and 406b may have an island shape.

[0139] The first via hole HOb may be defined in the first via insulating layer. The first via hole HOb exposing at least a portion of the sixth lower electrode pattern CE6 may be defined in the first via insulating layer.

[0140] The first intermediate electrode pattern 401b may overlap the active pattern ACT, the bias pattern VBIAS, the first lower electrode pattern CE1, the third lower electrode pattern CE3, the fifth lower electrode pattern CE5, the sixth lower electrode pattern CE6, and the eighth lower electrode pattern CE8, the first shield pattern BVIA1, and the second shield pattern BVIA2. The second intermediate electrode pattern 402b may overlap the active pattern ACT, the storage pattern CS1E, the first lower electrode pattern CE1, the third lower electrode pattern CE3, the sixth lower electrode pattern CE6, and the eighth lower electrode pattern CE8, the first shield pattern BVIA1, and the second shield pattern BVIA2.

[0141] The third intermediate electrode pattern 403b may overlap the active pattern ACT and the second lower electrode pattern CE2. The fourth intermediate electrode pattern 404b may overlap the active pattern ACT, the storage pattern CS1E, the third lower electrode pattern CE3, and the fourth lower electrode pattern CE4. The fifth intermediate electrode pattern 405b may overlap the active pattern ACT and the seventh lower electrode pattern CE7. The sixth intermediate electrode pattern 406b may overlap the storage pattern CS1E and the eighth lower electrode pattern CE8.

[0142] Fig.15 The second middle electrode pattern 402b may be a second initialization voltage line VAINT. The second middle electrode pattern 402b may be connected to the Figure 2 In the case where the second intermediate electrode pattern 402b is the second initialization voltage line VAINT, the second via hole HOb may be defined at the second intermediate electrode pattern 402b located at the first portion SEC1. The second via hole HOb may be formed at the first portion SEC1. Figure 2 The overlapping position of the first column C1 corresponds to the second via hole HOb.

[0143] Reference Figure 2 , Figure 3 , Fig.11 , Fig.14 as well as Fig.15 The shielding pattern BVIA may be formed not to overlap with the vias (eg, the first via HOa and the second via HOb). The first shielding patterns BVIA1, BVIA1b and the second shielding patterns BVIA2, BVIA2b may have different planar shapes according to the positions of the vias formed in the second via insulating layer VIA2.

[0144] like Figure 2 as well as Fig.14 As shown, the shielding pattern BVIA overlapping with the first initialization voltage line VINT may be formed so as not to overlap with the via in the second portion SEC2. In detail, the second shielding pattern BVIA2 may be adjacent to the first via HOa, and the first shielding pattern BVIA1 may be separated from the second shielding pattern BVIA2. According to the second shielding pattern BVIA2 being formed so as not to interfere with the first via HOa, the second shielding pattern BVIA2 may have a different planar shape from the first shielding pattern BVIA1.

[0145] like Figure 2 , Fig.15 as well as Fig.16As shown, the shielding pattern BVIA overlapping with the second initialization voltage line VAINT may be formed so as not to overlap with the via in the first portion SEC1. In detail, the first shielding pattern BVIA1b may be adjacent to the second via HOb, and the second shielding pattern BVIA2b may be separated from the first shielding pattern BVIA1b. According to the first shielding pattern BVIA1b being formed so as not to interfere with the second via HOb, the first shielding pattern BVIA1b may have a different planar shape from the second shielding pattern BVIA2b.

[0146] Fig.17 It is along Fig.14 Cross-sectional view of line I-I'.

[0147] Reference Fig.17 According to an embodiment of the present invention, a display device DD may include a substrate SUB, an active pattern ACT, a first gate insulating layer GI1, a first gate pattern 201, a second gate pattern 203, a second gate insulating layer GI2, a second conductive layer CL2, an interlayer insulating layer ILD, a third conductive layer CL3, a shielding pattern BVIA1, a first via insulating layer VIA1, a fourth conductive layer CL4, a second via insulating layer VIA2, a fifth conductive layer CL5, a third via insulating layer VIA3, a pixel definition film HPDL, and a light emitting element OLED.

[0148] The substrate SUB may include a transparent substance or an opaque substance. The substrate SUB may be a transparent resin substrate. Examples of the transparent resin substrate include a polyimide substrate and the like.

[0149] The active pattern ACT may be disposed on the substrate SUB. Specifically, the active pattern ACT may be disposed on the buffer layer. Figure 3 As described above, the active pattern ACT may include first to fourth channel regions CH1, CH2, CH3, CH4 separated from each other and first to fifth regions SE1, SE2, SE3, SE4, SE5 separated from each other. The active pattern ACT may be connected to the conductive pattern. For example, the third region SE3 of the active pattern ACT may be connected to the second lower electrode pattern CE2.

[0150] The first gate insulating layer GI1 may be disposed on the substrate SUB. In detail, the first gate insulating layer GI1 may be disposed on the substrate SUB and the active pattern ACT. That is, the first gate insulating layer GI1 may cover the active pattern ACT.

[0151] A first conductive layer CL1 may be disposed on the first gate insulating layer GI1. The first conductive layer CL1 may include a first gate pattern 201 and a second gate pattern 203. The first gate pattern 201 and the second gate pattern 203 may be disposed on the same layer.

[0152] A portion of the first gate pattern 201 may define a first gate electrode of the fourth transistor T4 by overlapping the first channel region CH1 and the second channel region CH2 of the active pattern ACT. A portion of the first gate pattern 201 overlapping the first channel region CH1 and the second channel region CH2 of the active pattern ACT may be the first gate electrode of the fourth transistor T4.

[0153] A portion of the second gate pattern 203 may define a second gate electrode of the third transistor T3 by overlapping the third channel region CH3 and the fourth channel region CH4 of the active pattern ACT. A portion of the second gate pattern 203 overlapping the third channel region CH3 and the fourth channel region CH4 of the active pattern ACT may be the second gate electrode of the third transistor T3.

[0154] The second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1. Specifically, the second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1 and the first conductive layer CL1. That is, the second gate insulating layer GI2 may cover the first gate electrode and the second gate electrode.

[0155] A second conductive layer CL2 may be disposed on the second gate insulating layer GI2. The second conductive layer CL2 may include a bias pattern VBIAS and a storage pattern CS1E. The bias pattern VBIAS and the storage pattern CS1E may be disposed on the same layer.

[0156] A portion of the bias pattern VBIAS may define a first storage electrode of the second hold capacitor N4 Hold by overlapping the second region SE2 of the active pattern ACT.

[0157] A portion of the storage pattern CS1E may define a second storage electrode of the first hold capacitor N3 Hold by overlapping the fourth region SE4 of the active pattern ACT.

[0158] An interlayer insulating layer ILD may be disposed on the second gate insulating layer GI2. Specifically, the interlayer insulating layer ILD may be disposed on the second gate insulating layer GI2 and the second conductive layer CL2. That is, the interlayer insulating layer ILD may cover the second conductive layer CL2.

[0159] A third conductive layer CL3 may be disposed on the interlayer insulating layer ILD. The third conductive layer CL3 may include a second lower electrode pattern CE2 and a third lower electrode pattern CE3. The second lower electrode pattern CE2 and the third lower electrode pattern CE3 may be disposed on the same layer. For example, the second lower electrode pattern CE2 may be connected to a portion of the active pattern ACT (e.g., the third region SE3), and the third lower electrode pattern CE3 may be connected to the storage pattern CS1E.

[0160] The shielding pattern BVIA1 may be disposed on the interlayer insulating layer ILD. In one embodiment, the shielding pattern BVIA1 may be disposed on the same layer as the third conductive layer CL3.

[0161] The shielding pattern BVIA1 may overlap the first gate electrode, the second gate electrode, the first storage electrode, and the second storage electrode. At this time, the shielding pattern BVIA1 may be formed so as not to overlap the via formed in the second via insulating layer VIA2. Thus, the shielding pattern BVIA1 may shield the third transistor T3, the fourth transistor T4, the first holding capacitor N3Hold, and the second holding capacitor N4Hold from light.

[0162] In addition, the shielding pattern BVIA1 may be covered by the first via insulating layer VIA1. Thus, the shielding pattern BVIA1 may not be damaged in a subsequent process (eg, a process of forming the via hole, etc.). However, the present invention is not limited thereto.

[0163] In another embodiment, as shown in FIG. Fig.25 As described later, the shielding pattern BVIA1B may also be arranged in the same layer as the fourth conductive layer CL4. The shielding pattern BVIA1B may overlap with the first gate electrode, the second gate electrode, the first storage electrode, and the second storage electrode. At this time, the shielding pattern BVIA1B may be formed so as not to overlap with the via formed in the second via insulating layer VIA2. In addition, the shielding pattern BVIA1B may be covered by the second via insulating layer VIA2.

[0164] In yet another embodiment, as shown in FIG. Fig.26 As described later, the shielding pattern BVIA1C may also be arranged in the same layer as the fifth conductive layer CL5. The shielding pattern BVIA1C may overlap with the first gate electrode, the second gate electrode, the first storage electrode, and the second storage electrode. In this case, the shielding pattern BVIA1C may be formed so as not to overlap with the via hole. In addition, the shielding pattern BVIA1C may be covered by the third via insulating layer VIA3.

[0165] For detailed description of the shielding pattern BVIA1B covered by the second via insulating layer VIA2 and the shielding pattern BVIA1C covered by the third via insulating layer VIA3, refer to Fig.25 as well as Fig.26 This will be described later.

[0166] A first via insulating layer VIA1 may be disposed on the interlayer insulating layer ILD. In one embodiment, the first via insulating layer VIA1 may be disposed on the interlayer insulating layer ILD, the third conductive layer CL3 and the shielding pattern BVIA1. That is, the first via insulating layer VIA1 may cover the third conductive layer CL3 and the shielding pattern BVIA1.

[0167] A second via insulation layer VIA2 and a third via insulation layer VIA3 may be sequentially disposed on the first via insulation layer VIA1 .

[0168] A fourth conductive layer CL4 may be disposed on the first via insulating layer VIA1 . The fourth conductive layer CL4 may include a second intermediate electrode pattern 402 a , a third intermediate electrode pattern 403 a , and a fourth intermediate electrode pattern 404 a . The fourth intermediate electrode pattern 404 a may be connected to the second upper electrode pattern 502 .

[0169] A fifth conductive layer CL5 may be disposed on the second via insulating layer VIA2 , and may include a first upper electrode pattern 501 and a second upper electrode pattern 502 .

[0170] A pixel electrode PXL may be disposed on the third via insulating layer VIA3. For example, the pixel electrode PXL may be an anode electrode. Alternatively, the pixel electrode PXL may also be a cathode electrode.

[0171] A pixel definition film HPDL may be disposed on the third via insulating layer VIA3 and the pixel electrode PXL. The pixel definition film HPDL may have an opening that exposes a portion of the pixel electrode PXL. The pixel definition film HPDL may define each pixel that emits light by having the opening.

[0172] A light emitting layer EML may be disposed on the pixel electrode PXL. Specifically, the light emitting layer EML may be formed in the opening of the pixel definition layer HPDL.

[0173] A common electrode CAT may be formed on the pixel definition film HPDL and the light emitting layer EML. For example, the common electrode CAT may be a cathode electrode. Alternatively, the common electrode CAT may also be an anode electrode.

[0174] Thus, the light emitting element OLED including the pixel electrode PXL, the light emitting layer EML and the common electrode CAT can be disposed on the shielding pattern BVIA1. Figure 3 The aforementioned light emitting element OLED corresponds.

[0175] Figures 18 to 24 It is used to illustrate Figure 1 A cross-sectional view of a method for manufacturing a display device.

[0176] The following is omitted or simplified with reference to Figures 1 to 17 The above description of the display device is repeated.

[0177] Reference Fig.17 as well as Fig.18 , a preliminary active pattern ACT' may be formed on the substrate SUB.

[0178] The substrate SUB may be formed of a transparent material or an opaque material. The substrate SUB may be a transparent resin substrate. Examples of the transparent resin substrate include a polyimide substrate and the like.

[0179] The active pattern ACT may be formed on the substrate. The active pattern ACT may be formed of a metal oxide semiconductor (eg, indium gallium zinc oxide (IGZO)), an inorganic semiconductor, an organic semiconductor, etc. In one embodiment, the active pattern ACT may include amorphous silicon (a-Si) or polycrystalline silicon (poly-Si).

[0180] Reference Fig.17 as well as Fig.19 , a first gate insulating layer GI1 , a first gate pattern 201 , a second gate pattern 203 , and a second gate insulating layer GI2 may be sequentially formed on the preliminary active pattern ACT′.

[0181] The first gate insulating layer GI1 may be formed on the substrate SUB and the active pattern ACT. The first gate insulating layer GI1 may be formed of an insulating material.

[0182] The first gate pattern 201 and the second gate pattern 203 may be formed on the first gate insulating layer GI1. Each of the first gate pattern 201 and the second gate pattern 203 may be formed of metal, alloy, conductive metal oxide, transparent conductive material, or the like.

[0183] The preliminary active pattern ACT' may be doped using the first gate pattern 201 and the second gate pattern 203 as a mask. According to this, the active pattern ACT may be formed on the substrate SUB.

[0184] A second gate insulating layer GI2 may be formed on the first gate insulating layer GI1, the first gate pattern 201, and the second gate pattern 203. The second gate insulating layer GI2 may be formed of an insulating substance.

[0185] The first to third regions SE1, SE2, SE3, the first to second channel regions CH1, CH2, and the first gate electrode (eg, a portion where the first gate pattern 201 overlaps each of the first and second channel regions CH1 and CH2 of the active pattern ACT) may constitute a fourth transistor T4.

[0186] The third to fifth regions SE3, SE4, SE5, the third to fourth channel regions CH3, CH4 and the second gate electrode (eg, a portion where the second gate pattern 203 overlaps with each of the third and fourth channel regions CH3 and CH4 of the active pattern ACT) may constitute a third transistor T3.

[0187] Reference Fig.17 as well as Fig. 20 , a bias pattern VBIAS, a storage pattern CS1E, and an interlayer insulating layer ILD may be sequentially formed on the second gate insulating layer GI2.

[0188] The bias pattern VBIAS and the storage pattern CS1E may be formed on the second gate insulating layer GI2. Each of the bias pattern VBIAS and the storage pattern CS1E may be formed of metal, alloy, conductive metal oxide, transparent conductive material, etc. They may be used alone or in combination with each other.

[0189] An interlayer insulating layer ILD may be formed on the bias pattern VBIAS and the storage pattern CS1E. The interlayer insulating layer ILD may be formed of an insulating material.

[0190] The second holding capacitor N4Hold may be formed by the second region SE2 of the active pattern ACT and the bias pattern VBIAS. The bias pattern VBIAS may form a first storage electrode by overlapping the second region SE2 of the active pattern ACT on a plane.

[0191] The first holding capacitor N3Hold may be formed by the fourth region SE4 of the active pattern ACT and the storage pattern CS1E. The storage pattern CS1E may form a second storage electrode by overlapping the fourth region SE4 of the active pattern ACT on a plane.

[0192] Reference Fig.21 as well as Fig. 22, the first contact holes CNT1 - 1 and CNT1 - 2 may be formed. Next, the second lower electrode pattern CE2 , the third lower electrode pattern CE3 , and the shielding pattern BVIA1 may be formed on the interlayer insulating layer ILD.

[0193] Each of the second lower electrode pattern CE2 and the third lower electrode pattern CE3 can be formed while filling the first contact holes CNT1-1 and CNT1-2. For example, the second lower electrode pattern CE2 can be connected to the third region SE3 of the active pattern ACT, and the third lower electrode pattern CE3 can be connected to the storage pattern CS1E. Figure 3 The second lower electrode pattern CE2 may correspond to the first power voltage line ELVDD, and the second lower electrode pattern CE2 may correspond to a node commonly connected to the gate electrode of the first transistor T1, the second terminal of the third sub-transistor T4-1, and the second terminal of the first sub-transistor T3-1.

[0194] In one embodiment, the shielding pattern BVIA1 may be formed on the interlayer insulating layer ILD. In other words, the shielding pattern BVIA1, the second lower electrode pattern CE2, and the third lower electrode pattern CE3 may be formed on the same layer.

[0195] The shielding pattern BVIA1 may overlap the first gate electrode, the second gate electrode, the first storage electrode, and the second storage electrode, and may be formed not to overlap with the first gate electrode, the second gate electrode, the first storage electrode, and the second storage electrode. Fig.23 The vias defined by the first via insulating layer VIA1 overlap.

[0196] The shielding pattern BVIA1 may be formed of a black substance. For example, the black substance may include an inorganic substance or an organic substance. The organic black substance may include a dark resin, etc. Accordingly, the shielding pattern BVIA1 may minimize the influence of light received in the third transistor T3, the fourth transistor T4, the first holding capacitor N3 Hold, and the second holding capacitor N4 Hold.

[0197] Reference Fig.23 , a first via insulating layer VIA1 may be formed on the interlayer insulating layer ILD, the second lower electrode pattern CE2 , the third lower electrode pattern CE3 , and the shielding pattern BVIA1 . The first via insulating layer VIA1 may be formed of an organic insulating material.

[0198] Reference Fig.24 A fourth conductive layer CL4 , a second via insulating layer VIA2 , a fifth conductive layer CL5 , a third via insulating layer VIA3 , a pixel definition layer HPDL and a light emitting element OLED may be sequentially formed on the first via insulating layer VIA1 .

[0199] Each of the fourth conductive layer CL4 and the fifth conductive layer CL5 may be formed of metal, alloy, conductive metal oxide, transparent conductive material, etc. They may be used alone or in combination with each other.

[0200] Each of the second via insulating layer VIA2 and the third via insulating layer VIA3 may be formed of an organic insulating substance.

[0201] The pixel definition film HPDL may be formed of an organic substance or an inorganic substance. For example, the pixel definition film HPDL may be formed of photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, etc. They may be used alone or in combination with each other.

[0202] The light emitting element OLED may be formed in the opening defined by the pixel definition film HPDL. In detail, the pixel electrode PXL, the light emitting layer EML, and the common electrode CAT may be sequentially formed in the opening defined by the pixel definition film HPDL.

[0203] The pixel electrode PXL may be formed of metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. These may be used alone or in combination with each other.

[0204] The light emitting layer EML may be formed of a substance for emitting light, for example, an organic light emitting substance or an inorganic light emitting substance.

[0205] The common electrode CAT may be formed of a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. They may be used alone or in combination with each other. Thus, a display device DD including a shielding pattern BVIA1 may be formed. The shielding pattern BVIA1 may be formed to cover the third transistor T3, the fourth transistor T4, the first hold capacitor N3 Hold, and the second hold capacitor N4 Hold. According to it, the third transistor T3, the fourth transistor T4, the first hold capacitor N3Hold, and the second hold capacitor N4 Hold may be shielded from light. In addition, the shielding pattern BVIA1 may be covered by the first via insulating layer VIA1. Thus, the shielding pattern BVIA1 may not be damaged in subsequent processes (e.g., a process of forming vias, etc.).

[0206] Figure 25 to Figure 26 It is used to illustrate Figure 1 A cross-sectional view of another embodiment of a display device.

[0207] For example, Fig.25 and Fig.24 The difference is that the shielding pattern BVIA1B is formed on the first via insulating layer VIA1. Fig.26and Fig.24 The difference is that the shielding pattern BVIA1C is formed on the second via insulation layer VIA2 .

[0208] like Fig.25 As shown, in the display device DDB, the shielding pattern BVIA1B may be disposed on the first via insulating layer VIA1. At this time, the shielding pattern BVIA1B may be formed to overlap the first gate electrode, the second gate electrode, the first storage electrode, and the second storage electrode, and not overlap the via defined by the second via insulating layer VIA2.

[0209] like Fig.26 As shown, in the display device DDC, the shielding pattern BVIA1C may be disposed on the second via insulating layer VIA2. At this time, the shielding pattern BVIA1C may be formed to overlap with the first gate electrode, the second gate electrode, the first storage electrode, and the second storage electrode, and not overlap with the via defined by the third via insulating layer VIA3.

[0210] The display devices DD, DDB, and DDC according to the embodiments of the present utility model may include shielding patterns BVIA1, BVIA1B, and BVIA1C. The shielding patterns BVIA1, BVIA1B, and BVIA1C may be covered by via insulating layers (e.g., first via insulating layers VIA1, second via insulating layers VIA2, and third via insulating layers VIA3). According to this, the shielding patterns BVIA1, BVIA2, and BVIA3 may not be damaged in subsequent processes (e.g., contact hole formation processes, etc.). Through this, the low-frequency driving characteristics of the display devices DD, DDB, and DDC may be improved, and the display devices DD, DDB, and DDC may have a rigid structure.

[0211] Fig. 27 1 is a diagram for explaining the effect of improving the low-frequency driving characteristics of the display device according to the embodiment of the present utility model. In detail, Fig. 27 : is the light waveform showing each frequency.

[0212] The display device according to the comparative example may not include the shielding pattern (eg, referring to Fig.24 Shielding pattern BVIA1, Fig.25 The shielding pattern BVIA1B and Fig.26 In the case of the display device according to the comparative example, the leakage current I in the self-scan interval is lower when the low-frequency driving (solid line) is compared with the high-frequency driving (one-dot dash line). off According to this, in the case of the display device according to the comparative example, the brightness can be reduced in the self-scan interval.

[0213] The display devices DD, DDB, DDC according to the embodiments of the present invention may include shielding patterns BVIA1, BVIA1B, BVIA1C. The shielding patterns BVIA1, BVIA1B, BVIA1C may be formed to cover the third transistor T3, the fourth transistor T4, the first holding capacitor N3 Hold, and the second holding capacitor N4 Hold. According to the invention, when the display devices DD, DDB, DDC are driven at a low frequency (dashed line), the amount of current I leaked in the self-scanning interval is off It can be reduced compared with the display device of the comparative example. According to this, the problem of reduced brightness of the display devices DD, DDB, and DDC in the self-scan interval can be improved.

[0214] The display device according to an exemplary embodiment of the present invention may be included in a computer, a notebook computer, a mobile phone, a smart phone, a smart tablet, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, etc.

[0215] The above description is made with reference to the embodiments of the present invention, but a person having ordinary knowledge in the corresponding technical field will understand that various modifications and changes can be made to the present invention without departing from the concept and scope of the present invention recorded in the attached claims.

Claims

1. A display device, It is characterized in that include: substrate; An active pattern is disposed on the substrate and includes a first region, a second region, a third region, a first channel region, and a second channel region; a first conductive layer disposed on the active pattern and comprising a first gate electrode overlapping each of the first channel region and the second channel region; A second conductive layer, disposed on the first conductive layer and comprising a first storage electrode overlapping the second region; a shielding pattern, which is disposed on the second conductive layer, overlaps with the first gate electrode and the first storage electrode, and includes a black substance; as well as The light emitting element is arranged on the shielding pattern.

2. The display device according to claim 1, It is characterized in that The display device further includes: an interlayer insulating layer, disposed on the second conductive layer; and A first via insulating layer is disposed between the interlayer insulating layer and the light emitting element. The first via insulating layer covers the shielding pattern.

3. The display device according to claim 2, It is characterized in that The display device further defines: a via hole penetrating through the first via insulating layer, The shielding pattern comprises: A first shielding pattern is disposed adjacent to the via hole; and The second shielding pattern is disposed apart from the first shielding pattern and has a planar shape different from that of the first shielding pattern.

4. The display device according to claim 1, It is characterized in that The display device further includes: an interlayer insulating layer, disposed on the second conductive layer; A first via insulating layer, disposed on the interlayer insulating layer; and A second via insulating layer is disposed between the first via insulating layer and the light emitting element. The second via insulating layer covers the shielding pattern.

5. The display device according to claim 4, It is characterized in that The display device further defines: a via hole penetrating through the second via insulating layer, The shielding pattern comprises: A first shielding pattern is disposed adjacent to the via hole; and The second shielding pattern is disposed apart from the first shielding pattern and has a planar shape different from that of the first shielding pattern.

6. The display device according to claim 1, It is characterized in that The display device further includes: an interlayer insulating layer, disposed on the second conductive layer; A first via insulating layer, disposed on the interlayer insulating layer; A second via insulating layer, disposed on the first via insulating layer; and A third via insulating layer is disposed between the second via insulating layer and the light emitting element. The third via insulating layer covers the shielding pattern.

7. The display device according to claim 6, It is characterized in that The display device further defines: a via hole penetrating the third via insulating layer, The shielding pattern comprises: A first shielding pattern is disposed adjacent to the via hole; and The second shielding pattern is disposed apart from the first shielding pattern and has a planar shape different from that of the first shielding pattern.

8. The display device according to claim 1, It is characterized in that The active pattern further includes a fourth region, a fifth region, a third channel region and a fourth channel region. The first conductive layer is disposed on the active pattern, and the first conductive layer further includes: a second gate electrode, which overlaps with the third channel region and the fourth channel region respectively, The shielding pattern overlaps the second gate electrode.

9. The display device according to claim 8, It is characterized in that The second conductive layer is disposed on the first conductive layer, and the second conductive layer further includes: a second storage electrode overlapping the fourth region, The shielding pattern overlaps the second storage electrode.

10. The display device according to claim 8, It is characterized in that The first gate electrode, the first region, the second region, the third region, the first channel region, and the second channel region of the active pattern together constitute a driving initialization transistor. The second gate electrode constitutes a diode transistor together with the third region, the fourth region, the fifth region, the third channel region, and the fourth channel region of the active pattern.

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